KM68U4000ALGI-8L [SAMSUNG]

Standard SRAM, 512KX8, 85ns, CMOS, PDSO32, 0.525 INCH, SOP-32;


型号：	KM68U4000ALGI-8L
厂家：	SAMSUNG
描述：	Standard SRAM, 512KX8, 85ns, CMOS, PDSO32, 0.525 INCH, SOP-32 静态存储器光电二极管
文件：	总9页 (文件大小：160K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KM68V4000A, KM68U4000A Family

CMOS SRAM

Document Title

512K x8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

Revision No. History

Draft Date

Remark

0.0

Initial Draft

August 16, 1994

Advance

0.1

Revise

December 22, 1994

Preliminary

- Speed bin=70/85/100ns at Vcc=3.3V

0.2

Revise

April 15, 1996

- Seperate read and write for ICC1, ICC2

: ICC1= ICC2 ® Read=10mA and Write=20mA at Vcc=3.3V

- One datasheet for commercial and industrial product.

1.0

2.0

Finalize

September 19, 1996 Final

- Add 85ns with 30pF part in 3.3V product.

Revise

February 25, 1998

Final

- Change datasheet format

- Remove 70/100ns part from KM68V4000A Family

- Remove 70ns part form KM68U4000A Family

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision 2.0

February 1998

KM68V4000A, KM68U4000A Family

CMOS SRAM

512K x8 bit Low Power and Low Voltage CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

· Process Technology :TFT

The KM68V4000A and KM68U4000A families are fabricated

by SAMSUNG¢s advanced CMOS process technology. The

families supports various operating temperature ranges and

have various package types for user flexibility of system design.

The families also support low data retention voltage for battery

back-up operation with low data retention current.

· Organization : 512Kx8

· Power Supply Voltage

KM68V4000A Family : 3.0~3.6V

KM68U4000A Family : 2.7~3.3V

· Low Data Retention Voltage : 2V(Min)

· Three state output and TTL Compatible

· Package Type : 32-SOP-525, 32-TSOP2-400F/R

PRODUCT FAMILY

Power Dissipation

Product Family

Operating Temperature Vcc Range

Speed(ns)

PKG Type

Standby

(ISB1, Max)

Operating

(Icc2, Max)

KM68V4000AL

KM68V4000AL-L

85¹⁾

Commercial(0~70°C)

Industrial(-40~85°C)

Commercial(0~70°C)

Industrial(-40~85°C)

3.0~3.6V

2.7~3.3V

50/15mA

50/20mA

30/10mA

30/15mA

KM68V4000ALI

LM68V4000ALI-L

32-SOP

32-TSOP2-F/R

50mA

KM68U4000AL

KM68U4000ALI-L

85¹⁾/100

KM68U4000ALI

KM68U4000ALI-L

1. The parameter is measured with 30pF test load.

PIN DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

A18

A16

A14

A12

VCC

A15

A17

A13

VCC

A15

A17

Clk gen.

A18

Precharge circuit.

A16

A14

A12

A13

A10

A11

A13

A14

A15

A17

Memory array

1024 rows

256K´ 8 columns

Row

select

32-SOP

32-TSOP2-F

32-TSOP2-R

A11

A10

A16

I/O8

I/O7

I/O6

I/O5

I/O4

I/O8

I/O7

I/O6

I/O5

I/O4

I/O1

I/O8

Data

cont

I/O Circuit

I/O1

I/O2

I/O3

VSS

I/O1

I/O2

I/O3

Column select

16 VSS

Data

cont

Name

Function

Name

Function

A0 A1 A2 A4 A5 A6 A7 A12

Chip Select Input

A0~A18 Address Inputs

Output Enable Input I/O1~I/O8 Data Inputs/Outputs

Write Enable Input

Vcc

Vss

Power

Contri

logic

Ground

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Revision 2.0

February 1998

KM68V4000A, KM68U4000A Family

CMOS SRAM

PRODUCT LIST

Commercial Temperature Products(0~70°C)

Industrial Temperature Products(-40~85°C)

Part Name

Function

Part Name

Function

KM68V4000ALG-8

KM68V4000ALG-8L

32-SOP, 85ns, 3.3V,L

32-SOP, 85ns, 3.3V,LL

KM68V4000ALGI-8

KM68V4000ALGI-8L

32-SOP, 85ns, 3.3V,L

32-SOP, 85ns, 3.3V,LL

KM68V4000ALT-8L

KM68V4000ALR-8L

32-TSOP2-F, 85ns, 3.3V,LL

32-TSOP2-R, 85ns, 3.3V,LL

KM68V4000ALTI-8L

KM68V4000ALRI-8L

32-TSOP2-F, 85ns, 3.3V,LL

32-TSOP2-R, 85ns, 3.3V,LL

KM68U4000ALG-8

KM68U4000ALG-8L

KM68U4000ALG-10

KM68U4000ALG-10L

32-SOP, 85ns, 3.0V,L

32-SOP, 85ns, 3.0V,LL

32-SOP, 100ns, 3.0V,L

32-SOP, 100ns, 3.0V,LL

KM68U4000ALGI-8

KM68U4000ALGI-8L

KM68U4000ALGI-10

KM68U4000ALGI-10L

32-SOP, 85ns, 3.0V,L

32-SOP, 85ns, 3.0V,LL

32-SOP, 100ns, 3.0V,L

32-SOP, 100ns, 3.0V,LL

KM68U4000ALT-8L

KM68U4000ALT-10L

KM68U4000ALR-8L

KM68U4000ALR-10L

32-TSOP2-F, 85ns, 3.0V,LL

32-TSOP2-F, 100ns, 3.0V,LL

32-TSOP2-R, 85ns, 3.0V,LL

32-TSOP2-R, 100ns, 3.0V,LL

KM68U4000ALTI-8L

KM68U4000ALTI-10L

KM68U4000ALRI-8L

KM68U4000ALRI-10L

32-TSOP2-F, 85ns, 3.0V,LL

32-TSOP2-F, 100ns, 3.0V,LL

32-TSOP2-R, 85ns, 3.0V,LL

32-TSOP2-R, 100ns, 3.0V,LL

FUNCTIONAL DESCRIPTION

I/O

High-Z

Dout

Mode

Power

Standby

Active

X¹⁾

Deselected

Output disbaled

Read

Active

X¹⁾

Din

Write

Active

1. X means don¢t care (Must be low or high state)

ABSOLUTE MAXIMUM RATINGS¹⁾

Item

Symbol

Ratings

Unit

Remark

Voltage on any pin relative to Vss

Voltage on Vcc supply relative to Vss

Power Dissipation

VIN,VOUT

VCC

-0.5 to VCC+0.5

-0.3 to 4.6

0.7

°C

Storage temperature

TSTG

-65 to 150

0 to 70

KM68V4000AL, KM68U4000AL

Operating Temperature

-40 to 85

°C

KM68V4000ALI, KM68U4000ALI

Soldering temperature and time

TSOLDER

260°C, 10sec (Lead Only)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be

restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Revision 2.0

February 1998

KM68V4000A, KM68U4000A Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS¹⁾

Item

Symbol

Product

Min

Typ

Max

Unit

KM68V4000A Family

KM68U4000A Family

3.0

2.7

3.3

3.0

3.6

3.3

Supply voltage

Vcc

Ground

Vss

VIH

VIL

All Family

Vcc+0.3²⁾

0.4

Input high voltage

Input low voltage

Note:

KM68V4000A, KM68U4000A Family

2.2

-0.3³⁾

1. Commercial Product : TA=0 to 70°C, otherwise specified

Industrial Product : TA=-40 to 85°C, otherwise specified

2. Overshoot : V_CC+3.0V in case of pulse width £ 30ns

3. Undershoot : -3.0V in case of pulse width £ 30ns

4. Overshoot and undershoot is sampled, not 100% tested.

CAPACITANCE¹⁾(f=1MHz, TA=25°C)

Item

Symbol

CIN

Test Condition

VIN=0V

Min

Max

Unit

Input capacitance

Input/Output capacitance

CIO

VIO=0V

1. Capacitance is sampled, not 100% tested.

DC AND OPERATING CHARACTERISTICS

Test Conditions¹⁾

Item

Symbol

ILI

Min Typ Max Unit

Input leakage current

VIN=Vss to Vcc

-1

Output leakage current

Operating power supply current

ILO

CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc

IIO=0mA, CS=VIL, VIN=VIL or VIH, Read

ICC

Read

Write

Cycle time=1ms, 100% duty, IIO=0mA

CS£0.2V, VIN³ 0.2V or VIN ³ Vcc-0.2V

ICC1

ICC2

Average operating current

Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

Output low voltage

Output high voltage

Standby Current(TTL)

VOL

VOH

ISB

IOL=2.1mA

2.2

0.4

IOH=-1.0mA

CS=VIH, Other inputs=VIL or VIH

0.5

KM68V4000AL

KM68V4000AL-L

KM68V4000ALI

KM68V4000ALI-L

Standby Current(CMOS)

ISB1

CS³ Vcc-0.2V, Other inputs=0~Vcc

KM68U4000AL

KM68U4000AL-L

KM68U4000ALI

KM68U4000ALI-L

Revision 2.0

February 1998

KM68V4000A, KM68U4000A Family

CMOS SRAM

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level : 0.4 to 2.2V

Input rising and faling time : 5ns

Input and output reference voltage :1.5V

Outpuy load(see right) : CL=100pF+1TTL

CL =30pF+1TTL

1. Including scope and jig capacitance

1. KM68V4000A-8 Family, KM68U4000A-8 Family

AC CHARACTERISTICS (KM68V4000A Family : Vcc=3.0~3.3V, KM68U4000A Family : Vcc=2.7~3.3V

Commercial Product : TA=0 to 70°C, Industrial Product : TA=-40 to 85°C)

Speed Bins

Parameter List

Symbol

Units

85ns

100ns

Min

Max

Min

100

Max

Read cycle time

tRC

tAA

Address access time

100

Chip select to output

tCO

tOE

tLZ

100

Output enable to valid output

Chip select to low-Z output

Output enable to low-Z output

Chip disable to high-Z output

Output disable to high-Z output

Output hold from address change

Write cycle time

Read

tOLZ

tHZ

tOHZ

tOH

tWC

tCW

tAS

100

Chip select to end of write

Address set-up time

Address valid to end of write

Write pulse width

tAW

tWP

tWR

tWHZ

tDW

tDH

tOW

Write

Write recovery time

Write to output high-Z

Data to write time overlap

Data hold from write time

End write to output low-Z

DATA RETENTION CHARACTERISTICS

Item

Symbol

Test Condition

Min

Typ

Max

Unit

Vcc for data retention

VDR

CS³ Vcc-0.2V

2.0

3.6

KM68V4000AL

KM68V4000AL-L

0.5

KM68V4000ALI

KM68V4000ALI-L

Data retention current

IDR

Vcc=3.0V, CS³ Vcc-0.2V

KM68U4000AL

KM68V4000AL-L

0.5

KM68U4000ALI

KM68V4000ALI-L

Data retention set-up time

Recovery time

tSDR

tRDR

See data retention waveform

Revision 2.0

February 1998

KM68V4000A, KM68U4000A Family

CMOS SRAM

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tAA

tOH

Data Valid

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tOH

tAA

tCO1

tHZ

tOE

tOHZ

tOLZ

tLZ

High-Z

Data out

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

Revision 2.0

February 1998

KM68V4000A, KM68U4000A Family

CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC

Address

tCW(2)

tWR(4)

tAW

tWP(1)

tAS(3)

tDW

tDH

Data Valid

Data in

Data out

tWHZ

tOW

Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

tWC

Address

tCW(2)

tAS(3)

tWR(4)

tAW

tWP(1)

tDW

tDH

Data in

Data Valid

High-Z

Data out

High-Z

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE

going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write

to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

DATA RETENTION WAVE FORM

CS controlled

Data Retention Mode

tSDR

tRDR

VCC

3.0/2.7V

2.2V

VDR

CS³ VCC - 0.2V

GND

Revision 2.0

February 1998

KM68V4000A, KM68U4000A Family

CMOS SRAM

PACKAGE DIMENSIONS

Units : millimeter(inch)

32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)

0~8°

#32

#17

14.12±0.30

0.556±0.012

11.43±0.20

0.450±0.008

0.80±0.20

0.031±0.008

#16

+0.10

-0.05

0.20

20.87

0.822

2.74±0.20

MAX

0.108±0.008

+0.004

0.008

-0.002

3.00

MAX

0.118

20.47±0.20

0.806±0.008

0.10 MAX

0.004 MAX

+0.100

-0.050

0.41

1.27

0.050

0.71

0.028

+0.004

-0.002

(

)

0.05

0.002

0.016

MIN

Revision 2.0

February 1998

KM68V4000A, KM68U4000A Family

CMOS SRAM

PACKAGE DIMENSIONS

Units : millimeter(inch)

0~8°

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

0.25

0.010

(

)

#32

#17

0.45 ~0.75

0.018 ~ 0.030

11.76±0.20

0.463±0.008

#16

0.50

0.020

(

)

+0.10

-0.05

+0.004

-0.002

21.35

0.841

0.15

1.00±0.10

0.039±0.004

MAX

0.006

1.20

0.047

20.95±0.10

0.825±0.004

MAX

0.10 MAX

0.004 MAX

0.05

0.002

MIN

1.27

0.050

0.40±0.10

0.016±0.004

0.95

0.037

(

)

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

0~8°

0.25

0.010

(

)

#16

0.45 ~0.75

0.018 ~ 0.030

11.76±0.20

0.463±0.008

#32

#17

0.50

0.020

(

)

+0.10

-0.05

+0.004

-0.002

0.15

21.35

MAX

1.00±0.10

0.039±0.004

0.841

0.006

1.20

0.047

20.95±0.10

0.825±0.004

MAX

0.10 MAX

0.004 MAX

1.27

0.050

0.40±0.10

0.016±0.004

0.05

0.002

0.95

0.037

MIN

(

)

Revision 2.0

February 1998

KM68U4000ALGI-8L [SAMSUNG]

相关型号：

KM68U4000ALT-10L

KM68U4000ALT-8L0

KM68U4000ALTI-10L

KM68U4000ALTI-10L0

KM68U4000ALTI-8L

KM68U4000BLG-8L

KM68U4000BLG-8L0

KM68U4000BLGI-8L

KM68U4000BLR-8L

KM68U4000BLR-8L0

KM68U4000BLRI-8L

KM68U4000BLT-10L