KM718V887T-9 [SAMSUNG]
Cache SRAM, 256KX18, 9ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100;
| 型号： | KM718V887T-9 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache SRAM, 256KX18, 9ns, CMOS, PQFP100, 20 X 14 MM, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KM718V887
256Kx18 Synchronous SRAM
Document Title
256Kx18-Bit Synchronous Burst SRAM
Revision History
Rev.No. History
Draft Date
Remark
Preliminary
Preliminary
0.0
0.1
Initial draft
May. 15. 1997
Modify power down cycle timing & Interleaved read timing,
Insert Note 4 at AC timing characteristics.
Change ISB1 value from 10mA to 30mA.
February. 11. 1998
Change ISB2 value from 10mA to 20mA.
Preliminary
Preliminary
0.2
0.3
Change Undershoot spec
April. 14. 1998
May 13. 1998
from -3.0V(pulse width£20ns) to -2.0V(pulse width£tCYC/2)
Add Overshoot spec 4.6V((pulse width£tCYC/2)
Change VIH max from 5.5V to VDD+0.5V
Change ISB2 value from 20mA to 30mA.
Change VDD condition from VDD=3.3V+10%/-5% to VDD=3.3V+0.3V/-0.165V.
Final
Final
1.0
2.0
Final spec Release
May 15. 1998
Dec. 02. 1998
Add VDDQ Supply voltage( 2.5V )
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Dec. 1998
Rev. 2.0
- 1 -
KM718V887
256Kx18 Synchronous SRAM
256Kx18-Bit Synchronous Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• On-Chip Address Counter.
• Write Self-Timed Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
The KM718V887 is a 4,718,592 bit Synchronous Static Ran-
dom Access Memory designed for support zero wait state per-
formance for advanced Pentium/Power PC address pipelining.
And with CS1 high, ADSP is blocked to control signal.
It is organized as 256K words of 18 bits and integrates address
and control registers, a 2-bit burst address counter and high
output drive circuitry onto a single integrated circuit for reduced
components count implementation of high performance cache
RAM applications.
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system¢s burst sequence and are controlled by the burst
address advance(ADV) input. ZZ pin controls Power Down
State and reduces Stand-by current regardless of CLK.
The KM718V887 is implemented in SAMSUNG¢s high perfor-
mance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
FAST ACCESS TIMES
Parameter
Cycle Time
Symbol -7
-8
8.5 10 12
7.5
-9 Unit
tCYC
tCD
ns
ns
ns
Clock Access Time
8
9
Output Enable Access Time
tOE
3.5 3.5 3.5
LOGIC BLOCK DIAGRAM
CLK
LBO
256Kx18
MEMORY
ARRAY
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
ADV
ADSC
A¢0~A¢1
A0 ~ A1
A2~A17
ADDRESS
A0~A17
REGISTER
ADSP
DATA-IN
REGISTER
CS1
CS2
CS2
GW
BW
OUTPUT
BUFFER
CONTROL
LOGIC
WEa
WEb
OE
ZZ
DQa0 ~ DQb7
DQPa, DQPb
Dec. 1998
Rev. 2.0
- 2 -
KM718V887
256Kx18 Synchronous SRAM
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
1
2
3
4
5
6
7
8
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin
TQFP
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
(20mm x 14mm)
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
32,33,34,35,36,37,
44,45,46,47,48,49,
50,80,81,82,99,100
83
VDD
VSS
N.C.
Power Supply(+3.3V) 15,41,65,91
Ground
17,40,67,90
No Connect
1,2,3,6,7,14,16,25,28,
29,30,38,39,42,43,51
52,53,56,57,66,75
78,79,95,96
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
OE
Burst Address Advance
Address Status Processor 84
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
85
89
98
97
92
93,94
86
DQa0~a7
DQb0~b7
DQPa, Pb
VDDQ
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
Output Power Supply 4,11,20,27,54,61,70,77
(2.5V or 3.3V)
VSSQ
Output Ground
5,10,21,26,55,60,71,76
GW
BW
ZZ
LBO
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
88
87
64
31
Dec. 1998
Rev. 2.0
- 3 -
KM718V887
256Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The KM718V887 is a synchronous SRAM designed to support the burst address accessing sequence of the Pentium and Power PC
based microprocessor. All inputs(with the exception of OE, LBO and ZZ) are sampled on rising clock edges.
The start and duration of the burst access is controlled by ADSP, ADSC, ADV and Chip Select pins.
When ZZ is pulled HIGH, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(or ADSC) using the new external address clocked into the on-chip address register when both
GW and BW are high or when BW is low and both WEa and WEb are high, When ADSP is sampled low, the chip selects are sam-
pled active, and the output buffer is enabled with OE, the data of cell array accessed by the current address are projected to the out-
put pins.
Write cycles are also initiated with ADSP(or ADSC)and are differentiated into two kinds of operations; All byte write operation and
individual byte write operation. All byte write occurs by enabling GW(in dependent of BW and WEx.), and individual byte write is per-
formed only when GW is High and BW is Low. WEa controls DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7 and DQPb.
CS1 is used to enable the device and conditions internal use of ADSP and is sampled only when a new external address is loaded.
ADV is ignored at the clock edge when ADSP is asserted, but can be sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when ADV is sampled low.
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
(Interleaved Burst)
Case 4
Case 1
Case 2
Case 3
LBO PIN
HIGH
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
Fourth Address
SEQUENCE TABLE
(Linear Burst)
Case 1
Case 2
Case 3
Case 4
LBO PIN
LOW
First Address
A1
A0
A1
A0
A1
A0
A1
A0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
Fourth Address
NOTE : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
TRUTH TABLES
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
Operation
ZZ
H
L
OE
X
I/O Status
High-Z
NOTE
Sleep Mode
1. X means "Don¢t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
L
DQ
Read
L
H
X
High-Z
Write
L
Din, High-Z
High-Z
5. Deselected means power down state of which stand-by current
depends on cycle time.
Deselected
L
X
Dec. 1998
Rev. 2.0
- 4 -
KM718V887
256Kx18 Synchronous SRAM
SYNCHRONOUS TRUTH TABLE
CS1
H
L
CS2
X
L
CS2 ADSP ADSC ADV WRITE CLK
Address Accessed
None
Operation
X
X
H
X
H
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Not Selected
None
Not Selected
L
X
L
L
None
Not Selected
L
X
X
L
None
Not Selected
L
X
H
H
H
X
X
X
X
X
X
X
X
L
None
Not Selected
L
X
L
External Address
External Address
External Address
Next Address
Next Address
Next Address
Next Address
Current Address
Current Address
Current Address
Current Address
Begin Burst Read Cycle
Begin Burst Write Cycle
Begin Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Read Cycle
Continue Burst Write Cycle
Continue Burst Write Cycle
Suspend Burst Read Cycle
Suspend Burst Read Cycle
Suspend Burst Write Cycle
Suspend Burst Write Cycle
L
L
H
H
H
X
H
X
H
X
H
X
L
L
L
H
H
H
L
X
H
X
H
X
H
X
H
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
NOTE : 1. X means "Don¢t Care".
2. The rising edge of clock is symbolized by • .
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE
GW
H
BW
H
L
WEa
X
WEb
X
Operation
READ
H
H
H
READ
H
L
L
H
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
H
L
H
L
L
L
L
X
X
X
NOTE : 1. X means "Don¢t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).
Dec. 1998
Rev. 2.0
- 5 -
KM718V887
256Kx18 Synchronous SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Voltage on I/O Pin Relative to VSS
Power Dissipation
Symbol
VDD
Rating
-0.3 to 4.6
VDD
Unit
V
VDDQ
VIN
V
-0.3 to 6.0
-0.3 to VDDQ+0.5
1.2
V
VIO
V
PD
W
°C
°C
°C
Storage Temperature
TSTG
TOPR
TBIAS
-65 to 150
0 to 70
Operating Temperature
Storage Temperature Range Under Bias
-10 to 85
*NOTE : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0°C£ TA£70°C)
Parameter
Supply Voltage
Ground
Symbol
VDD
Min
3.135
3.135
0
Typ.
3.3
3.3
0
Max
3.6
3.6
0
Unit
V
VDDQ
VSS
V
V
OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)
Parameter
Supply Voltage
Ground
Symbol
VDD
Min
3.135
2.375
0
Typ.
3.3
2.5
0
Max
3.6
2.9
0
Unit
V
VDDQ
VSS
V
V
CAPACITANCE*(TA=25°C, f=1MHz)
Parameter
Symbol
Test Condition
VIN=0V
Min
Max
5
Unit
pF
Input Capacitance
CIN
-
-
Output Capacitance
COUT
VOUT=0V
8
pF
*NOTE : Sampled not 100% tested.
Dec. 1998
Rev. 2.0
- 6 -
KM718V887
256Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
Parameter
Symbol
Test Conditions
Min
Max
2
Unit
mA
Input Leakage Current(except ZZ)
Output Leakage Current
IIL
VDD=Max ; VIN=VSS to VDD
-2
-2
-
IOL
Output Disabled, VOUT=VSS to VDDQ
2
mA
-7
-8
-9
-7
-8
-9
350
325
300
100
90
Device Selected, IOUT=0mA,
ZZ£VIL, All Inputs=VIL or VIH
Cycle Time ³ tCYC Min
Operating Current
ICC
ISB
-
mA
mA
-
-
Device deselected, IOUT=0mA,
ZZ£VIL, f=Max,
All Inputs£0.2V or ³ VDD-0.2V
-
-
80
-
Device deselected, IOUT=0mA, ZZ£0.2V,
f=0, All Inputs=fixed (VDD-0.2V or 0.2V)
Standby Current
ISB1
ISB2
30
30
mA
mA
Device deselected, IOUT=0mA,
ZZ³ VDD-0.2V, f=Max,
-
All Inputs£VIL or ³ VIH
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
VOL
VOH
VOL
VOH
VIL
IOL = 8.0mA
IOH = -4.0mA
IOL = 1.0mA
IOH = -1.0mA
-
0.4
V
V
V
V
V
V
V
V
2.4
-
-
0.4
-
2.0
-0.5*
2.0
-0.3*
1.7
0.8
VIH
VIL
VDD+0.5**
0.7
VIH
VDD+0.5**
*
VIL(Min)=-2.0(Pulse Width £ tCYC/2)
** VIH(Max)=4.6(Pulse Width £ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
Parameter
Value
0 to 3V
0 to 2.5V
1ns
Input Pulse Level(for 3.3V I/O)
Input Pulse Level(for 2.5V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
Input and Output Timing Reference Levels for 3.3V I/O
Input and Output Timing Reference Levels for 2.5V I/O
Output Load
1ns
1.5V
VDDQ/2
See Fig. 1
Dec. 1998
Rev. 2.0
- 7 -
KM718V887
256Kx18 Synchronous SRAM
Output Load(A)
Output Load(B)
(for tLZC, tLZOE, tHZOE & tHZC)
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
Dout
RL=50W
VL=1.5V for 3.3V I/O
319W / 1667W
VDDQ/2 for 2.5V I/O
30pF*
Dout
Z0=50W
353W / 1538W
5pF*
* Capacitive Load consists of all components of
the test environment.
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
KM718V887-7
KM718V887-8
KM718V887-9
Parameter
Symbol
Unit
Min
8.5
-
Max
Min
10
-
Max
Min
12
-
Max
Cycle Time
tCYC
tCD
-
-
-
ns
ns
Clock Access Time
7.5
8
9
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
tOE
-
3.5
-
3.5
-
3.5
ns
tLZC
tOH
0
-
0
-
0
-
ns
2
-
2
-
2
-
ns
tLZOE
tHZOE
tHZC
tCH
0
-
0
-
0
-
ns
-
3.5
-
3.5
-
3.5
ns
2
3.5
-
2
3.5
-
2
3.5
-
ns
3
4
4.5
4.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
ns
Clock Low Pulse Width
tCL
3
-
4
-
-
ns
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
tAS
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
-
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
2
-
-
ns
tSS
-
-
-
ns
tDS
-
-
-
ns
Write Setup to Clock High
tWS
-
-
-
ns
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
tADVS
tCSS
tAH
-
-
-
ns
-
-
-
ns
-
-
-
ns
tSH
-
-
-
ns
tDH
-
-
-
ns
Write Hold from Clock High(GW, BW, WEx)
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
tWH
tADVH
tCSH
tPDS
tPUS
-
-
-
ns
-
-
-
ns
-
-
-
ns
-
-
-
cycle
cycle
ZZ Low to Power Up
2
-
2
-
2
-
NOTE : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
4. At any given voltage and temperature, tHZC is less than tLZC.
Dec. 1998
Rev. 2.0
- 8 -
KM718V887
256Kx18 Synchronous SRAM
Dec. 1998
Rev. 2.0
- 9 -
KM718V887
256Kx18 Synchronous SRAM
Dec. 1998
Rev. 2.0
- 10
KM718V887
256Kx18 Synchronous SRAM
Dec. 1998
Rev. 2.0
- 11
KM718V887
256Kx18 Synchronous SRAM
Dec. 1998
Rev. 2.0
- 12
KM718V887
256Kx18 Synchronous SRAM
Dec. 1998
Rev. 2.0
- 13
KM718V887
256Kx18 Synchronous SRAM
Dec. 1998
Rev. 2.0
- 14
KM718V887
256Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
I/O[0:71]
Data
Address
A[18]
A[0:18]
A[18]
A[0:17]
A[0:17]
Address Data
CS2
Address Data
CS2
CLK
CS2
CLK
ADSC
WEx
OE
CS2
CLK
ADSC
WEx
OE
Microprocessor
256Kx18
SB
SRAM
256Kx18
SB
SRAM
Address
CLK
(Bank 1)
(Bank 0)
Cache
Controller
CS1
CS1
ADV ADSP
ADV ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
CLOCK
tSS
tSH
ADSP
tAS
tAH
A1
A2
ADDRESS
[0:n]
tWS
tWH
WRITE
CS1
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
ADV
OE
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tADVS
tADVH
tOE
tLZOE
tHZC
Data Out
(Bank 0)
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
Q2-2
Q2-3
Q2-4
Don¢t Care
*NOTES n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
Undefined
Dec. 1998
Rev. 2.0
- 15
KM718V887
256Kx18 Synchronous SRAM
PACKAGE DIMENSIONS
Units:millimeters/inches
100-TQFP-1420A
22.00 ±0.30
20.00 ±0.20
0~8°
0.127+ 0.10
- 0.05
16.00 ±0.30
0.10 MAX
14.00 ±0.20
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10
1.60 MAX
0.05 MIN
0.50 ±0.10
Dec. 1998
Rev. 2.0
- 16
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