KMM368L914BT-G0 [SAMSUNG]
DDR DRAM Module, 8MX64, 0.8ns, CMOS, DIMM-184;
| 型号： | KMM368L914BT-G0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 8MX64, 0.8ns, CMOS, DIMM-184 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总11页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
64MB DDR SDRAM MODULE
(8Mx64 based on 8Mx16 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.2
Aug. 1999
Rev. 0.2 Aug. 1999
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
Revision 0.1 (May. 1999)
1. Changed die revision from B-die to C-die
2. Changed DC/AC characteristics item from old version
Revision 0.2 (Aug. 1999)
1. Changed die revision from C-die to B-die
2. Modified binning policy
From
To
-Z (133Mhz)
-8 (125Mhz)
-0 (100Mhz)
-Z (133Mhz/266Mbps@CL=2)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz/200Mbps@CL=2)
3.Modified the following AC spec values
From.
-Z
To.
-0
-Z
-Y
-0
tAC
+/- 0.75ns
+/- 0.75ns
+/- 1ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
tDQSCK
tDQSQ
tDS/tDH
+/- 1ns
+/- 0.5ns
+/- 0.75ns
0.75 ns
0.5 ns
*1
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
1tCK
1tCK
1tCK
tCDLR
*1
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
tPRE
*1
tRPST
*1
tHZQ
*1
: Changed description method for the same functionality. This means no difference from the previous version.
4.Changed the following AC parameter symbol From tDQCK To tAC
Output data access time from CK/CK
Rev. 0.2 Aug. 1999
- 0 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
KMM368L914BT DDR SDRAM 184pin DIMM
8Mx64 DDR SDRAM 184pin DIMM based on 8Mx16
2. FEATURE
1. GENERAL DESCRIPTION
• Performance range
The Samsung KMM368L914BT is 8M bit x 64 Double Data
Rate SDRAM high density memory modules based on first gen
of 128Mb DDR SDRAM respectively.
Part No.
Max Freq.
Interface
•
•
•
•
•
•
133MHz(7.5ns@CL=2)
133MHz(7.5ns@CL=2.5)
100MHz(10ns@CL=2)
KMM368L914BT-G(F)Z
The Samsung KMM368L914BT consists of four CMOS 8M x
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 184pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The KMM368L914BT is Dual In-line Memory Modules and
intended for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
SSTL_2
•
•
•
•
•
•
•
•
•
•
KMM368L914BT-G(F)Y
KMM368L914BT-G(F)0
• Power supply
Vdd: 2.5V ± 0.2V
Power: G - normal, F - Low power
• MRS cycle with address key programs
CAS Latency (Access from column address):2,2.5
Burst length ;2, 4, 8
Data scramble ;Sequential & Interleave
• Serial presence detect with EEPROM
• PCB : Height 1450 (mil), double sided component
3. PIN CONFIGURATIONS (Front side/back side)
4. PIN DESCRIPTION
Pin Front Pin Front Pin Front Pin
Back
Pin
Back
Pin
Back
Pin Name
A0 ~ A11
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
1
2
3
VREF 32
DQ0 33 DQ24 63
VSS 34 VSS 64 DQ41 95
A5
62 VDDQ 93
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
*CB4
*CB5
VDDQ
*CK1
*/CK1
VSS
*DM8
A10
*CB6
VDDQ
*CB7
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0,CK0, CK2, CK2
CKE0
/WE 94
4
5
6
DQ1 35 DQ25 65 /CAS
DQS0 36 DQS3 66 VSS
DQ2 37 A4
96
97
Data Strobe input/output
Clock input
67 DQS5 98
Clock enable input
Chip select input
7
8
VDD 38 VDD 68 DQ42 99
DQ3 39 DQ26 69 DQ43 100
CS0
9
10
NC
NC
40 DQ27 70
41 A2 71
VDD 101
NC 102
NC
NC
RAS
Row address strobe
Column address strobe
Write enable
CAS
11 VSS 42 VSS 72 DQ48 103
12 DQ8 43 A1 73 DQ49 104
*A13
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
*A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
WE
13 DQ9 44 *CB0 74
14 DQS1 45 *CB1 75
15 VDDQ 46 VDD 76
VSS 105
/CK2 106
DM0 ~ DM7
VDD
Data - in mask
Power supply (2.5V)
Power Supply for DQs(2.5V)
Ground
CK2
107
VDDQ
16 CK0 47 *DQS8 77 VDDQ 108
17 /CK0 48 A0 78 DQS6 109
18 VSS 49 *CB2 79 DQ50 110
19 DQ10 50 VSS 80 DQ51 111
VSS
VREF
Power supply for reference
V33
Serial EEPROM Power
Supply (3.3V)
20 DQ11 51 *CB3 81
VSS 112
BA1 82 VDDID 113
KEY 83 DQ56 114
21 CKE0 52
22 VDDQ
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
KEY
SDA
SCL
Serial data I/O
Serial clock
23 DQ16 53 DQ32 84 DQ57 115
24 DQ17 54 VDDQ 85 VDD 116
25 DQS2 55 DQ33 86 DQS7 117
26 VSS 56 DQS4 87 DQ58 118
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
SA0 ~ 2
WP
Address in EEPROM
Write protection
VDD identification flag
Don’t use
27
28 DQ18 58 VSS 89
29 A7 59 BA0 90
A9
57 DQ34 88 DQ59 119
VSS 120
WP 121
SDA 122
SCL 123
DM4
VDDID
DU
DQ38
DQ39
VSS
SA1
SA2
V33
NC
No connection
30 VDDQ 60 DQ35 91
31 DQ19 61 DQ40 92
*
These pins are not used in this module.
DQ23
DQ44
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 Aug. 1999
- 1 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
5. Functional Block Diagram
CS0
DQS1
DM1
LDQS
LDM
CS
CS
LDQS
LDM
DQS5
DM5
DQ8
DQ9
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
D0
D2
DQ10
DQ11
DQ12
DQ13
DQ14
I/O 5
DQ15
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQS0
DM0
DQS4
DM4
DQ0
DQ1
DQ2
DQ32
DQ33
DQ34
DQ3
DQ4
DQ5
DQ6
DQ35
DQ36
DQ37
DQ38
DQ39
DQ7
CS
DQS3
DM3
LDQS
LDM
DQS7
DM7
CS
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D1
D3
I/O 7
DQS2
DM2
I/O 7
UDQS
UDM
UDQS
DQS6
DM6
UDM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
Clock Wiring
Clock
Input
SDRAMs
2 SDRAMs
NC
2 SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
*Clock Net Wiring
Dram1
BA0-BAN: DDR SDRAMs D0 - D3
A0-AN: DDR SDRAMs D0 - D3
BA0 - BAN
A0 - AN
Cap
Cap
R=60W
RAS
CAS
RAS: SDRAMs D0 - D3
Card
Edge
CAS: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
Cap
V
DDQ
D0 - D3
CKE0
0.1uF
0.1uF
0.1uF
Dram5
V
DD
D0 - D3
WE
WE: SDRAMs D0 - D3
0.1uF
VREF
D0 - D3
Serial PD
Cap
V
D0 - D3
SS
WP
V
SDA
DDID
Strap: see Note 2
A0
A1
A2
Notes:
SCL
1. DQ, DQS, DM/DQS resistors: 22 Ohms.
2. VDDID strap connections
47KW
SA0 SA1
SA2
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ¹ VDDQ.
Rev. 0.2 Aug. 1999
- 2 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
6. ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
-1.0 ~ 4.6
-0.5 ~ 3.6
-55 ~ +150
4
Unit
V
V
V
VDDQ
TSTG
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
7. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
Symbol
VDD
Min
2.3
Max
2.7
Unit
V
Note
VDDQ
VREF
2.3
2.7
V
I/O Reference voltage
1.15
1.35
V
1
2
I/O Termination voltage(system)
Input logic high voltage
V
VREF-0.04
VREF+0.18
-0.3
VREF+0.04
VDDQ+0.3
VREF-0.18
VDDQ+0.3
VDDQ+0.6
5
V
TT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
II
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input leakage current
-0.3
V
0.36
V
-5
uA
uA
mA
mA
3
Output leakage current
IOZ
-5
5
Output High Current (V
= 1.95V)
= 0.35V)
IOH
-15.2
15.2
OUT
Output Low Current (V
IOL
OUT
Note :
1. Typically, the value of VREF is expected to be about 0.5*VDDQ of the transmitting device.
VREF is expected to track variation in VDDQ.
2. Peak to peak AC noise on VREF may not exceed 2% VREF(DC).
3. Vtt of the transmitting device must track VREF of the receiving device.
Rev. 0.2 Aug. 1999
- 3 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
8. DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted,TA=0to70°C)
Version
-Y
CAS
Latency
Parameter
Operating Current
Symbol
Test Condition
Unit Note
-Z
-0
Burst=2 tRC=tRC(min), CL=2.5
IDD1
T.B.D T.B.D T.B.D mA 1
I
=0mA, Active-Read-Precharge
(One Bank Active)
OUT
Precharge Power-down Standby
Current
IDD2P
IDD2N
IDD3P
IDD3N
CKE£VIL(max), tCK=tCK(min), All banks idle
CKE³ VIH(min), CS³ VIH(min), tCK=tCK(min)
All banks idle,CKE£VIL(max),tCK=tCK(min)
T.B.D
T.B.D
T.B.D
mA
mA
mA
mA
Precharge Standby Current
in Non Power-down mode
Active Standby Current
in Power-down mode
One bank; Active-Precharge, tRC=tRAS(max),
tCK=tCK(min)
Active Standby Current
in Non Power-down mode
T.B.D
2.5
2
T.B.D T.B.D T.B.D
Burst=2, tCK=tCK(min),
=0mA
Operating Current(Read)
Operating Current(Write)
I
IDD4R
IDD4W
T.B.D T.B.D T.B.D mA
1
OUT
Burst=2, tCK=tCK(min)
2.5
2
T.B.D T.B.D T.B.D
T.B.D T.B.D T.B.D mA
1
2
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
mA
mA
T.B.D
T.B.D
tRC³ tRFC(min)
CKE£0.2V
Note : 1. Measured with outputs open.
2. Refresh period is 64ms
9. AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC) VREF + 0.35
VIL(AC)
V
V
V
V
VREF - 0.35
VDDQ+0.6
VID(AC) 0.7
1
2
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
Rev. 0.2 Aug. 1999
- 4 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
10. AC OPERATING TEST CONDITIONS (VDD=3.3V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate
Input Levels(VIH/VIL)
Value
Unit
V
Note
0.5 * VDDQ
1.5
V
1.0
VREF+0.35/VREF-0.35
VREF
V/ns
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
Vtt
V
See Load Circuit
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit (SSTL_2)
11. Input/Output CAPACITANCE (VDD=3.3V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,
WE )
CIN1
-
36
pF
Input capacitance(CKE0)
CIN2
CIN3
CIN4
-
-
-
-
-
36
34
34
9
pF
pF
pF
pF
pF
Input capacitance( CS0 )
Input capacitance( CLK0, CLK1)
Data & DQS input/output capacitance(DQ0~DQ63)
Input capacitance(DM0~DM8)
COUT
CIN5
9
Rev. 0.2 Aug. 1999
- 5 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
12. AC CHARACTERISTICS. (These AC charicteristics were tested on the Component)
- Z(PC266@CL=2)
- Y(PC266@CL=2.5) - 0(PC200@CL=2)
Parameter
Symbol
Unit Note
Min
65
75
45
20
20
15
2
Max
Min
65
75
48
20
20
15
2
Max
Min
70
80
48
20
20
15
2
Max
Row cycle time
tRC
ns
ns
Refresh row cycle time
Row active time
tRFC
tRAS
tRCD
tRP
12K
12K
12K
ns
RAS to CAS delay
ns
Row precharge time
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
ns
tCK
tCK
tCK
tCK
ns
Last data in to Read command
Last data in to Write command
Col. address to Col. address delay
tCDLR
tCDLW
tCCD
tCK
1
1
1
0
0
0
1
1
1
Clock cycle time
CL=2.0
CL=2.5
7.5
7
15
15
10
7.5
15
15
10
8
15
15
ns
Clock high level width
Clock low level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCL
0.45
-0.75
-0.75
-0.5
0.9
0.55
+0.75
+0.75
+0.5
1.1
0.45
-0.75
-0.75
-0.5
0.9
0.55
+0.75
+0.75
+0.5
1.1
0.45
-0.8
-0.8
-0.6
0.9
0.55
+0.8
+0.8
+0.6
1.1
tCK
ns
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
ns
tCK
tCK
Read Postamble
0.4
0.6
0.4
0.6
0.4
0.6
Data out high impedence time from CK/CK tHZQ
-0.75
0.75
0
+0.75
1.25
-0.75
0.75
0
+0.75
1.25
-0.8
0.75
0
+0.8
1.25
ns
tCK
ns
2
3
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
tDQSS
tWPRES
tWPREH
tDQSH
0.25
0.4
0.25
0.4
0.25
0.4
tCK
DQS-in high level width
0.6
0.6
0.6
0.6
1.1
tCK
DQS-in low level width
tDQSL
tDSC
tIS
0.4
0.9
1.1
1.1
15
0.6
1.1
0.4
0.9
1.1
1.1
15
0.6
1.1
0.4
0.9
1.2
1.2
16
tCK
tCK
ns
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tIH
ns
tMRD
tDS
ns
0.5
0.5
0.6
ns
tDH
ns
0.5
0.5
1.75
10
0.6
DQ & DM input pulse width
Power down exit time
tDIPW
tPDEX
tXSW
1.75
10
2
ns
ns
ns
10
Exit self refresh to write command
95
116
Rev. 0.2 Aug. 1999
- 6 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
PC266A
Min Max
PC266B
Min Max
PC200
Min Max
Parameter
Symbol
tXSA
Unit
Note
Exit self refresh to bank active command
Exit self refresh to read command
75
75
80
ns
Cycle
us
tXSR
tREF
tDV
200
15.6
0.35
0.25
35
200
15.6
0.35
0.25
35
200
15.6
0.35
0.25
35
Refresh interval time
128Mb
1
4
Output DQS valid window
DQS write postamble time
tCK
tCK
ns
tWPST
Auto precharge write recovery + Precharge time tDAL
.
1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
Rev. 0.2 Aug. 1999
- 7 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
13. SIMPLIFIED TRUTH TABLE
A11
A9 ~ A0
CKEn-1
CKEn
CS
RAS
CAS
WE
DM BA0,1
A10/AP
Note
COMMAND
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
L
X
X
OP CODE
OP CODE
1, 2
1, 2
3
H
L
L
L
H
X
X
X
X
Entry
3
Refresh
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
X
X
V
V
Row Address
Column
Address
(A0~A7)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
4
4
L
H
L
H
H
Column
Address
(A0~A7)
Write &
Column Address
L
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Active Power Down
X
X
H
L
Entry
H
Precharge Power Down Mode
X
H
L
Exit
L
H
H
H
X
X
V
X
DM
X
X
8
H
L
X
H
X
H
No Operation Command
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
Rev. 0.2 Aug. 1999
- 8 -
Preliminary
KMM368L914BT
184pin Unbuffered DDR SDRAM MODULE
14. PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.006
(133.350 ± 0.15)
0.089
(2.26)
5.077
(128.950)
1.45 ± 0.006
0.15)
(36.83
±
0.78
(19.80)
A
B
2.500
0.10 M
C
B
A
0.145 Max
(3.67 Max)
1.95
(49.53)
2.55
(64.77)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118
(3.00)
0.250
(6.350)
0.157
(4.00)
0.039 ± 0.002
(1.000 ± 0.050)
0.26
(6.62)
0.0787
(2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575
(4.00)
0.10
Detail A
M
C
A
B
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 8Mx16 SDRAM, TSOP.
SDRAM Part NO : KM416L8031BT
Rev. 0.2 Aug. 1999
- 9 -
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