KMM5321200C2W [SAMSUNG]
1Mx32 DRAM SIMM (1MX16 Base); 1Mx32 DRAM SIMM （ 1MX16基地）
| 型号： | KMM5321200C2W |
| 厂家： | 
SAMSUNG |
| 描述： | 1Mx32 DRAM SIMM (1MX16 Base) |
| 文件： | 总17页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRAM MODULE
KMM5321200C2W/C2WG
1Mx32 DRAM SIMM
(1MX16 Base)
Revision 0.0
November 1997
Rev. 0.0 (Nov. 1997)
- 1 -
DRAM MODULE
KMM5321200C2W/C2WG
Revision History
Version 0.0 (November 1997)
• Changed module PCB from 6-Layer to 4-Layer.
• Changed Module Part No. from KMM5321200CW/CWG to KMM5321200C2W/C2WG caused by PCB revision .
Rev. 0.0 (Nov. 1997)
- 2 -
DRAM MODULE
KMM5321200C2W/C2WG
KMM5321200C2W/C2WG with Fast Page Mode
1M x 32 DRAM SIMM using 1Mx16, 1K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM5321200C2W is a 1Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM5321200C2W consists of two CMOS 1Mx16bits DRAMs
in 42-pin SOJ packages mounted on a 72-pin glass-epoxy
substrate. A 0.1 or 0.22uF decoupling capacitor is mounted
on the printed circuit board for each DRAM. The
KMM5321200C2W is a Single In-line Memory Module with
edge connections and is intended for mounting into 72 pin
edge connector sockets.
• Part Identification
- KMM5321200C2W(1024 cycles/16ms Ref, SOJ, Solder)
- KMM5321200C2WG(1024 cycles/16ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDPin & pinout
PERFORMANCE RANGE
• PCB : Height(750mil), single sided component
Speed
tRAC
50ns
60ns
tCAC
15ns
15ns
tRC
-5
90ns
110ns
-6
PIN CONFIGURATIONS
PIN NAMES
Pin
Symbol
Pin
Symbol
Pin Name
A0 - A9
Function
Address Inputs
Data In/Out
1
2
3
4
5
6
7
8
VSS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
Res(A10)
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
NC
Vss
DQ0 - DQ31
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
W
NC
DQ8
DQ24
DQ9
Vss
Ground
NC
No Connection
Reserved Pin
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
Res
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
Res(A11)
Vcc
* Pin connection changing available
A8
A9
Res(RAS1)
RAS0
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
NC
Rev. 0.0 (Nov. 1997)
- 3 -
DRAM MODULE
KMM5321200C2W/C2WG
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ0
DQ1
RAS
RAS0
DQ2
DQ2
DQ3
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
LCAS
UCAS
CAS0
CAS1
U0
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
OE
W
A0-A9
DQ0
DQ1
DQ16
DQ17
RAS
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LCAS
UCAS
CAS2
CAS3
U1
OE
W
A0-A9
W
A0-A9
Vcc
Vss
.1 or .22uF Capacitor
for each DRAM
To all DRAMs
Rev. 0.0 (Nov. 1997)
- 4 -
DRAM MODULE
KMM5321200C2W/C2WG
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative to V SS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC
-1 to +7.0
-1 to +7.0
-55 to +150
2
V
V
°C
W
Tstg
Pd
Power Dissipation
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
4.5
0
2.4
5.5
0
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
5.0
0
-
V
V
V
V
*1
VCC+1
0.8
*2
-
-1.0
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC.
*2 : -2.0V/20ns, Pulse width is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
KMM5321200C2W/C2WG
Symbol
Speed
Unit
Min
Max
ICC1
-5
-6
300
280
mA
mA
-
-
ICC2
ICC3
Don¢t care
-
4
mA
-5
-6
-
-
300
280
mA
mA
ICC4
-5
-6
-
-
180
160
mA
mA
ICC5
ICC6
Don¢t care
-
2
mA
-5
-6
-
-
300
280
mA
mA
II(L)
IO(L)
-10
-5
10
5
uA
uA
Don¢t care
Don¢t care
VOH
VOL
2.4
-
-
V
V
0.4
ICC1 : Operating Current * (RAS, LCAS or UCAS, Address cycling @tRC=min)
ICC2 : Standby Current (RAS=LCAS=UCAS=W=VIH)
ICC3
ICC4
ICC5
ICC6
II(L)
: RAS Only Refresh Current * (LCAS=UCAS=VIH, RAS cycling @tRC=min)
: Fast Page Mode Current * ( RAS=VIL, LCAS or UCAS cycling : tPC=min)
: Standby Current (RAS=LCAS=UCAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0 £VIN£Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V £VOUT£Vcc)
: Output High Voltage Level (I OH = -5mA)
IO(L)
VOH
VOL : Output Low Voltage Level (I OL = 4.2mA)
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In I CC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one page mode cycle, tPC.
* NOTE :
Rev. 0.0 (Nov. 1997)
- 5 -
DRAM MODULE
KMM5321200C2W/C2WG
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A9]
Input capacitance[W]
CIN1
CIN2
CIN3
CIN4
CDQ
30
30
25
20
20
pF
pF
pF
pF
pF
-
-
-
-
-
Input capacitance[RAS0]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-31]
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
Access time from RAS
90
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
tRC
50
15
25
60
15
30
3,4
3,4,5
3,10
3
tRAC
tCAC
tAA
Access time from CAS
Access time from column address
CAS to output in Low-Z
0
0
0
0
tCLZ
tOFF
tT
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
13
50
15
50
6
3
3
2
30
50
13
50
13
20
15
5
40
60
15
60
15
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
37
10K
45
RAS to CAS delay time
4
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
10
0
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
10
25
0
10
30
0
0
0
8
8
0
0
10
10
13
13
0
10
10
15
15
0
tRWL
tCWL
tDS
9
9
Data-in hold time
10
10
tDH
Refresh period
16
30
16
35
tREF
tWCS
tCSR
tCHR
tRPC
tCPA
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS precharge to CAS hold time
Access time from CAS precharge
0
5
0
5
7
10
5
10
5
3
Rev. 0.0 (Nov. 1997)
- 6 -
DRAM MODULE
KMM5321200C2W/C2WG
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
35
10
50
10
10
Max
Min
40
10
60
10
10
Max
Fast page mode cycle time
ns
ns
ns
ns
ns
tPC
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
tCP
200K
200K
tRASP
tWRP
tWRH
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristic s only. If
tWCS³ tWCS(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
7.
2. VIH(min) and VIL(max) are reference levels for measuring
timing of input signals. Transition times are measured
between VIH(min) and VIL(max) and are assumed to be 5ns
for all inputs.
8.
9.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameter are referenced to the CAS leading edge in
early write cycles.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
4.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
10.
5.
6.
Assumes that tRCD³ tRCD(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V OH or
VOL.
Rev. 0.0 (Nov. 1997)
- 7 -
DRAM MODULE
KMM5321200C2W/C2WG
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tASR
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAL
tRAH
tASC
tRCS
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tAA
tOFF
tCAC
tCLZ
tRAC
VOH -
DQ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
Rev. 0.0 (Nov. 1997)
- 8 -
DRAM MODULE
KMM5321200C2W/C2WG
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCS
tWCH
tWP
VIH -
VIL -
W
tDS
tDH
DATA-IN
VIH -
VIL -
DQ
Don¢t care
Undefined
Rev. 0.0 (Nov. 1997)
- 9 -
DRAM MODULE
KMM5321200C2W/C2WG
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tPC
tCRP
tCP
tRCD
tCP
tRSH
tCAS
tCAS
VIH -
CAS
tCAS
VIL -
tRAD
tASC
¡ ó
tCSH
tASR
ROW
tASC
tCAH
tASC
tCAH
tRAH
tCAH
¡ ó
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
COLUMN
ADDRESS
A
ADDRESS
ADDR
tRRH
tRCS
tRCH
tCAC
tRCS
tRCS
tRCH
¡ ó
VIH -
VIL -
W
tCAC
tCAC
tAA
tOFF
tAA
tAA
tOFF
tOFF
tRAC
tCLZ
tCLZ
tCLZ
VOH -
VOL -
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
DQ
Don¢t care
Undefined
Rev. 0.0 (Nov. 1997)
- 10 -
DRAM MODULE
KMM5321200C2W/C2WG
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tPC
tPC
tCRP
tCP
tRCD
tCP
tRSH
tCAS
tCAS
VIH -
VIL -
tCAS
CAS
tRAD
tASC
tRAH
ROW
¡ ó
tCStHCAH
tASC
tCAH
tASC
tCAH
tASR
¡ ó
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
A
ADDRESS
ADDR
tWCS
tWCS
tWCH
tWP
tWCS
tWCH
¡ ó
tWCH
VIH -
VIL -
tWP
tWP
W
tCWL
tRWL
tDH
tCWL
tCWL
tDH
tDS
tDH
tDS
tDS
¡ ó
¡ ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don¢t care
Undefined
Rev. 0.0 (Nov. 1997)
- 11 -
DRAM MODULE
KMM5321200C2W/C2WG
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Don't care
DOUT = OPEN
tRC
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don't care
tRC
tRP
tRAS
tRP
VIH -
RAS
tRPC
tCP
VIL -
tRPC
VIH -
VIL -
tCSR
tWRP
CAS
W
tCHR
tWRH
VIH -
VIL -
tOFF
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
Rev. 0.0 (Nov. 1997)
- 12 -
DRAM MODULE
KMM5321200C2W/C2WG
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCAH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tRCS
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWRH
tWRP
tRRH
VIH -
VIL -
W
tAA
tCAC
tOFF
tCLZ
tRAC
VOH -
VOL -
DQ
OPEN
DATA-OUT
Don¢t care
Undefined
Rev. 0.0 (Nov. 1997)
- 13 -
DRAM MODULE
KMM5321200C2W/C2WG
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWRH
tWRP
tWCS
tDS
tWCH
VIH -
VIL -
W
tWP
tDH
VIH -
VIL -
DQ
DATA-IN
Don¢t care
Undefined
Rev. 0.0 (Nov. 1997)
- 14 -
DRAM MODULE
KMM5321200C2W/C2WG
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tRCH
tAA
tWRP
tWRH
tRCS
READ CYCLE
tCAC
VIH -
W
VIL -
tOFF
tCLZ
VOH -
DQ
DATA-OUT
VOL -
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
OPEN
VIL -
Don¢t care
Undefined
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
Rev. 0.0 (Nov. 1997)
- 15 -
DRAM MODULE
KMM5321200C2W/C2WG
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
tRPC
tCP
VIL -
tRPC
tCHS
VIH -
VIL -
tCSR
CAS
DQ
tOFF
VOH -
VOL -
OPEN
tWRP
tWRH
VIH -
VIL -
W
TEST MODE IN CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRAS
tRP
VIH -
RAS
VIL -
tRPC
tCP
tRPC
VIH -
tCSR
tWTS
tCHR
CAS
VIL -
tWTH
VIH -
W
VIL -
tOFF
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
Rev. 0.0 (Nov. 1997)
- 16 -
DRAM MODULE
KMM5321200C2W/C2WG
PACKAGE DIMENSIONS
Units : Inches (millimeters)
4.250(107.95)
3.984(101.19)
.125 DIA±.002(3.18±.051)
.133(3.38)
R.062(1.57)
.400(10.16)
.750(19.05)
.250(6.35)
.080(2.03)
.250(6.35)
R.062±.004(R1.57±.10)
.250(6.35)
3.750(95.25)
( Front view )
.125(3.17)
MIN
( Back view )
Gold & Solder Plating Lead
.200(5.08)
MAX
.100(2.54)
.010(.25)MAX
MIN
.050(1.27)
.041±.004(1.04±.10)
.054(1.37)
.047(1.19)
Tolerances : ±.005(.13) unless otherwise specified
NOTE : The used device is 1Mx16 DRAM
DRAM Part No. : KMM5321200C2W/C2WG -- KM416C1200CJ (400 mil)
Revision History
Rev 0.0 : Nov. 1997
Rev. 0.0 (Nov. 1997)
- 17 -
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SI9135_11
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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