KS0020_技术文档

KS0020

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

June. 1999.

Ver. 0.0

Prepared by:

Byung-Dae, Jeong

jeongb@samsung.co.kr

Contents in this document are subject to change without notice. No part of this document may be reproduced or

transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written

permission of LCD Driver IC Team.

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

KS0020 Specification Revision History

Content

Version

Date

May.1999

0.0

Original

2

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

CONTENTS

INTRODUCTION ..................................................................................................................................................4

FEATURES ..........................................................................................................................................................4

BLOCK DIAGRAM ...............................................................................................................................................5

PAD CONFIGURATION .......................................................................................................................................6

PAD Center Coordinates ....................................................................................................................................7

PIN DESCRIPTION ..............................................................................................................................................9

Power supply...............................................................................................................................................9

System control ............................................................................................................................................9

Microprocessor interface..........................................................................................................................11

FUNCTIONAL DESCRIPTION............................................................................................................................12

Microprocessor Interface..........................................................................................................................12

DISPLAY-DATA-RAM (DDRAM).................................................................................................................14

LCD Display Circuits .................................................................................................................................16

INSTRUCTION DESCRIPTION...........................................................................................................................22

SPECIFICATIONS..............................................................................................................................................29

Absolute Maximum Ratings......................................................................................................................29

DC Characteristics.....................................................................................................................................30

AC Characteristics.....................................................................................................................................32

REFERENCE APPLICATIONS...........................................................................................................................37

3

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

INTRODUCTION

The KS0020 is a high image quality mid-display-size-compatible RAM-integrated segment (column) driver that

boasts the low power consumption required by portable devices. It is used in a set with the KS0015 common

(low) drive and the KS0010 power supply IC. The KS0020 can be connected directly to the MPU bus. It stores

in its internal display RAM memory the 8-bit parallel display data send to it from the MPU and then issues the

LCD drive signals independent of the MPU. The chip has 160 LCD drive outputs and is equipped with 160 out x

240 line internal display RAM. Furthermore, because there is a one-to-one correspondence between picture

elements on the LCD display and internal RAM dots, displays can be created with a high degree of flexibility.

Because it is not necessary to supply an external clock when writing to the KS0020 internal RAM from the MPU

side, these operations can be performed with absolute minimum power consumption. Moreover, even when

multiple KS0020 chips are used, single chip select is supported; thus it is not necessary for the MPU to

distinguish between the multiple chips. The KS0020 has a slim from that is useful in creating thinner LCD

panels. It can operate using a low-voltage logic power supply system, and is thus suited to a broad range of

applications.

FEATURES

Driver Output Circuits

-

160 segment outputs

On-chip Display Data RAM

Capacity: 160 x 240 = 38,400 bits

-

Multi-chip Operation (Master, Slave) Available

Microprocessor Interface

-

8-bit parallel bi-directional interface with 6800-series or 8080-series

On-chip Oscillator Circuit

Operating Voltage Range

-

Supply voltage (VDD): 2.4 to 3.6 V

LCD driving voltage: 4.8 to 7.2 V

Low Power Consumption

-

TBD mA Max. (operation)

5 mA Max. (standby mode)

Wide Operating Temperature Range

Ta = -40°C to 85°C

Package Type

-

Gold bumped chip or TCP

4

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

BLOCK DIAGRAM

Status

CSB

RS

LR0

LR1

E_RD

Bus Holder

RW_WR

M

P

U

C68

MPU

Command

Decoder

RESETB

System

Control

Circuit

I

N

T

DB7

DB6

E

R

F

A

C

E

DB5

DB4

DB3

DB2

DB1

Column Address

Control Circuit

I/O Buffer

DB0

Page Address

Line Address

Control Circuit

Display data RAM

Control

240 X 160

Circuit

F1,F2

DOFFB

SLPB

FR

LCD

System

Control

Circuit

CL

CA

Decoder Circuit

SCK

MS

VSS

VDD

V3

V2

Liquid Crystal

Drive Circuit

VC

-V2

-V3

OSC1

OSC2

OSC3

Oscillator

Circuit

................

O1

................

O160

Figure 1. Block Diagram

5

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

PAD CONFIGURATION

217

114

ïïïïïïïïïïïïïïïïïïïï - - - - - - - - - - ïïïïïïïïïïïïïïïïï

113

218

255

Y

KS0020

(TOP VIEW)

(0,0)

X

76

ðððððððððððððððððð - - - - - - - ððððððððððððððððððððð

1

75

Figure 2. KS0020 Chip Configuration

Table 1. KS0020 Pad Dimensions

Size

Item

Pad No.

X

Unit

Y

Chip size

Pad pitch

-

8800

3400

1 to 75

90

80

76 to 255

1 to 75

60

100

60

100

60

mm

76 to 113

114 to 217

218 to 255

Bumped pad size

100

60

100

Bumped pad height

1 to 255

17 (Typ.)

6

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: mm]

No

Name

X

Y

No

Name

X

Y

No

Name

X

Y

1

DUMMY

-V3

-3330

-1590

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

COD4

1170

-1590

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

SEG24

4290

4120

4040

3960

3880

3800

3720

3640

3560

3480

3400

3320

3240

3160

3080

3000

2920

2840

2760

2680

2600

2520

2440

2360

2280

2200

2120

2040

1960

1880

1800

1720

1640

1560

1480

1400

1320

1240

446

526

606

686

766

846

926

2

3

4

5

6

7

8

9

-3240

-3150

-3060

-2970

-2880

-2790

-2700

-2610

-2520

-2430

-2340

-2250

-2160

-2070

-1980

-1890

-1800

-1710

-1620

-1530

-1440

-1350

-1260

-1170

-1080

-990

-900

-810

-720

-630

-540

-450

-360

-270

-180

-90

-1590

COD3

COD2

COD1

COD0

NC

VSS

NC

VSS

NC

VDD

1260

1350

1440

1530

1620

1710

1800

1890

1980

2070

2160

2250

2340

2430

2520

2610

2700

2790

2880

2970

3060

3150

3240

3330

4290

-1590

-1554

-1474

-1394

-1314

-1234

-1154

-1074

-994

SEG25

SEG26

SEG27

SEG28

DUMMY

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

-V2

VC

V2

V3

VSS

OSC1

OSC2

OSC3

VSS

NC

TEST1

VDD

CSB

RS

E_RD

RW_WR

RESETB

VSS

C68

VDD

LR0

VSS

LR1

VDD

MS

1006

1086

1166

1246

1326

1406

1590

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

VDD

V3

V2

VC

-V2

-V3

DUMMY

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

FR

-914

-834

-754

-674

-594

-514

-434

-354

-274

-194

-114

-34

46

126

206

286

0

90

180

270

360

450

540

630

720

810

900

990

CL

VSS

VDD

F1

F2

DOFFB

CA

SLPB

SCK

VSS

1080

366

7

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

Table 2. Pad Center Coordinates (Continued)

[Unit: mm]

No

Name

X

Y

No

Name

X

Y

No

Name

X

Y

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

SEG65

1160

1590

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

SEG115

SEG116

SEG117

SEG118

SEG119

SEG120

SEG121

SEG122

SEG123

SEG124

SEG125

SEG126

SEG127

SEG128

SEG129

SEG130

DUMMY

SEG131

SEG132

SEG133

SEG134

SEG135

SEG136

SEG137

SEG138

SEG139

SEG140

SEG141

SEG142

SEG143

SEG144

SEG145

SEG146

SEG147

SEG148

SEG149

SEG150

SEG151

SEG152

SEG153

SEG154

SEG155

-2840

1590

251

252

253

254

255

SEG156

SEG157

SEG158

SEG159

DUMMY

-4290

-1234

-1314

-1394

-1474

-1554

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

SEG77

SEG78

SEG79

SEG80

SEG81

SEG82

SEG83

SEG84

SEG85

SEG86

SEG87

SEG88

SEG89

SEG90

SEG91

SEG92

SEG93

SEG94

SEG95

SEG96

SEG97

SEG98

SEG99

SEG100

SEG101

SEG102

SEG103

SEG104

SEG105

SEG106

SEG107

SEG108

SEG109

SEG110

SEG111

SEG112

SEG113

SEG114

1080

1000

920

1590

-2920

-3000

-3080

-3160

-3240

-3320

-3400

-3480

-3560

-3640

-3720

-3800

-3880

-3960

-4040

-4120

-4290

1590

1406

1326

1246

1166

1086

1006

926

-4290

840

760

680

600

520

440

360

280

200

120

40

-40

-120

-200

-280

-360

-440

-520

-600

-680

-760

-840

-920

-1000

-1080

-1160

-1240

-1320

-1400

-1480

-1560

-1640

-1720

-1800

-1880

-1960

-2040

-2120

-2200

-2280

-2360

-2440

-2520

-2600

-2680

-2760

846

766

686

606

526

446

366

286

206

126

46

-34

-114

-194

-274

-354

-434

-514

-594

-674

-754

-834

-914

-994

-1074

-1154

8

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PIN DESCRIPTION

POWER SUPPLY

Table 3. Power Supply Pins Description

Description

Name

VDD

I/O

Supply Power supply

VSS

Supply Ground

-V3, -V2

VC, V2

V3

These are the liquid crystal drive multi-level power supplies.

The relationships between the various levels

Must be : -V3>-V2>VC>V2>V3 VSS

Supply

SYSTEM CONTROL

Table 4. System Control Pins Description

Description

Name

I/O

Master/slave operation selects pin

- MS = "H": Master operation

- MS = "L": Slave operation

The following table depends on the MS status.

MS

I

MS

H

CL

SCK

output

input

CA

F1, F2

output

input

FR

DOFFB

output

input

SLPB

Output

output

input

output

input

output

input

L

This is the field start signal. When using master/slave mode, this is connected to the

various CA terminals. This is also connected to the common driver YD terminals.

- MS = "H": Output

- MS = "L": Input

This is the display clock input/output terminal. When using master/slave mode, this is

connected to the various CL terminals. This is also connected to the common driver LP

CA

CL

I/O

terminals.

- MS = "H": Output

- MS = "L": Input

This is the memory scan clock input/output terminal. When using master/slave mode, this

is connected to the various SCK terminals.

- MS = "H": Output

- MS = "L": Input

This is the liquid crystal alternating current input/output terminal. When using

master/slave mode, this is connected to the various FR terminals. This is also connected

to the common driver FR terminals.

SCK

FR

I/O

- MS = "H": Output

- MS = "L": Input

9

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

This is the liquid crystal display blanking control terminal. When using master/slave

mode, this is connected to the various DOFFB terminals. This is also connected to the

common driver DOFFB terminals.

DOFFB

I/O

- MS = "H": Output

- MS = "L": Input

These are the drive pattern signal input/output terminals. When using master/slave mode,

these are connected to the F1 and F2 terminals respectively. These are connected to the

common driver F1 and F2 terminals.

- MS = "H": Output

- MS = "L": Input

F1, F2

SLPB

I/O

O

This is the sleep control terminal. When set to a sleep status by the MPU, both the

master and slave circuits enter the sleep mode. This terminal is not connected between

the master and the slave. Connect to the KS0010 SLPB terminal for the master only.

SEG0 ~

SEG159

Liquid crystal segment drive outputs

O

I

This is a terminal for the oscillator circuit. When an external input is used, it is input to this

terminal. Connect to “H” or “L” in case of slave operations.

OSC1

This is a terminal for the oscillator circuit. When the internal oscillator circuit is used,

connect to OSC1 through a capacitor. Make this terminal open in case of slave

operations.

OSC2

O

I

This is a terminal for the oscillator circuit. When the internal oscillator circuit is used,

connect to OSC2 through resistor. Make this terminal open in case of slave operations.

OSC3

When multiple KS0020 chips are used, these terminals specify the various segment

driver layout positions. Using this information, the KS0020 determines the relationships

between the various segments and the position in internal RAM.

LR0, LR1

COD0

COD1

COD2

COD3

COD4

These comprise the 5-bit output port. The status of this port can be controlled by

commands from the MPU. They can be used for controls of the electronic volume control

knobs and other applications.

O

10

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

MICROPROCESSOR INTERFACE

Table 5. Microprocessor Interface Pins Description

Description

Name

I/O

Reset input pin

When RESETB is “L”, initialization is executed.

RESETB

I

Microprocessor interface select input pin in parallel mode

- C68 = "H": 6800-series MPU interface

- C68 = "L": 8080-series MPU interface

C68

CSB

RS

I

This is the chip Select signal.

In the KS0020, even if multiple chips are used, the CSB is a shared line. When CSB is in

a non-active state, DB7 to DB0 enter a high-impedance state.

Register select input pin

- RS = "H": DB0 to DB7 are display data

- RS = "L": DB0 to DB7 are control data

When interface to a 6800-series MPU, Read/Write is enable.

RW_WR = “H”: read

RW_WR

E_RD

I

RW_WR = “L” : write

When interface to a 8080-series MPU, RW_WR is enable at low.

When interface to a 6800-series MPU: Active High.

This is used as an enable clock input pin of the 6800-series MPU.

I

When interface to a 8080-series MPU: Active Low.

This input connects the RD signal of the 8080-series MPU.

While this signal is low, KS0020 data bus output is enabled.

DB0

to

8-bit bi-directional data bus. It is connected to the standard 8-bit microprocessor data

bus.

I/O

DB7

When Chip select is not active, DB0 ~ DB7 will be high impedance.

11

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There is CSB terminal for chip selection. The KS0020 can interface with a microprocessor only when CSB is low.

When this pin is set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 ~ DB7 are to

be high impedance.

MPU (Parallel) Interface

The 8-bit bi-directional data bus is used in MPU interface and the type of MPU is selected by C68 as shown in

Table 6. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in Table 7.

Table 6. Microprocessor Interface

C68

H

CSB

RS

E_RD

E

RW_WR

RW

DB0 to DB7

MPU bus

6800-series

8080-series

L

RD

WR

Table 7. MPU Data Transfer

8080-series

Common

RS

6800-series

Description

E_RD

(E)

RW_WR

(RW)

E_RD

(RD)

RW_WR

(WR)

H

L

H

L

H

L

H

L

H

L

Display data write

Register status read

H

Writes to internal register(Instruction)

The KS0020 possesses a function that automatically identifies the segment driver position by the LR0 and LR1

terminals even when multiple KS0020 chips are used so form the perspective of the MPU, there is no need for the

MPU to identify the individual segment drivers. As a result, the CSB chip select terminals can share a common

line from the outside. The LR will be discussed below. When the chips are not selected, DB0 to DB7 enter a high

impedance state and terminals RS, E_RD and RW_WR inputs are disabled.

Accessing the Display Data RAM and the Internal Registers

The KS0020 uses a type of pipeline process between LSIs through the bus holders in the internal data bus in

order to match the operating frequencies between the MPU and the display data RAM and internal registers.

Consequently, when viewed from the MPU side, there are no constraints on accessing the KS0020 in terms of the

display data RAM access time (tACC), but rather the cycle time is dominant. When the cycle time is not adequate,

then the MPU may insert an NOP command, which is equivalent to executing a dummy wait.

12

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

· Writing

cyc

t

RW_WR

Command Write

Data Write

MCU

DATA

Bus Holder

Internal

Write Signal

Figure 3. MPU Interface for Writing

· Reading

RW_WR

E_RD

Command write

MCU

Data Read

DATA

Bus Holder

Read Signal

Internal

Figure 4. MPU Interface for Reading

13

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

Busy Flag

PRELIMINARY SPEC. VER. 0.0

KS0020

The busy flag indicates whether the KS0020 is operating or not. When DB7 is “H” in Read Status operation, this

device is in busy status and will accept only Read Status instruction. If the cycle time is correct, the

microprocessor needs not to check this flag before each instruction, which improves the MPU performance.

DISPLAY-DATA-RAM (DDRAM)

The display data RAM is RAM in which is stored the dot data for the display. It has a 160 x 240 bits structure. The

data can be selected by specifying the page address and the column address. The display data DB0 to DB7 from

the MPU corresponds to 8 dots in the common direction of the liquid crystal display, and thus when multiple

KS0020 chips are used, there are few constraints when the display data is sent, allowing the display to be

structured freely.

Page Address Circuit

Page direction address control is performed when the display RAM is accessed by the MPU. When the page

direction scan is designated by the scan direction select command, the page address will increment each time the

MPU makes the writing operation. While the internal RAM contains 240 lines worth of data, because the MPU

access processes in 8 dot units in the command direction, the number of pages is 240/8 = 30 pages.

Consequently, the count is locked when address value 29 is reached, and there is no increment beyond this level.

The count lock is cleared next time the page address is set. Moreover, the counter within the page address

control circuit is independent of the column address control circuit counter.

Line Address Circuit

Address control in the line direction is performed when contents of the display data RAM are read for the liquid

crystal display. When there is a read operation for the liquid crystal display, increment or decrement are

synchronized with the CL signal, and the count is reset when the display line that is set by a control command

from the MPU has been reached.

Column Address Circuit

Address control in the column direction is performed when the display RAM is accessed from the MPU. The

KS0020 unit has only 160 columns; however, using multiple chips the KS0020 can handle continuous column

addressing even when using four chips in the column direction (640 columns). Consequently, from the MPU

perspective, the MPU need not be aware of the multiple chips. The address value is increased or decreased

when a write operation is performed by the MPU. In the increment mode, the count is locked at 27f (639), while in

the decrement mode the count is locked at 000H(0). Increasing/decreasing will not proceed past that count. The

count lock is cleared the next time that a column address set is performed. Moreover, the counter within the

column address control circuit operates independently of the page address control circuit counter.

The I/O Buffer

The I/O buffer is a bi-directional buffer for cases where the MPU accesses the display data RAM via the KS0020

internal bus.

14

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

Line

Address

COM

Output

Page Address

Data

DB4 DB3 DB2 DB1 DB0

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

Page0

Page1

Page2

0 0

0

0 0

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

0 0

0

1

COM13

COM14

COM15

COM16

COM17

COM18

COM19

DB1

DB2

DB3

DB4

DB5

DB6

DB7

0

1 0

COM20

COM21

COM22

COM23

:

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

D8H

COM216

COM217

COM218

COM219

COM220

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

Page27

Page28

Page29

1

0

1

0

COM221

COM222

COM223

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

COM224

COM225

COM226

COM227

COM228

0

COM229

COM230

COM231

COM232

COM233

COM234

EAH

EBH

ECH

EDH

EEH

EFH

COM235

COM236

COM237

COM238

1 1

1

0

1

COM239

- - - - - - -

1

CAINC

0

2

157

159

158

Column

Address

CADEC

159

2

1

0

157

158

SEG1

SEG0

SEG2

SEG157 SEG158 SEG159

LCD OUTPUT

Figure 5. Display-Data-RAM Map

15

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

LCD DISPLAY CIRCUITS

Oscillator

The oscillator circuit generates the synch circuit for the liquid crystal drive. When the internal oscillator circuit of

the KS0020 is used, then a capacitor must be placed between OSC1 and OSC2, and a register must be placed

between OSC1 and OSC3, as shown in the figure below. Determine the C and R-values based on the oscillation

frequency formula given below.

OSC1

C

OSC2

R

KS0020

OSC3

(f = 1/2.2CR [HZ])

Figure 6. Oscillator Circuit

When the internal oscillator circuit is not used (i.e. when an external clock input is used instead), input the external

clock into OSC1. Leave OSC2 and OSC3 open.

MS

H

OSC1

OSC2

OSC3

Master operation

(using the internal

oscillation circuit)

Master operation

(using external signal

inputs)

Refer to Fig.6

indicated above

Input

terminal

H

L

Open

Connect

to

Slave operation

“H” or “L”

16

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

The Decoder

The decoder outputs the segment driver control signal that is required for the liquid crystal drive. This control

signal is determined by the display data, the drive pattern signals F1 and F2, and by the liquid crystal alternating

current signal FR.

The Liquid Crystal Drive Circuit

This outputs the liquid crystal drive voltage. The liquid crystal drive voltage can be of one of five values: -V3, -V2,

and VC, V2, V3. These values are selected by the drive control signal determined by the decoder.

The Internal Timing Generator Circuit

The internal timing generator circuit controls the internal write operations when the display data RAM is accessed

by the MPU. Moreover, in this case the internal timing generator circuit also controls the column address counter

and page address counter increment/decrement.

When a module is structured from multiple chips, the KS0020 automatically determines from LR0 and LR1 which

chip corresponds to which segment on the panel so that only the address relating to the corresponding segment

responds. Consequently, from the perspective of the MPU, there is no need to identify each individual KS0020

chip, but rather when accessing in the column direction, continues address can be handled in so far as the

address are in the same page. As a result, the CSB line can be shared. In this case, the relationship between the

actual segment output and the column address is as shown in the following figure.

KS0020

•

KS0020

Œ

KS0020

Ž

KS0020 ꢀ

Liquid Crystal Panel Segment-Direction Size:

640 Picture Elements

Multi-chip for MLS

Table 8. Column Address for Multiple Chips

LR1

LR0

“L”

“H”

“L”

“H”

Corresponding Picture Elements

to 160

Column Address (10-bit binary display)

KS0020 ¬

KS0020 •

KS0020 ®

KS0020 ¯

“L”

“H”

1

0000000000B to 0010011111B

0010100000B to 0100111111B

0101000000B to 0111011111B

0111100000B to 1001111111B

161 to 320

321 to 480

481 to 640

17

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

The Display Control Circuit

PRELIMINARY SPEC. VER. 0.0

KS0020

The display control circuit generates the timing signals CL, CA, FR, along with the drive pattern signals F1 and F2,

for the display based on the oscillator output from the oscillator circuit. Moreover, depending on the commands

from the MPU, this circuit generates the DOFFB display On/Off control signal and the SLPB sleep signals as well.

When multiple KS0020 chips are used, the input and output statuses of these signals are as given in Table9.

Table 9. I/O Statuses for Multiple Chips

Operating

Mode

CL

SCK

Output

Input

CA

F1, F2

Output

Input

FR

DOFFB

Output

Input

SLPB

Output

Master

Output

Input

Output

Input

Slave

The Relations between the Display Drive Output Voltage and the Display Data

Table 10 shows the relations between F1, F2 and the common drive voltage.

Table 10. Common Drive Voltage by F1, F2

FR

F1

F2

L

H

L

H

L

H

L

H

L

N Line

N + 1 Line

N + 2 Line

N + 3 Line

V1

-V1

V1

-V1

V1

-V1

V1

-V1

V1

-V1

V1

-V1

V1

-V1

V1

-V1

Note: The voltage relationships are as follows: V1 > VC > -V1 (where VC is the central voltage)

The values of F1 and F2 change for each horizontal interval (as described below) and for each CA set by the

commands. The changes are as shown below. Moreover, in this display the numbers are described as (F1, F2).

(1,1) ® (1,0) ® (0,1) ® (0,0) ® (0,0) ® (0,1) ® (1,0) ® (1,1)

¯

(1,0) ® (0,1) ® (0,0) ® (0,0) ® (0,1) ® (1,0) ® (1,1) ® (1,0)

¯

(0,1) ® (0,0) ® (0,0) ® (0,1) ® (1,0) ® (1,1) ® (1,0) ® (0,1)

¯

(0,0) ® (0,0) ® (0,1) ® (1,0) ® (1,1) ® (1,0) ® (0,1) ® (0,0)

Changes in the horizontal direction indicate changes that happen using commands set each horizontal internal.

The changes in the vertical direction, shown on the column on the left, show the value change that starts with

each CA. The relationships between the display data, the liquid crystal alternating current signal FR, and the

segment drive voltage are as shown in Table 11. These drive voltages change according to the combination of F1

and F2. In this table, “0” indicates “Off” and “1” indicates “On”.

18

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

Table 11. Segment Drive Voltage

FR = “H”

N

N +

1

N +

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Display

Picture

Element

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N +

3

1

2

3

4

V2 VC VC -V2 V3 V2 V2 VC VC V2 -V2 -V3 V2 VC VC -V2

V2 VC V3 V2 VC -V2 V2 VC VC -V2 V2 VC -V2 -V3 VC -V2

V2 VC VC -V2 VC -V2 -V2 -V3 V3 V2 V2 VC V2 VC VC -V2

V2 V3 VC V2 VC V2 -V2 VC VC V2 -V2 VC -V2 VC -V3 -V2

Drive

Voltage

FR = “L”

N

N +

1

N +

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Display

Picture

Element

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

N +

3

1

2

3

4

-V2 VC VC V2 -V3 -V2 -V2 VC VC -V2 V2 V3 -V2 VC VC V2

-V2 VC -V3 -V2 VC V2 -V2 VC VC V2 -V2 VC V2 V3 VC V2

-V2 VC VC V2 VC V2 V2 V3 -V3 -V2 -V2 VC -V2 VC VC V2

-V2 -V3 VC -V2 VC -V2 V2 VC VC -V2 V2 VC V2 VC V3 V2

Drive

Voltage

Notes: (1), (2), (3) and (4) correspond to the following drive pattern:

(1): (F2, F1) = (H, H)

(2): (F2, F1) = (H, L)

(3): (F2, F1) = (L, H)

(4): (F2, F1) = (L, L)

Timing Diagram

The timing diagram for the liquid crystal display is as shown in the following figure.

Example: The example shows the fields used in a 1/240 duty, where the liquid crystal drive pattern (F2, F1)

switches for each field.

19

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

60 61 62

120 121 122

181 182

180

240

1

2

CL

CA

F1, F2

Field

Output side

SEG

Figure 7. Timing Diagram

20

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

The figure below shows an example where the drive pattern (F2, F1) is different. The drive pattern is changed

width the falling edge of CL and the status is reflected to the driver output that changes at the next falling edge of

CL.

CL

CA

F2, F1 (Each Field)

F2, F1 (Every 16H)

F2, F1 (Every 8H)

F2, F1 (Every 4H)

The figure below shows the timing with which FR changes. FR changes on the falling edge of CL, and the

changes are reflected to the driver that changes on the next falling edge of CL (master mode). Moreover, in the

case of slave mode, the FR status is accepted with the falling edge of CL, and is reflected to the driver output that

changes on the next falling edge of CL.

CL

FR

S E G

21

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

INSTRUCTION DESCRIPTION

Table 12. Instruction Table

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Par.

Display ON (D0=1)

Display OFF (D0=0)

Inverse display (D0=1)

Normal display (D0=0)

DON / DOFF

0

1

0

1

0

1

0

1

0

1

D0

None

DISNOR /

DISINV

None

DTYSET

LINSET

PATSET

VOLCTL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Duty set

1 Byte

FR interval set

Drive pattern set

Output port control

SLPON /

SLPOFF

Sleep ON (D0=1)

Sleep OFF (D0=0)

0

1

0

1

0

1

0

1

0

D0

None

DVDSET

PASET

0

1

0

1

0

1

0

1

0

1

Divide offset

1 Byte

Page address set

Page direction

inverse (D0=1)

Page direction

normal (D0=0)

PDNOR /

PDINV

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D0

1

None

2 Byte

None

CASET

Column address set

Column address

decrement (D0=1)

Column address

increment (D0=0)

Column direction

Scan (D0=1)

CAINC /

D0

CADEC

PDIR / CDIR

0

1

0

1

0

1

0

1

D0

None

Page direction

Scan (D0=0)

MWRITE

CNTCLR

PCCLR

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Memory write

Counter clear

Data

None

1 Byte

None

1 Byte

Page address clear

Column address clear

Clock divide set

Return

CCCLR

CKSET

RETURN

VOLRD

STREAD

Output port set read

Status read

Scan address direction

inverse (D0=1)

SANOR /

SAINV

0

1

0

1

0

D0

None

Scan address direction

normal (D0=0)

22

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

The KS0020 identifies the data bus signals by a combination of RS, E_RD, and RW_WR. The command

interpretation and execution is performed based entirely on internal timing without relying on any external clock.

In the 8080 MPU interface, a low pulse is sent to the RW_WR terminal to launch the command when writing. In

the 6800 series MPU interface, a “L” input to the RW_WR terminal causes a write state, and then the commands

are launched when a high pulse input is sent to the E_RD terminal. Consequently, the 6800 series MPU interface

is different from the 8080 MPU interface in the command details and command tables, and in that the E_RD

terminal is “1” (“H”) when performing status reads and when reading display data. The commands will be

explained below using the 8080

MPU interface in the examples.

n

Display ON/OFF Command, Parameter : 0

This command forces the entire display ON or OFF. When the display is OFF, all outputs are fixed at VC.

Because the display is not possible when in sleep mode, make sure.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DON /

DOFF

Function

Display ON(D0=1)

Display OFF(D0=0)

0

1

0

1

0

1

0

1

D0

n

Page Address Set Command, Parameter : 1

This command and its following parameters makes it possible to set the page address corresponding to the

low address when accessing the display data RAM from the MPU side. Specifying the page address and the

column address can access the desired bit of the display data RAM. The page address are 5 bits,

corresponding to 30 page (pages 0 to 29). Even if the page address changes, there is no change to the

display status. This command is input into the registers and loaded in the counters. That which is input is

stored within the register, and can be reloaded by the PCCLR command.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

PASET

0

1

0

1

0

1

0

1

Page address set

Parameter

D4

D3

D2

D1

D0

n

Page Address Direction Command, Parameter : 0

This command makes it possible to reverse the position of page 0 in the page address of the display RAM

data. Consequently, it is possible to reverse the page address scan direction when the MPU uses the display

data in the page direction. The relationship between the physical position in internal RAM and the page

address is inverted (Normal: 0 à 29, Inverse: 29 à 0).

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Page direction

inverse (D0=1)

Page direction

normal (D0=0)

PDNOR /

PDINV

0

1

0

1

0

1

0

1

D0

23

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

n

Column Address set Command, Parameter : 2

This command and its following parameters make it possible to specify the column address when the MPU

access display data RAM in the column direction. Specifying the page address and the column address can

access the desired bit of display data RAM. The column address has 10 bits, and when four of the chips are

used in the column direction, up to 640 dots (pixels) is supported. Even when the address changes, the state

of the display does not change. There are 640 columns (columns 0 to 639). The address value is input with

the less significant address 5 bits first and then the more significant 5 bit. With the less significant alone,

when another command is entered, only the less significant is entered into the register, however, the counter

is not loaded. When the less significant is followed by the more significant, they are loaded into the counter

and the input is stored in the register. When the less significant address is followed by some other command,

the counter will not be loaded and the command will be cancelled. With this command, the set values can be

reloaded by the CCCLR command.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Column address

set

CASET

0

1

0

1

0

1

0

1

Parameter1

Parameter2

1

0

D4

D3

D2

D1

D0

Lower 5 bits

Upper 5 bits

n

Column Address Direction Command, Parameter : 0

This command specifies the behavior of the column address counter (increment vs. Decrement).

The addresses increment or decrement each time RAM access the display data. In the increment mode, the

count operation stops when the value reaches 27fH (639), or when the values 000H (0) in the decrement

mode.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Column address

decrement (D0=1)

Column address

increment (D0=0)

CAINC /

CADEC

0

1

0

1

0

1

0

1

D0

n

Scan Direction Select Command, Parameter : 0

When the MPU continuously access display memory, this determines whether the scanning will be done in

the page direction or in the column direction.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Column direction

scan (D0=1)

Page direction

scan (D0=0)

PDIR /

CDIR

0

1

0

1

0

1

0

1

D0

24

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

n

Display Data Write Command, Parameter : Number of Data to be Written

When the MPU writes data to the memory, this command places the chip in a data entry mode. By writing data

again this command, the display data RAM contents can be changed. The data write mode is cleared

automatically when another command is entered.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Memory write

Write data

MWRITE

0

1

0

1

0

1

0

Parameter

D7

D6

D5

D4

D3

D2

D1

D0

n

Status Read

This read operation makes it possible to monitor the internal operating status of the KS0020. No other

commands expect for the status read command will be accepted with a RAM busy status. If the cycle time is

followed, then there is no need to check for the RAM busy state under normal use.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

STREAD

D7: Busy/Ready

D6: Page Address Direction

Function

Status

0

1

O

Busy: 1, Ready: 0

Normal: 1, Inverted: 0

Column: 0, Page: 1

Off: 1, On: 0

D5: Column Address Direction

D4: Increment Direction

D3: Display ON/OFF

D2: SLEEP ON/OFF

D1: INVERT

Off: 1, On: 0

Normal Display: 1, Invert Display: 0

Normal: 1, Reserved: 0

D0: Reserved terminal

n

Display Normal/Inverted Command, Parameter:0

This command makes it possible to insert the ON/OFF status of each point on the display without having to

rewrite the contents of the display data RAM. Because all points in the display are either set to the normal

display or reverse, partial inversion are not supported.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Display

inverted (D0=1)

Display

DISNOR /

DISINV

0

1

0

1

0

1

0

1

D0

normal (D0=0)

25

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

n

Duty Set Command, Parameter : 1

This command combined with the following parameter sets the duty.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Duty set

DUTYSET

0

1

0

1

0

1

0

1

0

(Number of display

lines)/ 4/1

Parameter

1

0

D5

D4

D3

D2

D1

D0

Example

1/200 duty

Example

1/240 duty

1

0

1

0

1

0

1

n

Sleep Mode On/Off Command, Parameter:0

This command controls the sleep mode of the LCD module. Before launching this command, be sure that the

display OFF command has been entered and that the display is in an OFF state. Moreover, after issuing the

sleep OFF command, be sure to maintain the logic power supply for 40 ms to discharge the load of the power

supply IC.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SLPON

/SLPOFF

Function

Sleep ON(D0=1)

Sleep OFF(D0=0)

0

1

0

1

0

1

0

1

0

D0

n

Line Inverse Number Set Tab Command, Parameter:1

This command controls the number of lines inverted in the LCD module.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

LINSET

0

1

0

1

0

1

0

1

0

FR inverse set

value

Parameter

1

0

D3

D2

D1

D0

The default value is being set to 11H inverse. (D3 to D0 = 1010)

Pattern Set Command, Parameter:1

n

This command controls the MLS pattern-switching interval.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

PATSET

0

1

0

1

0

1

0

Drive pattern set

value

Parameter

D1

D0

The correspondence between the input data and the switching interval is as follows:

(The default value will be set to 8H)

8H

0

4H

1

0

16H Field

D0:

D1:

0

1

26

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

n

Output Port Control Command, Parameter:1

This command sets 5 bit data to control the LCD power supply.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

VOLCTL

0

1

0

1

0

1

0

Output port control

Drive pattern set

value

Parameter

D4

D3

D2

D1

D0

(D0 ~ D4: COD0 ~ COD4)

Partition DOFF Set Command, Parameter:1

n

This command controls the LCD module display on/off for each driver.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

DVDSET

0

1

0

1

0

1

0

1

0

Partition offset

Partition offset set

values

Parameter

D3

D2

D1

D0

D = “1”: Display ON D = “0”: Display OFF

(LR1, LR0): (0,0) à D0; (0,1) à D1; (1,0) à D2; (1,1) à D3

n

Initial Command, Parameter:0

These commands clear the contents of the page counter, the page register, the column counter, and the

column register to 0.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

CNTCLR

PCCLR

0

1

0

1

0

1

0

1

0

1

0

Counter clear

Page counter clear

Column counter

clear

CCCLR

0

1

0

1

0

1

CNTCLR: Resets the page counter and register to 0, and the column counter and register to 0.

PCCLR: Loads the register value to the page counter.

CCCLR: Loads the register value to the column counter.

n

Clock Divide Set Command, Parameter:1

This command sets the CL division ratio that severs as the basis for the timing signal for the liquid crystal

display.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

CKSET

0

1

0

1

0

1

Clock division set

value

Parameter

1

0

D1

D0

Correspondence of Divider Ratios

2

0

1

0

1

4

1

0

8

1

Data D1:

D0:

27

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

n

Return Command, Parameter:0

This command sets the scan direction counter to the set value and increments (+1) the counter in the fixed

direction.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RETURN

Function

0

1

0

1

0

1

0

Address return

n

Output Port Setting Read Command, Parameter:1

This command reads the output port set bit to the data bus. Perform a read operation after this command is

input. Only the master chip gives an output.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

VOLRD

0

1

0

1

0

1

0

1

0

Output port set read

Parameter

O

n

Scan address direction Command, Parameter:0

This command specifies the behavior of the scan address counter (inverse vs. normal).

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

Scan direction

inverse (D0=1)

Scan direction

normal (D0=0)

SANOR /

SAINV

0

1

0

1

0

D0

n

NOP (Non-operating) Command, Parameter:0

This command has no effect on operations.

Instruction RS E_RD RW_WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function

NOP

NOP1

NOP2

0

1

0

1

0

1

0

1

0

NOP

28

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Table 13. Absolute Maximum Ratings

Parameter

Symbol

VDD

Rating

-0.3 to +7.0

-0.3 to +8.0

-0.3 to VDD+0.3

-40 to +85

Unit

V

Supply voltage range

-V3

V

Input voltage range

Output voltage range

VIN

V

VOUT

TOPR

TSTR

V

Operating temperature range

Storage temperature range

°C

-55 to +150

Notes: 1. The voltage are all relative to VSS = 0V.

2. Voltages -V3 > -V2 > VC > V2 > V3 ³ VSS must always be satisfied.

3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.

It is desirable to use this LSI under electrical characteristic conditions during general operation.

Otherwise, this LSI may malfunction or reduced LSI reliability may result.

-V3

1. 5V

-V 2

1. 5V

V C

V D D

1. 5V

V 2

3. 0V

1. 5V

V 3

V S S

29

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

DC CHARACTERISTICS

Table 14. DC Characteristics

(Vss = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C)

Item

Symbol

Condition

Min.

2.4

Typ.

Max.

3.6

Unit Pin used

Operating voltage(1)

Operating voltage(2)

Operating voltage(3)

Operating voltage(4)

Operating voltage(5)

Operating voltage(6)

VDD

-V3

-V2

VC

V2

3.0

V

VDD

-V3

-V2

VC

V2

4.8

6.0

7.2

-V3 * 3/4

-V3 * 2/4

-V3 * 1/4

VDD = 2.4V to 3.6V

V

V3

Vss

VDD

V3

High

Input voltage

Low

VIH

VIL

0.7VDD

-

V

*1

*2

VSS

0.3VDD

VDD

High

VOH

VOL

IIL

IOH = -0.6mA

VDD-0.4

Output

voltage

Low

IOL = 0.6mA

VSS

Vss+0.4

+ 5.0

Input leakage current

-

*3

*4

VSS £ VIN £ VDD

VIN = VDD or VSS

mA

Output leakage current IOZ

LCD driver ON

+ 5.0

RON

V = 0.5V

-

0.6

1.0

5

kW SEGn

resistance

Static consumption

current (Sleep Mode)

ISSQ

I3Q

VIN = VDD or VSS

-

mA

VDD

-V3

Static consumption

current (Sleep Mode)

-V3 = 6V

5

MPU access *6

(Memory write,

OSC : OFF)

Dynamic consumption

current

ISSOP1

-

TBD

VDD

mA

Dynamic consumption

current

MPU no access *6

(OSC : ON)

ISSOP2

fOSC

-

TBD

-

Operating frequency

Ta = 25°C

33.6

kHz *5

30

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

[ * Remark Solves ]

*1 Input terminals: RS, RESETB, CSB, E_RD, RW_WR, MS, C68, OSC1, LR1, and LR0 .

Input / Output terminals (Input mode): DB[7:0], CL, FR, CA, DOFFB, F1, and F2.

*2 Input / Output terminals (output mode) : DB[7:0], CL, FR, CA, DOFFB, F1, and F2.

Output terminals: OSC2, OSC3, and SLPB.

*3 Input terminals: RS, RESETB, CSB, E_RD, RW_WR, MS, C68, OSC1, LR1, and LR0 .

*4 Input / Output terminals (Input mode): DB[7:0], CL, FR, CA, DOFFB, F1, and F2.

*5 Local oscillator circuit depending on CR.

*6 Frame frequency = 70 Hz, Duty = 1/240 and CR oscillator 33.6 kHz should be split into two-division

when used.

OSC3

OSC1

OSC2

C

R

31

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

AC CHARACTERISTICS

Read / Write Characteristics (8080-series MPU)

RS

AS80

AH80

t

CSB

CY80

t

CCH

t

PW80(R)

PW80(W)

t

,

t

E_RD,

RW_WR

DS80

DH80

t

DB0 to DB7

(Write)

ACC80

OD80

t

DB0 to DB7

(Read)

Figure 8. Read / Write Characteristics (8080-series MPU)

( VDD = 3.0 to 3.6V, Ta = -40 to +85°C)

Item

Signal

Symbol

Min.

Typ.

Max.

Unit.

Remark

Address setup time

Address hold time

Write cycle

tAS80

tAH80

5

1300

RS

-

ns

tCY80

Read cycle

300

( Status / Output port )

Control “H” pulse width

Pulse width(WR)

Pulse width(RD)

Data setup time

Data hold time

RW_WR

E_RD

tCCH

600

50

140

35

5

-

ns

tPW80(W)

tPW80(R)

tDS80

tDH80

tACC80

tOD80

-

ns

DB7

to

DB0

Read access time

Output disable time

-

30

140

90

CL = 100 pF

32

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

( VDD = 2.4 to 3.0V, Ta = -40 to +85°C)

Item

Signal

RS

Symbol

Min.

Typ.

Max.

Unit

Remark

Address setup time

Address hold time

Write cycle

tAS80

tAH80

5

1600

-

ns

tCY80

Read cycle

350

( Status / Output port )

Control “H” pulse width

Pulse width(WR)

Pulse width(RD)

Data setup time

Data hold time

RW_WR

E_RD

tCCH

900

70

160

50

5

-

ns

tPW80(W)

tPW80(R)

tDS80

tDH80

tACC80

tOD80

-

ns

DB7

to

DB0

Read access time

Output disable time

-

40

160

110

CL = 100 pF

· The timing for the input signal rising edge and the input signal falling edge (Tr, Tf) is specified at 15ns or less.

· All timing is specified based on 20% or 80% VDD-Vss.

· The “tPW80(W)” and “tPW80(R)” are being specified depending on the overlap period where the CSB is being on the

“L” level and the RW_WR, E_RD are being on the “L” level.

· These specifications guarantee writing into the RAM of the indicate data, output port reading and status reading

only.

33

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

PRELIMINARY SPEC. VER. 0.0

KS0020

Read / Write Characteristics (6800-series Microprocessor)

RS

RW_WR

tAS68

tAH68

CSB

tCY68

tCCL

tPW68(R), tPW68(W)

E_RD

tDS68

tDH68

DB0 to DB7

(Write)

tACC68

tOD68

DB0 to DB7

(Read)

Figure 9. Read / Write characteristics (6800-series Microprocessor)

( VDD = 3.0 to 3.6V, Ta = -40 to +85°C )

Item

Signal

Symbol

Min.

Typ.

Max.

Unit

Remark

Address setup time

Address hold time

RS

tAS68

5

-

ns

RW_WR tAH68

Write cycle

1300

ns

tCY68

Read cycle

( Status / Output port )

300

ns

E_RD

Control “L” pulse width

Pulse width(WR)

tCCL

600

50

-

ns

tPW68(W)

Pulse width(RD)

tPW68(R)

140

Data setup time

Data hold time

Access time

tDS68

tDH68

tACC68

tOD68

35

5

-

ns

DB7

to

DB0

140

90

CL = 100 pF

Output disable time

30

34

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

( VDD = 2.4 to 3.0V, Ta = -40 to +85°C )

Item

Signal

RS

RW_WR tAH68

Symbol

Min.

Typ.

Max.

Unit

Remark

Address setup time

Address hold time

tAS68

5

-

ns

Write cycle

1600

ns

tCY68

Read cycle

350

ns

( Status / Output port )

E_RD

Control “L” pulse width

Pulse width(WR)

tCCL

900

70

-

ns

tPW68(W)

Pulse width(RD)

tPW68(R)

160

Data setup time

Data hold time

Access time

tDS68

tDH68

tACC68

tOD68

50

5

-

ns

DB7

to

DB0

160

110

CL = 100 pF

Output disable time

40

· The timing for the input signal rising edge and the input signal falling edge (Tr, Tf) is specified at 15ns or less.

· All timing is specified based on 20% or 80% VDD-Vss.

· The “tPW68(W)” and “tPW68(R)” are being specified depending on the overlap period where the CSB is being on the

“L” level and the RW_WR, E_RD are being on the “L” level.

· These specifications guarantee writing into the RAM of the indicate data, output port reading and status reading

only.

35

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

Output Timing Characteristics

PRELIMINARY SPEC. VER. 0.0

KS0020

CL

thCL

tdCFR

FR

CA

tdCCA

tdCF

tdCO

F1, F2

On

Figure 10. Output Timing Characteristics

( VDD = 2.4 to 3.6V, Ta = -40 to +85°C )

Measurement

Unit

Signal

Symbol

Parameter

Min.

Typ.

Max.

Conditions

thCL

tdCFR

tdCCA

tdCF

CL

FR

CL pulse width

FR output delay

CA output delay

F1, F2 output delay

On output delay

100

10

-

1000

500

ns

CA

F1, F2

On

tdCO

36

KS0020

PRELIMINARY SPEC. VER. 0.0

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

REFERENCE APPLICATIONS

The use of the commands will be explaned based on actual examples of use.

Assuming 1/200 Duty (200-line Display)

SEG Driver : KS0020, COM Driver : KS0015, Power Supply : KS0010

MPU I/O

M

S

KS0020

SLPB

DOFFB

0,320

0,0

KS0010

24,0

24,320

Figure 11. Example of 200x320 Dot

Address (24, 320) is written with the page address first followed by the column address. The page is 24, and

because processing is performed in 1-byte units, 25x8 = 200 line displays.

37

160 SEG DRIVER & CONTROLLER FOR MLS STN LCD

Example of Connection

PRELIMINARY SPEC. VER. 0.0

KS0020

VSS

CIO1

SHL

SEL

CSEL

CA

DOFF

F2

120 x 160 DOT

1/120 DUTY

F1

YSCL

FR

TEST1

CIO2

160 OUT

KS0020

MPU

IF

VSS

VDD

-V3, -V2, VC, V2, V3

V1, VC, -V1

KS0020

KS0015

COD0

COD1

KS0010

Power Supply

External

Circuit

COD2

COD3

COD4

Figure 12. Example of Connection

38


型号：	KS0020
厂家：	SAMSUNG
描述：	Dot Matrix LCD Driver, CMOS 时钟驱动 CD 外围集成电路
文件：	总38页 (文件大小：360K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS0020 [SAMSUNG]

相关型号：

KS0031

KS0032

KS0035

KS0035-P

KS0035P

KS0035PCC

KS0040

KS0040TB-01-F00TF

KS0054C

KS0063

KS0063-G

KS0063-P