KS0073-Q_技术文档

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

INTRODUCTION

S6A0073 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It can

display 1, 2 or 4 lines with 5 ´ 8 or 6 ´ 8 dots format.

FUNCTIONS

·

Character type dot matrix LCD driver & controller

Internal driver : 34 common and 60 segment signal output

Easy interface with 4-bit or 8-bit MPU

Clock synchronized serial Interface

5 ´ 8 or 6 ´ 8 dots matrix possible

Extension driver interface possible

Bi-directional shift function

All character reverse display

Display shift per line

Voltage converter for LCD drive voltage : 13V max (2 times / 3 times)

Various instruction functions

Automatic power on reset

FEATURES

·

Internal Memory

- Character Generator ROM (CGROM) : 9,600 bits (240 characters ´ 5 ´ 8 dot)

- Character Generator RAM (CGRAM) : 64 ´ 8 bits (8 characters ´ 5 ´ 8 dot)

- Segment Icon RAM (SEGRAM) : 16 ´ 8 bits (96 icons max.)

- Display Data RAM (DDRAM) : 80 ´ 8 bits (80 characters max.)

Low power operation

·

- Power supply voltage range: 2.7 to 5.5V (V_DD

)

- LCD Drive voltage range: 3.0 to 13.0V (V_DD- V5)

·

CMOS process

Programmable duty cycle : 1/17, 1/33 (refer to Table 1)

Internal oscillator with an external resistor

Low power consumption

TCP or bare chip available

1

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Table 1. Programmable Duty Cycles

1) 5-dot Font Width

Display

Line

Single-chip Operation

With Extension Driver

Duty Ratio

Displayable

Possible

icons

60

Displayable

Possible icons

Numbers

1

characters

1/17

1/33

1 line of 24

characters

1 line of 52

characters

80

2

4

2 lines of 24

characters

60

2 lines of 32

characters

4 lines of 12

characters

4 lines of 20

characters

2) 6-dot Font Width

Display

Line

Single-chip Operation

With Extension Driver

Duty Ratio

Displayable

characters

Possible icons

Displayable

characters

Possible icons

Numbers

1

1/17

1/33

1 line of 20

characters

60

1 line of 50

characters

96

2

4

2 lines of 20

characters

2 lines of 30

characters

4 lines of 10

characters

4 lines of 20

characters

2

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

BLOCK DIAGRAM

IE OSC1 OSC2

EXT

Oscillator

Power on Reset

CLK1

CLK2

M

(POR)

Timing Generator

RESET

IM

7

RS/

CS

Instruction

Register

(IR)

8

Instruction

Decoder

System

Interface

Serial

E/

SCLK

COM0-

COM33

34-bit

Shift

Register

Common

Driver

Display Data

RAM (DDRAM)

80 x 8-bit

4-bit

8-bit

RW/SID

Address

Counter

7

D

8

Data

Register

(DR)

8

SEG1-

SEG60

60-bit

Shift

Register Circuit

60-bit

Latch

Segment

Driver

Input/

Output

Buffer

DB4-DB7

8

DB3-DB1

DB0-SOD

Busy Flag

LCD Driver

Voltage Selector

3

7

8

Character

Generator

RAM

(CGRAM)

64 bytes

Character

Generator

ROM

(CGROM)

9600 bits

Segment

Cursor &

Blink

Controller

V1 - V5

ICONRAM

(SEGRAM)

16 bytes

Vci

C1

C2

Voltage Converter

5

5/6

V5OUT2

V5OUT3

VDD

GND(VSS)

Parallel to Serial Converter and

Smooth Scroll Circuit

3

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

PAD CONFIGURATION

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53 10

SEG54 11

SEG55 12

SEG56 13

SEG57 14

SEG58 15

SEG59 16

SEG60 17

3

4

5

6

7

8

9

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

Y

COM9 18

COM10 19

COM11 20

COM12 21

COM13 22

COM14 23

COM15 24

COM16 25

COM25 26

COM26 27

COM27 28

COM28 29

COM29 30

COM30 31

COM31 32

COM32 33

COM33 34

VDD 35

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

V1

X

(0,0)

CHIP SIZE: 4870 x 5770

PAD SIZE: 100 x 100

UNIT: m m

OSC2 36

V2

4

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

PAD CENTER COORDINATES

PAD

NUM.

1

PAD

COORDINATE

PAD

NUM.

44

PAD

NAME

EXT

COORDINATE

PAD

NUM.

87

PAD

COORDINATE

NAME

X

Y

X

Y

NAME

X

Y

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

COM9

-1687

-1812

-2269

2719

2122

1997

1872

1747

1622

1497

1372

1247

1122

997

-986

-861

-736

-611

-486

-361

-2719

SEG2

2269

1813

1688

1563

1438

1313

1188

1063

938

497

2

45

IE

88

SEG3

622

3

46

VSS1

RS/CS

RW/SID

E/SCLK

89

SEG4

747

4

47

90

SEG5

872

5

48

91

SEG6

997

6

49

92

SEG7

1122

1247

1372

1497

1622

1747

1872

1997

2122

2719

7

50 DB0/SOD -236

93

SEG8

8

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

DB1

DB2

DB3

DB4

DB5

DB6

DB7

Vci

-111

14

94

SEG9

9

95

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

139

264

389

514

639

764

889

1014

1139

1264

96

97

98

872

99

747

-2719 100

-2719 101

-2719 102

-2719 103

-2719 104

-2719 105

-2719 106

-2719 107

-2719 108

-2719 109

-2116 110

-1991 111

-1866 112

-1741 113

-1616 114

-1491 115

-1366 116

-1241 117

-1116 118

622

497

C2

372

C1

134

VSS2

V5OUT2

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM25

COM26

COM27

COM28

COM29

COM30

COM31

9

-116

-241

-366

-491

-616

-741

-866

-991

-1116

-1241

-1366

-1491

-1616

V5OUR3 1389

V5

1514

1639

1764

2269

V4

V3

813

V2

688

V1

563

COM24

COM23

COM22

COM21

COM20

COM19

COM18

438

313

188

63

-62

-187

-312

5

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

PAD CENTER COORDINATES (Continued)

PAD

NUM.

33

PAD

NAME

COM32

COM33

VDD

COORDINATE

PAD

NUM.

76

PAD

NAME

COM17

COM8

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

SEG1

COORDINATE

PAD

NUM.

119

120

121

122

123

124

125

126

127

128

PAD

COORDINATE

X

Y

X

Y

NAME

X

Y

-2269

-1861

-1736

-1611

-1486

-1361

-1236

-1111

-1741

-1866

-1991

-2116

-2719

2269

-991

-866

-741

-616

-491

-366

-241

-116

9

SEG34

SEG35

SEG36

SEG37

SEG38

-437

-562

-687

-812

-937

2719

34

77

35

78

36

OSC2

OSC1

CLK1

CLK2

D

79

37

80

38

81

SEG39 -1062 2719

SEG40 -1187 2719

SEG41 -1312 2719

SEG42 -1437 2719

SEG43 -1562 2719

39

82

40

83

41

M

84

42

RESET

IM

85

134

372

43

86

6

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

PIN CONFIGURATION OF TCP

TCP OUTLINE

OUTPUT SIDE

S6A0073

7

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

...

......

...

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

S6A0073 PAD DIAGRAM

134-TCP-35mm

8

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

PIN DESCRIPTION

Pin (No)

I/O

Name

Description

for logical circuit (+3V, +5V)

0V (GND)

Interface

VDD(35)

VSS1, VSS2

(46, 61)

-

Power supply

Power Supply

V1-V5 (68 - 64)

Vci (58)

Bias voltage level for LCD driving

I

Input voltage to the voltage converter to

generate LCD drive voltage

(Vci = 1.0 to 4.5V).

SEG1 - SEG60

(86 -128, 1- 17)

O

Segment output

Common output

Segment signal output for LCD drive.

LCD

COM0 - COM33

(85 - 69, 18 - 34)

Common signal output for LCD drive

OSC1, OSC2

(37, 36)

I(OSC1), Oscillator

O(OSC2)

When using internal oscillator, connect

external Rf resistor.

If external clock is used, connect it to

OSC1.

External

resistor/oscilla

tor (OSC1)

CLK1, CLK2

(38, 39)

O

I

Latch (CLK1)/

When EXT = "High", each outputs latch

Extension

driver

Shift (CLK2) clock clock and shift clock for extension driver.

C1, C2

(60, 59)

External

capacitance input

To use the voltage converter (2 times /3

times), these pins must be connected to

the external capacitance.

External

capacitance

M (41)

O

Alternated signal

for LCD driver

output

When EXT = "High", outputs the

alternating signal to convert LCD driver

waveform to AC for Extension driver.

Extension

driver

D(40)

O

I

Display data

interface

When EXT = "High", outputs extension

driver data (the 61th dot's data)

Extension

driver

EXT(44)

Extension driver

control signal

When EXT = "High", makes extension

driver control signal enable, When EXT

= "Low", suppress extra current

consumption and CLK1,CLK2,M,D

should be open.

-

RESET (42)

IE (45)

I

Reset pin

Initialized to Low

-

Selection pin of

instruction set.

When IE = "High", instruction set is

selected as Table 6.

When IE = "Low", instruction set is

selected as Table 10.

9

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

PIN DESCRIPTION (continued)

Pin(No)

I/O

Name

Description

Interface

V5 /

V5OUT2 (62)

O

Two times

converter output

The value of Vci is converted two times.

To use three times converter, the same

capacitance as that of C1-C2 should be

connected here.

capacitance

V5OUT3 (63)

IM (43)

Three times

converter output

The value of Vci is converted three

times.

V5

-

I

Interface mode

selection

Select Interface mode with the MPU.

When IM = "Low" : serial mode,

When IM = "High" : 4-bit/8-bit bus mode.

RS/CS (47)

Register select

/Chip select

When bus mode, used as register

MPU

selection input. When RS/CS = "High",

Data register is selected. When RS/CS =

"Low", Instruction register is selected.

In serial mode, used as chip selection

input. When RS/CS = "Low", selected.

When RS/CS = "High", not selected.(Low

access enable)

RW/SID (48)

I

Read, write

In bus mode, used as read/write

MPU

/Serial input data selection input.

When RW/SID = "High", read operation

When RW/SID = "Low", write operation.

In serial mode, used for data input pin.

E/SCLK (49)

I

Read, write enable When bus mode, used as read, write

MPU

/Serial clock

enable signal.

When serial mode, used as serial clock

input pin.

DB0/SOD (50)

I/O, O

Data bus 0 bit

In 8-bit bus mode, used as lowest

/Serial output data bidirectional data bit. During 4-bit bus

mode, Open this pin.

In serial mode, used as serial data output

pin. If not in read operation, open this

pin.

DB1 - DB3

(51 - 53)

I/O

In 8-bit bus mode, used as low order

bidirectional data bus.

MPU

Data bus 1- 7

During 4-bit bus mode or serial mode,

open these pins.

DB4 - DB7

(54 - 57)

In 8-bit bus mode, used as high order

bidirectional data bus. In case of 4-bit

bus mode, used as both high and low

order.

DB7 used for Busy Flag output.

During serial mode, open these pins.

10

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

FUNCTION DESCRIPTION

System Interface

This chip has all three kinds of interface type with MPU : serial, 4-bit bus and 8-bit bus. Serial and bus(4-bit/8-bit)

are selected by IM input, and 4-bit bus and 8-bit bus are selected by DL bit in the instruction register. During read

or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR). The

data register(DR) is used as temporary data storage place for being written into or read from

DDRAM/CGRAM/SEGRAM, target RAM is selected by RAM address setting instruction. Each internal operation,

reading from or writing into RAM, is done automatically. Hence, after MPU reads DR data, the data in the next

DDRAM/CGRAM/SEGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the

data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically. The Instruction register(IR) is used only

to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use

RS/CS input pin in 4-bit/8-bit bus mode(IM = "High") or RS bit in serial mode(IM = "Low").

Table 2. Various Kinds of Operations according to RS and R/W Bits

RS

L

R/W

L

Operation

Instruction Write operation (MPU writes Instruction code into IR)

Read Busy flag(DB7) and address counter (DB0 – DB6)

Data Write operation (MPU writes data into DR)

Data Read operation (MPU reads data from DR)

L

H

L

H

Busy Flag (BF)

When BF = "High", it indicates that the internal operation is being processed. So during this time the next

instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),

through DB7. Before executing the next instruction, be sure that BF is not High.

Display Data RAM (DDRAM)

DDRAM stores display data of maximum 80 ´ 8 bits (80 characters). DDRAM address is set in the address

counter (AC) as a hexadecimal number. (refer to Figure 1.)

MSB

AC6

LSB

AC0

AC5

AC4

AC3

AC2

AC1

Figure 1. DDRAM Address

11

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

1) Display of 5-dot Font Width Character

(1) 5-dot 1-line Display

In case of 1 line display with 5-dot font, the address range of DDRAM is 00H - 4FH (refer to Figure 2). When EXT

= "High", extension driver will be used. Figure 3 shows the example that 40 segment extension driver is added

Display position

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

COM1

COM8

COM9

00 01 02 03 04 05 06 07 08 09 0A 0B

0C 0D 0E 0F 10 11 12 13 14 15 16 17

COM16

SEG1

1

S6A0073

SEG60

SEG1

S6A0073

SEG60

DDRAM Address

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

0D 0E 0F 10 11 12 13 14 15 16 17 18

COM1

COM8

COM9

01 02 03 04 05 06 07 08 09 0A 0B 0C

(After Shift Left)

10 11 12

4F 00 01 02 03 04 05 06 07 08 09 0A

(After Shift Right)

COM16

1

2

3

4

5

6

7

8

9

13 14 15 16 17 18 19 20 21 22 23 24

0B 0C 0D 0E 0F 10 11 12 13 14 15 16

COM1

COM8

COM9

COM16

Figure 2. 1-line

´ 24ch. Display (5-dot font width)

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

25 26 27 28 29 30 31 32

COM1

COM8

COM9

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17

18 19 1A 1B 1C 1D 1E 1F

COM16

SEG1

S6A0073

SEG60

SEG1

S6A0073

SEG60

SEG1

SEG40

Extension Driver (40SEG)

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

25 26 27 28 29 30 31 32

COM1

COM8

COM9

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18

(After Shift Left)

19 1A 1B 1C 1D 1E 1F 20

COM16

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

25 26 27 28 29 30 31 32

COM1

COM8

COM9

4F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16

(After Shift Right)

17 18 19 1A 1B 1C 1D 1E

COM16

Figure 3. 1-line

´ 32ch. Display with 40 SEG. extension driver (5-dot font width)

12

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

(2) 5-dot 2-line Display

In case of 2 line display with 5-dot font, the address range of DDRAM is 00H - 27H,40H - 67H (refer to Figure 4).

When EXT = "High", extension driver will be used. Figure 5 shows the example that 40 segment extension driver

is added.

Display position

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

0C 0D 0E 0F 10 11 12 13 14 15 16 17

DDRAM Address

COM1

COM8

COM9

00 01 02 03 04 05 06 07 08 09 0A 0B

COM16

COM17

COM24

COM25

COM32

40 41 42 43 44 45 46 47 48 49 4A 4B

4C 4D 4E 4F 50 51 52 53 54 55 56 57

SEG1

1

S6A0073

SEG60

SEG1

S6A0073

SEG60

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

0D 0E 0F 10 11 12 13 14 15 16 17 18

COM1

COM8

COM9

01 02 03 04 05 06 07 08 09 0A 0B 0C

COM16

COM17

COM24

COM25

COM32

41 42 43 44 45 46 47 48 49 4A 4B 4C

4D 4E 4F 50 51 52 53 54 55 56 57 58

(After Shift Left)

10 11 12

1

2

3

4

5

6

7

8

9

13 14 15 16 17 18 19 20 21 22 23 24

0B 0C 0D 0E 0F 10 11 12 13 14 15 16

COM1

COM8

COM9

27 00 01 02 03 04 05 06 07 08 09 0A

COM16

COM17

COM24

COM25

COM32

67 40 41 42 43 44 45 46 47 48 49 4A

4B 4C 4D 4E 4F 50 51 52 53 54 55 56

(After Shift Right)

Figure 4. 2-line

´ 24ch. Display (5-dot Font Width)

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

0C 0D 0E 0F 10 11 12 13 14 15 16 17

25 26 27 28 29 30 31 32

COM1

COM9

00 01 02 03 04 05 06 07 08 09 0A 0B

18 19 1A 1B 1C 1D 1E 1F

COM8

COM17

COM24

COM16

COM25

COM32

40 41 42 43 44 45 46 47 48 49 4A 4B

4C 4D 4E 4F 50 51 52 53 54 55 56 57

58 59 5A 5B 5C 5D 5E 5F

SEG1

S6A0073

SEG60 SEG1

S6A0073

SEG60 SEG1

SEG40

Extension Driver (40SEG)

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

0D 0E 0F 10 11 12 13 14 15 16 17 18

25 26 27 28 29 30 31 32

19 1A 1B 1C 1D 1E 1F 20

COM1

COM8

COM9

01 02 03 04 05 06 07 08 09 0A 0B 0C

41 42 43 44 45 46 47 48 49 4A 4B 4C

COM16

COM25

COM32

COM17

COM24

4D 4E 4F 50 51 52 53 54 55 56 57 58

59 5A 5B 5C 5D 5E 5F 60

(After Shift Left)

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20 21 22 23 24

25 26 27 28 29 30 31 32

17 18 19 1A 1B 1C 1D 1E

COM1

COM8

COM9

4F 00 01 02 03 04 05 06 07 08 09 0A

67 40 41 42 43 44 45 46 47 48 49 4A

0B 0C 0D 0E 0F 10 11 12 13 14 15 16

COM16

COM25

COM32

COM17

COM24

4B 4C 4D 4E 4F 50 51 52 53 54 55 56

(After Shift Right)

57 58 59 5A 5B 5C 5D 5E

Figure 5. 2-line

´ 32ch. Display with 40 SEG. Extension Driver (5-dot Font Width)

13

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(3) 5-dot 4-line Display

In case of 4 line display with 5-dot font, the address range of DDARM is 00H - 13H, 20H - 33H, 40H - 53H, 60H -

73H (refer to Figure 6). When EXT = "High", extension driver will be used. Figure 7 shows the example that 40

segment extension driver is added.

1

2

3

4

5

6

7

8

9

10 11 12

Display position

COM1

00 01 02 03 04 05 06 07 08 09 0A 0B

20 21 22 23 24 25 26 27 28 29 2A 2B

40 41 42 43 44 45 46 47 48 49 4A 4B

60 61 62 63 64 65 66 67 68 69 6A 6B

DDRAM Address

COM8

COM9

COM16

COM17

COM24

COM25

COM32

SEG1

1

S6A0073

SEG60

2

3

4

5

6

7

8

9

10 11 12

COM1

01 02 03 04 05 06 07 08 09 0A 0B 0C

21 22 23 24 25 26 27 28 29 2A 2B 2C

41 42 43 44 45 46 47 48 49 4A 4B 4C

COM8

COM9

COM16

COM17

COM24

COM25

61 62 63 64 65 66 67 68 69 6A 6B 6C

(After Shift Left)

COM32

1

2

3

4

5

6

7

8

9

10 11 12

COM1

13 00 01 02 03 04 05 06 07 08 09 0A

33 20 21 22 23 24 25 26 27 28 29 2A

53 40 41 42 43 44 45 46 47 48 49 4A

COM8

COM9

COM16

COM17

COM24

COM25

73 60 61 62 63 64 65 66 67 68 69 6A

(After Shift Right)

COM32

Figure 6. 4-line

´ 12ch. Display (5-dot Font Width)

14

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20

0C 0D 0E 0F 10 11 12 13

Display position

DDRAM Address

COM1

00 01 02 03 04 05 06 07 08 09 0A 0B

20 21 22 23 24 25 26 27 28 29 2A 2B

40 41 42 43 44 45 46 47 48 49 4A 4B

60 61 62 63 64 65 66 67 68 69 6A 6B

COM8

COM9

2C 2D 2E 2F 30 31 32 33

4C 4D 4E 4F 50 51 52 53

6C 6D 6E 6F 70 71 72 73

COM16

COM17

COM24

COM25

COM32

SEG1

1

S6A0073

SEG60 SEG1

10 11 12

SEG40

Extension Driver (40SEG)

2

3

4

5

6

7

8

9

13 14 15 16 17 18 19 20

0D 0E 0F 10 11 12 13 00

COM1

01 02 03 04 05 06 07 08 09 0A 0B 0C

21 22 23 24 25 26 27 28 29 2A 2B 2C

41 42 43 44 45 46 47 48 49 4A 4B 4C

COM8

COM9

2D 2E 2F 30 31 32 33 20

4D 4E 4F 50 51 52 53 40

6D 6E 6F 70 71 72 73 60

COM16

COM17

COM24

COM25

61 62 63 64 65 66 67 68 69 6A 6B 6C

(After Shift Left)

COM32

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16 17 18 19 20

0B 0C 0D 0E 0F 10 11 12

COM1

13 00 01 02 03 04 05 06 07 08 09 0A

33 20 21 22 23 24 25 26 27 28 29 2A

53 40 41 42 43 44 45 46 47 48 49 4A

COM8

COM9

2B 2C 2D 2E 2F 30 31 32

4B 4C 4D 4E 4F 50 51 52

6B 6C 6D 6E 6F 70 71 72

COM16

COM17

COM24

COM25

73 60 61 62 63 64 65 66 67 68 69 6A

(After Shift Right)

COM32

Figure 7. 4-line

´ 20ch. Display with 40 SEG. Extension Driver (5-dot Font Width)

15

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

2) Display of 6-dot Font Width Character

(1) 6-dot 1-line Display

In case of 1 line display with 6-dot font, the address range of DDRAM is 00H - 4FH (refer to Figure 8). When EXT

= "High", extension driver will be used. Figure 9 shows the example that 40 segment extension driver is added.

Display position

1

2

3

4

5

6

7

8

9

10

00 01 02 03 04 05 06 07 08 09

SEG1 S6A0073 SEG60

11 12 13 14 15 16 17 18 19 20

COM1

COM8

COM9

0A 0B 0C 0D 0E 0F 10 11 12 13

COM16

SEG1

S6A0073

SEG60

DDRAM Address

COM9

COM1

COM8

01 02 03 04 05 06 07 08 09 0A

(After Shift Left)

4F 00 01 02 03 04 05 06 07 08

(After Shift Right)

0B 0C 0D 0E 0F 10 11 12 13 14

COM16

COM1

COM8

COM9

09 0A 0B 0C 0D 0E 0F 10 11 12

COM16

Figure 8. 1-line

´ 20ch. Display (6-dot Font Width)

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

0A 0B 0C 0D 0E 0F 10 11 12 13

21 22 23 24 25 26

COM1

COM8

COM9

00 01 02 03 04 05 06 07 08 09

14 15 16 17 18 19

COM16

SEG1

1

S6A0073

SEG60 SEG1

S6A0073

SEG60 SEG1

SEG36

Extension Driver (40SEG)

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

0B 0C 0D 0E 0F 10 11 12 13 14

(After Shift Left)

21 22 23 24 25 26

15 16 17 18 19 1A

COM9

COM1

COM8

01 02 03 04 05 06 07 08 09 0A

COM16

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

09 0A 0B 0C 0D 0E 0F 10 11 12

21 22 23 24 25 26

13 14 15 16 17 18

COM9

COM1

COM8

4F 00 01 02 03 04 05 06 07 08

COM16

(After Shift Right)

Figure 9. 1-line

´ 26ch. Display with 40 SEG. Extension Driver (6-dot Font Width)

16

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

(2) 6-dot 2-line Display

In case of 2 line display with 6-dot font, the address range of DDRAM is 00H - 27H, 40H - 67H. (refer to Figure

10) When EXT = "High", extension driver will be used. Figure 11 shows the example that 40 segment extension

driver is added.

Display position

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

COM1

COM9

00 01 02 03 04 05 06 07 08 09

40 41 42 43 44 45 46 47 48 49

0A 0B 0C 0D 0E 0F 10 11 12 13

COM8

COM17

COM16

COM25

4A 4B 4C 4D 4E 4F 50 51 52 53

COM24

COM32

SEG1

1

S6A0073

SEG60

10

SEG1

S6A0073

SEG60

DDRAM Address

2

3

4

5

6

7

8

9

11 12 13 14 15 16 17 18 19 20

0B 0C 0D 0E 0F 10 11 12 13 14

COM1

COM9

01 02 03 04 05 06 07 08 09 0A

41 42 43 44 45 46 47 48 49 4A

COM8

COM17

COM16

COM25

4B 4C 4D 4E 4F 50 51 52 53 54

COM24

COM32

(After Shift Left)

10

1

2

3

4

5

6

7

8

9

11 12 13 14 15 16 17 18 19 20

09 0A 0B 0C 0D 0E 0F 10 11 12

COM9

COM1

27 00 01 02 03 04 05 06 07 08

67 40 41 42 43 44 45 46 47 48

COM16

COM25

COM8

COM17

49 4A 4B 4C 4D 4E 4F 50 51 52

COM32

COM24

(After Shift Right)

Figure 10. 2-line

´ 20ch. Display (6-dot Font Width)

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

0A 0B 0C 0D 0E 0F 10 11 12 13

21 22 23 24 25 26

COM1

COM9

00 01 02 03 04 05 06 07 08 09

40 41 42 43 44 45 46 47 48 49

14 15 16 17 18 19

54 55 56 57 58 59

COM8

COM17

COM16

COM25

4A 4B 4C 4D 4E 4F 50 51 52 53

COM24

COM32

SEG1

S6A0073

SEG60 SEG1

S6A0073

SEG60 SEG1

SEG36

Extension Driver (40SEG)

21 22 23 24 25 26

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

0B 0C 0D 0E 0F 10 11 12 13 14

COM1

COM9

01 02 03 04 05 06 07 08 09 0A

41 42 43 44 45 46 47 48 49 4A

15 16 17 18 19 1A

55 56 57 58 59 5A

COM8

COM17

COM16

COM25

4B 4C 4D 4E 4F 50 51 52 53 54

(After Shift Left)

COM24

COM32

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16 17 18 19 20

09 0A 0B 0C 0D 0E 0F 10 11 12

21 22 23 24 25 26

13 14 15 16 17 18

COM1

COM9

27 00 01 02 03 04 05 06 07 08

67 40 41 42 43 44 45 46 47 48

COM8

COM17

COM16

COM25

49 4A 4B 4C 4D 4E 4F 50 51 52

(After Shift Right)

53 54 55 56 57 58

COM24

COM32

Figure 11. 2-line

´ 26ch. Display with 40 SEG. Extension Driver (6-dot Font Width)

17

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(3) 6-dot 4-line Display

In case of 4 line display with 6-dot font, the address range of DDARM is 00H-13H, 20H-33H, 40H-53H, 60H-73H

(refer to Figure 12). When EXT = "High", extension driver will be used. Figure 13 shows the example that 40

segment extension driver is added.

1

2

3

4

5

6

7

8

9

10

Display position

COM1

00 01 02 03 04 05 06 07 08 09

20 21 22 23 24 25 26 27 28 29

40 41 42 43 44 45 46 47 48 49

60 61 62 63 64 65 66 67 68 69

DDRAM Address

COM8

COM9

COM16

COM17

COM24

COM25

COM32

COM1

SEG1

1

S6A0073

SEG60

9 10

2

3

4

5

6

7

8

01 02 03 04 05 06 07 08 09 0A

21 22 23 24 25 26 27 28 29 2A

41 42 43 44 45 46 47 48 49 4A

COM8

COM9

COM16

COM17

COM24

COM25

61 62 63 64 65 66 67 68 69 6A

(After Shift Left)

COM32

1

2

3

4

5

6

7

8

9

10

COM1

13 00 01 02 03 04 05 06 07 08

33 20 21 22 23 24 25 26 27 28

53 40 41 42 43 44 45 46 47 48

COM8

COM9

COM16

COM17

COM24

COM25

73 60 61 62 63 64 65 66 67 68

(After Shift Right)

COM32

Figure 12. 4-line

´ 10 ch. Display (6-dot Font Width)

18

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16

0A 0B 0C 0D 0E 0F

Display position

DDRAM Address

COM1

00 01 02 03 04 05 06 07 08 09

20 21 22 23 24 25 26 27 28 29

40 41 42 43 44 45 46 47 48 49

60 61 62 63 64 65 66 67 68 69

COM8

COM9

2A 2B 2C 2D 2E 2F

4A 4B 4C 4D 4E 4F

6A 6B 6C 6D 6E 6F

COM16

COM17

COM24

COM25

COM32

SEG1

S6A0073

SEG60

SEG1

SEG36

Extension Driver (40SEG)

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16

0B 0C 0D 0E 0F 10

COM1

COM8

01 02 03 04 05 06 07 08 09 0A

21 22 23 24 25 26 27 28 29 2A

41 42 43 44 45 46 47 48 49 4A

2B 2C 2D 2E 2F 30

4B 4C 4D 4E 4F 50

6B 6C 6D 6E 6F 70

COM16

COM17

COM24

COM25

61 62 63 64 65 66 67 68 69 6A

(After Shift Left)

COM32

1

2

3

4

5

6

7

8

9

10

11 12 13 14 15 16

09 0A 0B 0C 0D 0E

COM1

13 00 01 02 03 04 05 06 07 08

33 20 21 22 23 24 25 26 27 28

53 40 41 42 43 44 45 46 47 48

COM8

COM9

29 2A 2B 2C 2D 2E

49 4A 4B 4C 4D 4E

69 6A 6B 6C 6D 6E

COM16

COM17

COM24

COM25

73 60 61 62 63 64 65 66 67 68

(After Shift Right)

COM32

Figure 13. 4-line

´ 16ch. Display with 40 SEG. Driver (6-dot Font Width)

19

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Timing Generation Circuit

Timing generation circuit generates clock signals for the internal operations.

Address Counter (AC)

Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR. After writing into (reading

from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W =

"High", AC can be read through DB0-DB6 ports.

Cursor/Blink Control Circuit

It controls cursor/blink ON/OFF and black/white inversion at cursor position.

LCD Driver Circuit

LCD Driver circuit has 34 common and 60 segment signals for LCD driving. Data from

SEGRAM/CGRAM/CGROM is transferred to 60-bit segment latch serially, which is then stored to a 60-bit shift

latch. When each com is selected by 34-bit common register, segment data also output through segment driver

from 100-bit segment latch. In case of 1-line display mode, COM0 - COM17 have a 1/17 duty ratio, and in 2-line

or 4-line mode, COM0-COM33 have a 1/33 duty ratio.

20

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

CGROM (Character Generator ROM)

CGROM has 5 ´ 8-dot 240 character pattern.

CGRAM (Character Generator RAM)

CGRAM has up to 5 ´ 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used

(refer to Table 4).

Table 4. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)

1) 5 ´ 8 dots Character Pattern

Character Code (DDRAM data)

CGRAM Address

CGRAM Data

Pattern

Number

D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Pattern 1

.

0

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

x

1

0

1

0

1

0

1

0

1

0

Pattern 8

.

21

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

2) 6 ´ 8 dots Character Pattern

Character Code (DDRAM data)

CGRAM Address

CGRAM Data

Pattern

Number

D7 D6 D5 D4 D3 D2 D1 D0 A5 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0

0

x

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Pattern 1

.

0

x

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

0

1

0

1

0

1

0

1

0

1

0

Pattern 8

.

NOTES:

1. When Be(Blink Enable bit) = "High", blink is controlled by B1 and B0 bit. In case of 5-dot font width, when B1 = "1",

enabled dots of P0 - P4 will blink, and when B1 = "0" and B0 = "1", enabled dots in P4 will blink, when B1 = "0" and

B0 = “0", blink will not happen.

In case of 6-dot font width, when B1 = "1", enabled dots of P0-P5 will blink, and

when B1 = "0" and B0 = "1", enabled dots of P5 will blink, when B1 = "0" and

B0 = "0", blink will not happen.

2. "X" : don't care

22

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

SEGRAM (Segment Icon RAM)

S6A0073

SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0(COM17)

makes the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0(COM33) does

that. Its higher 2-bits are blinking control data, and lower 6-bits are pattern data (refer to Table 5 and Figure 8).

Table 5. Relationship between SEGRAM Address and Display Pattern

SEGRAM Address

SEGRAM Data Display Pattern

5-dot Font Width 6-dot Font Width

A3 A2 A1 A0 D7 D6 D5 D4

D3

S2

S7

D2

S3

S8

D1 D0 D7

S4 S5 B1

S9 S10 B1

D6

B0

D5

S1

S7

D4

S2

S8

D3

S3

D2

S4

D1

S5

D0

S6

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B1 B0

X

S1

S6

S9 S10 S11 S12

S11 S12 S13 S14 S15 B1

S16 S17 S18 S19 S20 B1

S21 S22 S23 S24 S25 B1

S26 S27 S28 S29 S30 B1

S31 S32 S33 S34 S35 B1

S36 S37 S38 S39 S40 B1

S41 S42 S43 S44 S45 B1

S46 S47 S48 S49 S50 B1

S51 S52 S53 S54 S55 B1

S56 S57 S58 S59 S60 B1

S61 S62 S63 S64 S65 B1

S66 S67 S68 S69 S70 B1

S71 S72 S73 S74 S75 B1

S76 S77 S78 S79 S80 B1

B0 S13 S14 S15 S16 S17 S18

B0 S19 S20 S21 S22 S23 S24

B0 S25 S26 S27 S28 S29 S30

B0 S31 S32 S33 S34 S35 S36

B0 S37 S38 S39 S40 S41 S42

B0 S43 S44 S45 S46 S47 S48

B0 S49 S50 S51 S52 S53 S54

B0 S55 S56 S57 S58 S59 S60

B0 S61 S62 S63 S64 S65 S66

B0 S67 S68 S69 S70 S71 S72

B0 S73 S74 S75 S76 S77 S78

B0 S79 S80 S81 S82 S83 S84

B0 S85 S86 S87 S88 S89 S90

B0 S91 S92 S93 S94 S95 S96

NOTES:

1. B1, B0 : Blinking control bit

Control Bit

Blinking Port

BE

0

B1

X

0

B0

X

5-dot font width

No blink

D4

6-dot font width

No blink

D5

1

0

1

0

1

X

D4 - D0

D5 - D0

2. S1 - S80 : Icon pattern ON/OFF in 5-dot font width

S1 - S96 : Icon pattern ON/OFF in 6-dot font width

3. "X" : don't care

23

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

5-Dot Font Width (FW = 0)

S1 S2 S3 S4 S5

S6 S7 S8 S9 S10 S11 S12 S13 S14 S15

S56 S57 S58 S59 S60 S61 S62 S63 S64 S65

. . .

Extension

Driver

6-Dot Font Width (FW = 1)

S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18

S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66

. . .

Extension

Driver

Figure 14. Relationship between SEGRAM and Segment Display

24

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

INSTRUCTION DESCRIPTION

OUTLINE

To overcome the speed difference between internal clock of S6A0073 and MPU clock, S6A0073 performs

internal operation by storing control information to IR or DR. The internal operation is determined according to the

signal from MPU, composed of read/write and data bus. Instruction can be divided largely four kinds,

(1) S6A0073 function set instructions ( set display methods, set data length, etc.)

(2) address set instructions to internal RAM

(3) data transfer instructions with internal RAM

(4) others .

The address of internal RAM is automatically increased or decreased by 1.

When IE = "High", S6A0073 is operated according to Instruction Set 1 (Table 6) and

when IE = "Low", S6A0073 is operated according to Instruction Set 2 (Table 10).

NOTE: During internal operation, Busy Flag (DB7) is read High. Busy Flag check must be preceded the next instruction.

When an MPU program with Busy Flag (DB7) checking is made, 1/2 f

is necessary for executing the next

OSC

instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW".

25

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(1) INSTRUCTION DESCRIPTION 1 (IE = "HIGH")

Table 6. Instruction Set 1

Instruction Code

Instruction

Description

Execution time

(fosc=270kHz)

RE RS

R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

W

Clear display

Return home

X

0

1

Write "20" to DDRAM, and set DDRAM

address to "00H" from AC.

1.53ms

0

1

x

Set DDRAM address to "00H" from AC

and return cursor to its original position if

shifted. The contents of DDRAM are not

changed.

Power down

mode

1

0

1

PD Set power down mode bit.

(PD = "1" : power down mode set,

PD = "0" : power down mode disable)

39ms

Assign cursor moving direction,

(I/D = "1": increment,

Entry mode

set

I/D

S

I/D = "0": decrement, and

display shift enable bit.

(S = "1": make display shift of

the enabled lines by the DS4-

DS1 bits in the shift Enable

instruction S = "0": display shift

disable)

1

0

1

B/D Segment bidirectional function.

(BID = "1": Seg60 ® Seg1

BID = "0": Seg1 ® Seg60)

Set display/cursor/blink on/off

D = "1" : display on,

D = "0" : display off,

C = "1" : cursor on,

C = "0" : cursor off,

B = "1" : blink on,

Display

ON/OFF

Control

D

C

B

39ms

B = "0" : blink off.

Assign font width, black/white

inverting of cursor, and 4-line

display mode control bit.

FW = "1" : 6-dot font width,

FW = "0" : 5-dot font width,

B/W = "1" : black/white inverting

of cursor enable,

Extended

1

0

1

FW B/W NW

39ms

function set

B/W = "0" : black/white inverting

of cursor disable.

NW = "1" : 4-line display mode,

NW = "0" : 1-line or 2-line

display mode.

26

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

Table 6. Instruction Set 1 Continued

Instruction Code

Instruction

Description

Execution time

(fosc=270kHz)

RE RS

R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

W

Cursor or

0

1

S/C R/L

X

Cursor or display shift.

39ms

Display Shift

S/C = "1" : display shift,

S/C = "0" : cursor shift,

R/L = "1" : shift to right,

R/L = "0" : shift to left.

Shift Enable

1

0

DS4 DS3 DS2 DS1 (when DH = "1")

Determine the line for display shift .

39ms

DS1 = "1/0": 1st line display shift

enable/disable

DS2 = "1/0": 2nd line display shift

enable/disable

DS3 = "1/0": 3rd line display shift

enable/disable

DS4 = "1/0": 4th line display shift

enable/disable.

Scroll Enable

1

0

1

0

1

HS4 HS3 HS2 SH1 (when DH = "0")

39ms

Determine the line for horizontal smooth

scroll.

HS1 = "1/0" : 1st line dot scroll

enable/disable

HS2 = "1/0" : 2nd line dot scroll

enable/disable

HS3 = "1/0" : 3rd line dot scroll

enable/disable

HS4 = "1/0" : 4th line dot scroll

enable/disable.

Function Set

DL

N

RE DH RE Set interface data length

(0)

V

(DL = "1" : 8-bit, DL = "0" : 4-bit),

numbers of display line when NW = "0",

(N = "1" : 2-line, N = "0" : 1-line),

extension register, RE("0"), shift/scroll

enable

DH = "1" : display shift enable

DH = "0" : dot scroll enable.

And reverse bit

REV = "1" : reverse display,

REV = "0" : normal display.

DL

N

RE BE LP Set DL, N, RE("1") and

(1) CGRAM/SEGRAM blink enable (BE)

BE = " 1/0" : CGRAM/SEGRAM blink

enable/disable

LP = "1" : low power mode

LP = "0" : normal operation mode

27

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Table 6. Instruction Set 1 continued

Instruction Code

Instruction

Description

Execution time

(fosc=270kHz)

RE RS

R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

W

Set CGRAM

Address

0

1

0

1

x

0

1

0

1

AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.

39ms

0ms

Set SEGRAM

Address

1

X

AC3 AC2 AC1 AC0 Set SEGRAM address in address

counter.

Set DDRAM

Address

AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter.

Set Scroll

Quantity

X

SQ SQ SQ SQ SQ SQ Set the quantity of horizontal dot scroll.

5

4

3

2

1

0

Read Busy

flag and

BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Can be known whether during internal

operation or not by reading BF.

The contents of address counter can also

be read.

Address

BF = “1” : busy state,

BF = “0” : ready state.

Write Data

Read Data

X

1

0

1

D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM

(DDRAM / CGRAM / SEGRAM).

43ms

D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM

(DDRAM / CGRAM / SEGRAM).

NOTE: When an MPU program with Busy Flag (DB7) checking is mode, 1/2 f

is necessary for executing the next

OSC

instruction by the falling edge of the "E" signal after the Busy Flag (DB7) goes to "low".

"X": Don't care

28

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

1) Display Clear

S6A0073

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

0

DB0

1

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"

into AC (address counter). Return cursor to the original status, bring the cursor to the left edge on first line of the

display. Make entry mode increment (I/D = "1").

2) Return Home: (RE = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

1

DB0

X

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return

cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.

3) Power Down Mode Set: (RE = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

1

DB0

PD

Power down mode enable bit set instruction. When PD = "High", it makes S6A0073 suppress current

consumption except the current needed for data storage by executing next three functions.

·

Make the output value of all the COM/SEG ports VDD

Make the COM/SEG output value of extension driver VDD by setting D output to "High" and M output to

"Low"

·

Disable voltage converter to remove the current through the divide resistor of power supply.

This instruction can be used s power sleep mode. When PD = "Low", power down mode becomes disabled.

29

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

4) Entry Mode Set

(1) RE = 0

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

1

DB1

I/D

DB0

S

Set the moving direction of cursor and display.

I/D : Increment/decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.

* CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.

When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits in the Shift Enable instruction

is shifted to the right (I/D = "0") or to the left(I/D = "1"). But it will seem as if the cursor does not move.

When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display as the above

function is not performed.

(2) RE = 1

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

1

DB1

1

DB0

BID

Set the data shift direction of segment in the application set.

BID : Data Shift Direction of Segment

When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG100.

When BID = "High", segment data shift direction is set to reversely from SEG100 to SEG1.

By using this instruction, the efficiency of application board area can be raised.

* The BID setting instruction is recommended to be set at the same time level of function set instruction.

* DB1 bit must be set to "1".

30

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

5) Display ON/OFF Control ( RE = 0 )

S6A0073

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

1

DB2

D

DB1

C

DB0

B

Control display/cursor/blink ON/OFF 1 bit register.

D : Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

C : Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

B : Cursor Blink ON/OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the

cursor position. If fosc has frequency of 270kHz, blinking has 370 ms interval.

When B = "Low", blink is off.

6) Extended Function Set ( RE = 1 )

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

1

DB2

F/W

DB1

B/W

DB0

NW

FW : Font Width control

When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than

that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-

0,including the left most space bit of CGRAM.(refer to Figure 15)

When FW = "Low", 5-dot font width is set.

B/W : Black/White Inversion enable bit

When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF

control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion has 370 ms intervals.

NW : 4 Line mode enable bit

When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care

condition.

6-bit

S

p

a

c

CGROM

Characte

Font

CGRAM

Characte

Font

8-bit

(5-dot)

(6-dot)

e

CGROM

CGRAM

Figure 15. 6-dot Font Width CGROM/CGRAM

31

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

7) Cursor or Display Shift (RE = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

S/C

DB2

R/L

DB1

-

DB0

-

Shift right/left cursor position or display without writing or reading of display data. This instruction is used to

correct or search display data (refer to Table 7). During 2-line mode display, cursor moves to the 2nd line after

40th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 20th digit of the current line.

Note that display shift is performed simultaneously in all the line enabled by DS1 - DS4 in the Shift Enable

instruction. When displayed data is shifted repeatedly, each line shifted individually. When display shift is

performed, the contents of address counter are not changed. During low power consumption mode, display shift

may not be performed normally.

Table 7. Shift Patterns according to S/C and R/L Bits

S/C

0

R/L

0

Operation

Shift cursor to the left, ADDRESS COUNTER is decreased by 1

Shift cursor to the right, ADDRESS COUNTER is increased by 1

Shift all the display to the left, cursor moves according to the display

Shift all the display to the right, cursor moves according to the display

0

1

0

1

8) Shift/Scroll Enable (RE = 1)

(1) DH = 0

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

HS4

DB2

HS3

DB1

HS2

DB0

HS1

HS : Horizontal Scroll per Line Enable. This instruction makes valid dot shift by a display line unit.

HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each

line. If you want to scroll the line in 1-line display mode or the 1st line in 2-line display mode, set HS1 and HS2 to

"High". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8)

(2) DH = 1

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

DS4

DB2

DS3

DB1

DS2

DB0

DS1

DS : Display Shift per Line Enable. This instruction selects shifting line to be shifted according to each line mode

in display shift right/left instruction. DS1, DS2, DS3 and DS4 indicate each line to be shifted, and each shift is

performed individually in each line. If you set DS1 and DS2 to "High" (enable) in 2 line mode, only the 1st line is

shifted and the 2nd line is not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS

bits (DS1 to DS4) are set to "Low" (disable), no display is shifted.

32

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

Table 8. Relationship between DS and COM signal

Enabled common signal Description

Enable bit

during shift

COM1 - COM8

COM9 - COM16

COM17 - COM24

COM25 - COM32

HS1/DS1

HS2/DS2

HS3/DS3

HS4/DS4

The part of display line that corresponds to enabled

common signal can be shifted.

33

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

9) Function Set

(1) RE = 0

RS

0

R/W

DB7

0

DB6

0

DB5

1

DB4

DL

DB3

N

DB2

DB1

DH

DB0

REV

0

RE(0)

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus

mode. In 4-bit bus mode, it needs to transfer 4-bit data by two times.

N : Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", 1-line display mode is set.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE : Extended function registers enable bit

At this instruction, RE must be "Low".

DH : Display shift enable selection bit.

When DH = "High", enables display shift per line.

When DH = "Low", enables smooth dot scroll.

This bit can be accessed only when IE pin input is "High".

REV : Reverse enable bit

When REV = "High", all the display data are reversed. i.e., all the white dots become black and black dots

become white. When REV = "Low", the display mode set normal display.

34

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

(2) RE = 1

RS

0

R/W

0

DB7

0

DB6

0

DB5

1

DB4

DL

DB3

N

DB2

DB1

DH

DB0

REV

RE(0)

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode.

When 4-bit bus mode, it is required to transfer 4-bit data by two times.

N : Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", 1-line display mode is set.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE : Extended function registers enable bit

When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits of

shift/scroll enable instruction and BE bits of function set register can be accessed.

BE : CGRAM/SEGRAM data blink enable bit

BE = "High", makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is assigned the

highest 2 bit of CGRAM/SEGRAM.

LP : Low power consumption mode enable bit

When EXT input is "Low"(without extension driver) and LP bit is set to "High", S6A0073 operates in low power

consumption mode.

During 1-line mode S6A0073 operates on a 4-division clock, and in 2-line or 4-line mode it operates on a 2-

division clock. According to this instruction, execution time becomes 4 or 2 times longer.

Note not to use display shift instruction, as it may result incorrect operation.

And the frame frequency is lower to 5/6 times lower than that of normal operation.

35

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

10) Set CGRAM Address (RE = 0)

RS

0

R/W

0

DB7

0

DB6

1

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set CGRAM address to AC.

This instruction makes CGRAM data available from MPU.

11) Set SEGRAM Address (RE = 1)

RS

0

R/W

0

DB7

0

DB6

1

DB5

X

DB4

X

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set SEGRAM address to AC.

This instruction makes SEGRAM data available from MPU.

12) Set DDRAM Address (RE = 0)

RS

0

R/W

0

DB7

1

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU.

In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "4FH".

In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM

address in the 2nd line is from "40H" to "67H".

In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "33H" in

the 2nd line, from "40H" to "53H" in the 3rd line and from "60H" to "73H" in the 4th line.

13) Set Scroll Quantity (RE = 1)

RS

0

R/W

0

DB7

1

DB6

X

DB5

SQ5

DB4

SQ4

DB3

SQ3

DB2

SQ2

DB1

SQ1

DB0

SQ0

As set SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (refer to Table 9).

In this case S6A0073 can show hidden areas of DDRAM by executing smooth scroll from 1 to 48 dots.

Table 9. Scroll Quantity According to HDS bits

SQ5

SQ4

SQ3

SQ2

SQ1

SQ0

Function

No shift

0

:

0

:

0

:

0

:

0

1

:

0

1

0

1

:

shift left by 1-dot

shift left by 2-dot

shift left by 3-dot

:

1

0

1

X

1

X

1

X

1

X

shift left by 47-dot

shift left by 48-dot

36

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

14) Read Busy Flag & Address

S6A0073

RS

0

R/W

1

DB7

BF

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

This instruction shows whether S6A0073 is in internal operation or not. If the resultant BF is High, the internal

operation is in progress and should wait until BF to be Low, which by then the next instruction can be performed.

In this instruction the value of address can also be read.

15) Write Data to RAM

RS

1

R/W

0

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

DB1

D1

DB0

D0

Write binary 8-bit data to DDRAM/CGRAM/SEGRAM.

The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction :

DDRAM address set, CGRAM address set, SEGRAM address set.

RAM set instruction can also determines the AC direction to RAM.

After write operation, the address is automatically increased/decreased by 1, according to the entry mode.

16) Read Data from RAM

RS

1

R/W

1

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

DB1

D1

DB0

D0

Read binary 8-bit data from DDRAM/CGRAM/SEGRAM.

The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not

performed before this instruction, the data that read first is invalid, as the direction of AC is not determined.

If RAM data read several times without RAM address set instruction before read operation, the correct RAM data

can be obtained from the second, but the first data would be incorrect, as there is no time margin to transfer RAM

data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set

instruction : it also transfer RAM data to output data register.

After read operation address counter is automatically increased/decreased by 1 according to the entry mode.

After CGRAM/SEGRAM read operation, display shift may not be executed correctly.

* In case of RAM write operation, AC is increased/decreased by 1 like read operation after this.

In this time, AC indicates the next address position, but the previous data can only be read by instruction.

37

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(2) INSTRUCTION DESCRIPTION 2 (IE = "LOW")

Table 10. Instruction Set 2

Instruction Code

Instruction

RE

Description

Execution time

(fosc=270kHz)

RS

0

R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

W

Clear Display

Return Home

X

0

1

Write "20H" to DDRAM. and set

DRAM address to "00H" from AC.

1.53ms

0

1

X

Set DDRAM address to "00H" from AC

and return cursor to its original position if

shifted. The contents of DDRAM are not

changed.

Entry Mode

Set

X

0

1

0

1

I/D

S

Assign cursor moving direction.

I/D = "1" : increment,

39ms

I/D = "0" : decrement.

and display shift enable bit.

S = "1" :make entire display shift of all

lines during DDRAM write,

S = "0":display shift disable

Display

ON/OFF

Control

D

C

B

Set display/cursor/blink on/off

D = "1" : display on,

D = "0" : display off,

C = "1" : cursor on,

C = "0" : cursor off,

B = "1" : blink on,

B = "0" : blink off.

Extended

FW BW NW Assign font width, black/white inverting of

cursor, and 4-line display mode control

bit.

function set

FW = "1" : 6-dot font width,

FW = "0" : 5-dot font width,

B/W = "1" : black/white inverting of

cursor enable,

B/W = "0" : black/white inverting of

cursor disable

NW = "1" : 4-line display mode,

NW = "0" : 1-line or 2-line display mode

Cursor or

0

00

0

1

S/C R/L

X

Cursor or display shift.

S/C = “1” : display shift,

S/C = “0” : cursor shift,

R/L = “1” : shift to right,

R/L = “0” : shift to left

39ms

Display Shift

38

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

Table 10. Instruction Set 2 (continued)

Instruction Code

Instruction

RE

1

Description

Execution time

(fosc=270kHz)

RS

R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

W

Scroll Enable

1

HS4 HS3 HS2 HS1 Determine the line for horizontal smooth

39ms

scroll.

HS1 = "1/0" :

1st line dot scroll enable/disable

HS2 = "1/0" :

2nd line dot scroll enable/disable

HS3 = "1/0" :

3rd line dot scroll enable/disable

HS4 = "1/0" :

4th line dot scroll enable/disable

Function Set

0

1

DL

N

RE

(0)

X

Set interface data length

DL = "1" : 8-bit,

39ms

DL = "0" : 4-bit

numbers of display line when NW = "0",

N = "1" : 2-line,

N = "0" : 1-line

extension register, RE("0"),

1

DL

N

RE BE LP Set DL, N, RE("1") and

(1) CGRAM/SEGRAM blink enable (BE)

39ms

BE = " 1/0" : CGRAM/SEGRAM blink

enable/disable

LP = "1" : low power mode

LP = "0" : normal operation mode

Set CGRAM

Address

0

1

0

1

AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.

39ms

Set SEGRAM

Address

X

AC3 AC2 AC1 AC0 Set SEGRAM address in address

counter.

39

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Table 10. Instruction Set 2 (continued)

Instruction Code

Instruction

RE

Description

Execution time

(fosc=270kHz)

RS

0

R/ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

W

Set DDRAM

Address

0

1

X

0

1

AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter.

39ms

0ms

Set Scroll

Quantinty

1

X

SQ SQ SQ SQ SQ SQ Set the quantity of horizontal dot scroll.

5

4

3

2

1

Read Busy

flag and

0

1

BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Can be known whether during internal

operation or not by reading BF.

The contents of address counter can also

be read.

Address

BF = "1" : busy state,

BF = "0" : ready state.

Write Data

Read Data

X

1

0

1

D7 D6 D5 D4 D3 D2 D1 D0 Write data into internal RAM

(DDRAM / CGRAM / SEGRAM).

43ms

D7 D6 D5 D4 D3 D2 D1 D0 Read data from internal RAM

(DDRAM / CGRAM / SEGRAM).

NOTE: When an MPU program with Busy Flag (DB7) checking is made, 1/2 f

(is necessary) for executing the next

OSC

instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "low".

40

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

1) Display Clear

S6A0073

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

0

DB0

1

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"

into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first

line of the display. And entry mode is set to increment mode (I/D = "1").

2) Return Home

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

0

DB1

1

DB0

X

Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return

cursor to its original site and return display to its original status, if shifted. Contents of DDRAM does not change.

3) Entry Mode Set

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

0

DB2

1

DB1

I/D

DB0

S

Set the moving direction of cursor and display.

I/D : Increment / decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.

* CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.

When S = "High", after DDRAM write, the entire display of all lines is shifted to the right (I/D = "low") or to the

left(I/D = "high"). But it will seem as if the cursor is not moving. When S = "Low", or DDRAM read, or

CGRAM/SEGRAM read/write operation, shift of entire display is not performed.

41

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

4) Display ON/OFF Control ( RE = 0 )

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

1

DB2

D

DB1

C

DB0

B

Control display/cursor/blink ON/OFF 1 bit register.

D : Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

C : Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display, but I/D register preserves its data.

B : Cursor Blink ON/OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the

cursor position. If fosc has 270kHz frequency, blinking has 370ms interval.

When B = "Low", blink is off.

5) Extended Function Set ( RE = 1 )

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

0

DB3

1

DB2

FW

DB1

BW

DB0

NW

FW : Font Width control

When FW = "High", display character font width is assigned to 6-dot and execution time becomes 6/5 times than

that of 5-dot font width. The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-

0,including the leftmost space bit of CGRAM.(refer to Figure 16). When FW = "Low", 5-dot font width is set.

B/W : Black/White Inversion enable bit

When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display ON/OFF

control instruction becomes don't care condition. If fosc has frequency of 270kHz, inversion has 370ms intervals.

NW : 4 Line mode enable bit

When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes don't care

condition.

42

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

6-bit

S

CGROM

p

CGRAM

Characte

Font

Characte

a

c

e

8-bit

Font

(5-dot)

(6-dot)

CGROM

CGRAM

Figure 16. 6-dot Font Width CGROM/CGRAM

6) Cursor or Display Shift (RE = 0)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

SC

DB2

R/L

DB1

-

DB0

-

Shift right/left cursor position or display without writing or reading of display data. This instruction is used to

correct or search display data (refer to Table 7). During 2-line mode display, cursor moves to the 2nd line after

40th digit of 1st line. In 4-line mode, cursor moves to the next line, only after every 20th digit of the current line.

Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each

line shifted individually. When display shift is performed, the contents of address counter are not changed.

Table 11. Shift Patterns According to S/C and R/L bits

S/C

0

R/L

0

Operation

Shift cursor to the left, ADDRESS COUNTER is decreased by 1

Shift cursor to the right, ADDRESS COUNTER is increased by 1

Shift all the display to the left, cursor moves according to the display

Shift all the display to the right, cursor moves according to the display

0

1

0

1

43

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

7) Scroll Enable (RE = 1)

RS

0

R/W

0

DB7

0

DB6

0

DB5

0

DB4

1

DB3

HS4

DB2

HS3

DB1

HS2

DB0

HS1

HS : Horizontal Scroll per Line Enable

This instruction makes valid dot shift by a display line unit.

HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each

line.

If the line in 1-line display mode or the 1st line in 2-line display mode is to be scrolled, set HS1 and HS2 to

"high". If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "high". (Refer to table 8)

8) Function Set

(1) RE = 0

RS

0

R/W

0

DB7

0

DB6

0

DB5

1

DB4

DL

DB3

N

DB2

DB1

-

DB0

-

RE(0)

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode.

When 4-bit bus mode, it is required to transfer 4-bit data twice.

N : Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", 1-line display mode is set.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE : Extended function registers enable bit

At this instruction, RE must be "Low".

44

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

(2) RE = 1

RS

0

R/W

0

DB7

0

DB6

0

DB5

1

DB4

DL

DB3

N

DB2

DB1

RE

DB0

LP

RE(1)

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus

mode. When 4-bit bus mode, it is required to transfer 4-bit data twice.

N : Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", 1-line display mode is set.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE : Extended function registers enable bit

When RE = "High", extended function set registers, SEGRAM address set registers, HS bits of scroll enable

instruction and BE bits of function set register can be accessed.

BE : CGRAM/SEGRAM data blink enable bit

BE = "High", makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is assigned the

highest 2 bit of CGRAM/SEGRAM.

LP : Low power consumption mode enable bit

When EXT port input is "Low"(without extension driver) and LP bit is set to "High", S6A0073 operates in low

power consumption mode.

During 1-line mode S6A0073 operates on a 4-division clock, and in 2-line or 4-line mode it operates on a 2-

division clock. According to this instruction, execution time becomes 4 or 2 times longer.

Note not to use display shift instruction, it may happen wrong operation.

And the frame frequency is lower to 5/6 than that of normal operation.

9) Set CGRAM Address (RE = 0)

RS

0

R/W

0

DB7

0

DB6

1

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.

45

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

10) Set SEGRAM Address (RE = 1)

RS

0

R/W

0

DB7

0

DB6

1

DB5

X

DB4

X

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set SEGRAM address to AC.

This instruction makes SEGRAM data available from MPU.

11) Set DDRAM Address (RE = 0)

RS

0

R/W

0

DB7

1

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU.

In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "4FH".

In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM

address in the 2nd line is from "40H" to "67H".

In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from "20H" to "33H" in

the 2nd line, from "40H" to "53H" in the 3rd line and from "60H" to "73H" in the 4th line.

12) Set Scroll Quantity (RE = 1)

RS

0

R/W

0

DB7

1

DB6

X

DB5

SQ5

DB4

SQ4

DB3

SQ3

DB2

SQ2

DB1

SQ1

DB0

SQ0

Setting SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (refer to Table 12). In this case

S6A0073 execute dot smooth scroll from 1 to 48 dots.

Table 12. Scroll Quantity According to HDS bits

SQ5

SQ4

SQ3

SQ2

SQ1

SQ0

Function

No shift

0

:

0

:

0

:

0

:

0

1

:

0

1

0

1

:

shift left by 1-dot

shift left by 2-dot

shift left by 3-dot

:

1

0

1

X

1

X

1

X

1

X

shift left by 47-dot

shift left by 48-dot

46

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

13) Read Busy Flag & Address

S6A0073

RS

0

R/W

1

DB7

BF

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

This instruction shows whether S6A0073 is in internal operation or not. If the resultant BF is High, the internal

operation is in progress and should wait until BF becomes "LOW", which by then the next instruction can be

performed. In this instruction value of address counter can also be read.

14) Write data to RAM

RS

1

R/W

0

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

DB1

D1

DB0

D0

Write binary 8-bit data to DDRAM/CGRAM/SEGRAM.

The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction :

DDRAM address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the

AC direction to RAM.

After write operation, the address is automatically increased/decreased by 1, according to the entry mode.

15) Read data from RAM

RS

1

R/W

1

DB7

D7

DB6

D6

DB5

D5

DB4

D4

DB3

D3

DB2

D2

DB1

D1

DB0

D0

Read binary 8-bit data from DDRAM/CGRAM/SEGRAM.

The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not

performed before this instruction, the data that read first is invalid, because the direction of AC is not determined.

If the RAM data several is read times without RAM address set instruction before read operation, the correct

RAM data from the second, but the first data would be incorrect, as there is no time margin to transfer RAM data.

In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set

instruction : it also transfer RAM data to output data register.

After read operation address counter is automatically increased/decreased by 1 according to the entry mode.

After CGRAM/SEGRAM read operation, display shift may not be executed correctly.

* In case of RAM write operation, after this AC is increased/decreased by 1 as in read operation after this. In this

time, AC indicates the next address position, but the previous data can only be read by read instruction.

47

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

INTERFACE WITH MPU

S6A0073 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. Hence, both types 4 or 8-bit

MPU can be used. In case of 4-bit bus mode, data transfer is performed by two times to transfer 1 byte data.

(1) When interfacing data length are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus.

At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in

case of 8-bit bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by two times.

Busy Flag outputs "High" after the second transfer are ended.

(2) When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7.

(3) If IM is set to "Low", serial transfer mode is set.

48

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

INTERFACE WITH MPU IN BUS MODE

1) Interface with 8-bits MPU

If 8-bits MPU is used, S6A0073 can connect directly with that. In this case, port E, RS, R/W and DB0 to DB7

need to interface each other. Example of timing sequence is shown below.

RS

R/W

E

Internal

Internal Operation

signal

No

Busy

DB7

DATA

Busy

Instruction

Busy Flag Check Busy Flag Check

Busy Flag Check

Instruction

Figure 17. Example of 8-bit Bus Mode Timing Sequence

2) Interface with 4-bits MPU

If 4-bits MPU is used, S6A0073 can connect directly with this. In this case, E, RS, R/W and DB4 to DB7 need to

interface each other. The transfer is performed by twice. Example of timing sequence is shown below.

RS

R/W

E

Internal

Internal Operation

signal

No

Busy

DB7

D7

D3

AC3

D7

D3

Busy

Instruction

Busy Flag Check

Instruction

Fig 18. Example of 4-bit Bus Mode Timing Sequence

49

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Interface with MPU in Serial Mode

When IM input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing

transfer clock), SID (serial input data), and SOD (serial output data), are used. If S6A0073 is to be used with

other chips, chip select port (CS) can be used. By setting CS to "Low", S6A0073 can receive SCLK input. If CS is

set to "High", S6A0073 reset the internal transfer counter.

Before transfer real data, start byte has to be transferred. It is composed of succeeding 5 "High" bits, register

read write control bit (R/W), register selection bit (RS) and end bit that indicates the end of start byte. Whenever

succeeding 5 "High" bits are detected by S6A0073, it resets the serial transfer counter and prepares to receive

next information. The next input data is the register selection bit which determines which register will be used,

and read write control bit that determine the direction of data. Then end bit is transferred, which must have "Low"

value to show the end of start byte. (refer to Figure 19, Figure 20)

(1) Write Operation (R/W = 0)

After start byte is transferred from MPU to S6A0073, 8-bit data is transferred which is divided into 2 bytes, each

byte has 4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then

serially transferred data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe

transfer. To transfer several bytes continuously without changing RS bit and RW bit, start byte transfer is needed

only at first starting time, I, e, after first start byte is transferred, real data succeeding can be transferred.

(2) Read Operation (R/W = 1)

After start byte is transferred to S6A0073, MPU can receive 8-bit data through the SOD at a time from the LSB.

Waiting time is needed to insert between start byte and data reading, as internal reading from RAM requires

some delay. Continuous data reading is possible such as serial write operation. It also needs only one start bytes,

only if some delay between reading operations of each byte is inserted. During the reading operation, S6A0073

observes succeeding 5 "High" from MPU. If it is detected, S6A0073 restarts serial operation at once and prepares

to receive RS bit. So in continuous reading operation, SID port must be "low".

50

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

Serial Write Operation

CS (Input)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SCLK (Input)

SID (Input)

1

1 R/WRS 0 D0 D1 D2 D3 0

0

0 D4 D5 D6 D7 0

0 0 0

Starting Byte

Instruction

Upper Data

Synchronizing

Bit String

Lower Data

1'st Byte

2'nd Byte

Serial Read Operation

CS (Input)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCLK (Input)

SID (Input)

1

1 R/W RS 0

0

0 0

D0 D1 D2 D3 D4 D5 D6 D7

SOD (Output)

Busy Flag/

Read Data

Starting Byte

Lower

Data

Upper

Data

Synchronizing

Bit String

Figure 19. Timing Diagram of Serial Data Transfer

51

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Continuous Write Operation

SCLK

SID

Wait

Start Byte

1'st Byte

2'nd Byte

1'st Byte

2'nd Byte

1'st Byte

2'nd Byte

Instruction1

Instruction2

Instruction1

Execution Time

Instruction3

Instruction2

Execution Time

Instruction3

Execution Time

Continuous Read Operation

SCLK

Wait

Start

SID

Byte

Data

Data

Data

SOD

Instruction1

Execution Time

Instruction2

Execution Time

Instruction3

Execution Time

Fig 20. Timing Diagram of Continuous Data Transfer

52

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

APPLICATION INFORMATION ACCORDING TO LCD PANEL

1) LCD Panel: 24 Character x 1-line Format (5-dot Font,1/17 Duty)

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

(COM0)

§

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

S6A0073

SEG7

SEG8

SEG9

SEG10

SEG58

SEG59

SEG60

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

2) LCD Panel: 24 Character x 2-line Format (5-dot Font, 1/33 Duty)

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM33

(COM0)

SEG1

SEG2

SEG3

SEG4

SEG5

S6A0073

SEG58

SEG59

SEG60

COM32

COM31

COM30

COM29

COM28

COM27

COM26

COM25

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

53

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

3) LCD Panel: 12 Character x 4-line Format (5-dot Font, 1/33 Duty)

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

S6A0073

COM30

COM31

COM32

COM33

(COM0)

%

§

SEG1

SEG2

SEG3

SEG4

SEG5

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG58

SEG59

SEG60

54

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

4) LCD Panel: 10 Character

´ 4-line Format (6-dot Font, 1/33 Duty)

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

S6A0073

COM33

(COM0)

§

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG58

SEG59

SEG60

55

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

5) LCD Panel: 20 Character

´ 4-line Format (5-dot Font, 1/33 Duty)

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

S6A0073

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

VDD

COM33

(COM0)

EXT

SEG1

SEG2

SEG3

SEG4

SEG5

SEG58

SEG59

SEG60

SEG1

SEG2

SEG3

SEG4

SEG5

Extension

Driver

SEG36

SEG37

SEG38

SEG39

SEG40

56

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

INITIALIZING

1) Initializing by Internal Reset Circuit

When the power is turned on, S6A0073 is initialized automatically by power on reset circuit. During the

initialization, the following instructions are executed, and BF(Busy Flag) is kept "High"(busy state) to the end of

initialization.

(1) Display Clear instruction

Write "20H" to all DDRAM

(2) Set Functions instruction

DL = 1 : 8-bit bus mode

N = 1 : 2-line display mode

RE = 0 : Extension register disable

BE = 0 : CGRAM/SEGRAM blink OFF

LP = 0 : Operate in normal mode (Not in Low Power Mode)

DH = 0 : Horizontal scroll enable

REV = 0 : Normal display mode (Not reversed display)

(3)Control Display ON/OFF instruction

D = 0 : Display OFF

C = 0 : Cursor OFF

B = 0 : Blink OFF

(4) Set Entry Mode instruction

I/D = 1 : Increment by 1

S = 0 : No entire display shift

BID = 0 : Normal direction segment port

(5) Set Extension Function instruction

FW = 0 : 5-dot font width character display

B/W = 0 : Normal cursor (8th line)

NW = 0 : Not 4-line display mode, 2-line mode is set because of N("1")

(6) Enable Scroll/Shift instruction

HS = 0000 : Scroll per line disable

DS = 0000 : Shift per line disable

(7) Set scroll Quantity instruction

SQ = 000000 : Not scroll

2) Initializing by Hardware RESET input

When RESET pin = "Low", S6A0073 can be initialized like the case of power on reset. During the power on reset

operation, this pin is ignored.

57

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

INITIALIZING BY INSTRUCTION

1) 8-bit Interface Mode

Power On

Wait for more than 20ms after

D

V

D

rises to 4.5V

Wait for more than 30ms after DVD rises to 2.7V

Condition: fosc = 270kHz

0

1

4-bit interface

8-bit interface

DL

N

Function Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DL(1)

0

1

1-line mode

2-line mode

0

1

N

0

X

Wait for more than 39m s

0

1

Display off

Display on

D

C

B

Display ON/OFF Control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

Cursor off

Cursor on

0

1

D

C

B

0

1

Blink off

Blink on

m

Wait for more than 39s

Display Clear

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

Wait for more than 1.53ms

Entry Mode Set

0

1

Decrement mode

Increment mode

I/D

S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

I/D

0

1

Entire shift off

Entire shift on

0

1

S

Initialization End

58

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

2) 4-bit Interface Mode

Power On

Wait for more than 20ms after VDD rises to 4.5V

Wait for more than 30ms after VDD rises to 2.7V

Condition: fosc = 270kHz

Function Set

0

1

4-bit interface

8-bit interface

DL

N

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

DL(0)

X

0

1

1-line mode

2-line mode

Wait for more than 39ms

Function Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

X

N

X

Wait for more than 39ms

0

1

Display off

Display on

D

C

B

Display ON/OFF Control

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

Cursor off

Cursor on

0

1

0

X

D

C

B

0

1

Blink off

Blink on

Wait for more than 39ms

Clear Display

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

X

Wait for more than 1.53ms

Entry Mode Set

0

1

Decrement mode

Increment mode

I/D

SH

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

X

0

1

Entire shift off

Entire shift on

I/D

SH

Initialization End

59

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE

1) IE = "Low"

1. Power supply on: Initialized by the internal power on reset circuit

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LCD DISPLAY

2. Function Set: 8-bit, 1-line, RE (0)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

X

3. Display ON/OFF Control: Display/Cursor on

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

0

4. Entry Mode Set: Increment

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

0

5. Write Data to DDRAM: Write S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

S_

SA_

1

0

1

0

1

0

1

6. Write Data to DDRAM: Write A

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

7. Write Data to DDRAM: Write M

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAM_

1

0

1

0

1

0

1

8. Write Data to DDRAM: Write S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMS_

1

0

1

0

1

0

1

60

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

9. Write Data to DDRAM: Write U

LCD DISPLAY

SAMSU_

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

0

1

10. Write Data to DDRAM: Write N

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUN_

1

0

1

0

1

0

11. Write Data to DDRAM: Write G

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG_

SAMSUNG _

AMSUNG K_

MSUNG KS_

SUNG KS0_

1

0

1

0

1

12. Cursor or Display Shift: Cursor shift to right

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

X

13. Entry Mode Set: Entire Display Shift Enable

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

14. Write Data to DDRAM: Write K

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

15. Write Data to DDRAM: Write S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

16. Write Data to DDRAM: Write 0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

61

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

17. Write Data to DDRAM: Write 0

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LCD DISPLAY

UNG KS00_

NG KS007_

G KS0073_

G KS0073

KS0073_

1

0

1

0

18. Write Data to DDRAM: Write 7

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

19. Write Data to DDRAM: Write 2

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

20. Cursor or Display Shift: Cursor shift left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

x

21. Write Data to DDRAM: Write 8

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

22. Return Home

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG KS0073

0

1

x

23. Clear Display

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

62

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

2) IE = "High"

S6A0073

1. Power Supply on: Initialized by the internal power on reset circuit

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

2. Function Set: 8-bit, RE(1)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

3. Extended Function Set: 5-font, 4-line

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

4. Function Set: RE(0)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

5. Display ON/OFF Control: Display/Cursor on

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

0

6. Write Data to DDRAM: Write S

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

S_

1

0

1

0

1

0

1

63

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

7. Write Data to DDRAM: Write A

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SA_

1

0

1

0

1

12. Write Data to DDRAM: Write G

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG_

1

0

1

0

1

13. Set DDRAM Address 20H

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

_

0

1

0

1

0

14. Write Data to DDRAM: Write K

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

K_

1

0

1

0

1

0

1

19. Write Data to DDRAM: Write 3

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073_

1

0

1

0

1

20. Set DDRAM Address 40H

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

_

0

1

0

64

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

21. Write Data to DDRAM: Write L

SAMSUNG

KS0073

L_

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

30. Write Data to DDRAM: Write R

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER_

1

0

1

0

1

0

1

0

31. Set DDRAM Address 60H

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

_

0

1

0

43. Write Data to DDRAM: Write R

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER_

1

0

1

0

1

0

1

0

44. Function Set: RE("0"), DH("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER_

0

1

0

1

0

45. Function Set: RE("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER_

0

1

0

65

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

46. Shift/Scroll Enable: DS4("1"), DS3/2/1("0")

SAMSUNG

KS0073

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LCD DRIVER

& CONTROLLER_

0

1

0

47. Function Set: RE("0")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER_

0

1

0

1

0

48. Cursor or Display Shift: Display shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

CONTROLLER_

0

1

0

x

49. Cursor or Display Shift: Display shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

CONTROLLER_

0

1

0

x

50. Cursor or Display Shift: Display shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

ONTROLLER_

0

1

0

x

51. Cursor or Display Shift: Display shift to left

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

NTROLLER_

0

1

0

x

66

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

52. Return Home

SAMSUNG

KS0073

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LCD DRIVER

& CONTROLLER

0

1

x

53. Function Set: RE("0), REV("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER

0

1

0

1

54. Cursor or Display Shift: Display shift to right

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER

0

1

x

55. Cursor or Display Shift: Display shift to right

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER

0

1

x

56. Return Home

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER

0

1

x

57. Function Set: RE("0"), REV("0")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER

0

1

0

67

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

58. Function Set: RE("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SAMSUNG

KS0073

LCD DRIVER

& CONTROLLER

0

1

0

59. Entry Mode Set: BID("1")

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

60. Write Data to DDRAM: Write B

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

61. Write Data to DDRAM: Write I

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

1

62. Write Data to DDRAM: Write D

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

1

0

63. Clear Display

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

_

0

1

68

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

FRAME FREQUENCY

1) 1/17 Duty Cycle

1-line selection period

1

2

3

4

...

16 17

1

2

3

...

16 17

VDD

V1

COM1

V4

V5

1 Frame

Item

Normal Display Mode (LP = 0)

5-dot font width

200 clocks

79.4Hz

6-dot font width

240 clocks

66.2Hz

1-line selection period

Frame frequency

Item

Low Power Mode (LP = 1)

5-dot font width

60 clocks

6-dot font width

72 clocks

1-line selection period

Frame frequency

66.2Hz

55.1Hz

* fosc = 270kHz (1 clock = 3.7ms)

69

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

2) 1/33 Duty Cycle

1-line selection period

1

2

3

4

...

32 33

1

2

3

...

32 33

VDD

V1

COM1

V4

V5

1 Frame

Item

Normal Display Mode (LP = 0)

5-dot font width

100 clocks

81.8Hz

6-dot font width

120 clocks

68.2Hz

1-line selection period

Frame frequency

Item

Normal Display Mode (LP = 1)

5-dot font width

60 clocks

6-dot font width

72 clocks

1-line selection period

Frame frequency

68.2Hz

56.8Hz

¡ Øfosc = 270kHz (1 clock = 3.7ms)

70

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

POWER SUPPLY FOR DRIVING LCD PANEL

1) When an external power supply is used

VDD

V1

R

V2

R0

R

V3

V4

R

V5

VEE

2) When an internal booster is used

Boosting Twice

Boosting Three Times

VDD

V_CI

VDD

V1

V_CI

VDD

V1

+

R

+

R

-

GND

C1

C2

-

GND

C1

C2

R

V2

V3

V2

V3

-

+

-

+

R0

R

R0

R

1

m F

1

m F

V5OUT2 V4

V5OUT3 V5

V5OUT2 V4

V5OUT3 V5

R

-

+

1m F

-

+

-

Can be detached

if not using

power down mode

Can be detached

if not using

power down mode

1m

F

1m F

+

NOTES:

1. Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving voltage. Especially, a voltage

of over 4.3V should not be input to the reference voltage(Vci) when boosting three times.

2. A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting twice.

3. The value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (Refer to Table 13)

71

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Table 13. Duty Ratio and Power Supply for LCD Driving

Item

Number of lines

Duty ratio

Data

1

1/17

1/5

R

2 or 4

1/33

1/6.7

R

Bias

Divided resistance

R

R0

R

2.7R

MAXIMUM ABSOLUTE RATE

Characteristic

Symbol

Value

UNIT

V_DD

Power Supply Voltage (1)

-0.3 to +7.0

V_DD-15.0 to V_DD+0.3

-0.3 to V_DD+0.3

-30 to +80

V

V_LCD

V_IN

Power Supply Voltage (2)

Input Voltage

V

T_OPR

T_STG

Operating Temperature

Storage Temperature

°C

-55 to +125

¡ ØVoltage greater than above may damage to the circuit (V_DD³ V1 ³ V2 ³ V3 ³ V4 ³ V5)

72

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

ELECTRICAL CHARACTERISTICS

DC Characteristics

(V_DD= 2.7V to 5.5V, Ta = -30 to +85°C)

Characteristic

Operating Voltage

Supply Current

Symbol

Condition

Min

2.7

-

Typ

-

Max

5.5

Unit

V

-

DD

I

Internal oscillation or

external clock.

0.15

0.3

mA

DD

(V =3.0V, f

= 270kHz)

DD

OSC

V

0.7V

V

Input Voltage (1)

(except OSC1)

-

IH1

DD

V

= 2.7 to 3.0

= 3.0 to 5.5

0.2V

DD

-0.3

-

V

IL1

DD

-

0.6

DD

V

0.7V

V

DD

Input Voltage (2)

(OSC1)

-

IH2

DD

V

0.2V

DD

-

IL2

V

I

= -0.1mA

0.75V

DD

Output Voltage (1)

(DB0 to DB7)

-

OH1

OH

V

I

= 0.1mA

0.2V

-

OL1

OL

DD

V

0.8V

= -40mA

= 40mA

Output Voltage (2)

(expect DB0 to DB7)

Voltage Drop

-

OH2

DD

O

V

0.2V

-

OL2

DD

Vd

= ± 0.1mA

-

1

V

COM

vd

SEG

I

V

= 0V to V

DD

Input Leakage Current

Low Input Current

-1

-

mA

IL

IN

I

= 0V, V

= 3V (pull up)

-10

190

-50

270

-120

IN

DD

f

Rf = 91kW ± 2% (V

= 5V)

Internal Clock (external R_f)

350

kHz

OSC

DD

f

125

45

270

50

410

55

0.2

-

kHz

%

EC

External Clock

Duty

t , t

-

ms

V

R

F

V

Voltage Converter Out2

(Vci = 4.5V)

Ta = 25°C, C = 1mF,

-3.0

-4.2

OUT2

I

= 0.25mA,

OUT

V

f

= 270kHz

Voltage Converter Out3

(Vci = 2.7V)

-4.3

-5.1

-

OUT3

OSC

Voltage Converter Input

LCD Driving Voltage

Vci

-

2.5

3.0

-

4.5

V

-V5

1/5 bias

13.0

V

LCD

DD

1/6.7 bias

73

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

AC Characteristics

(V_DD= 4.5 to 5.5V, Ta = -30 to +85°C)

Mode

Item

Symbol

Min

Typ

Max

Unit

t_C

E Cycle Time

500

-

t_R, t_F

t_W

E Rise / Fall Time

-

20

(1) Write Mode

E Pulse Width (High, Low)

230

40

10

60

10

500

-

t_SU1

t_H1

t_SU2

t_H2

t_C

( refer to Figure 21) R/W and RS Setup Time

R/W and RS Hold Time

Data Setup Time

-

ns

-

Data Hold Time

-

E Cycle Time

-

20

-

t_R, t_F

t_W

t_SU

t_H

E Rise / Fall Time

(2) Read Mode

E Pulse Width (High, Low)

230

40

10

-

(refer to Figure 22) R/W and RS Setup Time

R/W and RS Hold Time

-

ns

ms

ns

-

t_D

Data Output Delay Time

160

-

t_DH

t_C

Data Hold Time

5

Serial Clock Cycle Time

0.5

-

20

50

-

t_R,t_F

t_W

Serial Clock Rise / Fall Time

Serial Clock Width (High, Low)

200

60

t_SU1

(3) Serial

Chip Select Setup Time

Chip Select Hold Time

-

Interface Mode

tH1

20

-

t_SU2

(refer to Figure 23) Serial Input Data Setup Time

Serial Input Data Hold Time

100

t_H2

t_D

100

-

160

-

Serial Output Data Delay Time

-

t_DH

Serial Output Data Hold Time

5

74

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

AC Characteristics (Continued)

S6A0073

(V_DD= 2.7 to 4.5V, Ta = -30 to +85°C)

Mode

Item

Symbol

Min

Typ

Max

Unit

t_C

E Cycle Time

1000

-

t_R, t_F

t_W

E Rise / Fall Time

-

450

60

20

195

10

1000

-

25

(4) Write Mode

E Pulse Width (High, Low)

-

t_SU1

t_H1

t_SU2

t_H2

t_C

( refer to Figure 21) R/W and RS Setup Time

R/W and RS Hold Time

Data Setup Time

-

ns

-

Data Hold Time

-

E Cycle Time

-

t_R, t_F

t_W

t_SU

t_H

E Rise / Fall Time

25

(5) Read Mode

E Pulse Width (High, Low)

450

60

20

-

(refer to Figure 22) R/W and RS Setup Time

R/W and RS Hold Time

-

ns

ms

ns

-

t_D

Data Output Delay Time

360

t_DH

t_C

Data Hold Time

5

-

Serial Clock Cycle Time

1

20

t_R,t_F

t_W

Serial Clock Rise / Fall Time

Serial Clock Width (High, Low)

-

50

400

60

20

200

-

t_SU1

t_H1

t_SU2

t_H2

t_D

(6) Serial

Chip Select Setup Time

Chip Select Hold Time

-

Interface Mode

-

(refer to Figure 23) Serial Input Data Setup Time

Serial Input Data Hold Time

-

360

-

Serial Output Data Delay Time

t_DH

Serial Output Data Hold Time

5

75

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

AC Characteristics (Continued)

(V_DD= 2.7 to 5.5V, Ta = -30 to + 85°C)

Mode

Item

Clock Pulse Width (High, Low)

(7) Interface Mode Clock Rise / Fall Time

Symbol

Min

Typ

Max

Unit

t_W

800

-

t_R, t_F

t_SU1

t_SU2

t_DH

-

100

with Extension

Driver

Clock Setup Time

Data Setup Time

500

300

-1000

-

ns

-

(refer to Figure 24) Data Hold Time

M Delay Time

t_DM

1000

VIH1

VIL1

RS

th1

tsu1

R/W

VIL1

th1

th2

tw

tf

VIH1

VIL1

VIH1

VIL1

E

VIL1

tsu2

tr

VIH1

VIL1

VIH1

VIL1

DB0 - DB7

Valid Data

tc

Figure 21. Write Mode

76

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

S6A0073

V

IH1

IL1

t_su

RS

V

th

VIH1

R/W

th

t

w

t

f

VIH1

E

VIL1

tDH

t

r

tD

V

IH1

V

IH1

DB0 - DB7

Valid Data

VIL1

t

c

Figure 22. Read Mode

tC

CS

VIL1

t

su1

tr

t

w

tw

t

h1

tf

SCLK

V

IH1

V

IH1

V

IH1

IL1

h2

V

IH1

VIL1

V

VIL1

su2

t

SID

t

D

DH

t

V

OH1

SOD

VOL1

Figure 23. Serial Interface Mode

77

S6A0073

34COM/60SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

t

f

V_OH2

V

OH2

CLK1

CLK2

D

t

w

VOL2

t

w

t

r

V

OH2

VOH2

V_OL2

t

SU1

tw

V

OH2

VOL2

t

SU1

t

DH

M

VOL2

t

DM

Figure 24. Interface Mode with Extension Driver

RESET TIMING

(V_DD= 2.7 to 5.5V, Ta = -30 to +85°C)

Item

Symbol

Min

Typ

Max

Unit

Reset low level width

(refer to Figure 25)

t_RES

10

-

ms

t

RES

RESET

V

IL1

VIL1

Figure 25. Reset Timing Diagram

78


型号：	KS0073-Q
厂家：	SAMSUNG
描述：	暂无描述驱动器控制器 CD
文件：	总78页 (文件大小：921K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS0073-Q [SAMSUNG]

相关型号：

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KS0073P

KS0073P-03CC

KS0073Q

KS0073TB

KS0074

KS0074-P

KS0074P-06CC

KS0075

KS0075-P

KS0075P

KS0075P-02CC