KS0075_技术文档

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

INTRODUCTION

KS0075 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology.

It can display 1, 2, or 4 lines with 5 x 8 or 6 x 8 dots format.

FUNCTIONS

ꢀ Character type dot matrix LCD driver & controller

ꢀ Internal driver : 34 common and 100 segment signal output

ꢀ Easy interface with 4-bit or 8-bit MPU

ꢀ Clock synchronized serial Interface

ꢀ 5 x 8 dot matrix possible

ꢀ 6 x 8 dot matrix possible

ꢀ Bi-directional shift function

ꢀ All character reverse display

ꢀ Display shift per line

ꢀ Voltage converter for LCD drive voltage : 13 V max (2 times / 3 times)

ꢀ Various instruction functions

ꢀ Automatic power on reset

FEATURES

ꢀ Internal Memory

- Character Generator ROM (CGROM) : 9,600 bits (240 characters x 5 x 8 dot)

- Character Generator RAM (CGRAM) : 64 x 8 bits (8 characters x 5 x 8 dot)

- Segment Icon RAM (SEGRAM) : 16 x 8 bits (96 icons max.)

- Display Data RAM (DDRAM) : 80 x 8 bits (80 characters max.)

ꢀ Low power operation

- Power supply voltage range : 2.7 ꢁ 5.5 V (VDD)

- LCD Drive voltage range : 3.0 ꢁ 13.0 V (VDD - V5)

ꢀ CMOS process

ꢀ Programmable duty cycle : 1/17, 1/33 (refer to Table 1.)

ꢀ Internal oscillator with an external resistor

ꢀ Bare chip available

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Table 1. Programmable duty cycles

5-dot font width

Display Line

Duty Ratio

Single-chip Operation

Numbers

Displayable characters

1 line of 40 characters

2 lines of 40 characters

4 line of 20 characters

Possible icons

1

2

4

1/17

1/33

80

6-dot font width

Display Line

Duty Ratio

Single-chip Operation

Numbers

Displayable characters

1 line of 32 characters

2 lines of 32 characters

4 line of 16 characters

Possible icons

1

2

4

1/17

1/33

96

ꢗꢄꢘꢌꢂꢃꢄꢈ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

BLOCK DIAGRAM

ꢆ $ ꢔ ꢀ ꢞ & ꢔ ꢀ ꢞ /

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ꢙ+ꢔꢗꢚ

-ꢌꢅꢌꢇꢘ %ꢄꢇꢄꢈꢊꢃꢛꢈ

ꢗ $ ꢀ $ -

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3 ꢋ ꢌ

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4

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;

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3 &

0 3 4

3 ꢖ ꢖ

% : ꢖ

ꢙ 3 ꢀ ꢀ ꢚ

ꢓ ꢓ ꢓ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

PAD CONFIGURATION

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

129 SEG33

128 SEG32

127 SEG31

126 SEG30

125 SEG29

124 SEG28

123 SEG27

122 SEG26

121 SEG25

120 SEG24

119 SEG23

118 SEG22

117 SEG21

116 SEG20

115 SEG19

114 SEG18

113 SEG17

112 SEG16

111 SEG15

110 SEG14

109 SEG13

108 SEG12

107 SEG11

106 SEG10

105 SEG9

104 SEG8

103 SEG7

102 SEG6

101 SEG5

100 SEG4

99 SEG3

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

SEG75

SEG76

1

2

3

4

5

6

7

8

9

ꢀ

SEG77 10

SEG78 11

SEG79 12

SEG80 13

SEG81 14

SEG82 15

SEG83 16

SEG84 17

SEG85 18

SEG86 19

SEG87 20

SEG88 21

SEG89 22

SEG90 23

SEG91 24

SEG92 25

SEG93 26

SEG94 27

SEG95 28

SEG96 29

SEG97 30

SEG98 31

SEG99 32

SEG100 33

COM9 34

COM10 35

COM11 36

COM12 37

COM13 38

COM14 39

COM15 40

COM16 41

COM25 42

COM26 43

COM27 44

COM28 45

COM29 46

COM30 47

COM31 48

COM32 49

COM33 50

Y

(0, 0)

X

98 SEG2

97 SEG1

96 COM0

chip size : 7450 x 5340

PAD size : 100 x 100

95 COM1

94 COM2

93 COM3

µm

unit

:

92 COM4

91 COM5

90 COM6

89 COM7

88 COM8

87 COM17

86 COM18

85 COM19

84 COM20

83 COM21

82 COM22

81 COM23

80 COM24

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

PAD LOCATION

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ꢎꢑꢒꢓ

ꢔꢕꢖꢇꢒ

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ꢘꢓ

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KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢀꢁꢂꢃꢄꢅꢆ

ꢀꢁꢂ

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ꢇꢊꢋꢌꢉꢅ ꢇꢁꢋꢉ

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ꢇꢇꢌꢐ

ꢇꢒꢋꢎ

ꢏꢗꢐ

ꢇꢋꢇ

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ꢇꢋꢗ

!

ꢈꢉꢊꢋꢑ

ꢍꢗꢑꢑꢏ

ꢍꢇꢌꢇꢎ

!

ꢈꢉꢊꢋꢋ

ꢍꢗꢑꢑꢏ

ꢍꢇꢏꢗꢐ

ꢈꢉꢊꢋꢐ

!

ꢍꢗꢑꢑꢏ

!

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!

ꢌꢇꢎ

!

ꢋꢌꢐ

!

ꢑꢋꢎ

!

ꢓꢗꢐ

!

ꢗꢇꢎ

!

!!

!

ꢇꢌꢐ

!

ꢋꢎ

!

ꢍꢋꢎ

!

ꢍꢇꢌꢐ

ꢍꢗꢇꢎ

ꢍꢓꢗꢐ

ꢍꢑꢋꢎ

ꢍꢋꢌꢐ

ꢍꢌꢇꢎ

ꢍꢏꢗꢐ

ꢍꢇꢒꢋꢎ

ꢍꢇꢇꢌꢐ

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ꢍꢇꢓꢗꢐ

ꢍꢇꢑꢋꢎ

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!

!!

!

ꢀ

"!#ꢞꢈꢒꢒꢐꢑ#!ꢖ$%&'()!*!+$,-!./!0'(1!.2+!34ꢙ!ꢁ/5ꢇꢇꢑ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

PAD DESCRIPTION

PAD (NO)

INPUT/

NAME

DESCRIPTION

INTERFACE

OUTPUT

VDD (51)

VSS1,VSS2

(57,72)

for logical circuit(+3V,+5V)

0V(GND)

-

Power supply Bias voltage level for LCD driving.

Power supply

V1ꢁV5

(79ꢁ75)

Vci (69)

Input

Input voltage to the voltage converter to

generate LCD drive voltage(Vci = 1.0-4.5V).

SEG1ꢁSEG100

(97-163,

Output

Segment output Segment signal output for LCD drive.

LCD

1-33)

Output

Common output Common signal output for LCD drive.

COM0ꢁCOM33

(80ꢁ96,

34ꢁ50)

OSC1,OSC2

(53,52)

Input

(OSC1),

Output

(OSC2)

Input

Oscillator

When use internal oscillator, connect external Rf

resistor.

External

resistor/oscillator

If external clock is used, connect it to OSC1.

(OSC1)

C1,C2 (71,70)

External

To use the voltage converter(2 times /3 times),

these pins must be connected to the external

capacitance.

External

capacitance input

capacitance

RESET (54)

IE (56)

Input

Reset pin

Select pin

of

Initialized to Low

-

When IE = "High", Instruction set is

selected as Table 6.

instruction

set

When IE = "Low", Instruction set is selected as

Table 10.

V5OUT2(73)

V5OUT3(74)

Output

Two times

converter

output

The value of Vci is converted two times. To

use three times converter, the same

capacitance as that of C1-C2 should be

connected here.

V5

capacitance

Three times

converter

output

The value of Vci is converted three times.

V5

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

PAD DESCRIPTION (continued)

PAD (NO)

INPUT/

OUTPUT

Input

NAME

DESCRIPTION

INTERFACE

Select Interface mode with the MPU.

When IM = "Low" : Serial mode,

IM (55)

Interface mode

selection

-

When IM = "High" : 4-bit/8-bit bus mode.

Register select/

Chip select

In bus mode, used as register selection input.

When RS/CS = "High", Data register is selected.

When RS/CS = "Low", Instruction register is

selected.

RS/CS (58)

Input

MPU

In serial mode, used as chip selection input.

When RS/CS = "Low", selected. When RS/CS =

"High", not selected.(Low access enable)

In bus mode, used as read/write selection input.

When RW/SID = "High", read operation. When

RW/SID = "Low", write operation.

RW/SID (59)

Input

Read ꢀ

write/Serial input

data

In serial mode, used for data input pin.

In bus mode, used as read ꢀwrite enable signal.

E/SCLK (60)

MPU

Read ꢀwrite

enable/Serial

clock

In serial mode, used as serial clock input pin.

In 8-bit bus mode, used as lowest bi-directional

data bit. During 4-bit bus mode, Open this pin.

DB0/SOD (61)

Data bus 0

bit/Serial output

data

Input ꢀ

Output/Output

In serial mode, used as serial data output pin. If

not in read operation, open this pin.

In 8-bit bus mode, used as low order bi-

directional data bus.

DB1ꢁDB3

(62ꢁ64)

Input.

Data bus 1 ~ 7

MPU

Output

During 4-bit bus mode or serial mode, open

these pins.

In 8-bit bus mode, used as high order bi-

directional data bus. In case of 4-bit bus mode,

used as both high and low order.

DB4ꢁDB7

(65ꢁ68)

DB7 used for Busy Flag output.

During serial mode, open these pins.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

FUNCTION DESCRIPTION

System Interface

This chip has all three kinds interface type with MPU : serial, 4-bit bus and 8-bit bus. Serial and bus(4-bit/8-bit) is selected by

IM input, and 4-bit bus and 8-bit bus is selected by DL bit in the instruction register.

During read or write operation, two 8-bit registers are used. one is data register (DR), the other is instruction register(IR).

The data register(DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/SEGRAM,

target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done

automatically.

Hence, after MPU reads DR data, the data in the next DDRAM/CGRAM/SEGRAM address is transferred into DR

automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/SEGRAM automatically.

The Instruction register(IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction

data.

To select register, use RS/CS input pin in 4-bit/8-bit bus mode(IM = "High") or RS bit in serial mode(IM = "Low").

Table 2. Various kinds of operations according to RS and R/W bits.

RS

0

R/W

0

Operation

Instruction Write operation (MPU writes Instruction code into IR)

0

1

Read Busy flag(DB7) and address counter (DB0 ꢁ DB6)

Data Write operation (MPU writes data into DR)

Data Read operation (MPU reads data from DR)

1

0

1

Busy Flag (BF)

When BF = "High", it indicates that the internal operation is being processed. So during this time the next instruction cannot

be accepted. BF can be read, when RS = Low and R/W = High(Read Instruction Operation), through DB7 port .

Before executing the next instruction, be sure that BF is not High.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Display Data RAM (DDRAM)

DDRAM stores display data of maximum 80 x 8 bits (80 characters).

DDRAM address is set in the address counter (AC) as a hexadecimal number. (refer to Fig-1.)

ꢘꢙꢚ

ꢏꢐꢑ

ꢛꢙꢚ

ꢏꢐꢗ

ꢏꢐꢒ

ꢏꢐꢓ

ꢏꢐꢔ

ꢏꢐꢕ

ꢏꢐꢖ

Fig-1. DDRAM Address

1) Display of 5-dot font width character

ꢂ 5-dot 1 line display

In the case of 1 line display with 5-dot font, the address range of DDRAM is 00H ꢁ 4FH.

(Refer to Fig-2)

ꢕ

ꢖ ꢗ ꢘ ꢍ ꢙ ꢌ ꢚ ꢛ ꢕꢋ ꢕꢕ ꢕꢖ ꢕꢗ ꢕꢘ ꢕꢍ ꢕꢙ ꢕꢌ ꢕꢚ ꢕꢛ ꢖꢋ

ꢅꢆꢇꢃ

ꢅꢆꢇꢈ

ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢀ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ ꢂꢏ ꢂꢁ ꢃꢂ ꢃꢃ ꢃꢄ ꢃꢅ

ꢀꢁꢂꢃꢄꢄ

ꢀꢒꢈꢜꢝꢄꢞ ꢜ ꢈꢒꢐꢒ !

ꢀꢁꢂꢃ

ꢉꢊꢋꢋꢌꢍ

ꢖꢕ ꢖꢖ ꢖꢗ ꢖꢘ ꢖꢍ ꢖꢙ ꢖꢌ ꢖꢚ ꢖꢛ ꢗꢋ ꢗꢕ ꢗꢖ ꢗꢗ ꢗꢘ ꢗꢍ ꢗꢙ ꢗꢌ ꢗꢚ ꢗꢚ ꢘꢋ

ꢅꢆꢇꢉ

ꢃꢀ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢊ ꢃꢋ ꢃꢌ ꢃꢍ ꢃꢎ ꢃꢏ ꢃꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢀ ꢄꢆ ꢄꢇ ꢄꢈ

ꢅꢆꢇꢃꢊ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢄ

ꢀꢀꢁꢂꢃ ꢄꢅꢅꢆꢇꢈꢈꢈ

ꢉꢊꢋꢋꢌꢍ

ꢕ

ꢖ

ꢗ

ꢘ

ꢍ

ꢙ

ꢌ

ꢚ

ꢛ

ꢕꢋ ꢕꢕ ꢕꢖ ꢕꢗ ꢕꢘ ꢕꢍ ꢕꢙ ꢕꢌ ꢕꢚ ꢕꢛ ꢖꢋ

ꢅꢆꢇꢃ

ꢅꢆꢇꢈ

ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢀ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ ꢂꢏ ꢂꢁ ꢃꢂ ꢃꢃ ꢃꢄ ꢃꢅ ꢃꢀ

ꢖꢕ ꢖꢖ ꢖꢗ ꢖꢘ ꢖꢍ ꢖꢙ ꢖꢌ ꢖꢚ ꢖꢛ ꢗꢋ ꢗꢕ ꢗꢖ ꢗꢗ ꢗꢘ ꢗꢍ ꢗꢙ ꢗꢌ ꢗꢚ ꢗꢚ ꢘꢋ

ꢅꢆꢇꢉ

ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢊ ꢃꢋ ꢃꢌ ꢃꢍ ꢃꢎ ꢃꢏ ꢃꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢀ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ

ꢅꢆꢇꢃꢊ

ꢎꢂꢏꢐꢇꢆ ꢊꢑꢒꢏꢐ "ꢇꢏꢐꢔ

ꢕ

ꢖ

ꢗ

ꢘ

ꢍ

ꢙ

ꢌ

ꢚ

ꢛ

ꢕꢋ ꢕꢕ ꢕꢖ ꢕꢗ ꢕꢘ ꢕꢍ ꢕꢙ ꢕꢌ ꢕꢚ ꢕꢛ ꢖꢋ

ꢀꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢀ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ ꢂꢏ ꢂꢁ ꢃꢂ ꢃꢃ ꢃꢄ

ꢀꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢀ ꢂꢆ ꢂꢇ

ꢅꢆꢇꢃ

ꢅꢆꢇꢈ

ꢖꢕ ꢖꢖ ꢖꢗ ꢖꢘ ꢖꢍ ꢖꢙ ꢖꢌ ꢖꢚ ꢖꢛ ꢗꢋ ꢗꢕ ꢗꢖ ꢗꢗ ꢗꢘ ꢗꢍ ꢗꢙ ꢗꢌ ꢗꢚ ꢗꢚ ꢘꢋ

ꢅꢆꢇꢉ

ꢃꢌ ꢃꢍ ꢃꢎ ꢃꢏ ꢃꢁ ꢄꢂ

ꢃꢅ ꢃꢀ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢊ ꢃꢋ

ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢀ ꢄꢆ ꢄꢇ

ꢅꢆꢇꢃꢊ

ꢎꢂꢏꢐꢇꢆ ꢊꢑꢒꢏꢐ ꢁꢒꢓꢑꢐꢔ

Fig-2. 1-line X 40ch. display

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢃ 5-dot 2 line display

In the case of 2 line display with 5-dot font, the address range of DDRAM is 00H ꢁ 27H, 40H ꢁ 67H. (Refer to Fig-3)

D

E

F

G

C

H

B

I

J

DA DD DE DF DG DC DH DB DI DJ EA

ꢅꢆꢇꢃ

ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ

ꢅꢆꢇꢈ

ꢅꢆꢇꢃꢋ

ꢅꢆꢇꢌꢍ

ꢄꢀ ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ ꢅꢀ ꢅꢁ ꢅꢂ ꢅꢃ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢄ

6K>LM:N LO>KPKOQ

?@AABC

ED EE EF EG EC EH EB EI EJ FA FD FE FF FG FC FH FB FI FJ GA

ꢅꢆꢇꢉ

ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ ꢁꢋ ꢁꢌ ꢁꢍ ꢁꢎ ꢁꢏ ꢂꢀ ꢂꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢆ ꢂꢇ

ꢅꢆꢇꢃꢊ

ꢅꢆꢇꢌꢎ

ꢅꢄ ꢅꢅ ꢅꢆ ꢅꢇ ꢅꢈ ꢅꢉ ꢅꢊ ꢅꢋ ꢅꢌ ꢅꢍ ꢅꢎ ꢅꢏ ꢆꢀ ꢆꢁ ꢆꢂ ꢆꢃ ꢆꢄ ꢆꢅ ꢆꢆ ꢆꢇ

ꢅꢆꢇꢏꢌ

ꢀꢁꢂꢃꢄꢄ

ꢀꢁꢂꢃ

66789 :;;<=>>>

?@AABC

D

E

F

G

C

H

B

I

J

DA DD DE DF DG DC DH DB DI DJ EA

ꢅꢆꢇꢃ

ꢅꢆꢇꢈ

ꢅꢆꢇꢃꢋ

ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ

ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ ꢅꢀ ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ

ꢅꢆꢇꢌꢍ

ED EE EF EG EC EH EB EI EJ FA FD FE FF FG FC FH FB FI FJ GA

ꢅꢆꢇꢉ

ꢀꢁ ꢀꢂ

ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ

ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ

ꢀꢋ ꢌꢍ ꢌꢀ ꢌꢌ

ꢌꢎ ꢌꢏ ꢌꢁ ꢌꢂ

ꢌꢃ ꢍꢍ

ꢅꢆꢇꢃꢊ

ꢅꢆꢇꢌꢎ

ꢁꢁ ꢁꢂ

ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ

ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ

ꢁꢋ ꢂꢍ ꢂꢀ ꢂꢌ

ꢂꢎ ꢂꢏ ꢂꢁ ꢂꢂ

ꢂꢃ ꢏꢍ

ꢅꢆꢇꢏꢌ

R8SP=< @TKSP U=SPV

D

E

F

G

C

H

B

I

J

DA DD DE DF DG DC DH DB DI DJ EA

ꢅꢆꢇꢃ

ꢅꢆꢇꢈ

ꢅꢆꢇꢃꢋ

ꢂꢇ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ ꢁꢁ ꢁꢂ

ꢆꢇ ꢄꢀ ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ ꢅꢀ ꢅꢁ ꢅꢂ

ꢅꢆꢇꢌꢍ

ED EE EF EG EC EH EB EI EJ FA FD FE FF FG FC FH FB FI FJ GA

ꢅꢆꢇꢉ

ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ ꢁꢋ ꢁꢌ ꢁꢍ ꢁꢎ ꢁꢏ ꢂꢀ ꢂꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢆ

ꢅꢆꢇꢃꢊ

ꢅꢆꢇꢌꢎ

ꢅꢃ ꢅꢄ ꢅꢅ ꢅꢆ ꢅꢇ ꢅꢈ ꢅꢉ ꢅꢊ ꢅꢋ ꢅꢌ ꢅꢍ ꢅꢎ ꢅꢏ ꢆꢀ ꢆꢁ ꢆꢂ ꢆꢃ ꢆꢄ ꢆꢅ ꢆꢆ

ꢅꢆꢇꢏꢌ

R8SP=< @TKSP 7KWTPV

Fig-3. 2-line X 40ch. display (5-dot font width)

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢄ 5-dot 4 line display

In the case of 4 line display with 5-dot font, the address range of DDARM is 00H ꢁ 13H, 20H ꢁ 33H, 40H ꢁ 53H,

60H ꢁ 73H. (Refer to Fig-4)

ꢊꢋꢌꢍꢎꢏꢐ ꢍꢑꢌꢋꢒꢋꢑꢓ

ꢊꢊꢔꢕꢖ ꢏꢗꢗꢘꢙꢌꢌꢌ

ꢀ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ

ꢅꢆꢇꢃ

ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ

ꢂꢀ ꢂꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ ꢂꢏ ꢃꢀ ꢃꢁ ꢃꢂ ꢃꢃ

ꢄꢀ ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ ꢅꢀ ꢅꢁ ꢅꢂ ꢅꢃ

ꢆꢀ ꢆꢁ ꢆꢂ ꢆꢃ ꢆꢄ ꢆꢅ ꢆꢆ ꢆꢇ ꢆꢈ ꢆꢉ ꢆꢊ ꢆꢋ ꢆꢌ ꢆꢍ ꢆꢎ ꢆꢏ ꢇꢀ ꢇꢁ ꢇꢂ ꢇꢃ

ꢅꢆꢇꢎ

ꢅꢆꢇꢈ

ꢅꢆꢇꢃꢏ

ꢅꢆꢇꢃꢉ

ꢅꢆꢇꢊꢋ

ꢅꢆꢇꢊꢌ

ꢅꢆꢇꢍꢊ

ꢀꢁꢂꢃ

ꢀꢁꢂꢃꢄꢄ

ꢚꢛꢉꢉꢆꢄ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ

ꢅꢆꢇꢃ

ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢀꢀ

ꢅꢆꢇꢎ

ꢅꢆꢇꢈ

ꢂꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ ꢂꢏ ꢃꢀ ꢃꢁ ꢃꢂ ꢃꢃ ꢂꢀ

ꢅꢆꢇꢃꢏ

ꢅꢆꢇꢃꢉ

ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ ꢅꢀ ꢅꢁ ꢅꢂ ꢅꢃ

ꢄꢀ

ꢅꢆꢇꢊꢋ

ꢅꢆꢇꢊꢌ

ꢆꢁ ꢆꢂ ꢆꢃ ꢆꢄ ꢆꢅ ꢆꢆ ꢆꢇ ꢆꢈ ꢆꢉ ꢆꢊ ꢆꢋ ꢆꢌ ꢆꢍ ꢆꢎ ꢆꢏ ꢇꢀ ꢇꢁ ꢇꢂ ꢇꢃ

ꢆꢀ

ꢅꢆꢇꢍꢊ

ꢜꢕꢝꢒꢙꢘ ꢛꢞꢋꢝꢒ ꢙꢝꢒ!

ꢀ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ

ꢅꢆꢇꢃ

ꢁꢃ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ ꢁꢁ ꢁꢂ

ꢃꢃ ꢂꢀ ꢂꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ ꢂꢏ ꢃꢀ ꢃꢁ ꢃꢂ

ꢅꢃ ꢄꢀ ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ ꢅꢀ ꢅꢁ ꢅꢂ

ꢅꢆꢇꢎ

ꢅꢆꢇꢈ

ꢅꢆꢇꢃꢏ

ꢅꢆꢇꢃꢉ

ꢅꢆꢇꢊꢋ

ꢅꢆꢇꢊꢌ

ꢇꢃ ꢆꢀ ꢆꢁ ꢆꢂ ꢆꢃ ꢆꢄ ꢆꢅ ꢆꢆ ꢆꢇ ꢆꢈ ꢆꢉ ꢆꢊ ꢆꢋ ꢆꢌ ꢆꢍ ꢆꢎ ꢆꢏ ꢇꢀ ꢇꢁ ꢇꢂ

ꢅꢆꢇꢍꢊ

ꢜꢕꢝꢒꢙꢘ ꢛꢞꢋꢝꢒ ꢔꢋ"ꢞꢒ!

Fig-4. 4-line X 20ch.

display (5-dot font width)

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

2) Display of 6-dot font width character

When this device is used in 6-dot font width mode, SEG97,SEG98,SEG99 and SEG100

must be open.

ꢂ 6-dot 1 line display

In the case of 1 line display with 6-dot font, the address range of DDRAM is 00H ꢁ 4FH.

(Refer to Fig-5)

ꢊꢋꢌꢍꢎꢏꢐ ꢍꢑꢌꢋꢒꢋꢑꢓ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢂꢉ ꢂꢀ ꢂꢁ

ꢀ

ꢞꢔ &

ꢞꢔ ꢐ

ꢞꢔ )

ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ

ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ ꢁꢋ ꢁꢌ ꢁꢍ ꢁꢎ ꢁꢏ

ꢞꢔ &'

ꢀ$%&

ꢀ$%)'

ꢊꢊꢔꢕꢖ ꢏꢗꢗꢘꢙꢌꢌꢌ

ꢚꢛꢉꢉꢆꢄ

ꢀ$%)' ꢀ$%&

ꢚꢛꢉꢉꢆꢄ

ꢀ

ꢁ

ꢂ

ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢂꢉ ꢂꢀ ꢂꢁ

ꢞꢔ &

ꢞꢔ ꢐ

ꢞꢔ )

ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ

ꢜꢕꢝꢒꢙꢘ ꢛꢞꢋꢝꢒ ꢙꢝꢒ!

ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢂꢉ ꢂꢀ ꢂꢁ

ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ ꢁꢋ ꢁꢌ ꢁꢍ ꢁꢎ ꢁꢏ ꢂꢀ

ꢞꢔ &'

ꢀ

ꢁ

ꢂ

ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ

ꢞꢔ &

ꢞꢔ ꢐ

ꢞꢔ )

ꢄꢏ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ

ꢀꢏ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ ꢁꢋ ꢁꢌ ꢁꢍ ꢁꢎ

ꢞꢔ &'

ꢜꢕꢝꢒꢙꢘ ꢛꢞꢋꢝꢒ ꢔꢋ"ꢞꢒ!

Fig-5. 1-line X 32ch. display

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢃ 6-dot 2 line display

In the case of 2 line display with 6-dot font, the address range of DDRAM is 00H ꢁ 27H, 40H ꢁ 67H. (refer to Fig-6)

ꢊꢋꢌꢍꢎꢏꢐ ꢍꢑꢌꢋꢒꢋꢑꢓ

ꢀ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢂꢉ ꢂꢀ ꢂꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢅ

ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ

ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ ꢁꢋ ꢁꢌ ꢁꢍ ꢁꢎ ꢁꢏ

ꢀꢁꢂꢄ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢈꢋ

ꢀꢁꢂꢃꢇ

ꢄꢀ ꢄꢁ ꢄꢄ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ

ꢅꢀ ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ ꢅꢅ ꢅꢆ ꢅꢇ ꢅꢈ ꢅꢉ ꢅꢊ ꢅꢋ ꢅꢌ ꢅꢍ ꢅꢎ ꢅꢏ

ꢀꢁꢂꢊꢈ

ꢌꢍꢎꢅꢆ

ꢀꢁꢂꢈꢉ

ꢌꢍꢎꢃ

ꢊꢊꢔꢕꢖ ꢏꢗꢗꢘꢙꢌꢌꢌ

!ꢜꢉꢉꢆꢄ

ꢌꢍꢎꢅꢆ ꢌꢍꢎꢃ

!ꢜꢉꢉꢆꢄ

ꢀ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢂꢉ ꢂꢀ ꢂꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢅ

ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ

ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ ꢁꢋ ꢁꢌ ꢁꢍ ꢁꢎ ꢁꢏ ꢂꢀ

ꢀꢁꢂꢄ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢈꢋ

ꢀꢁꢂꢃꢇ

ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ ꢅꢀ

ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ ꢅꢅ ꢅꢆ ꢅꢇ ꢅꢈ ꢅꢉ ꢅꢊ ꢅꢋ ꢅꢌ ꢅꢍ ꢅꢎ ꢅꢏ ꢆꢀ

ꢀꢁꢂꢊꢈ

ꢀꢁꢂꢈꢉ

ꢚꢕꢛꢒꢙꢘ ꢜꢝꢋꢛꢒ ꢞꢙꢛꢒ

ꢀ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢁꢉ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢂꢉ ꢂꢀ ꢂꢁ

ꢀꢁꢂꢃ

ꢀꢁꢂꢅ

ꢂꢇ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ

ꢀꢏ ꢁꢀ ꢁꢁ ꢁꢂ ꢁꢃ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢊ ꢁꢋ ꢁꢌ ꢁꢍ ꢁꢎ

ꢀꢁꢂꢄ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢈꢋ

ꢀꢁꢂꢃꢇ

ꢆꢇ ꢄꢀ ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ

ꢄꢏ ꢅꢀ ꢅꢁ ꢅꢂ ꢅꢃ ꢅꢄ ꢅꢅ ꢅꢆ ꢅꢇ ꢅꢈ ꢅꢉ ꢅꢊ ꢅꢋ ꢅꢌ ꢅꢍ ꢅꢎ

ꢀꢁꢂꢊꢈ

ꢀꢁꢂꢈꢉ

ꢚꢕꢛꢒꢙꢘ ꢜꢝꢋꢛꢒ ꢔꢋ"ꢝꢒ

Fig-6. 2-line X 32ch. display (6-dot font width)

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢄ 6-dot 4 line display

In the case of 4 line display with 6-dot font, the address range of DDARM is 00H ꢁ 13H, 20H ꢁ 33H, 40H ꢁ 53H,

60H ꢁ 73H. (refer to Fig-7)

ꢀ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ

ꢊꢋꢌꢍꢎꢏꢐ ꢍꢑꢌꢋꢒꢋꢑꢓ

ꢊꢊꢔꢕꢖ ꢏꢗꢗꢘꢙꢌꢌꢌ

ꢀꢁꢂꢃ

ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ

ꢂꢀ ꢂꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ ꢂꢏ

ꢄꢀ ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ

ꢆꢀ ꢆꢁ ꢆꢂ ꢆꢃ ꢆꢄ ꢆꢅ ꢆꢆ ꢆꢇ ꢆꢈ ꢆꢉ ꢆꢊ ꢆꢋ ꢆꢌ ꢆꢍ ꢆꢎ ꢆꢏ

ꢀꢁꢂꢄ

ꢀꢁꢂꢅ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢃꢇ

ꢀꢁꢂꢈꢉ

ꢀꢁꢂꢈꢋ

ꢀꢁꢂꢊꢈ

ꢌꢍꢎꢅꢆ

ꢌꢍꢎꢃ

ꢚꢛꢉꢉꢆꢄ

ꢀ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ

ꢀꢁꢂꢃ

ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ ꢀꢏ ꢁꢀ

ꢂꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ ꢂꢏ ꢃꢀ

ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ ꢄꢏ ꢅꢀ

ꢀꢁꢂꢄ

ꢀꢁꢂꢅ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢃꢇ

ꢀꢁꢂꢈꢉ

ꢀꢁꢂꢈꢋ

ꢆꢁ ꢆꢂ ꢆꢃ ꢆꢄ ꢆꢅ ꢆꢆ ꢆꢇ ꢆꢈ ꢆꢉ ꢆꢊ ꢆꢋ ꢆꢌ ꢆꢍ ꢆꢎ ꢆꢏ ꢇꢀ

ꢀꢁꢂꢊꢈ

ꢜꢕꢝꢒꢙꢘ ꢛꢞꢋꢝꢒ ꢙꢝꢒ!

ꢀ

ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ ꢇ ꢈ ꢀꢉ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ

ꢀꢁꢂꢃ

ꢁꢃ ꢀꢀ ꢀꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢇ ꢀꢈ ꢀꢉ ꢀꢊ ꢀꢋ ꢀꢌ ꢀꢍ ꢀꢎ

ꢃꢃ ꢂꢀ ꢂꢁ ꢂꢂ ꢂꢃ ꢂꢄ ꢂꢅ ꢂꢆ ꢂꢇ ꢂꢈ ꢂꢉ ꢂꢊ ꢂꢋ ꢂꢌ ꢂꢍ ꢂꢎ

ꢅꢃ ꢄꢀ ꢄꢁ ꢄꢂ ꢄꢃ ꢄꢄ ꢄꢅ ꢄꢆ ꢄꢇ ꢄꢈ ꢄꢉ ꢄꢊ ꢄꢋ ꢄꢌ ꢄꢍ ꢄꢎ

ꢀꢁꢂꢄ

ꢀꢁꢂꢅ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢃꢇ

ꢀꢁꢂꢈꢉ

ꢀꢁꢂꢈꢋ

ꢇꢃ ꢆꢀ ꢆꢁ ꢆꢂ ꢆꢃ ꢆꢄ ꢆꢅ ꢆꢆ ꢆꢇ ꢆꢈ ꢆꢉ ꢆꢊ ꢆꢋ ꢆꢌ ꢆꢍ ꢆꢎ

ꢀꢁꢂꢊꢈ

ꢜꢕꢝꢒꢙꢘ ꢛꢞꢋꢝꢒ ꢔꢋ"ꢞꢒ!

Fig-7. 4-line X 16ch. display (6-dot font width)

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Timing Generation Circuit

Timing generation circuit generates clock signals for the internal operations.

Address Counter (AC)

Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from IR.

After writing into (reading from) DDRAM/CGRAM/SEGRAM, AC is automatically increased (decreased) by 1.

When RS = "Low" and R/W = "High", AC can be read through DB0ꢁDB6 ports

Cursor/Blink Control Circuit

It controls cursor/blink ON/OFF and black/white inversion at cursor position.

LCD Driver Circuit

LCD Driver circuit has 34 common and 100 segment signals for LCD driving.

Data from SEGRAM/CGRAM/CGROM is transferred to 100-bit segment latch serially, which is stored to 100-bit shift latch.

When each common is selected by 34-bit common register, segment data also output through segment driver from 100-bit segment

latch.

In 1-line display mode, COM0 ꢁ COM17 have 1/17 duty, and in 2-line or 4-line mode, COM0-COM33 have 1/33 duty

ratio.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

CGROM (Character Generator ROM)

CGROM has 5 X 8-dot 240 character pattern. (refer to Table 3)

Table 3. CGROM Character Code Table

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

CGRAM (Character Generator RAM)

CGRAM has up to 5 X 8-dot 8 characters. By writing font data to CGRAM, user defined character can be used.

(Refer to Table 4)

Table 4. Relationship between Character Code(DDRAM) and Character Pattern(CGRAM)

1) 5x8 dot Character pattern

ꢀꢁꢂꢃꢂꢄꢅꢆꢃ ꢀꢇꢈꢆꢉꢊꢊꢋꢌꢍ ꢈꢂꢅꢂꢎ

ꢀꢏꢋꢌꢍ ꢂꢈꢈꢃꢆꢐꢐ

ꢀꢏꢋꢌꢍ ꢈꢂꢅꢂ

ꢑꢂꢅꢅꢆꢃꢒ

ꢒꢓꢔꢕꢆꢃ

ꢊꢖ ꢊꢗ ꢊꢘ ꢊꢙ ꢊꢚ ꢊꢛ ꢊꢜ ꢊꢝ ꢌꢘ ꢌꢙ ꢌꢚ ꢌꢛ ꢌꢜ ꢌꢝ

ꢑꢖ ꢑꢗ ꢑꢘ ꢑꢙ ꢑꢚ ꢑꢛ ꢑꢜ ꢑꢝ

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ꢞ

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ꢜ ꢝ

ꢞ

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"ꢂꢅꢅꢆꢃꢒ ꢜ

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"ꢂꢅꢅꢆꢃꢒ $

ꢝ

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KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

2) 6x8 dot Character pattern

ꢐꢜꢝꢞꢝ !"ꢞ ꢐ#$"%&&'ꢏꢘ$ꢝ!ꢝ(

ꢐ)'ꢏꢘ ꢝ$$ꢞ"**

ꢐ)'ꢏꢘ $ꢝ!ꢝ

+ꢝ!!"ꢞ,

,-./"ꢞ

&0 &ꢑ &ꢒ &ꢓ &ꢔ &ꢕ &ꢖ &ꢗ ꢏꢒ ꢏꢓ ꢏꢔ ꢏꢕ ꢏꢖ ꢏꢗ

+0 +ꢑ +ꢒ +ꢓ +ꢔ +ꢕ +ꢖ +ꢗ

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1

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3ꢝ!!"ꢞ, 5

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1. When BE(Blink Enable bit) = “HIGH”, blink is controlled by B1 and B0 bit.

In displaying 5-dot font width, when B1 = "1", enabled dots of P0 ꢁ P4 will blink, and

when B1 = "0" and B0 = "1", enabled dots in P4 will blink, when B1 = "0" and

B0 = "0", blink will not happen.

In displaying 6-dot font width, when B1 = "1", enabled dots of P0 ꢁ P5 will blink, and

when B1 = "0" and B0 = "1", enabled dots of P5 will blink, when B1 = "0" and

B0 = "0", blink will not happen.

2. "X" : Don't care

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

SEGRAM (Segment Icon RAM)

SEGRAM has segment control data and segment pattern data. During 1-line display mode, COM0(COM17) makes

the data of SEGRAM enable to display icons. When used in 2/4-line display mode COM0(COM33) does that.

Its higher 2-bits are blinking control data, and lower 6-bits are pattern data. (refer to Table 5 and Fig-8)

Table 5. Relationship between SEGRAM address and display pattern

ꢀꢁꢂꢃꢄꢅ ꢆꢇꢇꢈꢉꢊꢊ

ꢀꢁꢂꢃꢄꢅ ꢇꢆꢋꢆ ꢇꢌꢊꢍꢎꢆꢏ ꢍꢆꢋꢋꢉꢈꢐ

ꢑꢒꢇꢓꢋ ꢔꢓꢐꢋ ꢕꢌꢇꢋꢖ

ꢄꢘ ꢄꢙ ꢄꢚ ꢄꢛ ꢜꢝ ꢜꢗ ꢜꢑ ꢜꢞ ꢜꢘ ꢜꢙ ꢜꢚ ꢜꢛ

ꢗꢒꢇꢓꢋ ꢔꢓꢐꢋ ꢕꢌꢇꢋꢖ

ꢜꢝ ꢜꢗ ꢜꢑ ꢜꢞ ꢜꢘ ꢜꢙ ꢜꢚ ꢜꢛ

ꢚ ꢛ ꢀꢚ ꢀꢙ ꢀꢘ ꢀꢞ ꢀꢑ ꢀꢗ

ꢚ ꢛ ꢀꢝ ꢀ" ꢀ# ꢀꢚꢛ ꢀꢚꢚ ꢀꢚꢙ

ꢚ ꢛ ꢀꢚꢘ ꢀꢚꢞ ꢀꢚꢑ ꢀꢚꢗ ꢀꢚꢝ ꢀꢚ"

ꢚ ꢛ ꢀꢚ# ꢀꢙꢛ ꢀꢙꢚ ꢀꢙꢙ ꢀꢙꢘ ꢀꢙꢞ

ꢚ ꢛ ꢀꢙꢑ ꢀꢙꢗ ꢀꢙꢝ ꢀꢙ" ꢀꢙ# ꢀꢘꢛ

ꢚ ꢛ ꢀꢘꢚ ꢀꢘꢙ ꢀꢘꢘ ꢀꢘꢞ ꢀꢘꢑ ꢀꢘꢗ

ꢚ ꢛ ꢀꢘꢝ ꢀꢘ" ꢀꢘ# ꢀꢞꢛ ꢀꢞꢚ ꢀꢞꢙ

ꢚ ꢛ ꢀꢞꢘ ꢀꢞꢞ ꢀꢞꢑ ꢀꢞꢗ ꢀꢞꢝ ꢀꢞ"

ꢚ ꢛ ꢀꢞ# ꢀꢑꢛ ꢀꢑꢚ ꢀꢑꢙ ꢀꢑꢘ ꢀꢑꢞ

ꢚ ꢛ ꢀꢑꢑ ꢀꢑꢗ ꢀꢑꢝ ꢀꢑ" ꢀꢑ# ꢀꢗꢛ

ꢚ ꢛ ꢀꢗꢚ ꢀꢗꢙ ꢀꢗꢘ ꢀꢗꢞ ꢀꢗꢑ ꢀꢗꢗ

ꢚ ꢛ ꢀꢗꢝ ꢀꢗ" ꢀꢗ# ꢀꢝꢛ ꢀꢝꢚ ꢀꢝꢙ

ꢚ ꢛ ꢀꢝꢘ ꢀꢝꢞ ꢀꢝꢑ ꢀꢝꢗ ꢀꢝꢝ ꢀꢝ"

ꢚ ꢛ ꢀꢝ# ꢀ"ꢛ ꢀ"ꢚ ꢀ"ꢙ ꢀ"ꢘ ꢀ"ꢞ

ꢛ

ꢚ

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!

ꢀꢚ ꢀꢙ ꢀꢘ ꢀꢞ ꢀꢑ

ꢀꢗ ꢀꢝ ꢀ" ꢀ# ꢀꢚꢛ

ꢀꢚꢚ ꢀꢚꢙ ꢀꢚꢘ ꢀꢚꢞ ꢀꢚꢑ

ꢀꢚꢗ ꢀꢚꢝ ꢀꢚ" ꢀꢚ# ꢀꢙꢛ

ꢀꢙꢚ ꢀꢙꢙ ꢀꢙꢘ ꢀꢙꢞ ꢀꢙꢑ

ꢀꢙꢗ ꢀꢙꢝ ꢀꢙ" ꢀꢙ# ꢀꢘꢛ

ꢀꢘꢚ ꢀꢘꢙ ꢀꢘꢘ ꢀꢘꢞ ꢀꢘꢑ

ꢀꢘꢗ ꢀꢘꢝ ꢀꢘ" ꢀꢘ# ꢀꢞꢛ

ꢀꢞꢚ ꢀꢞꢙ ꢀꢞꢘ ꢀꢞꢞ ꢀꢞꢑ

ꢀꢞꢗ ꢀꢞꢝ ꢀꢞ" ꢀꢞ# ꢀꢑꢛ

ꢀꢑꢚ ꢀꢑꢙ ꢀꢑꢘ ꢀꢑꢞ ꢀꢑꢑ

ꢀꢑꢗ ꢀꢑꢝ ꢀꢑ" ꢀꢑ# ꢀꢗꢛ

ꢀꢗꢚ ꢀꢗꢙ ꢀꢗꢘ ꢀꢗꢞ ꢀꢗꢑ

ꢀꢗꢗ ꢀꢗꢝ ꢀꢗ" ꢀꢗ# ꢀꢝꢛ

ꢚ

ꢛ

ꢚ

ꢚ ꢛ

!

ꢀꢝꢚ ꢀꢝꢙ ꢀꢝꢘ ꢀꢝꢞ ꢀꢝꢑ

ꢀꢝꢗ ꢀꢝꢝ ꢀꢝ" ꢀꢝ# ꢀ"ꢛ

ꢚ ꢛ ꢀ"ꢑ ꢀ"ꢗ ꢀ"ꢝ ꢀ"" ꢀ"# ꢀ#ꢛ

ꢚ ꢛ ꢀ#ꢚ ꢀ#ꢙ ꢀ#ꢘ ꢀ#ꢞ ꢀ#ꢑ ꢀ#ꢗ

ꢅ 1. B1, B0 : Blinking control bit

Control Bit

Blinking Port

BE B1 B0

5-dot font width

No blink

D4

6-dot font width

No blink

D5

0

1

X

0

1

X

0

1

X

D4 ~ D0

D5 ~ D0

2. S1~S80 : Icon pattern ON/OFF in 5-dot font width

S1~S96 : Icon pattern ON/OFF in 6-dot font width

3. "X" : Don't care

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢚ$ ꢑꢒꢇꢓꢋ ꢔꢓꢐꢋ ꢕꢌꢇꢋꢖ %&' ( ꢛ$

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ꢂꢋꢈ ꢂꢋꢉ ꢂꢋꢊ ꢂꢋꢋ ꢂꢃꢌꢌ

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ꢂꢊꢇ ꢂꢊꢈ ꢂꢊꢉ ꢂꢊꢊ ꢂꢊꢋ ꢂꢋꢌ ꢂꢋꢃ ꢂꢋꢄ ꢂꢋꢅ ꢂꢋꢆ ꢂꢋꢇ ꢂꢋꢈ

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ꢆ

ꢇ

ꢀ

ꢁ

ꢂ

ꢆ

ꢀ

ꢁ

ꢂ

ꢆ

ꢅ

ꢀ

ꢁ

ꢂ

ꢅ

ꢄ

ꢀ

ꢁ

ꢂ

ꢅ

ꢃ

ꢀ

ꢁ

ꢂ

ꢅ

ꢌ

ꢀ

ꢁ

ꢂ

ꢅ

ꢋ

ꢀ

ꢁ

ꢂ

ꢅ

ꢊ

ꢀ

ꢁ

ꢂ

ꢅ

ꢉ

ꢀ

ꢁ

ꢂ

ꢅ

ꢈ

ꢀꢀꢀ

Fig-8. Relationship between SEGRAM and segment display

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

INSTRUCTION DESCRIPTION

OUTLINE

To overcome the speed difference between internal clock of KS0075 and MPU clock, KS0075performs internal operation by

storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of

read/write and data bus. (refer to Table 6/10)

Instruction can be divided largely four kinds,

(1) KS0075 function set instructions ( set display methods, set data length, etc.)

(2) address set instructions to internal RAM

(3) data transfer instructions with internal RAM

(4) others .

The address of internal RAM is automatically increased or decreased by 1.

When IE = "High", KS0075 is operated according to Instruction Set 1(Table 6) and

when IE = "Low", KS0075 is operated according to Instruction Set 2(Table 10).

* Note : During internal operation, Busy Flag (DB7) is read High. Busy Flag check must

precede the next instruction.

When an MPU program with Busy Flag(DB7) checking is made, 1/2 fosc (is necessary) for executing the next

instruction by the falling edge of the “E” signal after the Busy Flag(DB7) goes to “Low”.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(1) INSTRUCTION DESCRIPTION 1 (IE = "High")

Table 6. Instruction Set 1

Execution

Time

Instruction RE

Instruction Code

Description

(fosc =

R

S

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270 kHz)

Clear

Write "20H" to DDRAM. and set

DDRAM address to "00H" from AC.

X

0

1

1.53ms

Display

Return

Set DDRAM address to "00H" from AC

and return cursor to its original position

if shifted. The contents of DDRAM are

not changed.

Home

0

1

X

Power

Down

Mode

Set power down mode bit.

PD = "1" :power down mode set,

PD = "0" :power down mode disable

Assign cursor moving direction.

I/D = "1" : increment,

0

1

PD

39µs

I/D = "0" : decrement

Entry

Mode

Set

and display shift enable bit.

S = "1" : make display shift of the

enabled lines by the DS4

0

I/D

S

39 µs

- DS1 bits in the Shift Enable

instruction.

S = "0":display shift disable

Segment bi-direction function.

BID = "1" : Seg100 → Seg1,

BID = "0" : Seg1 → Seg100.

Set display/cursor/blink on/off

D = "1" : display on,

1

0

1

BID

D = "0" : display off,

Display

ON/OFF

Control

D

C

B

39 µs

C = "1" : cursor on,

C = "0" : cursor off,

B = "1" : blink on,

B = "0" : blink off.

Assign font width, black/white inverting

of cursor, and 4-line display mode

control bit.

FW = "1" : 6-dot font width,

FW = "0" : 5-dot font width,

B/W = "1" : black/white inverting of

cursor enable,

Extended

function

set

1

0

1

FW B/W NW

39 µs

B/W = "0" : black/white inverting of

cursor disable

NW = "1" : 4-line display mode,

NW = "0" : 1-line or 2-line display

mode.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(Table 6. continued)

Execution

Instruction Code

Instruction RE

Cursor

Description

Time

(fosc =

R

S

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270 kHz)

Cursor or display shift.

S/C = "1" : display shift,

S/C = "0" : cursor shift,

R/L = "1" : shift to right,

or

0

1

S/C R/L

X

39 µs

Display

Shift

R/L = "0" : shift to left.

(when DH = "1")

Determine the line for display shift .

DS1 = "1/0": 1st line display shift

enable/disable

DS2 = "1/0": 2nd line display shift

enable/disable

Shift

1

0

DS4 DS3 DS2 DS1

39 µs

Enable

DS3 = "1/0": 3rd line display shift

enable/disable

DS4 = "1/0": 4th line display shift

enable/disable.

(when DH = "0")

Determine the line for horizontal smooth

scroll.

HS1 = "1/0" : 1st line dot scroll

enable/disable

HS2 = "1/0" : 2nd line dot scroll

enable/disable

Scroll

1

0

1

HS4 HS3 HS2 HS1

39 µs

Enable

HS3 = "1/0" : 3rd line dot scroll

enable/disable

HS4 = "1/0" : 4th line dot scroll

enable/disable.

Set interface data length

(DL = "1" : 8-bit, DL = "0" : 4-bit),

numbers of display line when

NW = "0",

(N = "1" : 2-line, N = "0" : 1-line),

extension register, RE("0"),

shift/scroll enable

DH = "1" : display shift enable

DH = "0" : dot scroll enable.

reverse bit

0

1

DL

N

RE(0) DH REV

39 µs

Function

Set

REV = "1" : reverse display,

REV = "0" : normal display.

Set DL, N, RE("1") and

CGRAM/SEGRAM blink enable (BE)

BE = " 1/0" : CGRAM/SEGRAM

1

DL

RE(1) BE

0

39 µs

blink enable/disable

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(Table 6. continued)

Execution

Instruction Code

Instruction RE

Description

Time

(fosc =

R

S

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270 kHz)

Set

0

1

AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.

39 µs

CGRAM

Address

Set

1

X

AC3 AC2 AC1 AC0 Set SEGRAM address in address

counter.

SEGRAM

Address

Set

0

AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter.

DDRAM

Address

Set

1

X

SQ5 SQ4 SQ3 SQ2 SQ1 SQ0 Set the quantity of horizontal dot scroll.

Scroll

Quantity

Read

Can be known whether during internal

operation or not by reading BF. The

contents of address counter can also be

read.

Busy

X

0

1

BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

0 µs

flag and

Address

BF = “1” : busy state,

BF = “0” : ready state.

Write data into internal RAM

(DDRAM / CGRAM / SEGRAM).

Write

X

1

0

1

D7 D6 D5 D4 D3 D2 D1 D0

43 µs

Data

Read

X

Read data from internal RAM

Data

(DDRAM / CGRAM / SEGRAM).

* Note : 1. When an MPU program with Busy Flag(DB7) checking is made, 1/2 fosc (is necessary) for executing the

next instruction by the “E” signal after the Busy Flag (DB7) goes to “Low”.

2. “X” : Don’t care

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

1) Display Clear

'ꢙ

'67

&ꢚ0

&ꢚꢑ

&ꢚꢒ

&ꢚꢓ

&ꢚꢔ

&ꢚꢕ

&ꢚꢖ

&ꢚꢗ

ꢀ

ꢁ

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H"

into AC (address counter). Return cursor to the original status, hence, bring the cursor to the left edge on first line

of the display. Make entry mode increment (I/D = "1").

2) Return Home : (RE = 0)

'ꢙ

'67

&ꢚ0

&ꢚꢑ

&ꢚꢒ

&ꢚꢓ

&ꢚꢔ

&ꢚꢕ

&ꢚꢖ

&ꢚꢗ

ꢀ

ꢁ

ꢂ

Return Home is cursor return home instruction.

Set DDRAM address to "00H" into the address counter.

Return cursor to its original site and return display to its original status, if shifted.

Contents of DDRAM does not change.

3) Power Down Mode Set : (RE = 1)

'ꢙ

'67

&ꢚ0

&ꢚꢑ

&ꢚꢒ

&ꢚꢓ

&ꢚꢔ

&ꢚꢕ

&ꢚꢖ

&ꢚꢗ

ꢁ

ꢀ

ꢁ

ꢃꢄ

Power down mode enable bit set instruction.

PD = "High", it makes KS0075 suppress current consumption except the current needed for

data storage by executing next three functions.

1. make the output value of all the COM/SEG ports VDD

2. make the COM/SEG output value of extension driver VDD by setting D output to "High"

and M output to "Low"

3. disable voltage converter to remove the current through the divide resistor of power supply.

This instruction can be used as power sleep mode.

When PD = "Low", power down mode becomes disabled.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

4) Entry Mode Set

ꢂ (RE = 0)

ꢔꢛ

ꢔ#$ ꢊ%ꢆ ꢊ%ꢅ ꢊ%ꢄ ꢊ%ꢃ ꢊ%ꢂ ꢊ%ꢁ ꢊ%ꢀ ꢊ%ꢉ

ꢂꢃꢄ

ꢀ

ꢁ

ꢅ

Set the moving direction of cursor and display.

I/D : Increment / decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.

* CGRAM/SEGRAM operates the same as DDRAM, when read from or write to CGRAM/SEGRAM.

When S = "High", after DDRAM write, the display of enabled line by DS1 - DS4 bits

in the Shift Enable instruction is shifted to the right (I/D = "0") or to the left(I/D = "1").

But it will seem as if the cursor does not move.

When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of display

like this function is not performed.

ꢃ (RE = 1)

ꢔꢜ

ꢔ#$ ꢊ%ꢆ ꢊ%ꢅ ꢊ%ꢄ ꢊ%ꢃ ꢊ%ꢂ ꢊ%ꢁ ꢊ%ꢀ ꢊ%ꢉ

ꢂꢃꢄ

ꢀ

ꢁ

Set the data shift direction of segment in the application set.

BID : Data Shift Direction of Segment

When BID = "Low", segment data shift direction is set to normal order from SEG1 to SEG100.

When BID = "High", segment data shift direction is set to reverse from SEG100 to SEG1.

By using this instruction, the efficiency of application board area can be raised.

* The BID setting instruction is recommended to be set at the same time level of function set instruction.

* DB1 bit must be set to "1".

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

5) Display ON/OFF Control ( RE = 0 )

ꢔꢛ

ꢔ#$ ꢊ%ꢆ ꢊ%ꢅ ꢊ%ꢄ ꢊ%ꢃ ꢊ%ꢂ ꢊ%ꢁ ꢊ%ꢀ ꢊ%ꢉ

ꢉ

ꢀ

ꢊ

&

%

Control display/cursor/blink ON/OFF 1 bit register.

D : Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

C : Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

B : Cursor Blink ON/OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and

display character at the cursor position. If fosc has 270 kHz frequency, blinking has 370 ms interval.

When B = "Low", blink is off.

6) Extended Function Set ( RE = 1 )

ꢀꢁ ꢀꢂꢃ ꢄꢅꢆ ꢄꢅꢇ ꢄꢅꢈ ꢄꢅꢉ ꢄꢅꢊ ꢄꢅꢋ ꢄꢅꢌ ꢄꢅꢍ

ꢀ

ꢁ

ꢂꢃ ꢄꢅꢃ ꢆꢃ

FW : Font Width control

When FW = "High", display character font width is assigned to 6-dot and execution time becomes

6/5 times than that of 5-dot font width.

The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including the

leftmost space bit of CGRAM.(refer to Fig-9)

When FW = "Low", 5-dot font width is set.

B/W : Black/White Inversion enable bit

When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit of display

ON/OFF control instruction becomes don't care condition. If fosc has frequency of 270 kHz, inversion

has 370 ms intervals.

NW : 4 Line mode enable bit

When NW = "High", 4 line display mode is set. In this case N bit of function set instruction becomes

don't care condition.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

6-bit

s

p

a

c

e

CGRAM

character

font

CGROM

character

font

8

b

i

t

b

i

t

(6-dot)

(5-dot)

(CGRAM)

(CGROM)

Fig-9. 6-dot font width CGROM/CGRAM

7) Cursor or Display Shift (RE = 0)

ꢀꢁ

ꢀꢂꢃ ꢄꢅꢆ ꢄꢅꢇ ꢄꢅꢈ ꢄꢅꢉ ꢄꢅꢊ ꢄꢅꢋ ꢄꢅꢌ ꢄꢅꢍ

ꢂꢃꢄ ꢅꢃꢆ

ꢀ

ꢁ

ꢇ

Shift right/left cursor position or display, with out writing or reading of display data,

This instruction is used to correct or search display data.(refer to Table 7)

During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line.

In 4-line mode, cursor moves to the next line, only after every 20th digit of the current line.

Note that display shift is performed simultaneously in all the line enabled by DS1 - DS4 in the Shift Enable instruction.

When displayed data is shifted repeatedly, each line shifted individually.

When display shift is performed, the contents of address counter are not changed.

During low power consumption mode, display shift may not be performed normally.

Table 7. Shift patterns according to S/C and R/L bits

S/C

0

R/L

0

Operation

Shift cursor to the left, ADDRESS COUNTER is decreased by 1

Shift cursor to the right, ADDRESS COUNTER is increased by 1

Shift all the display to the left, cursor moves according to the display

Shift all the display to the right, cursor moves according to the display

0

1

0

1

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

8) Shift/Scroll Enable (RE = 1)

ꢂ (DH = 0)

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢀ

ꢁ

ꢂꢃꢄ

ꢂꢃꢅ

ꢂꢃꢆ

ꢂꢃꢁ

HS : Horizontal Scroll per Line Enable

This instruction makes valid dot shift by a display line unit.

HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is performed individually in each line.

If the line in 1-line display mode or the 1st line in 2-line display mode, is to be scrolled set HS1 and HS2 to "High".

If the 2nd line scroll is needed in 2-line mode, set HS3 and HS4 to "High". (refer to Table 8)

ꢃ (DH = 1)

ꢍꢀ

ꢍꢎꢏ

ꢐꢑꢇ

ꢐꢑꢈ

ꢐꢑꢉ

ꢐꢑꢊ

ꢐꢑꢋ

ꢐꢑꢌ

ꢐꢑꢃ

ꢐꢑꢄ

ꢝ

ꢜ

ꢊ%ꢙ

ꢊ%ꢚ

ꢊ%ꢛ

ꢊ%ꢜ

DS : Display Shift per Line Enable

This instruction selects shifting line to be shifted according to each line mode in display shift right/left instruction.

DS1, DS2, DS3 and DS4 indicate each line to be shifted, and each shift is performed individually in each line.

If DS1 and DS2 is set to "High" (enable) in 2 line mode, only the 1st line is shifted

and the 2nd line is not shifted. When only DS1 = "High", only the half of the 1st line is shifted. If all the DS bits

(DS1 to DS4) are set to "Low" (disable), no display is shifted.

Table 8. Relationship between DS and COM signal

Enable bit

Enabled common signals

during shift

Description

HS1/DS1

HS2/DS2

HS3/DS3

HS4/DS4

The part of display line that corresponds to enabled

common signal can be shifted.

COM1 ꢁ COM8

COM9 ꢁ COM16

COM17 ꢁ COM24

COM25 ꢁ COM32

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

9) Function Set

ꢂ (RE = 0)

ꢒꢀ

ꢒꢔꢕ

ꢐꢖꢉ

ꢐꢖꢏ

ꢐꢖꢌ

ꢐꢖꢋ

ꢐꢖꢍ

ꢐꢖꢊ

ꢐꢖꢃ

ꢐꢑ

ꢐꢖꢄ

ꢒꢁꢓ

ꢅꢆ

ꢀ

ꢁ

ꢂꢃ

ꢄ

ꢇꢀꢈ

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode.

In 4-bit bus mode, it is required to transfer 4-bit data twice.

N : Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", it means 1-line display mode.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE : Extended function registers enable bit

At this instruction, RE must be "Low".

DH : Display shift enable selection bit.

When DH = "High", enable display shift per line.

When DH = "Low", enable smooth dot scroll.

This bit can be accessed only when IE pin input is "High".

REV : Reverse enable bit

When REV = "High", all the display data are reversed. I.e., all the white dots become

black and black dots become white.

When REV = "Low", the display mode set normal display.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢃ (RE = 1)

ꢗꢀ

ꢗꢓ8

ꢖꢕ5

ꢖꢕ'

ꢖꢕ4

ꢖꢕꢎ

ꢖꢕ1

ꢖꢕ/

ꢖꢕ&

ꢕ$

ꢖꢕ!

!

ꢅꢆ

ꢀ

ꢁ

ꢂꢃ

ꢄ

ꢇꢁꢈ

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select

8-bit or 4-bit bus mode.

When 4-bit bus mode, it is required to transfer 4-bit data twice.

N : Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", 1-line display mode is set.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE : Extended function registers enable bit

When RE = "High", extended function set registers, SEGRAM address set registers, BID bit, HS/DS bits of

shift/scroll enable instruction and BE bits of function set register can be accessed.

BE : CGRAM/SEGRAM data blink enable bit

BE =”High”, makes user font of CGRAM and segment of SEGRAM blinking. The quantity of blink is

assigned the highest 2 bit of CGRAM/SEGRAM.

10) Set CGRAM Address (RE = 0)

ꢍꢀ

ꢍꢎꢏ

ꢐꢑꢇ

ꢐꢑꢈ

ꢐꢑꢉ

ꢐꢑꢊ

ꢐꢑꢋ

ꢐꢑꢌ

ꢐꢑꢃ

ꢐꢑꢄ

ꢝ

ꢜ

ꢌꢀꢘ ꢌꢀꢙ ꢌꢀꢚ ꢌꢀꢛ ꢌꢀꢜ ꢌꢀꢝ

Set CGRAM address to AC.

This instruction makes CGRAM data available from MPU.

11) Set SEGRAM Address (RE = 1)

ꢏꢌ

ꢏꢐꢑ

ꢒꢓꢇ

ꢒꢓꢆ

ꢒꢓꢋ

ꢒꢓꢉ

ꢒꢓꢊ

ꢒꢓꢈ

ꢒꢓꢃ

ꢒꢓꢔ

ꢋ

ꢕ

#

ꢂ$ꢗ

ꢂ$ꢖ

ꢂ$ꢕ

ꢂ$ꢋ

Set CGRAM address to AC.

This instruction makes CGRAM data available from MPU.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

12) Set DDRAM Address (RE = 0)

ꢅꢉ

ꢅꢊꢋ

ꢂꢌꢍ

ꢂꢌꢎ

ꢂꢌꢏ

ꢂꢌꢐ

ꢂꢌꢑ

ꢂꢌꢒ

ꢂꢌꢁ

ꢂꢌꢀ

ꢀ

ꢁ

ꢂꢃꢄ

ꢂꢃꢅ

ꢂꢃꢆ

ꢂꢃꢇ

ꢂꢃꢈ

ꢂꢃꢁ

ꢂꢃꢀ

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU.

In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "4FH".

In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "27H",

and DDRAM address in the 2nd line is from "40H" to "67H".

In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from

"20H" to "33H" in the 2nd line, from "40H" to "53H" in the 3rd line and from "60H" to "73H"

in the 4th line.

13) Set Scroll Quantity (RE = 1)

ꢄꢅꢆ

ꢌ

ꢄꢅꢇ

ꢎ

ꢄꢅꢈ

ꢁꢏꢈ

ꢄꢅꢉ

ꢁꢏꢉ

ꢄꢅꢊ

ꢁꢏꢊ

ꢄꢅꢋ

ꢁꢏꢋ

ꢄꢅꢌ

ꢁꢏꢌ

ꢄꢅꢍ

ꢁꢏꢍ

ꢀꢁ

ꢍ

ꢀꢂꢃ

ꢍ

Setting SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (Refer to Table 9)

In this case of KS0075 can show hidden areas of DDRAM by executing smooth scroll

from 1 to 48 dots.

Table 9. Scroll quantity according to HDS bits

SQ5

SQ4

SQ3

SQ2

SQ1

SQ0

Function

No shift

0

:

0

:

0

:

0

:

0

1

:

0

1

0

1

:

shift left by 1-dot

shift left by 2-dot

shift left by 3-dot

:

1

0

1

X

1

X

1

X

1

X

shift left by 47-dot

shift left by 48-dot

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

14) Read Busy Flag & Address

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

A

D

XY

8ZH

8ZC

8ZG

8ZF

8ZE

8ZD

8ZA

This instruction shows whether KS0075 is in internal operation or not. If the resultant BF is High, the internal operation is in

progress and you have to wait until BF to be Low, which by then the next instruction can be performed. In this instruction

the value of address counter can also be read.

15) Write data to RAM

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢀ

ꢁ

ꢐꢇ

ꢐꢈ

ꢐꢉ

ꢐꢊ

ꢐꢋ

ꢐꢌ

ꢐꢃ

ꢐꢄ

Write binary 8-bit data to DDRAM/CGRAM/SEGRAM.

The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address

set instruction : DDRAM address set, CGRAM address set, SEGRAM address set.

RAM set instruction can also determines the AC direction to RAM.

After write operation, the address is automatically increased/decreased by 1, according

to the entry mode.

16) Read data from RAM

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢃ

ꢐꢇ

ꢐꢈ

ꢐꢉ

ꢐꢊ

ꢐꢋ

ꢐꢌ

ꢐꢃ

ꢐꢄ

Read binary 8-bit data from DDRAM/CGRAM/SEGRAM.

The selection of RAM is set by the previous address set instruction. If address set instruction

of RAM is not performed before this instruction, the data that read first is invalid, as the

direction of AC is not determined. If RAM data is read several times without RAM address

set instruction before read operation, the correct RAM data can be obtained from

the second, but the first data would be incorrect, as there is no time margin to transfer

RAM data. In DDRAM read operation, cursor shift instruction plays the same role as

DDRAM address set instruction : it also transfer RAM data to output data register.

After read operation address counter is automatically increased/decreased by 1 according

to the entry mode. After CGRAM/SEGRAM read operation, display shift may not be executed correctly.

In case of RAM write operation, AC is increased/decreased by 1 as in read operation after this.

In this time, AC indicates the next address position, but the previous data can only be read by read instruction.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(2) INSTRUCTION DESCRIPTION 2 (IE = "LOW")

Table 10. Instruction Set 2

Execution

Time

Instruction Code

Instruction RE

Description

(fosc =

R

S

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270 kHz)

Clear

Write "20H" to DDRAM. and set DDRAM

address to "00H" from AC.

X

0

1

1.53ms

Display

Set DDRAM address to "00H" from AC and

return cursor to its original position if

shifted. The contents of DDRAM are not

changed.

Return

Home

X

Assign cursor moving direction.

I/D = "1" : increment,

Entry

Mode

Set

I/D = "0" : decrement.

X

0

1

I/D

S

39µs

and display shift enable bit.

S = "1" :make entire display shift of all

lines during DDRAM write,

S = "0":display shift disable

Set display/cursor/blink on/off

D = "1" : display on,

D = "0" : display off,

Display

ON/OFF

Control

0

1

D

C

B

39µs

C = "1" : cursor on,

C = "0" : cursor off,

B = "1" : blink on,

B = "0" : blink off.

Assign font width, black/white inverting of

cursor, and 4-line display mode control bit.

FW = "1" : 6-dot font width,

FW = "0" : 5-dot font width,

B/W = "1" : black/white inverting of

cursor enable,

Extended

function

set

1

0

1

FW B/W NW

39µs

B/W = "0" : black/white inverting of

cursor disable

NW = "1" : 4-line display mode,

NW = "0" : 1-line or 2-line display mode

Cursor or display shift.

Cursor

or

S/C = “1” : display shift,

S/C R/L

X

S/C = “0” : cursor shift,

Display

Shift

R/L = “1” : shift to right,

R/L = “0” : shift to left

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(Table 10. continued)

Execution

Instruction RE

Instruction Code

Description

Time

(fosc =

R

S

R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

270 kHz)

Determine the line for horizontal smooth

scroll.

HS1 = "1/0" : 1st line dot scroll

enable/disable

HS2 = "1/0" : 2nd line dot scroll

enable/disable

Scroll

Enable

1

0

1

HS4 HS3 HS2 HS1

39µs

HS3 = "1/0" : 3rd line dot scroll

enable/disable

HS4 = "1/0" : 4th line dot scroll

enable/disable

Set interface data length

DL = "1" : 8-bit,

DL = "0" : 4-bit

numbers of display line when NW = "0",

N = "1" : 2-line,

N = "0" : 1-line

0

1

0

1

DL

N

RE(0)

X

39µs

Function

Set

extension register, RE("0"),

Set DL, N, RE("1") and

CGRAM/SEGRAM blink enable (BE)

BE = " 1/0" : CGRAM/SEGRAM

DL

RE(1) BE

0

blink enable/disable

Set

CGRAM

Address

Set

0

1

0

1

0

1

AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.

39µs

Set SEGRAM address in address

counter.

X

X AC3 AC2 AC1 AC0

SEGRAM

Address

Set

AC6 AC5 AC4 AC3 AC2 AC1 AC0

Set DDRAM address in address counter.

DDRAM

Address

Set

X

QC5 QC4 QC3 QC2 QC1 QC0

Set the quantity of horizontal dot scroll.

Scroll

Quantity

Read

Can be known whether during internal

operation or not by reading BF. The

contents of address counter can also be

read. BF = “1” : busy state,

BF = “0” : ready state.

Write data into internal RAM

Busy

X

0

1

BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

0µs

flag and

Address

Write

X

1

0

1

D7 D6 D5

D4 D3 D2 D1

D0

43µs

(DDRAM / CGRAM / SEGRAM).

Data

Read

Read data from internal RAM

Data

(DDRAM / CGRAM / SEGRAM).

* Note : 1. When an MPU program with Busy Flag(DB7) checking is made, 1/2 fosc (is necessary) for executing the next

instruction by the falling edge of the “E” signal after the Busy Flag(DB7) goes to “Low”

2. “X” : don’t care

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

1) Display Clear

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢍ

ꢌ

Clear all the display data by writing "20H" (space code) to all DDRAM address, and set

DDRAM address to "00H" into AC (address counter). Return cursor to the original status,

hence, bring the cursor to the left edge on first line of the display.

And entry mode is set to increment mode (I/D = "1").

2) Return Home

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢍ

ꢌ

ꢎ

Return Home is cursor return home instruction.

Set DDRAM address to "00H" into the address counter. Return cursor to its original

site and return display to its original status, if shifted.

Contents of DDRAM does not change.

3) Entry Mode Set

ꢁꢊ

ꢁ%&

ꢀ'ꢌ

ꢀ'ꢙ

ꢀ'ꢍ

ꢀ'ꢘ

ꢀ'ꢗ

ꢀ'ꢖ

ꢀ'ꢕ

ꢀ'ꢋ

ꢉ

ꢀ

&#ꢊ

ꢜ

Set the moving direction of cursor and display.

I/D : Increment / decrement of DDRAM address (cursor or blink)

When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1.

When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1.

* CGRAM/SEGRAM operates identically to the DDRAM, when reading from or writing to CGRAM/SEGRAM.

When S = "High", after DDRAM write, the entire display of all lines is shifted to

the right (I/D = "0") or to the left(I/D = "1").

But it will seem as if the cursor does not moving.

When S = "Low", or DDRAM read, or CGRAM/SEGRAM read/write operation, shift of entire

display is not performed.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

4) Display ON/OFF Control ( RE = 0 )

ꢏꢌ

ꢏꢐꢑ

ꢒꢓꢇ

ꢒꢓꢆ

ꢒꢓꢋ

ꢒꢓꢉ

ꢒꢓꢊ

ꢒꢓꢈ

ꢒꢓꢃ

ꢒꢓꢔ

ꢋ

ꢕ

ꢀ

$

'

Control display/cursor/blink ON/OFF 1 bit register.

D : Display ON/OFF control bit

When D = "High", entire display is turned on.

When D = "Low", display is turned off, but display data is remained in DDRAM.

C : Cursor ON/OFF control bit

When C = "High", cursor is turned on.

When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

B : Cursor Blink ON/OFF control bit

When B = "High", cursor blink is on, that performs alternate between all the high data and

display character at the cursor position. If fosc has 270 kHz frequency, blinking has 370 ms interval.

When B = "Low", blink is off.

5) Extended Function Set ( RE = 1 )

ꢗꢀ

ꢗꢓ8

ꢖꢕ5

ꢖꢕ'

ꢖꢕ4

ꢖꢕꢎ

ꢖꢕ1

ꢖꢕ/

ꢖꢕ&

ꢖꢕ!

ꢉ

ꢀ

&$

%#$

'$

FW : Font Width control

When FW = "High", display character font width is assigned to 6-dot and execution time

becomes 6/5 times than that of 5-dot font width.

The user font, specified in CGRAM, is displayed into 6-dot font width, bit-5 to bit-0,including

the leftmost space bit of CGRAM.(Refer to Fig-10)

When FW = "Low", 5-dot font width is set.

B/W : Black/White Inversion enable bit

When B/W = "High", black/white inversion at the cursor position is set. In this case C/B bit

of display ON/OFF control instruction becomes don't care condition. If fosc has frequency of

270 kHz, inversion has 370 ms intervals.

NW : 4 Line mode enable bit

When NW = "High", 4 line display mode is set. In this case N bit of function set instruction

becomes don't care condition.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

6-bit

s

p

a

c

e

CGRAM

character

font

CGROM

character

font

8

b

i

t

b

i

t

(6-dot)

(5-dot)

(CGRAM)

(CGROM)

Fig-10. 6-dot font width CGROM/CGRAM

6) Cursor or Display Shift (RE = 0)

ꢅꢉ

ꢅꢊꢋ

ꢂꢌꢍ

ꢂꢌꢎ

ꢂꢌꢏ

ꢂꢌꢐ

ꢂꢌꢑ

ꢂꢌꢒ

ꢂꢌꢁ

ꢂꢌꢀ

ꢀ

ꢁ

ꢉꢊꢓ

ꢅꢊꢃ

ꢔ

Shift right/left cursor position or display, without writing or reading of display data

This instruction is used to correct or search display data.(Refer to Table 7)

During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line.

In 4-line mode, cursor moves to the next line, only after every 20th digit of the current line.

Note that display shift is performed simultaneously in all the line.

When displayed data is shifted repeatedly, each line shifted individually.

When display shift is performed, the contents of address counter are not changed.

Table 11. Shift patterns according to S/C and R/L bits

S/C

0

R/L

0

Operation

Shift cursor to the left, ADDRESS COUNTER is decreased by 1

Shift cursor to the right, ADDRESS COUNTER is increased by 1

0

1

0

Shift all the display to the left, cursor moves according to the display

Shift all the display to the right, cursor moves according to the display

1

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

7) Scroll Enable (RE = 1)

ꢗꢀ

!

ꢗꢓ8

!

ꢖꢕ5

!

ꢖꢕ'

!

ꢖꢕ4

!

ꢖꢕꢎ

&

ꢖꢕ1

<ꢀꢎ

ꢖꢕ/

<ꢀ1

ꢖꢕ&

<ꢀ/

ꢖꢕ!

<ꢀ&

HS : Horizontal Scroll per Line Enable

This instruction makes valid dot shift by a display line unit.

HS1, HS2, HS3 and HS4 indicate each line to be dot scrolled, and each scroll is

performed individually in each line.

If the line in 1-line display mode or the 1st line in 2-line display

mode is to be scrolled, set HS1 and HS2 to "High". If the 2nd line scroll is needed in 2-line mode,

set HS3 and HS4 to "High". (refer to Table 8)

8) Function Set

ꢂ (RE = 0)

ꢅꢉ

ꢅꢊꢋ

ꢂꢌꢍ

ꢂꢌꢎ

ꢂꢌꢏ

ꢂꢌꢐ

ꢂꢌꢑ

ꢂꢌꢒ

ꢂꢌꢁ

ꢔ

ꢂꢌꢀ

ꢔ

ꢌꢍ

ꢀ

ꢁ

ꢉꢊ

ꢋ

ꢎꢀꢏ

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select

8-bit or 4-bit bus mode.

In 4-bit bus mode, it is required to transfer 4-bit data.

N : Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", 1-line display mode is set.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, it means 4-line mode independent of N bit.

RE : Extended function registers enable bit

At this instruction, RE must be "Low".

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢃ (RE = 1)

ꢗꢀ

ꢗꢓ8

ꢖꢕ5

ꢖꢕ'

ꢖꢕ4

ꢖꢕꢎ

ꢖꢕ1

ꢖꢕ/

ꢖꢕ&

ꢕ$

ꢖꢕ!

!

ꢔ(

ꢉ

ꢀ

ꢊ

'

ꢜꢀ!

DL : Interface data length control bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU. Hence, DL is a signal to select

8-bit or 4-bit bus mode.

In 4-bit bus mode, it is required to transfer 4-bit data twice.

N : Display line number control bit

It is variable only when NW bit of extended function set instruction is Low.

When N = "Low", 1-line is set.

When N = "High", 2-line display mode is set.

When NW = "High", N bit is invalid, 4-line mode independent of N bit.

RE : Extended function registers enable bit

When RE = "High", extended function set registers, SEGRAM address set registers, HS bits

of scroll enable instruction and BE bits of function set register can be accessed.

BE : CGRAM/SEGRAM data blink enable bit

If BE is "High", makes user font of CGRAM and segment of SEGRAM blinking. The quantity

of blink is assigned the highest 2 bit of CGRAM/SEGRAM.

9) Set CGRAM Address (RE = 0)

ꢍꢀ

ꢍꢎꢏ

ꢐꢑꢇ

ꢐꢑꢈ

ꢐꢑꢉ

ꢐꢑꢊ

ꢐꢑꢋ

ꢐꢑꢌ

ꢐꢑꢃ

ꢐꢑꢄ

ꢝ

ꢜ

ꢌꢀꢘ

ꢌꢀꢙ

ꢌꢀꢚ

ꢌꢀꢛ

ꢌꢀꢜ

ꢌꢀꢝ

Set CGRAM address to AC.

This instruction makes CGRAM data available from MPU.

10) Set SEGRAM Address (RE = 1)

ꢍꢀ

ꢍꢎꢏ

ꢐꢑꢇ

ꢐꢑꢈ

ꢐꢑꢉ

ꢐꢑꢊ

ꢐꢑꢋ

ꢐꢑꢌ

ꢐꢑꢃ

ꢐꢑꢄ

ꢝ

ꢜ

&

ꢌꢀꢚ

ꢌꢀꢛ

ꢌꢀꢜ

ꢌꢀꢝ

Set SEGRAM address to AC.

This instruction makes SEGRAM data available from MPU.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

11) Set DDRAM Address (RE = 0)

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢄ

ꢃ

ꢒꢓꢈ

ꢒꢓꢉ

ꢒꢓꢊ

ꢒꢓꢋ

ꢒꢓꢌ

ꢒꢓꢃ

ꢒꢓꢄ

Set DDRAM address to AC.

This instruction makes DDRAM data available from MPU.

In 1-line display mode (N = 0, NW = 0), DDRAM address is from "00H" to "4FH".

In 2-line display mode (N = 1, NW = 0), DDRAM address in the 1st line is from "00H" to "27H",

and DDRAM address in the 2nd line is from "40H" to "67H".

In 4-line display mode (NW = 1), DDRAM address is from "00H" to "13H" in the 1st line, from

"20H" to "33H" in the 2nd line, from "40H" to "53H" in the 3rd line and from "60H" to "73H" in the 4th line.

12) Set Scroll Quantity (RE = 1)

ꢗꢀ

ꢗꢓ8

ꢖꢕ5

ꢖꢕ'

ꢖꢕ4

ꢖꢕꢎ

ꢖꢕ1

ꢖꢕ/

ꢖꢕ&

ꢖꢕ!

ꢍ

ꢌ

ꢎ

ꢁꢏꢈ

ꢁꢏꢉ

ꢁꢏꢊ

ꢁꢏꢋ

ꢁꢏꢌ

ꢁꢏꢍ

Setting SQ5 to SQ0, horizontal scroll quantity can be controlled in dot units. (Refer to Table 12).

In this case of KS0075 execute dot smooth scroll from 1 to 48 dots.

Table 12. Scroll quantity according to HDS bits

SQ5

SQ4

SQ3

SQ2

SQ1

SQ0

Function

No shift

0

:

0

:

0

:

0

:

0

1

:

0

1

0

1

:

shift left by 1-dot

shift left by 2-dot

shift left by 3-dot

:

1

0

1

X

1

X

1

X

1

X

shift left by 47-dot

shift left by 48-dot

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

13) Read Busy Flag & Address

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢍ

ꢌ

ꢅꢐ

ꢑꢒꢇ

ꢑꢒꢈ

ꢑꢒꢉ

ꢑꢒꢊ

ꢑꢒꢋ

ꢑꢒꢌ

ꢑꢒꢍ

This instruction shows whether KS0075 is in internal operation or not. If the resultant BF is High, it means the internal

operation is in progress and should to wait until BF to become “Low”.

Which by then the next instruction can be performed. In this instruction value of address counter can also be read.

14) Write data to RAM

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢆ

ꢇ

ꢄꢆ

ꢄꢇ

ꢄꢈ

ꢄꢉ

ꢄꢊ

ꢄꢋ

ꢄꢌ

ꢄꢍ

Write binary 8-bit data to DDRAM/CGRAM/SEGRAM.

The selection of RAM from DDRAM, CGRAM, or SEGRAM, is set by the previous address set instruction : DDRAM

address set, CGRAM address set, SEGRAM address set. RAM set instruction can also determines the AC direction to

RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode.

15) Read data from RAM

ꢀꢁ

ꢀꢂꢃ

ꢄꢅꢆ

ꢄꢅꢇ

ꢄꢅꢈ

ꢄꢅꢉ

ꢄꢅꢊ

ꢄꢅꢋ

ꢄꢅꢌ

ꢄꢅꢍ

ꢌ

ꢄꢆ

ꢄꢇ

ꢄꢈ

ꢄꢉ

ꢄꢊ

ꢄꢋ

ꢄꢌ

ꢄꢍ

Read binary 8-bit data from DDRAM/CGRAM/SEGRAM.

The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before

this instruction, the data that read first is invalid, as the direction of AC is not determined. If the RAM data is read several

times without RAM address set instruction before read operation, the correct RAM data from

the second, but the first data would be incorrect, as there is no time margin to transfer RAM data. In case of DDRAM read

operation, cursor shift instruction plays the same role as DDRAM address set instruction : it also transfer RAM data to output

data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode.

After CGRAM/SEGRAM read operation, display shift may not be executed correctly.

* In case of RAM write operation, AC is increased/decreased by 1 like read operation after this. In this time, AC indicates the next

address position, but the previous data can only be read by read instruction.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

INTERFACE WITH MPU

KS0075 can transfer data in bus mode (4-bit or 8-bit) or serial mode with MPU. Hence, both types of 4 or 8-bit MPU can

be used. In case of 4-bit bus mode, data transfer is performed by twice to transfer 1 byte data.

(1) When interfacing data length are 4-bit, only 4 ports, from DB4 to DB7, are used as data bus.

At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4 - DB7) are transferred, and then lower 4-bit (in case of 8-bit

bus mode, the contents of DB0 - DB3) are transferred. So transfer is performed by twice. Busy Flag outputs "High" after the

second transfer is ended.

(2) When interfacing data length are 8-bit, transfer is performed at a time through 8 ports, from DB0 to DB7.

(3) If IM is set to "Low", serial transfer mode is set.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Interface with MPU in Bus Mode

1) Interface with 8-bits MPU

If 8-bits MPU is used, KS0075 can connect directly with that.

In this case, port E, RS, R/W and DB0 to DB7 need to interface each other.

Example of timing sequence is shown below.

RS

R/W

E

Internal

Internal operation

signal

No Busy

DATA

Busy

DATA

DB7

INSTRUCTION

Busy Flag Check

INSTRUCTION

Fig 11. Example of 8-bit Bus Mode Timing Sequence

2) Interface with 4-bits MPU

If 4-bits MPU is used, KS0075 can connect directly with this.

In this case, port E, RS, R/W and DB4 to DB7 need to interface each other. The transfer is performed by twice.

Example of timing sequence is shown below.

RS

R/W

E

Internal

Internal operation

signal

No

DB7

D7

D3

Busy

AC3

Busy

AC3

D7

D3

INSTRUCTION

Busy Flag Check

INSTRUCTION

Fig 12. Example of 4-bit Bus Mode Timing Sequence

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Interface with MPU in Serial Mode

When IM port input is "Low", serial interface mode is started. At this time, all three ports, SCLK (synchronizing transfer clock),

SID (serial input data), and SOD (serial output data), are used. If KS0075 is to be used with other chips, chip select port

(cs) be used.

By setting CS to "Low", KS0075 can receive SCLK input. If CS is set to "High", KS0075 reset the internal transfer counter.

Before transfer real data, start byte has to be transferred. It is composed of succeeding 5 "High" bits, read write control bit

(R/W), register selection bit (RS), and end bit that indicates the end of start byte. Whenever succeeding 5 "High" bits are

detected by KS0075, it resets serial transfer counter and prepares to receive next information.

The next input data are register selection bit which determine which register is to be used, and read write control bit that

determine the direction of data. Then end bit is transferred, which must have "Low" value to show the end of start byte.

(Refer to Fig 13. Fig 14)

(1) Write Operation (R/W = 0)

After start byte is transferred from MPU to KS0075, 8-bit data is transferred which is divided into 2 bytes, each byte has

4 bit's real data and 4 bit's partition token data. For example, if real data is "10110001" (D0 - D7), then serially transferred

data becomes "1011 0000 0001 0000" where 2nd and 4th 4 bits must be "0000" for safe transfer.

To transfer several bytes continuously without changing R/W bit and RS bit, start byte transfer is needed only at first starting

time. I.e., after first start byte is transferred, real data succeeding can be transferred.

(2) Read Operation (R/W = 1)

After start byte is transferred to KS0075, MPU can receive 8-bit data through the SOD port at a time from the LSB. Wait time

is needed to insert between start byte and data reading, as internal reading from RAM requires some delay.

Continuous data reading is possible such as serial write operation. It also needs only one start bytes, only if some delay between

reading operations of each byte is inserted. During the reading operation, KS0075 observes succeeding 5 "High" from MPU.

If detected, KS0075 restarts serial operation at once and prepares to receive RS bit. So in continuous reading operation,

SID port must be "Low".

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(1) Serial Write Operation

CS

(Input)

ꢁ

ꢒ

ꢑ

ꢐ

ꢏ

ꢎ

ꢍ

ꢓ

ꢔ ꢁꢀ ꢁꢁ ꢁꢒ ꢁꢑ ꢁꢐ ꢁꢏ ꢁꢎ ꢁꢍ ꢁꢓ ꢁꢔ ꢒꢀ ꢒꢁ ꢒꢒ ꢒꢑ ꢒꢐ

ꢐꢃꢊꢑ

(Input)

SID

0

D0 D1 D2 D3 "0" "0" "0" "0"

"1" "1" "1" "1" "1" "R/W""RS"

Starting Byte

D4 D5 D6 D7 "0" "0" "0" "0"

(Input)

Instruction

Lower Data

1'st Byte

Upper Data

2'nd Byte

Synchronizing

Bit string

(2) Serial Read Operation

CS

(Input)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCLK

(Input)

SID

"1" "1" "1" "1" "1" "R/W" "RS""0" "0" "0" "0" "0" "0" "0" "0" "0"

(Input)

SOD

Invalid Data

D0 D1 D2 D3 D4 D5 D6 D7

(Output)

Busy Flag/

Read Data

Starting Byte

Synchronizing

Bit string

Lower

Data

Upper

Data

Fig 13. Timing Diagram of Serial Data Transfer

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

(1) Continuous Write Operation

SCLK

SID

Wait

Start byte 1st byte

2nd byte

1st byte

2nd byte

(Instruction3)

1st byte

(Instruction2)

(Instruction1)

Instruction1

execution time

Instruction2

execution time

Instruction3

execution time

(2) Continuous Read Operation

Wait

SCLK

Start byte

SID

Data

Data

Data

SOD

Instruction1

execution time

Instruction2

execution time

Instruction3

execution time

Fig 14. Timing Diagram of Continuous Data Transfer

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

APPLICATION INFORMATION ACCORDING TO LCD PANEL

1) LCD Panel : 40 character x 1 line format (5-dot font,1/17 duty)

ꢀꢁꢂꢃ

ꢀꢁꢂꢄ

ꢀꢁꢂꢅ

ꢀꢁꢂꢆ

ꢀꢁꢂꢇ

ꢀꢁꢂꢈ

ꢀꢁꢂꢉ

ꢀꢁꢂꢊ

ꢓꢔꢔꢔꢔ

ꢔꢓꢓꢓꢓ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢔ

ꢔꢔꢔꢔꢓ

ꢔꢔꢔꢔꢔ

ꢓꢔꢔꢔꢓ

ꢔꢓꢓꢓꢔ

ꢔꢔꢔꢔꢔ

ꢔꢓꢓꢓꢔ

ꢓꢓꢓꢓꢓ

ꢔꢔꢓ

ꢓꢓꢔ

ꢓꢓꢓ

ꢔꢔꢔ

ꢓꢓꢔ

ꢔꢔꢔ

ꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢓ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓ

ꢔꢔꢔ

ꢓꢓꢓ

ꢔꢔꢓ

ꢓꢓꢔ

ꢔꢔꢓ

ꢓꢓꢓ

ꢀꢁꢂꢃꢉ

ꢋꢀꢁꢂꢌꢍ

ꢕꢖꢗꢘꢙ

ꢚꢚꢚꢚꢚ

ꢎꢏꢐꢃ

ꢎꢏꢐꢄ

ꢎꢏꢐꢅ

ꢎꢏꢐꢆ

ꢎꢏꢐꢇ

ꢎꢏꢐꢈ

ꢎꢎꢐꢉ

ꢎꢏꢐꢊ

ꢎꢏꢐꢑ

ꢎꢏꢐꢃꢌ

ꢒ

ꢀ

ꢀꢁꢂꢂꢃꢄ

ꢀ

ꢎꢏꢐꢑꢊ

ꢎꢏꢐꢑꢑ

ꢎꢏꢐꢃꢌꢌ

ꢀ

ꢀꢁꢂꢃꢈ

ꢀꢁꢂꢃꢇ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢃꢅ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢃ

ꢀꢁꢂꢃꢌ

ꢀꢁꢂꢑ

2) LCD Panel : 40 character x 2 line format (5-dot font, 1/33 duty)

ꢀꢁꢂꢃ

ꢀꢁꢂꢄ

ꢀꢁꢂꢅ

ꢀꢁꢂꢆ

ꢀꢁꢂꢇ

ꢀꢁꢂꢈ

ꢀꢁꢂꢉ

ꢀꢁꢂꢊ

ꢓꢔꢔꢔꢔ

ꢔꢓꢓꢓꢓ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢔ

ꢔꢔꢔꢔꢓ

ꢔꢔꢔꢔꢔ

ꢔꢔꢓ

ꢓꢓꢔ

ꢓꢓꢓ

ꢔꢔꢔ

ꢓꢓꢔ

ꢔꢔꢔ

ꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢔꢔꢔ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢓ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓ

ꢓꢓꢓ

ꢔꢔꢓ

ꢓꢓꢔ

ꢔꢔꢓ

ꢓꢓꢓ

ꢀꢁꢂꢃꢉ

ꢀꢁꢂꢃꢊ

ꢀꢁꢂꢃꢋ

ꢀꢁꢂꢄꢌ

ꢀꢁꢂꢄꢃ

ꢀꢁꢂꢄꢄ

ꢀꢁꢂꢄꢅ

ꢀꢁꢂꢄꢆ

ꢓꢔꢔꢔꢓ

ꢔꢓꢓꢓꢔ

ꢔꢓꢓꢓꢓ

ꢔꢓꢓꢓꢔ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓ

ꢓꢓꢔ

ꢓꢔꢓ

ꢔꢓꢓ

ꢓꢓꢓ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓ

ꢔꢓꢓ

ꢓꢔꢓ

ꢓꢓꢔ

ꢓꢔꢓ

ꢔꢓꢓ

ꢓꢓꢓ

ꢀꢁꢂꢅꢅ

ꢍꢀꢁꢂꢌꢎ

ꢕꢖꢗꢘꢙ

ꢏꢐꢑꢃ

ꢏꢐꢑꢄ

ꢏꢐꢑꢅ

ꢏꢐꢑꢆ

ꢏꢐꢑꢇ

ꢒ

ꢏꢐꢑꢋꢊ

ꢏꢐꢑꢋꢋ

ꢏꢐꢑꢃꢌꢌ

ꢇꢃꢀꢀꢈꢉ

ꢀ

ꢀꢁꢂꢅꢄ

ꢀꢁꢂꢅꢃ

ꢀꢁꢂꢅꢌ

ꢀꢁꢂꢄꢋ

ꢀꢁꢂꢄꢊ

ꢀꢁꢂꢄꢉ

ꢀꢁꢂꢄꢈ

ꢀꢁꢂꢄꢇ

ꢀ

ꢀꢁꢂꢃꢈ

ꢀꢁꢂꢃꢇ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢃꢅ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢃ

ꢀꢁꢂꢃꢌ

ꢀꢁꢂꢋ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

3) LCD Panel : 20 character x 4 line format (5-dot font, 1/33 bias)

ꢀꢁꢂꢃ

ꢀꢁꢂꢄ

ꢀꢁꢂꢅ

ꢀꢁꢂꢆ

ꢀꢁꢂꢇ

ꢀꢁꢂꢈ

ꢀꢁꢂꢉ

ꢀꢁꢂꢊ

ꢓꢔꢔꢔꢔ

ꢔꢓꢓꢓꢓ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢔ

ꢔꢔꢔꢔꢓ

ꢔꢔꢔꢔꢔ

ꢓꢔꢔꢔꢓ

ꢔꢓꢓꢓꢔ

ꢔꢓꢓꢓꢓ

ꢔꢓꢓꢓꢔ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓ

ꢓꢔꢔꢔꢓ

ꢔꢓꢓꢓꢔ

ꢔꢔꢔꢔꢔ

ꢔꢓꢓꢓꢔ

ꢓꢓꢓꢓꢓ

ꢔꢔꢓ

ꢓꢓꢔ

ꢓꢓꢓ

ꢔꢔꢔ

ꢓꢓꢔ

ꢔꢔꢔ

ꢓꢓꢓ

ꢀꢁꢂꢋ

ꢔꢔꢔꢔꢔ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢓ

ꢔꢓꢓꢓꢓ

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ꢓꢔꢔꢔꢓ

ꢔꢓꢓꢓꢔ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓ

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ꢓꢓꢓ

ꢔꢔꢓ

ꢓꢓꢔ

ꢔꢔꢓ

ꢓꢓꢓ

ꢀꢁꢂꢃꢌ

ꢀꢁꢂꢃꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢅ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢃꢇ

ꢀꢁꢂꢃꢈ

ꢀꢁꢂꢃꢉ

ꢀꢁꢂꢃꢊ

ꢀꢁꢂꢃꢋ

ꢀꢁꢂꢄꢌ

ꢀꢁꢂꢄꢃ

ꢀꢁꢂꢄꢄ

ꢀꢁꢂꢄꢅ

ꢀꢁꢂꢄꢆ

ꢓꢔꢔꢔꢓ

ꢔꢓꢓꢓꢔ

ꢔꢓꢓꢓꢓ

ꢔꢓꢓꢓꢔ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢓꢓꢔꢓꢓ

ꢓꢓꢓꢓꢓ

ꢓꢔꢔꢔꢓ

ꢔꢓꢓꢓꢔ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓ

ꢓꢓꢔ

ꢓꢔꢓ

ꢔꢓꢓ

ꢓꢓꢓ

ꢀꢁꢂꢄꢇ

ꢀꢁꢂꢄꢈ

ꢀꢁꢂꢄꢉ

ꢀꢁꢂꢄꢊ

ꢀꢁꢂꢄꢋ

ꢀꢁꢂꢅꢌ

ꢀꢁꢂꢅꢃ

ꢀꢁꢂꢅꢄ

ꢔꢓꢓꢓꢓ

ꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓ

ꢔꢓꢓꢓꢔ

ꢓꢔꢓꢔꢓ

ꢓꢓꢔꢓꢓ

ꢓꢓꢓꢓꢓ

ꢓꢔꢔꢔꢓ

ꢓꢓꢔꢓꢓ

ꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓ

ꢔꢓꢓ

ꢓꢔꢓ

ꢓꢓꢔ

ꢓꢔꢓ

ꢔꢓꢓ

ꢓꢓꢓ

ꢇꢈꢀꢀꢉꢊ

ꢀꢁꢂꢅꢅ

ꢍꢀꢁꢂꢌꢎ

ꢕꢖꢗꢘꢙ

ꢚꢚꢚꢚꢚ

ꢏꢐꢑꢃ

ꢏꢐꢑꢄ

ꢏꢐꢑꢅ

ꢏꢐꢑꢆ

ꢏꢐꢑꢇ

ꢒ

ꢏꢐꢑꢉꢈ

ꢏꢐꢑꢉꢉ

ꢏꢐꢑꢉꢊ

ꢏꢐꢑꢉꢋ

ꢏꢐꢑꢊꢌ

ꢏꢐꢑꢊꢃ

ꢏꢐꢑꢊꢄ

ꢏꢐꢑꢊꢅ

ꢏꢐꢑꢊꢆ

ꢏꢐꢑꢊꢇ

ꢏꢐꢑꢋꢊ

ꢏꢐꢑꢋꢋ

ꢏꢐꢑꢃꢌꢌ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

4) LCD Panel : 16 character x 4 line format (6-dot font, 1/33 bias)

ꢓꢓꢔꢔꢔꢔ

ꢓꢔꢓꢓꢓꢓ

ꢓꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓꢔ

ꢓꢔꢔꢔꢔꢓ

ꢓꢔꢔꢔꢔꢔ

ꢔꢔꢓ

ꢓꢓꢔ

ꢓꢓꢓ

ꢔꢔꢔ

ꢓꢓꢔ

ꢔꢔꢔ

ꢓꢓꢓ

ꢀꢁꢂꢃ

ꢀꢁꢂꢄ

ꢀꢁꢂꢅ

ꢀꢁꢂꢆ

ꢀꢁꢂꢇ

ꢀꢁꢂꢈ

ꢀꢁꢂꢉ

ꢀꢁꢂꢊ

ꢓꢓꢔꢔꢔꢓ

ꢓꢔꢓꢓꢓꢔ

ꢓꢔꢔꢔꢔꢔ

ꢓꢔꢓꢓꢓꢔ

ꢓꢓꢓꢓꢓꢓ

ꢓꢔꢔꢔꢔꢔ

ꢓꢔꢓꢓꢓꢓ

ꢓꢔꢔꢔꢔꢓ

ꢓꢔꢓꢓꢓꢓ

ꢓꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓꢓ

ꢔꢔꢔ

ꢓꢓꢓ

ꢔꢔꢓ

ꢓꢓꢔ

ꢔꢔꢓ

ꢓꢓꢓ

ꢀꢁꢂꢋ

ꢓꢔꢓꢓꢓꢓ

ꢓꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓꢓ

ꢀꢁꢂꢃꢌ

ꢀꢁꢂꢃꢃ

ꢀꢁꢂꢃꢄ

ꢀꢁꢂꢃꢅ

ꢀꢁꢂꢃꢆ

ꢀꢁꢂꢃꢇ

ꢀꢁꢂꢃꢈ

ꢓꢓꢔꢔꢔꢓ

ꢓꢔꢓꢓꢓꢔ

ꢓꢔꢓꢓꢓꢓ

ꢓꢔꢓꢓꢓꢔ

ꢓꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓꢓ

ꢓꢓꢔ

ꢓꢔꢓ

ꢔꢓꢓ

ꢓꢓꢓ

ꢀꢁꢂꢃꢉ

ꢀꢁꢂꢃꢊ

ꢀꢁꢂꢃꢋ

ꢀꢁꢂꢄꢌ

ꢀꢁꢂꢄꢃ

ꢀꢁꢂꢄꢄ

ꢀꢁꢂꢄꢅ

ꢀꢁꢂꢄꢆ

ꢓꢓꢔꢔꢔꢓ

ꢓꢔꢓꢓꢓꢔ

ꢓꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓꢓ

ꢓꢔꢓꢓꢓꢓ

ꢓꢔꢔꢔꢔꢔ

ꢓꢓꢓꢓꢓꢓ

ꢔꢓꢓ

ꢓꢔꢓ

ꢓꢓꢔ

ꢓꢔꢓ

ꢔꢓꢓ

ꢓꢓꢓ

ꢀꢁꢂꢄꢇ

ꢀꢁꢂꢄꢈ

ꢀꢁꢂꢄꢉ

ꢀꢁꢂꢄꢊ

ꢀꢁꢂꢄꢋ

ꢀꢁꢂꢅꢌ

ꢀꢁꢂꢅꢃ

ꢀꢁꢂꢅꢄ

ꢓꢓꢔꢔꢔꢓ

ꢓꢓꢓꢔꢓꢓ

ꢓꢓꢔꢔꢔꢓ

ꢓꢓꢓꢓꢓꢓ

ꢇꢈꢀꢀꢉꢊ

ꢕꢖꢗꢘꢙꢚ

ꢙ!ꢕ

ꢀꢁꢂꢅꢅ

ꢍꢀꢁꢂꢌꢎ

ꢕꢚꢕ"!ꢗ

ꢏꢐꢑꢃ

ꢏꢐꢑꢄ

ꢏꢐꢑꢅ

ꢏꢐꢑꢆ

ꢏꢐꢑꢇ

ꢏꢐꢑꢈ

ꢒ

ꢏꢐꢑꢉꢋ

ꢏꢐꢑꢊꢌ

ꢏꢐꢑꢊꢃ

ꢏꢐꢑꢊꢄ

ꢏꢐꢑꢊꢅ

ꢏꢐꢑꢊꢆ

ꢒ

ꢏꢐꢑꢋꢆ

ꢏꢐꢑꢋꢇ

ꢏꢐꢑꢋꢈ

ꢏꢐꢑꢋꢉ

ꢏꢐꢑꢋꢊ

ꢏꢐꢑꢋꢋ

ꢏꢐꢑꢃꢌꢌ

ꢀꢁꢂꢃ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

INITIALIZING

1) Initializing by Internal Reset Circuit

When the power is turned on, KS0075 is initialized automatically by power on reset circuit.

During the initialization, the following instructions are executed, and BF(Busy Flag) is

kept "High"(busy state) to the end of initialization.

ꢂ Display Clear instruction

Write "20H" to all DDRAM

ꢃ Set Functions instruction

DL = 1 : 8-bit bus mode

N

= 1 : 2-line display mode

RE = 0 : Extension register disable

BE = 0 : CGRAM/SEGRAM blink OFF

DH = 0 : Horizontal scroll enable

REV = 0 : Normal display (Not reversed display)

ꢄ Control Display ON/OFF instruction

D = 0 : Display OFF

C = 0 : Cursor OFF

B = 0 : Blink OFF

ꢈ Set Entry Mode instruction

I/D = 1 : Increment by 1

S = 0 : No entire display shift

BID = 0 : Normal direction segment port

ꢉ Set Extension Function instruction

FW = 0 : 5-dot font width character display

B/W = 0 : Normal cursor (8th line)

NW = 0 : Not 4-line display mode, 2-line mode is set because of N("1")

ꢊ Enable Shift instruction

HS = 0000 : Scroll per line disable

DS = 0000 : Shift per line disable

ꢊ Set scroll Quantity instruction

SQ = 000000 : Not scroll

2) Initializing by Hardware RESET input

When RESET pin = "Low", KS0075 can be initialized like the case of power on reset.

During the power on reset operation, this pin is ignored.

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

INITIALIZING BY INSTRUCTION

1) 8-bit interface mode

Power on

Condition: 270 kHz

Wait for more than 20 ms

after VDD rises to 4.5V

(DL=“1”)

Function set

0

1

0

1

4-bit interface

8-bit interface

1-line mode

DL

N

DB4

DB1 DB0

DB3 DB2

RS RW DB7 DB6 DB5

DL

(1)

0

1

N

0

x

2-line mode

µ

Wait for more than 39

s

0

1

0

1

0

1

display off

display on

cursor off

D

C

B

Dsplay ON/OFF Control

DB4

0

DB1 DB0

RS RW

DB6 DB5

DB3 DB2

DB7

0

cursor on

blink off

blink on

0

D

C

B

1

µ

Wait for more than 39

s

ClearꢀDsplay

DB4

0

DB1 DB0

DB3 DB2

RS RW DB7 DB6 DB5

0

1

0

Wait for more than 1.53ms

0

1

0

1

decrement mode

increment mode

entire shift off

Entry Mode Set

I/D

S

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

I/D

0

1

S

0

entire shift on

Initialization end

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

2) 4-bit interface mode

Power on

Condition: 270 kHz

Wait for more than 20 ms

after VDD rises to 4.5V

(DL=“0”)

Function set

0

1

0

1

4-bit interface

8-bit interface

1-line mode

2-line mode

DL

N

DB4

DB1 DB0

DB3 DB2

RS RW DB7 DB6 DB5

DL

(0)

0

1

x

Wait for more than 39µs

Function set

DB4

DB1 DB0

RS RW DB7 DB6 DB5

DB3 DB2

x

0

x

1

x

0

x

N

Wait for more than 39µs

0

1

0

1

0

1

display off

display on

cursor off

D

C

B

Dsplay ON/OFF Control

DB4

DB1 DB0

DB3 DB2

RS RW DB7 DB6 DB5

cursor on

blink off

blink on

x

0

1

0

D

C

B

Wait for more than 39µs

Clear Dsplay

DB4

DB1 DB0

RS RW DB7 DB6 DB5

DB3 DB2

x

0

1

Wait for more than 1.53ms

0

1

0

1

Entry ModeSet

decrement mode

increment mode

entire shift off

I/D

S

DB4

DB1 DB0

RS RW DB7 DB6 DB5

DB3 DB2

x

0

1

0

entire shift on

I/D

S

Initialization end

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

EXAMPLE OF INSTRUCTION AND DISPLAY CORRESPONDENCE

1) IE = "Low"

ꢁꢏꢐꢑꢒꢓꢔ ꢅꢕꢖꢖꢗꢘ ꢑꢙ ꢚ ꢂꢙꢛꢜꢛꢝꢗꢛꢞꢓ !ꢘ ꢜ"ꢓ ꢛꢙꢜꢓꢔꢙꢝꢗ

ꢖꢑꢒꢓꢔ ꢑꢙ ꢔꢓ#ꢓꢜ $ꢛꢔ$ꢕꢛꢜꢏ

%&ꢄ ꢄꢂꢅꢐ%'(

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ꢄꢈꢉ ꢄꢈꢊ ꢄꢈꢋ ꢄꢈꢌ ꢄꢈꢍ ꢄꢈꢎ ꢄꢈꢁ ꢄꢈꢀ

ꢎꢏ*ꢕꢙ$ꢜꢛꢑꢙ ꢅꢓꢜ ꢚ +,!ꢛꢜ- ꢁ,ꢗꢛꢙꢓ- ꢆ./ꢀ0

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ꢍꢏꢄꢛ#ꢖꢗꢝꢘ 12ꢃ1** &ꢑꢙꢜꢔꢑꢗ ꢚ ꢄꢛ#ꢖꢗꢝꢘꢃ&ꢕꢔ#ꢑꢔ ꢑꢙ

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ꢁꢂꢃꢁꢀ

ꢀ

ꢁ

ꢀ

ꢁ

ꢀ

ꢁ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

89 7ꢞ:!" $ꢝ!ꢝ !# &&'ꢏꢘ 4 7ꢞ:!"

;

'ꢙ

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ꢗ

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ꢀꢁꢂꢀꢃꢄ

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ꢖ

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ꢖꢗ9 7ꢞ:!" $ꢝ!ꢝ !# &&'ꢏꢘ 4 7ꢞ:!"

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ꢗ

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ꢀꢁꢂꢀꢃꢅꢆꢄ

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ꢗ

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ꢄ

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ꢖ

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B

'ꢙ

ꢖ

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ꢗ

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ꢂꢀꢃꢅꢆ ꢇꢀꢄ

ꢗ

ꢖ

ꢗ

ꢖ

ꢗ

ꢖ

ꢖꢒ9 7ꢞ:!" $ꢝ!ꢝ !# &&'ꢏꢘ 4 7ꢞ:!"

ꢙ

'ꢙ

ꢖ

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ꢗ

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ꢀꢃꢅꢆ ꢇꢀꢈꢄ

ꢗ

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ꢗ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ꢁꢉꢏ ꢇꢔꢛꢜꢓ ꢝꢜꢝ ꢜꢑ ꢄꢄꢆ'3 ꢚ ꢇꢔꢛꢜꢓ ꢀ

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ꢄꢅꢆ ꢇꢁꢈꢈꢀ

ꢅꢆ ꢇꢁꢈꢈꢉꢀ

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ꢎꢍꢏ &ꢗꢓꢝꢔ ꢄꢛ#ꢖꢗꢝꢘ

ꢆꢅ

ꢀ

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ꢀ

ꢁ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

2) IE = "High"

ꢚ) *ꢓꢕꢉꢈ ꢀ+ꢍꢍꢎꢏ ꢓꢐ , -ꢐꢌꢋꢌꢆꢎꢌ.ꢉꢇ /ꢏ ꢋꢖꢉ ꢌꢐꢋꢉꢈꢐꢆꢎ

ꢍꢓꢕꢉꢈ ꢓꢐ ꢈꢉꢊꢉꢋ 0ꢌꢈ0+ꢌꢋ)

ꢃꢀ

ꢃ' ꢜ ꢝ ꢜ ꢗ ꢜ ꢑ ꢜ ꢞ ꢜ ꢘ ꢜ ꢙ ꢜ ꢚ ꢜ ꢛ

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ꢃꢀ

ꢛ

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ꢛ

ꢚ

ꢛ

ꢘ) ꢁ6ꢋꢉꢐꢇꢉꢇ &+ꢐ0ꢋꢌꢓꢐ ꢀꢉꢋ , ꢑꢒꢔꢓꢐꢋ1 ꢞꢒꢎꢌꢐꢉ

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ꢛ

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ꢛ

ꢚ

ꢛ

ꢚ

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ꢛ

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ꢛ

ꢚ

ꢛ

ꢑ) ꢜꢌꢊꢍꢎꢆꢏ 2342&& 5ꢓꢐꢋꢈꢓꢎ , ꢜꢌꢊꢍꢎꢆꢏ45+ꢈꢊꢓꢈ ꢓꢐ

ꢀ

ꢃꢀ

ꢛ

ꢃ' ꢜ ꢝ ꢜ ꢗ ꢜ ꢑ ꢜ ꢞ ꢜ ꢘ ꢜ ꢙ ꢜ ꢚ ꢜ ꢛ

ꢛ

ꢚ

ꢛ

ꢗ) 'ꢈꢌꢋꢉ ꢇꢆꢋꢆ ꢋꢓ ꢜꢜꢃꢄꢅ , 'ꢈꢌꢋꢉ ꢀ

ꢁꢀ

ꢃꢀ

ꢚ

ꢃ' ꢜ ꢝ ꢜ ꢗ ꢜ ꢑ ꢜ ꢞ ꢜ ꢘ ꢜ ꢙ ꢜ ꢚ ꢜ ꢛ

ꢛ

ꢚ

ꢛ

ꢚ

ꢛ

ꢚ

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

7. Write data to DDRAM : Write A

SA_

ꢁꢊ

ꢕ

ꢁ&

ꢋ

ꢀ'ꢌ

ꢋ

ꢀ'ꢙ

ꢕ

ꢀ'ꢍ

ꢋ

ꢀ'ꢘ

ꢋ

ꢀ'ꢗ

ꢋ

ꢀ'ꢖ

ꢋ

ꢀ'ꢕ

ꢋ

ꢀ'ꢋ

ꢕ

ꢀ

12. Write data to DDRAM : Write G

SAMSUNG_

RS

1

RW

0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

13. Set DDRAM Address 20H

SAMSUNG

_

RS

0

RW

0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

0

14. Write data to DDRAM : Write K

SAMSUNG

K_

RS

1

RW

0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

ꢀ

19. Write data to DDRAM : Write 5

SAMSUNG

KS0075_

RS

1

RW

0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

20. Set DDRAM Address 40H

SAMSUNG

KS0075

_

RS

0

RW

0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

FRAME FREQUENCY

1) 1/17 duty cycle

Item

Display Font Width

5-dot font width

200 clocks

79.4Hz

6-dot font width

240 clocks

1-line selection period

Frame frequency

66.2Hz

* fosc = 270 kHz (1 clock = 3.7µs)

‘

2) 1/33 duty cycle

Item

Display Font Width

5-dot font width

100 clocks

81.8Hz

6-dot font width

120 clocks

1-line selection period

Frame frequency

68.2Hz

ꢅ fosc = 270 kHz (1 clock = 3.7 µs)

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

POWER SUPPLY FOR DRIVING LCD PANEL

1) When an external power supply is used

2) When an internal booster is used

ꢅ 1. Boosted output voltage should not exceed the maximum value (13 V) of the LCD driving

voltage. Especially, a voltage of over 4.3V should not be input to the reference voltage

(Vci) when boosting three times.

2. A voltage of over 5.5V should not be input to the reference voltage (Vci) when boosting

twice.

3. The value of resistance, according to the number of lines, duty ratio and the bias, is

shown below. (Refer to Table 13)

Table 13. Duty Ratio and Power Supply for LCD Driving

Item

Number of lines

Duty ratio

Bias

Data

1

1/17

1/5

R

2 or 4

1/33

1/6.7

R

Divided resistance

R

R0

R

2.7R

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

MAXIMUM ABSOLUTE RATE

Characteristic

Power Supply Voltage (1)

Power Supply Voltage (2)

Input Voltage

Symbol

V_DD

Value

-0.3 ~ +7.0

Unit

V

V_LCD

V_IN

V_DD-15.0 ~ V_DD+0.3

-0.3 ~ V_DD+0.3

-30 ~ +85

V

Operating Temperature

Storage Temperature

T_OPR

T_STG

^oC

-55 ~ +125

ꢅ Voltage greater than above may damage to the circuit (VDD≥V1≥V2≥V3≥V4≥V5)

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

ELECTRICAL CHARACTERISTICS

DC Characteristics

(VDD = 2.7V ~ 5.5V, Ta=-30 ~ + 85 ^oC)

Characteristic

Operating Voltage

Supply Current

Symbol

V_DD

Condition

Min

2.7

-

Typ

-

Max

5.5

Unit

V

-

I_DD

Internal oscillation or external clock.

0.15

0.3

mA

(V_DD=3.0V,fosc=270KHz)

Input Voltage (1)

(Except OSC1)

V_IH1

V_IL1

-

0.7V_DD

-

V_DD

0.2V_DD

0.6

V_DD=2.7 to 3.0

V_DD=3.0 to 5.5

-

-0.3

-

-0.3

Input Voltage (2)

(Osc1)

V_IH2

V_IL2

0.7V_DD

V_DD

V

-

0.2V_DD

-

Output Voltage (1)

(DB0 To DB7)

V_OH1

V_OL1

V_OH2

V_OL1

Vd_COM

I_OH=-0.1 mA

I_OL=0.1 mA

0.75V_DD

-

0.2V_DD

-

Output Voltage(2)

(Except DB0 To Db7)

Voltage Drop

0.8V_DD

I_O=-40 µA

I_O=40 µA

-

0.2V_DD

1

V

I_O= ꢋ0.1mA

Vd_SEG

I_LKG

I_IL

-

1

Input Leakage Current

Low Input Current

V_IN=0V to V_DD

-1

µA

V_IN=0V, V_DD=3V

(PULL UP)

-10

-50

-120

Internal Clock

(external Rf)

f_OSC

190

270

350

KHz

Rf=91[kΩ] ꢋ2%

(V_DD=5V)

External Clock

f_EC

125

45

-

270

50

-

410

55

0.2

-

KHz

%

duty

t_R, t_F

V_OUT2

-

µs

V

Voltage Converter Out2

(Vci = 4.5V)

-3.0

-4.2

Ta = 25ꢌ, C=1µF,

I_OUT= 0.25mA,

f_OSC=270KHz

Voltage Converter Out3

(Vci = 2.7V)

V_OUT3

-4.3

-5.1

-

Voltage Converter Input

LCD Driving Voltage

Vci

-

1.0

3.0

-

4.5

V_LCD

V_DD-V5

1/5 Bias

13.0

V

1/6.7 Bias

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

AC Characteristics

(V_DD=4.5~ 5.5V, Ta=-30 ~ +85 ^oC)

Mode

Item

Symbol

Min

Typ

Max

Unit

E Cycle Time

tc,

500

-

E Rise / Fall Time

E Pulse Width (High, Low)

R/W and RS Setup Time

R/W and RS Hold Time

Data Setup Time

t_R, t_F

tw

-

230

40

10

60

10

500

-

20

-

ns

(1) Write Mode

(refer to Fig-15)

tsu1

t_H1

tsu2

t_H2

tc

-

Data Hold Time

-

E Cycle Time

-

E Rise / Fall Time

t_R,t_F

tw

20

E Pulse Width (High, Low)

R/W and RS Setup Time

R/W and RS Hold Time

Data Output Delay Time

Data Hold Time

230

40

10

-

ns

(2) Read Mode

(refer to Fig-16)

tsu

t_H

-

t_D

160

t_DH

5

-

Serial Clock Cycle Time

Serial Clock Rise/Fall Time

Serial Clock Width (High, Low)

Chip Select Setup Time

Chip Select Hold Time

Serial Input Data Setup Time

Serial Input Data Hold Time

Serial Output Data Delay Time

Serial Output Data Hold Time

tc

0.5

-

20

µs

t_R,t_F

tw

50

200

60

20

100

-

(3) Serial

tsu1

t_H1

-

Interface Mode

(refer to Fig-17)

-

ns

tsu2

t_H2

-

160

-

t_D

t_DH

5

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

AC Characteristics

(continued)

(V_DD=2.7 ~ 5.5V, Ta=-30 ~ +85 ^oC)

Mode

Item

Symbol

Min

Typ

Max

Unit

E Cycle Time

tc,

1000

-

E Rise / Fall Time

E Pulse Width (High, Low)

R/W and RS Setup Time

R/W and RS Hold Time

Data Setup Time

t_R, t_F

tw

-

450

60

20

195

10

1000

-

25

-

ns

(4) Write Mode

(refer to Fig-15)

tsu1

t_H1

tsu2

t_H2

tc

-

Data Hold Time

-

E Cycle Time

-

E Rise / Fall Time

t_R,t_F

tw

25

E Pulse Width (High, Low)

R/W and RS Setup Time

R/W and RS Hold Time

Data Output Delay Time

Data Hold Time

450

60

20

-

ns

(5) Read Mode

(refer to Fig-16)

tsu

t_H

-

t_D

360

t_DH

5

-

Serial Clock Cycle Time

Serial Clock Rise/Fall Time

tc

1

20

µs

t_R,t_F

tw

-

50

Serial Clock Width (High, Low)

Chip Select Setup Time

400

60

20

200

-

(6) Serial

tsu1

t_H1

tsu2

t_H2

t_D

-

Interface Mode

(refer to Fig-17)

Chip Select Hold Time

-

ns

Serial Input Data Setup Time

Serial Input Data Hold Time

Serial Output Data Delay Time

Serial Output Data Hold Time

-

360

-

t_DH

5

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Fig-15. Write Mode

Fig-16. Read Mode

KS0075

34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD

Fig-17. Serial Interface Mode

Reset Timing

(V_DD= 2.7 ~ 5.5V, Ta = -30 ~ +85 ^oC)

Item

Symbol

t_RES

Min

10

Typ

-

Max

-

Unit

ms

Reset low level width

(refer to Fig-18)


型号：	KS0075
厂家：	SAMSUNG
描述：	34COM/100SEG DRIVER & CONTROLLER FOR DOT MATRIX LCD 34COM / 100SEG驱动器和控制器的点阵LCD 驱动器显示控制器微控制器和处理器外围集成电路 CD 时钟
文件：	总71页 (文件大小：529K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS0075 [SAMSUNG]

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