KS0119Q2 [SAMSUNG]
Color Signal Encoder, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100;
| 型号： | KS0119Q2 |
| 厂家： | 
SAMSUNG |
| 描述： | Color Signal Encoder, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100 编码器 商用集成电路 |
| 文件： | 总50页 (文件大小：530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS0119 Data Sheet
MULTIMEDIA VIDEO
VIDEO ENCODER
The KS0119 combines NTSC encoding with conventional
RAM-DAC functions so that digitized video or computer
generated graphics can be displayed on either NTSC or PC
monitors. There are two data input channels which allow
mixing. Provision is also made for analog mixing at the
output. Operation modes can be programmed under host
control. The KS0119 can be used with other members of the
Samsung multimedia chip set in a typical desktop
multimedia environment.
80 or 100 PQFP
FEATURES
ORDERING INFORMATION
• Accepts true color; high color; color indexed; CCIR
601 4:4:4, 4:2:2, 4:1:1, or 2:1:1 formatted video
inputs
• Supports analog NTSC CVBS, S-VIDEO, or RGB
display
• Fully programmable timing generation; supports
CGA, VGA, SVGA display up to 45 MHz pixel clock
rate (with 100 pin package)
Device Package Temp. Range Max. CKV
KS0119 80-QFP 0° ~ +65°C
KS0119Q2 100-QFP 0° ~ +65°C
32 MHz
45 MHz
• Accepts up to 2 input channels for digital mixing
• Operate as slave or master in timing generation
• Supports alpha, chroma, and window keying for
digital mixing
APPLICATIONS
• PC Video
• RAM DAC, Gamma Correction
• YUV DAC for MPEG, JPEG Play Back
• NTSC Video Encoder
• Provides an analog RGB mixing function
• Contains 3 256X8 color palette tables and 3 15X8
overlay color look up tables
RELATED PRODUCT
• Contains 3 10-bit video grade DACs
• Provides a parallel microprocessor or a 3-wire serial
interface
• KS0122 MULTISTANDARD VIDEO DECODER
• Contains a two way color space converter:
RGB -> NTSC, YCbCr -> RGB
• Supports power down mode
BLOCK DIAGRAM
RIN,GIN,BIN
AKY
CLUT
3X8X256
Triple
Analog
MUX
R/CVBS
G/Y
B/C
Overlay
Triple
10-bit
DAC
Color
Space
Input
Formatter
CLUT
P[0:31]
Mixing
3X8X15
Converter
NTSC
Processor
AV
VBLK
Interpolator
HSYN
VSYN
CSYN
Mixing
Control
DKY/R
Timing
Control
F2
MRQST/MODE
CKP
Microprocessor
Interface
CK27
CKV
A[0:3]
D[0:7]
CS R/W
P/S
PAGE 1 OF 50
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ELECTRONICS
MULTIMEDIA VIDEO
KS0119 Data Sheet
PIN ASSIGNMENT
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
65
66
67
68
69
70
71
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
R/CVBS
RIN
F2
VBLK
AV
G/Y
GIN
VSS
VDD
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
B/C
BIN
AKY
72 VREF
73 IREF
74 COMP
75 CKV
KS0119
76
77
78
79
80
VSS
CK27
VDD
DKY/R
P0
3
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1
2
4
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81 NCP
82 NCP
NCP
NCP
F2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
83 R/CVBS
84 RIN
VBLK
AV
85 G/Y
GIN
VSS
VDD
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
NCP
NCP
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
B/C
BIN
AKY
VREF
IREF
COMP
CKV
VSS
CK27
VDD
DKY/R
P0
KS0119Q2
NCP
NCP
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
PAGE 2 OF 50
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ELECTRONICS
MULTIMEDIA VIDEO
KS0119 Data Sheet
TYPICAL APPLICATIONS
The KS0119 is shown in a VGA overlay application with the KS0122 Multistandard Video Decoder in Figure 1.
FRAME
BUFFER
ENCODER
KS0119
VGA Display
NTSC/PAL Video Input
TV,VCR,Laser Disc
S-video or Composite
MULTI
MEMORY
CONTROLLER
STANDARD
DECODER
KS0122
µP Bus
Figure 1. VGA Overlay
Figure 2 shows a video CD playback system using the KS0119 as a video encoder.
VIDEO CD
DECODER
ENCODER
KS0119
NTSC Display
Figure 2. Video CD Playback
PAGE 3 OF 50
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ELECTRONICS
MULTIMEDIA VIDEO
KS0119 Data Sheet
PIN DESCRIPTION
Pin #
(80)
Pin #
(100)
Pin Name
Type
Description
VIDEO BUFFER INTERFACE
P0 - P31 80,1-15, 98,4-18, 23-
I
Digital video input bus.
20 - 35
27,33-43
F2
40
48
53
O
Field 2 indicator. Active low signal.
MRQST 41
/MODE
I/O Dual function pin. During power-on, it is an input and its logic state
determines whether the chip operates in NTSC mode or VGA pass
through mode. A 4.7 K pull-up resistor sets the chip in VGA pass
through mode. Otherwise it defaults to NTSC mode. After power-on
this pin becomes an output and is high during active lines’ sync tip.
AV
38
39
17
79
46
47
20
97
I/O Active video indicator. Input in slave mode; output in master mode.
I/O Vertical blank. Input in slave mode; output in master mode.
VBLK
CKP
DKY/R
O
I
Pixel clock output.
CMD
Dual function input pin. Configured by the
register bit 2. It can
be used as either digital mixing or hardware RUN input. Please refer
to the command register description for more detail.
ANALOG MULTIPLEXER INPUT
RIN
GIN
BIN
AKY
66
68
70
71
84
86
88
89
I
I
I
I
Analog R input to the analog mixing multiplexer.
Analog G input to the analog mixing multiplexer.
Analog B input to the analog mixing multiplexer.
Analog multiplexer control. A logic ‘0’ connects analog RGB inputs to
the output pins. A ‘1’ connects DACs’ outputs to the output pins.
VIDEO OUTPUT PORT
HSYN
VSYN
CSYN
58
57
59
70
O
O
Horizontal Sync. Active low, TTL signal for monitor. In the pass
through mode HSYN is the inverted AV (pin 38).
69
Vertical Sync. Active low, TTL signal for monitor. In the pass through
mode VSYN is the inverted VBLK (pin 39)
71
83
O
O
Composite Sync. Active low, TTL signal for monitor.
CMD
bits 5
R/CVBS 65
Either an analog R or Composite output, controlled by
and 1. It can drive a 37.5 Ω load (doubly terminated 75 Ω load).
CMD
CMD
G/Y
B/C
67
69
85
87
O
O
Either an analog G or S-video Y output, controlled by
1. It can drive a 37.5 Ω load.
bits 5 and
bits 5 and
Either an analog B or S-video C output, controlled by
1. It can drive a 37.5 Ω load.
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ELECTRONICS
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KS0119 Data Sheet
PIN DESCRIPTION (Continued)
Pin #
(80)
Pin #
(100)
Pin Name
Type
Description
REFERENCE AND COMPENSATION
VREF
72
90
I/O Voltage reference. It has an internal voltage reference circuit, but may
be overridden by an external voltage reference input. A 0.1 µF
ceramic capacitor is required between this pin and GND.
IREF
73
74
91
92
I
A resistor is connected between this pin and GND to control the DAC
output current.
COMP
I
Compensation capacitor for the DAC internal reference amplifier. A
0.1 µF ceramic capacitor is required between this pin and VDDA.
HOST INTERFACE
P/S
46
47
48
49
58
59
60
61
I
I
I
Microprocessor interface configuration control. Tie to VDD to select
parallel mode. Tie to VSS to select serial mode.
CS
(SFRS)
Chip select strobe in parallel mode (Frame Sync in serial mode).
R/W
(SCLK)
Read/write in parallel mode (Serial clock in serial mode).
D7
I/O Data bus msb in parallel mode (Serial data in serial mode).
(SDAT)
D0 - D6
A0 - A3
56-50
45-42
68-62
57-54
I/O Parallel data bus bit 0 to 6.
I
Address bus for parallel interface.
CLOCK INPUT
CKV
75
77
93
95
I
I
Clock input used to generate pixel clock for VGA display.
27 MHz clock input, required for NTSC display.
CK27
POWER AND GROUND
VDD
16,36,
60,78
19,44,72,96 +5V Digital power supply.
VSS
18,19,
37,62,
63,76
21,22,45,74, GND Digital ground.
75,94
VDDA
NCP
NCP
61,64
76,80
+5V Analog power supply.
N/A
1-3,28-32,
49-52,77-
79,81,82,99,
100
-
These pins are directly connected to the die substrate. They are
intended as heat dissipation points. It is recommended that each
corner set of NCP pins be connected to as large as possible solid
metal plane on the PCB component surface side. If electrical connect
is desired (not required) only connection to VDDA is allowed.
PAGE 5 OF 50
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ELECTRONICS
MULTIMEDIA VIDEO
KS0119 Data Sheet
PIN CROSS REFERENCE (Numerical Order by Pin Number):
80-PQFP
Pin #
1
Pin Name
P1
Pin #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
VDD
VSS
AV
Pin #
Pin Name
Pin #
Pin Name
VDDA
VSS
41 MRQST/MODE 61
2
P2
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A3
A2
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
3
P3
VSS
4
P4
A1
VDDA
R/CVBS
RIN
5
P5
A0
6
P6
P/S
7
P7
CS(SFRS)
R/W(SCLK)
D7(SDAT)
D6
G/Y
8
P8
GIN
9
P9
B/C
10
11
12
13
14
15
16
17
18
19
20
P10
P11
P12
P13
P14
P15
VDD
CKP
VSS
VSS
P16
BIN
D5
AKY
D4
VREF
IREF
COMP
CKV
D3
D2
D1
D0
VSS
VSYN
HSYN
CSYN
VDD
CK27
VDD
VBLK
F2
DKY/R
P0
PAGE 6 OF 50
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KS0119 Data Sheet
PIN CROSS REFERENCE (Continued):
100-PQFP
Pin #
1
Pin Name
NCP
NCP
NCP
P1
Pin #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
P19
Pin #
51
Pin Name
NCP
Pin #
76
Pin Name
VDDA
NCP
NCP
NCP
VDDA
NCP
NCP
R/CVBS
RIN
2
P20
52
NCP
77
3
NCP
NCP
NCP
NCP
NCP
P21
53 MRQST/MODE 78
4
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
A3
A2
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
5
P2
6
P3
A1
7
P4
A0
8
P5
P/S
9
P6
P22
CS(SFRS)
R/W(SCLK)
D7(SDAT)
D6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P7
P23
G/Y
P8
P24
GIN
P9
P25
B/C
P10
P11
P12
P13
P14
P15
VDD
CKP
VSS
VSS
P16
P17
P18
P26
D5
BIN
P27
D4
AKY
P28
D3
VREF
IREF
COMP
CKV
P29
D2
P30
D1
P31
D0
VDD
VSS
AV
VSYN
HSYN
CSYN
VDD
VDDA
VSS
VSS
CK27
VDD
DKY/R
P0
VBLK
F2
NCP
NCP
NCP
NCP
VSS
PAGE 7 OF 50
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ELECTRONICS
MULTIMEDIA VIDEO
KS0119 Data Sheet
1. GENERAL DESCRIPTION
The KS0119 is a digital NTSC encoder combined with basic RAM-DAC functions. It is designed to be a high
performance, cost effective NTSC or PC display driver. The chip consists of a two way Color Space Converter,
which is capable of supporting almost all the popular input formats pertaining to PC video, graphics, or image
compression/decompression. The chip contains signal processing blocks to enhance image quality and reduce
artifacts due to sampling. It provides image manipulation facilities such as masking, mixing, hue control, and color
lookup tables to create special effects. It includes a programmable Timing Generator to generate the
synchronization signals and color burst for different display monitors.
1.1. Application
The KS0119 is a versatile chip, which can be used for many application such as NTSC encoding, YUV DAC, RAM
DAC, Gamma correction, mixing, and VGA overlay. CK27 must be used for NTSC encoder, whereas CKV must be
used for the others. It is recommended that the unused clock input pin be tied to a static state.
1.2. Power On Default
The KS0119 can be configured for two power-on default states: one for NTSC video encoding and the other for VGA
overlay application. For the latter the MRQST/MODE pin must be pulled up so the KS0119 defaults to sync pass
through mode and Channel A is set to support 8-bit pseudo color format after power up. In this mode, the KS0119
functions as a RAM-DAC. The internal video timing generator is disabled; the horizontal and vertical syncs are delay
compensated for the video path delay and passed to the sync output pins. The sync pass through mode is
recommended for VGA overlay application.
Table 1: Power On Default State
Power On MRQST/MODE Pin State
Operations Channel A Input Format SYNCPT Clock Source
0
1
NTSC encoding 4:2:2 YCbCr
VGA overlay 8 bit pseudo color
0
1
CK27
CKV
1.3. Operation Mode
The KS0119 can be configured to operate either in master mode or slave mode. In the master mode the encoder
uses the parameter stored in the CRT control registers to generate all the video timings and outputs synchronizing
signals (refer to “VIDEO OPERATIONAL TIMING” on page 18). In the slave mode the encoder synchronize the
,
internal pixel counter on the falling edge of AV and line counter on the rising edge or VBLK. The sync outputs, HSYN
SYNCPT
and VSYN, waveform can be modified if sync pass through is disabled (
related to the sync generation.
=0). Table 2 shows the registers
Table 2: Sync Output Generation
MASTER
SLAVE
MSTR
=1
MSTR
SYNCPT
MSTR
SYNCPT
=0, =0
Control Registers
HSYN, VSYN
=0,
Pass through
Inverted AV and VBLK
=1
Internally generated
Active low
Regenerated
Active low
Video Output Port Sync
Polarity
VSP HSP
Input Sync Polarity Control
CRT Control Registers
Comments
N/A
,
Index Registers 70 - 79h
Recommend for VGA
overlay application
PAGE 8 OF 50
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ELECTRONICS
MULTIMEDIA VIDEO
KS0119 Data Sheet
1.4. Power Down Mode
The KS0119 supports power down mode; the DAC outputs can be put into high impedance state by turning off the
current source to conserve power.
1.5. Digital Video Input Format
The digital video input is a 32 bit port. This port can be used as a single channel or logically divided into two channels:
A and B. Channel A’s input can be true color, color indexed, or CCIR 601 formats. Channel B’s input is restricted to
CCIR 601 formats.The supported formats and their bit assignments are shown in Table 3 and Table 4.
The KS0119 accepts certain input combinations from Channel A and B. However the following rules must be
observed when both channels are selected (their format registers contain valid numbers):
1. Channel B’s input is ignored if mixing is not enabled.
2. If mixing is enabled, channel A is the foreground and will be displayed if the mixing key is false.
3. In YC/YC mixing, both channels must have the same format (e.g. Channel A’s format is 4:1:1A, Channel B’s
format must be 4:1:1A. See Table 3 and Table 4).
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ELECTRONICS
MULTIMEDIA VIDEO
KS0119 Data Sheet
Table 3: Channel A Input Format
FORMAT REGISTER (BIT 7 - 4)
VALUE
1
2
3
4
RGB
15
5
12
N
6
9
A
2:1:1 A
16
B
4:1:1 A
12
C
4:1:1 B
16
TYPE
4:2:2
16
# of Bits 24 16 16
8
Pixel Byte Sequence
2N +1 2N +1 4N +1 +2 +3 4N +1
Pixel Bus
N
N
N
N
N
+2 +3
Cr0
P0
B0 B0 B0 B0
B1 B1 B1 B1
B2 B2 B2 B2
B3 B3 B3 B3
B4 B4 G0 B4
B5 G0 G1 G0
B6 G1 G2 G1
B7 G2 G3 G2
G0 G3 G4 G3 OVL0
G1 G4 G5 G4 OVL1
G2 G5 R0 R0 OVL2
G3 R0 R1 R1 OVL3
G4 R1 R2 R2
G5 R2 R3 R3
G6 R3 R4 R4
G7 R4 R5 TKEY
R0
P0 P0 Cb0 Cr0 Cb0 Cr0
P1 P1 Cb1 Cr1 Cb1 Cr1
P2 P2 Cb2 Cr2 Cb2 Cr2
P3 P3 Cb3 Cr3 Cb3 Cr3
Cb0
Cb1
Cb2
Cb3
P1
Cr1
P2
Cr2
P3
Cr3
P4
P4 P4 Cb4 Cr4 Cb4 Cr4 Cr6 Cr4 Cr2 Cr0 Cb4
P5 P5 Cb5 Cr5 Cb5 Cr5 Cr7 Cr5 Cr3 Cr1 Cb5
P6 P6 Cb6 Cr6 Cb6 Cr6 Cb6 Cb4 Cb2 Cb0 Cb6
P7 P7 Cb7 Cr7 Cb7 Cr7 Cb7 Cb5 Cb3 Cb1 Cb7
Cr4
P5
Cr5
P6
Cr6
P7
Cr7
P8
Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0
Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1
Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2
Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3
Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4
Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5
Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6
Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
R1
R2
R3
R4
R5
R6
R7
PAGE 10 OF 50
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KS0119 Data Sheet
Table 4: Channel B Input Format
FORMAT REGISTER (BIT 3 - 0)
VALUE
1
2
3
4
5
6
7
9
TYPE 4:4:4 4:2:2 A
4:2:2 B
24
2:1:1 A
16
2:1:1 B
24
4:1:1 A
12
4:1:1 B
16
4:4:4
24
# of Bits 24
Pixel
16
Pixel Byte Sequence
2N +1 2N +1 2N +1 2N +1 4N +1 +2 +3 4N +1
Bus
N
+2
+3
N
P0
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
P1
P2
P3
P4
P5
P6
P7
P8
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
Cr0
Cr1
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
Cb0 Cb0 Cr0 Cb0
Cb1 Cb1 Cr1 Cb1
Cb2 Cb2 Cr2 Cb2
Cb3 Cb3 Cr3 Cb3
Cb4 Cb4 Cr4 Cb4
Cb5 Cb5 Cr5 Cb5
Cb6 Cb6 Cr6 Cb6
Cb7 Cb7 Cr7 Cb7
Cb0 Cr0 Cb0
Cb1 Cr1 Cb1
Cb2 Cr2 Cb2
Cb3 Cr3 Cb3
Cb4 Cr4 Cb4
Cb5 Cr5 Cb5
Cb6 Cr6 Cb6
Cb7 Cr7 Cb7
Cb0
Cb1
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cb6
Cb7
Y0
Cb2
Cb3
Cr6 Cr4 Cr2 Cr0 Cb4
Cr7 Cr5 Cr3 Cr1 Cb5
Cb6 Cb4 Cb2 Cb0 Cb6
Cb7 Cb5 Cb3 Cb1 Cb7
Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0
Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1
Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2
Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3
Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4
Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5
Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6
Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
PAGE 11 OF 50
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ELECTRONICS
MULTIMEDIA VIDEO
KS0119 Data Sheet
2. DIGITAL MIXING
The KS0119 supports digital mixing between the two input channels. Digital mixing is the process of replacing a
selected area in the foreground (Channel A) with the corresponding area in the background (Channel B) according
to the output of the keying function. The result is that the foreground objects appear situated in front of the
background’s. Mixing is an indispensable tool to create special effects, such as animation, picture in picture, and
video overlay. The ability to select a small area to display can be used to reduce or hide the image download time
MXCTR
during presentations. The digital mixing is controlled by the Mixing Control Register (
05h to 0Dh.
) and control registers
Figure 3. Digital Mixer Signal Flow Diagram
2.1. Mixing Methods
The KS0119 supports two types of mixing: RGB/YC and YC/YC.
2.1.1. RGB/YC Mixing
RGB/YC mixing is automatically selected if channel A’s format is either high color or pseudo color. The process
simply replaces channel A’s video with Channel B’s when the output of the Keying function is 1.
2.1.2. YC/YC Mixing
If channel A’s input is YCbCr formatted (format register value greater than 7), then YC/YC mixing is selected. In YC/
YC mixing, when the output of the Keying function is 1, the Channel A’s chrominance components are replaced with
Channel B’s, while the luminance signals are linearly blended according to the equation
1
8
--
Yout =
[ K Ya + (1 – K) Yb]
Mixing Control
MXCTR
). Linear Mixing
where K is a programmable value, from 0 to 7, stored in the
preserves the shadows inside the keyed area.
register (
2.2. Keying Methods
The KS0119 supports Window Keying, Index Keying, Chroma Keying, Alpha Keying, External Keying, and certain
combinations of them. These are described in detail below.
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KS0119 Data Sheet
2.2.1. Index Keying
If channel A’s input format is 2, 3, 4, 5, or 6, Index Keying can be used for mixing. Channel A’s inputs are first
TEMPLATE TMPLB TMPLA
compared with the contents in the two 8 bit
registers (
,
). The results are then filtered by
MASK MSKB MSKA
the
registers (
,
) and ANDed together to generate the key signal. If the input is 8 or 15 bits wide,
the unused bits are automatically masked out. Figure 4 shows the logic operation involved in Index Keying.
T
C
H
E
M
P
L
A
N
N
E
L
M
A
S
K
INDEX
KEY
A
T
E
A
Figure 4. Index Keying Generation
2.2.2. Chroma Keying
If channel A’s input is YCbCr format, Chroma Keying can be used for mixing. A rectangular area is specified in the
Cb-Cr space (Figure 5). If Channel A’s Cb/Cr values fall within this area, Channel B’s video will be displayed. In this
TMPLA
TMPLB
MSKA
MSKB
and specify the lower
mode,
and
specify the lower and upper Cb, respectively, and
and upper Cr, respectively, in the Cb-Cr space. Note that Cb and Cr are binary offset numbers with 128
corresponding to zero intensity, 0 and 255 corresponding to maximum intensity.
Cr
128,255
CCIR Color
Key
255,128Cb
128,128
Figure 5. Cb-Cr Chroma Keying
2.2.3. Window Keying
A rectangular key window is specified in X-Y coordinates in the active display area. If window mixing is enabled and
OUTSD
Mixing Control
the
outside the window. The converse is true if the
OUTSD
bit of the
register is 0, Channel B is displayed inside the window, and Channel A is
OUTSD
bit is 1. If both the Chroma and Window Keyings are enabled,
bit specifies where the Chroma Keying will be applied: 0 inside the window and 1 outside the window.
the
The 8 msb’s of the four 10 bit coordinate registers, Window Horizontal Start Address, Window Horizontal End
WHS WHE WVS
Address, Window Vertical Start Address and Window Vertical End Address, are stored in the
,
,
and
register. The four msb registers are double
WVE
register will transfer the four msb registers’
WVE
WHV
registers, respectively, while the 2 lsb bits are stored in the
WVE
clocked, and synchronized to the
write. A write to the
contents, concatenated with their corresponding lsb’s, to the respective final address registers. Modifying the msb
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KS0119 Data Sheet
WVE
register without writing to the
register will have no effect on the final address register. For multiplexed YCbCr
video inputs, it is recommended that the horizontal window boundaries equal integer multiples of the block size.
2.2.4. Alpha Keying
If Channel A’s input is only 15 bits (format 4, RGB 5:5:5), bit 15 of the input can be used as a mixing key.
2.2.5. External Key
DKF
Command
CMD
register ( ) configures this pin as an
Pin DKY/R can be used as a mixing key if the
external key input.
bit of the
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KS0119 Data Sheet
3. SIGNAL PROCESSING
3.1. Y/C Interpolation Filters
The incoming YCbCr signals are processed by the Interpolation Unit to increase the data rates to 13.5 MHz. (4:4:4
format). The multiplexed chroma signals are up sampled first, and then pass through either a 6th-order half-band or
an 8th-order quarter-band filter. The reconstruction filters have flat 0 to 0.6 MHz frequency response as shown in
Figure 6-(a). The received half-sampled luminance component (MPEG decoder output, 360 samples/line), which
has a bandwidth less than 3 MHz, after being up sampled, will pass through a 14th-order smooth filter whose
frequency response characteristic is shown in Figure 6-(b). These filters ensure the preservation of base band
signals as well as the elimination of attendant high frequency aliasing components due to up sampling.
HALF-BAND
QUARTER-BAND
Frequency (MHz)
Frequency (MHz)
(a) Chrominance
(b) Luminance
Figure 6. Interpolation Filter Characteristics
3.2. Band-limit Filter
The NTSC Encoder Unit consists of a 4 MHz luminance low pass filter and two equal bandwidth 1.2 MHz
chrominance low pass filters. The functions of these filters are to limit the frequency contents of the computer
generated image, to reduce the cross-luminance/chrominance distortion due to the mixing processes, and to
enhance the resolutions.The digital filters are designed to have faster roll-off than the analog counterparts so that
the quantization noise, which is monotonic decreasing along the frequency axis, are removed as soon as they pass
the band of interest. Figure 7 shows the overall filter characteristics (interpolation cascaded with band-limit) for X:1:1
and X:2:2 formatted data. Also shown in Figure 8 are the luminance band-limit characteristics with and without the
chroma filter.
At the filters’ outputs, each pixel is represented by 3 10-bit numbers, which are maintained until the DAC inputs.
Hence the block effects due to the limited quantization levels are reduced.
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KS0119 Data Sheet
X:2:2 INPUT
X:1:1 INPUT
Frequency (MHz)
Figure 7. Chrominance Filter Characteristics
WITHOUT CHROMA
FILTER
WITH CHROMA
FILTER
Frequency (MHz)
Figure 8. Luminance Band-limit Filter Characteristics
3.3. SINC (Sinx/x) Function Effect
The digital-to-analog converter exhibits a high frequency roll-off SINC filter characteristic owing to the zeroth order
sample and hold process. The roll-off is a function of the DAC’s conversion rate. The NTSC Encoder Unit also
incorporates a 6th-order interpolation filter to raise the data rate to 27 MHz. The roll-off at 4 MHz is reduced from
-1 dB (sampled at 13.5 MHz) to -0.2 dB. The up sampling also pushes the high frequency “image” beyond 23 MHz,
greatly reducing the analog reconstruction filter requirement at the DAC’s outputs.
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KS0119 Data Sheet
4. SIGNAL MANIPULATION FUNCTIONS
The NTSC Encoder Unit provides the facilities for the user to control the contrast, hue, color killer and the vertical
Command Register B CMDB
Hue Control
HUE
register( ).
blanking period by programming the
(
) and
4.1. Hue Control
°
The chromaticity can be changed by modifying the modulation angle. The entire 360 hue range is divided into 264
HUE
equal units. To move the hue angle by k units the congruent 83*k MOD 264 should be loaded into the
register
register until a write to
register must be loaded first followed
register. The following examples show the value to be programmed into the HUE register
CMDB HUE Hue Control
and bit 7 of
CMDB
register. The
register occurs. Therefore, when changing the hue angle, the
CMDB
register will not be transferred to the final
HUE
the
by a write to the
for +5 and -5 degree hue angle:
Examples:
+5 degree Hue angle
5
--------
360
k =
× 264 = 3
HUE = mod(k 83, 264) = mod(249, 264) = 249
-5 degree Hue angle
355
360
--------
k =
× 264 = 260
HUE = mod(260 83, 264) = mod(264 81 + 196, 264) = 196
4.2. Chroma Trap Filter
CMDB
The luminance path includes a Chroma Trap filter. When this filter is enabled (
is reduced to 2.8 MHz, resulting in a softer picture.
[4] = 1), the effective bandwidth
4.3. Color Killer
CMDB
When bit 3 of the
black and white.
register is set to 1, the chroma data will be removed and the picture will be displayed as
4.4. Vertical Blanking
Normally, line 1 to line 9 in field 1 and the second half of line 263 to 272 in field 2 are blanked automatically. However,
CMDB
VBLK
register.
if bit 2 of
register is 1, the blanking period is extended to the line specified in the
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KS0119 Data Sheet
5. VIDEO OPERATIONAL TIMING
The KS0119 can operate in either slave or master mode. In slave mode, the chip uses two external input signals,
active video (AV) and vertical blank (VBLK), to synchronize the internal operation. In master mode, however, the
chip outputs these two signals. The chip generates two additional signals: Memory Transfer Request (MRQST) and
field two indicator (F2), which can be used to simplify the interface to an external frame buffer controller. Figure 9
shows the timing waveform for the NTSC output mode.
FIRST FIELD
525
1
2
3
4
5
6
7
8
9
10
11
20
21
CVBS
AV
VBLK
F2
MRQST(BLKALL=0)
MRQST(BLKALL=1)
SECOND FIELD
263
264
265
266
267
268
269
270
271
272
273
274
283
284
CVBS
AV
VBLK
F2
MRQST(BLKALL=0)
MRQST(BLKALL=1)
Figure 9. NTSC Output Timing
In Master mode, the timing shown in Figure 10 is maintained among AV, VBLK, and F2, where n is the leading pixel
number (see Figure 12 for more detail). In Slave mode, the two inputs AV and VBLK must meet the timing
requirement as shown in Figure 11 in order for the Encoder to obtain the correct field information.
AV
n
VBLK
F2
Figure 10. Master Mode AV, VBLK, and F2 Timing
AV
4 PCK(min)
4 PCK(min)
400 PCK(max)
VBLK
F2
Figure 11. Slave Mode AV and VBLK Timing Requirement
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KS0119 Data Sheet
5.1. Horizontal Timing
Each scan line contains hn pixels as shown in Figure 12. Of the hn pixels, only (hn - hblk) pixels are displayed. The
AV signal is used to indicate the active portion of the horizontal scan line. The Horizontal Blank portion actually
consists of three parts: Horizontal Front Porch, Horizontal Sync, and Horizontal Back Porch. The KS0119 outputs
the Horizontal Sync signal to the display monitor.
In Master mode, the NTSC Encoder generates the AV signal. AV can be used by the external frame buffer to control
the pixel read out. Because of the memory access latency associated with the external memory subsystem, AV
should lead the pixel data by n pixel clocks. This is done by controlling the hav parameter. All horizontal timing
parameters are programmable and Table 5 contains the information on how to calculate the line timing control
register values for both NTSC and RGB displays.
CVBS
hfp
hsyn
hblk
n
hn
hav
AV
hn
Figure 12. Horizontal Timing
Table 5: Line Timing Register Values
Register
HFP
Parameter
Horizontal Front Porch
Horizontal Sync Tip
Horizontal Blanking
Number of Pixels per Line
End of Active Video
NTSC Value RGB Value
11
184*
135
Thfp + 1
Thsyn + 1
Thblk - 3
Thn - 2
HSYN
HBLK
HN
856
HAV
854 - n
Thn - 4 - n
*: This number is not used to control the Horizontal Sync Tip in NTSC mode.
5.2. Vertical Timing
Each field contains the active line and vertical blank portions. The vertical blank portion is further divided into Vertical
Front Porch, Verical Sync, and Vertical Back Porch.There are four parameters that control the vertical timing: VFP,
VSYN, VBLK, and VN. They are specified in terms of lines. Figure 13 shows the timing related to the four
parameters. For NTSC output, these parameters are fixed and the power on default values should be used.
BLKALL
Command Register
VBLK
is set to 1, the value will be used instead. Table 6
However, if the
bit in the
provides information on how to program these parameters.
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KS0119 Data Sheet
In Master mode, the NTSC Encoder outputs the VBLK signal. This signal can be used to synchronize the external
frame buffer controller’s line counter. In Slave mode, VBLK is an input and is used to synchronize the chip’s internal
operation.
vfp
VERTICAL
SYNC
vsyn
vn
VERTICAL
BLANKING
vblk
Figure 13. Vertical Timing
.
Table 6: Frame Timing Register Value
Register
VFP
Parameter
Vertical Front Porch
Vertical Sync Tip
Value
Tvfp - 1.
Tvsyn - 1.
Tvblk - 1.
Tvn - 1.
VSYN
VBLK
VN
Vertical Blanking
Number of Lines per Frame
5.3. MRQST/MODE and F2
MRQST/MODE is output during AV low for the active lines. This signal can be used to transfer video data from
DRAM to shift registers in the VRAM. F2 can be used by the external frame buffer controller for interlaced display.
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KS0119 Data Sheet
6. COLOR PALETTE RAM, OVERLAY LOOKUP TABLE, AND PIXEL MASK REGISTER
The KS0119 contains a Color Palette RAM, an Overlay Lookup Table, and a Pixel Mask Register. They can be
accessed through the host interface.
6.1. Accessing the Color Palette RAM
The Color Palette RAM is organized as 3 256x8 arrays. From the programmer’s point of view, there are 256 entries;
each entry has 3 bytes. To write to the Color Palette RAM, the entry offset is written to the Color Palette Write Index
register, then three bytes, in the order of R, G, and B, are written to the Color Palette Data register. If consecutive
entries are to be written, only the first offset address needs to be written to the Color Palette Write Index register. It
is important to note that writing to the Color Palette Data register should always consist of multiples of three bytes.
Unpredictable result will occur if this is not strictly followed.
Reading the Color Palette RAM is similar to writing the Color Palette RAM except the entry offset is written to the
Color Palette Read Index register.
The Color Palette RAM is located at the center of the RGB path. There is no bypass path. Consequently, for 24-bit
true color inputs even though the translations are not required the Color Palette RAM still needs to be loaded.
6.2. 6-Bit Color Palette Mode
Command Register
The KS0119 also supports 6-bit color palette mode. When this mode is selected by setting
bit
3 to 0, only the 6 LSB’s for each color entry are loaded into the corresponding color palette register. Internally, the
6 LSB’s are shifted to the MSB positions with the 2 LSB’s padded with 0’s. When reading from the palette RAM, the
two MSB’s must be ignored.
6.3. High Color and Pseudo Color Input Lookup Address.
The high color and pseudo color inputs pass through a formatter, which expands the inputs to a full 24 bits according
to Table 7. For inputs with R, G, and B components less than 8 bits, the LSB’s are padded with 0’s. The outputs of
the formatter, after passing through the pixel mask filter, become the color palette table addresses.
Table 7: RGB Input Formatter Conversion Table
Video Input
<msb..lsb>
Color Lookup Table Input
<msb..lsb>
Mode
Byte 2
Byte 1
G<7:0>
Byte 0
1
2
3
4
R<7:0>:G<7:0>:B<7:0>
R<4:0>:G<5:0>:B<4:0>
R<5:0>:G<5:0>:B<3:0>
R<4:0>:G<4:0>:B<4:0>
R<7:0>
R<4:0>000
R<5:0>00
R<4:0>000
P<7:0>
B<7:0>
B<4:0>000
B<3:0>0000
B<4:0>000
P<7:0>
G<5:0>00
G<5:0>00
G<4:0>000
P<7:0>
5 and 6 P<7:0>
6.4. Overlay Lookup Table
Four overlay input bits address the Overlay Lookup Table. If the overlay input is non-zero, overlay data will be
displayed. The Overlay Look Up Table contains 15 entries, and each entry has three bytes, in the order of R, G, and
B. The entry offset starts from 1 instead of 0. The access method for the Overlay Lookup Table is the same as that
for the Color Palette RAM.
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KS0119 Data Sheet
6.5. Pixel Mask Register
The Pixel Mask Register is used to filter the pixel data coming out from the RGB Input Formatter. Each R, G, B pixel
byte is bit-wise ANDed with the pixel mask register. Special effects can be created by selectively masking out certain
bits. This register needs to be initialized after power up.
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KS0119 Data Sheet
7. DAC AND EXTERNAL RECONSTRUCTION FILTER
The three DACs on the chip are identical; they are video grade 10 bit current DACs. Figure 14 shows a typical
configuration for the DAC portion of the chip. RREF is connected to IREF to adjust the DAC output full scale. The
DAC output is designed to drive a doubly terminated 75 Ω load. A 105 Ω resistor connected to RREF can be used to
set the output voltage peak to the RS-170A standard of 1 V. The built-in voltage reference has a large variation due
to manufacturing technology limitations. For precise control of the DAC, an external voltage reference can be used.
A variable resistor may also be used for RREF to adjust the full scale DAC output current. The recommended analog
filter circuit and its characteristic are shown in Figure 15 and Figure 16, respectively.
Analog Power Plane
CCOMP
KS0119
RBIAS
1.2V
-
VREF
IREF
+
1.235V
GIN
G/Y
CVREF
LPF
DAC
To 75Ω Display
AKY
RREF
Only one DAC output is shown
with the optional 1.235V
external voltage reference and
RBIAS
Analog Ground Plane
Figure 14. DAC Reference Circuit and Termination
2.0µH 1.3µH
75Ω
100pF
300pF
100pF
Figure 15. DAC Output Analog Reconstruction Filter
Frequency (Mhz)
Figure 16. DAC Output Analog Reconstruction Filter Response
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KS0119 Data Sheet
8. HOST INTERFACE
The KS0119 contains a conventional parallel microprocessor interface and a proprietary serial interface. The
parallel microprocessor interface consists of 11 pins, some of which are shared by the three pin serial bus. The logic
sense of the P/S control pin defines the host interface mode, parallel or serial. Three of the interface pins serve a
dual purpose depending upon the mode selected. The CS, R/W, and D7 pins in parallel mode become SFRS,
SCLK, and SDAT pins in serial mode, respectively.
8.1. Microprocessor Address Map
The KS0119 contains three groups of registers. The first group is the control registers. The control registers are used
for feature/option selection. The second group is the color palette RAM. The third group is the overlay color look up
table. Table 8 shows the microprocessor address map for the KS0119.
Table 8: Microprocessor Address Map
Address
Description
(Hex)
00
01
02
03
04
05
06
07
08
09
Color Palette Write Index
Color Palette Data
Pixel Mask Register
Color Palette Read Index
Overlay CLUT Write Index
Overlay CLUT Data
Reserved
Overlay CLUT Read Index
Control Register Index
Control Register Data
8.2. Transfer Mode
Both the read and write cycles require that the index be written to the KS0119 first. The index is written to location
ADDR = 08. The index is the internal address location for each register. The internal address is indicated by the
register number associated with each register. Once the index is written, the selected register can have data read
from or written to location ADDR = 09. Non-sequential internal registers are accessed individually by writing an
index and then reading or writing one byte of data. Sequential locations can be accessed by writing the index for the
first register and then reading or writing multiple bytes of data. The index auto-increments internally by one for each
successive byte of data accessed while ADDE = 09. This mode is useful when initializing the device or when
accessing word wide or blocks of registers.
The color palette and overlay CLUT operate in a similar fashion, except that separate index locations exist for read
and write operations. The color palette write index is written to ADDR=00, and palette data is written to ADDR=01.
For read operation, the index is written to ADDR=03. The color palette and overlay exhibit the same auto-increment
capability as the control registers. This simplifies loading the color palette.
8.3. Serial Host Interface
The serial interface is selected by connecting the P/S pin to ground. This interface uses three signals: SFRS, SDAT,
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KS0119 Data Sheet
and SCLK. The SFRS indicates a valid data transfer. Serial data is carried through the SDAT and clocked in or out
with the SCLK. The data protocol sends each byte as msb first.
8.3.1. Serial Host Write/Read to KS0119
Each data transfer cycle is called a frame. A valid frame is indicated by a HIGH on the SFRS signal. A frame
consists at least three bytes: the first byte contains a 7-bit slave device ID and a R/W bit (bit assignment shown in
Figure 17); the second byte indicates the internal address of register the data transfer is intended for (see Table 8);
and the third and consequent byte(s) are the data to be transferred to/from the register. If the data transfer is to/
from the index register, three bytes are needed each frame. Since the KS0119 features an auto index increment
function, consecutive data transfer to/from the data registers can be completed within the same frame.
msb
R/W
lsb
1
0
0
0
0
0
1
slave device ID
Figure 17. KS0119 Device ID and R/W
Figure 18 shows an example of a write to the index register. Each bit is latched into the device by the rising edge of
the SCLK. A write to the data register is similar to a write to the index register except the second byte is 01h and
the third and so on byte(s) are the data to be written (Figure 19). When the data is read from the device, the
KS0119 outputs each bit is after the falling edge of the SCLK.
SFRS
SCLK
SDAT
08h
0
device ID
index
Figure 18. Serial Host Write to Index Register
SFRS
SCLK
SDAT
0
data
data
device ID
09h
Figure 19. Serial Host Write to Data Register
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KS0119 Data Sheet
8.4. Parallel Host Interface
Figure 20 shows the timing relation for a parallel read cycle. Figure 21 shows the timing for a parallel write cycle.
The address ADDR and read/write R/W are stable before the CS signal is lowered. Data written to the KS0119 must
be stable before CS goes high. Data is read from the KS0119 when CS is low.
CS
W
R
R
R/W
ADDR
D[0:7]
INDEX
DATA 1
DATA 2
Figure 20. Parallel Host Interface Read Cycle
CS
W
W
W
R/W
ADDR
D[0:7]
DATA 2
INDEX
DATA 1
Figure 21. Parallel Host Interface Write Cycle
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KS0119 Data Sheet
9. DETAILED CONTROL REGISTER DESCRIPTION
This section contains the detailed description of the control registers. The control registers can be categorized into
three functional groups: indexes 60h to 63h are general control registers; indexes 64h to 6Dh are mixing control
registers; indexes 70h to 79h are CRT control registers. Table 9 is a register summary, followed by the individual
register description. Default values are noted with an asterisk (*) after the value description.
Table 9: Control Registers
Index Mnemonic
Default
12h/A2h
90h/60h
02h
Description
Command Register
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
70h
71h
72h
73h
74h
75h
76h
77h
78h
79h
CMD
FMT
Input Format
CMDB
HUE
Second Command Register
Chroma Phase Offset Bits 7..0
Mixing Control
00h
MXCTR
WHS
WHE
WVS
WVE
WHV
TMPLA
TMPLB
MSKA
MSKB
HAVN
HAV
00h
00h
Window Row Start Address
Window Row End Address
Window Column Start Address
Window Column End Address
Window Overflow Address(lsbs)
Chroma Key TMPLATE Byte 0
Chroma Key TMPLATE Byte 1
Chroma Key MASK Byte 0
Chroma Key MASK Byte 1
HN and HAV Overflow Bits
Master Mode’s AVout Lead Control
Number of Pixels per Line
Horizontal Front Porch
00h
00h
00h
00h
00h
00h
00h
00h
33h/B3h
54h
HN
58h
HFP
0Bh
HSYN
HBLK
VN
B8h
End of Horizontal Sync
87h
End of Horizontal Blanking
Number of Lines per Field
Vertical Front Porch
00h
VFP
83h
VSYN
VBLK
06h
End of Vertical Sync
14h
End of Vertical Blanking
Some registers have two default values. The first number is for MRQST/MOED pin pulled
low. The second number is for MRQST/MODE pin pulled high.
Note:
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KS0119 Data Sheet
Command Register
Index Mnemonic
bit 7
RUN
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MSTR
RGB
CKSL
8/6*
DKF
CVBS
YC
60h
CMD
RUN
Software RUN control. The internal state machine is controlled by the logically ORed
software and hardware RUN inputs.
1
0
Software run enable.
Software run disable.
The logic state of the MRQST/MODE is latched into this bit during power-on.
Timing generation Master/Slave mode select.
MSTR
RGB
1
0
Master.
Slave.*
Analog output format select.
1
0
RGB.
Composite and Super video.
The logic state of the MRQST/MODE is latched into this bit during power-on.
Clock input and output control.
CKSL
/
1
0
CK27 is selected, and pixel clock CKP’s rate is f(CK27) 2.
CKV is selected as the source, and CKP has the same rate as the clock input.
The inverted logic state of the MRQST/MODE is latched into this bit during power-on.
8/6 bit palette select.
8/6*
1
0
8 bit palette.
6 bit palette.*
DKF
CVBS
YC
DKY/R pin configuration control.
1
0
DKY/R is input key for digital mixing.
DKY/R is hardware RUN input.*
If bit 5 of this register is 0 this bit controls R/CVBS DAC.
1
0
R/CVBS DAC is on.*
R/CVBS DAC is in the power down state.
If bit 5 of this register is 0 this bit controls G/Y and B/C DACs.
1
0
G/Y and B/C DACs are on.
G/Y and B/C DACs are in power down state.*
PAGE 28 OF 50
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KS0119 Data Sheet
Input Format Register
Index
61h
Mnemonic
FMT
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FMTA2
FMTA1
FMTA0
FMTB3
FMTB2
FMTB1
FMTB0
FMTA3
FMTA
FMTB
Channel A input format. See Table 3 for supported format on Channel A.
The power-on default is 6 if there is an external pull-up resistor on the MRQST/MODE pin,
or 9 otherwise.
Channel B input format. See Table 4 for supported format on Channel B.
Command Register B
Index
62h
Mnemonic
CMDB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HUE8
VSP
HSP
CTRAP
MONO
BLKALL
SLT1
SLT0
VSP
Vertical sync input (VBLK) polarity control.
1
vertical sync input is active low.
vertical sync input is active high.*
0
HSP
Horizontal sync input (AV) polarity control.
1
0
horizontal sync input is active high.
horizontal sync input is active low.*
CTRAP
Chroma trap filter control. When enabled, the high frequency luminance signals near the
color subcarrier are filtered out. This function is available for NTSC output only.
1
0
enables filtering.
disables filtering.*
MONO
Color Killer control. When enabled, the chrominance signal is suppressed. This function is
available for NTSC output only.
1
0
Color Killer enable.
Color Killer disable.*
VBLK
When set, the output from line 1 to the line set by the register is blanked.
These two bits control the assertion of the MRQST signal.
BLKALL
SLT[1:0]
00
MRQST is asserted for the active lines whose line numbers are greater than or
VBLK
equal to the value contained in the
register.
01
10
11
MRQST is always asserted.
MRQST is not asserted during the vertical blanking period.*
Reserved. Do not use.
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KS0119 Data Sheet
Hue Control Register
Index
Mnemonic
bit 7
bit 6
VSP
bit 5
HSP
bit 4
CTRAP
HUE4
bit 3
MONO
HUE3
bit 2
BLKALL
HUE2
bit 1
SLT1
HUE1
bit 0
SLT0
HUE0
62h
63h
CMDB
HUE
HUE8
HUE7
HUE6
HUE5
HUE[8:0]
Hue control. To have a phase shift of k divisions, the 9 bit register should be loaded with the
value <83*k> MOD 264. Each division is equal to 360/264 degrees. Hue can be adjusted
only for NTSC output mode.
Mixing Control Register
Index
64h
Mnemonic
MXCTR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MXEN
CMEN
AMEN
WMEN
OUTSD
K2
K1
K0
DIGITAL MIXING
” section for additional
This register controls the digital mixing function. Please see the “
information.
MXEN
CMEN
AMEN
WMEN
OUTSD
K[2:0]
Master mixing control.
1
0
mixing is allowed.
no mixing is allowed.*
Index or chroma mixing control.
1
0
Index or Chroma Mixing enable.
Index or Chroma Mixing disable.*
Alpha mixing control.
1
0
Alpha Mixing enable.
Alpha Mixing disable.*
Window mixing control.
1
0
Window Mixing enable.
Window Mixing disable.*
Channel B inside/outside mixing window control.
1
0
Channel B is outside the Mixing Window.
Channel B is inside the Mixing Window.*
During linear blend mixing, these bits set the luminance attenuation factors for Channel A
and Channel B. For Channel A, the attenuation factor is K/8, and for Channel B, the
attenuation factor is 1-K/8, where K = K[2:0].
PAGE 30 OF 50
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KS0119 Data Sheet
Window Horizontal Start Address
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WHS8
WHS0
WHS7
WHE1
WHS6
WHE0
WHS5
WVS1
WHS4
WVS0
WHS3
WVE1
WHS2
WVE0
65h
69h
WHS
WHV
WHS9
WHS1
WHS[9:0]
This 10-bit register contains the horizontal pixel start location for the Mixing Window.
Window Horizontal End Address
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WHE8
WHS0
WHE7
WHE1
WHE6
WHE0
WHE5
WVS1
WHE4
WVS0
WHE3
WVE1
WHE2
WVE0
66h
69h
WHE
WHV
WHE9
WHS1
WHE[9:0]
This 10-bit register contains the horizontal pixel end location for the Mixing Window.
Window Vertical Start Address
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WVS8
WHS0
WVS7
WHE1
WVS6
WHE0
WVS5
WVS1
WVS4
WVS0
WVS3
WVE1
WVS2
WVE0
67h
69h
WVS
WHV
WVS9
WHS1
WVS[9:0]
This 10-bit register contains the vertical line start number for the Mixing Window.
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KS0119 Data Sheet
Window Vertical End Address
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WVE8
WHS0
WVE7
WHE1
WVE6
WHE0
WVE5
WVS1
WVE4
WVS0
WVE3
WVE1
WVE2
WVE0
68h
69h
WVE
WHV
WVE9
WHS1
WVE[9:0]
This 10-bit register contains the vertical line end number for the Mixing Window.
Chroma Key TEMPLATE Byte 0 (A)
Index
6Ah
Mnemonic
TMPLA
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMPLA
7
TMPLA
6
TMPLA
5
TMPLA
4
TMPLA
3
TMPLA
2
TMPLA
1
TMPLA
0
TEMPLATE
TMPLA[7:0]
For RGB Index Keying, this register is the lower byte of the
register. For CbCr
Digital
Chroma Keying, this register contains the lower limit of the Cb key. See the section “
Mixing
” for a more detailed description of this register.
Chroma Key TEMPLATE Byte 1 (B)
Index
6Bh
Mnemonic
TMPLB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMPLB
7
TMPLB
6
TMPLB
5
TMPLB
4
TMPLB
3
TMPLB
2
TMPLB
1
TMPLB
0
TEMPLATE
TMPLB[7:0]
For RGB Index Keying, this register is the higher byte of the
register. For CbCr
Digital
Chroma keying, this register contains the upper limit of the Cb key. See the section “
Mixing
” for a more detailed description of this register.
PAGE 32 OF 50
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KS0119 Data Sheet
Chroma Key MASK Byte 0 (A)
Index
6Ch
Mnemonic
MSKA
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MSKA7
MSKA6
MSKA5
MSKA4
MSKA3
MSKA2
MSKA1
MSKA0
MASK
register. For CbCr Chroma
MSKA[7:0]
For RGB Index Keying, this is the lower byte of the
Digital Mixing
Keying, this register contains the lower limit of the Cr key. See the section “
for more detail.
”
Chroma Key MASK Byte 1 (B)
Index
6Dh
Mnemonic
MSKB
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
MSKB1
bit 0
MSKB7
MSKB6
MSKB5
MSKB4
MSKB3
MSKB2
MSKB0
MASK
MSKB[7:0]
For RGB index keying, this is the upper byte of the
register. For CbCr keying, this
Digital Mixing
register sets the upper limit of the Cr key. See the section “
” for more detail.
Master Mode’s AVout Lead Control
Index
Mnemonic
bit 7
bit 6
HN10
HAV6
bit 5
HN9
bit 4
HN8
bit 3
0
bit 2
HAV10
HAV2
bit 1
bit 0
HAV8
HAV0
HAV9
HAV1
70h
71h
HAVN
HAV
SYNCPT
HAV7
HAV5
HAV4
HAV3
SYNCPT
Sync pass through.
1
HSYN and VSYN are the delayed outputs of AV and VBLK, respectively.
HSYN and VSYN are internally generated.
0
The logic state of the MRQST/MODE is latched into this bit during power-on.
HAV[10:0]
In Master Mode, this 11-bit register defines the AVout lead control timing. In Slave Mode,
Horizontal Timing
this register has no effect. See the section “
” for detail.
PAGE 33 OF 50
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KS0119 Data Sheet
Number of Pixels per Line
Index
Mnemonic
bit 7
bit 6
HN10
HN6
bit 5
HN9
HN5
bit 4
HN8
HN4
bit 3
0
bit 2
HAV10
HN2
bit 1
HAV9
HN1
bit 0
HAV8
HN0
70h
72h
HAVN
HN
SYNCPT
HN7
HN3
HN[10:0]
This 11-bit register controls the total number of pixels per line, which is equal to
HN[10:0]+2.
Horizontal Front Porch
Index
73h
Mnemonic
HFP
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HFP7
HFP6
HFP5
HFPB4
HFP3
HFP2
HFP1
HFP0
HFP[7:0]
This register controls the horizontal front porch timing in number of pixels, which is equal to
HFP[7:0]-1.
Horizontal Sync End
Index
74h
Mnemonic
HSYN
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HSYN7
HSYN6
HSYN5
HSYN4
HSYN3
HSYN2
HSYN1
HSYN0
HSYN[7:0]
This register controls the horizontal sync end timing in number of pixels, which is equal to
HSYN[7:0]-1.
Horizontal Blanking End
Index
75h
Mnemonic
HBLK
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HBLK7
HBLK6
HBLK5
HBLK4
HBLK3
HBLK2
HBLK1
HBLK0
HBLK[7:0]
This register controls the horizontal blanking end timing in number of pixels, which is equal
to HBLK[7:0]+3.
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KS0119 Data Sheet
Number of Lines per Field
Index
Mnemonic
bit 7
bit 6
VN6
VN8
bit 5
VN5
bit 4
VN4
bit 3
VN3
bit 2
VN2
bit 1
VN1
bit 0
VN0
76h
77h
VN
VN7
VN9
VFP
VFP5
VFP4
VFP3
VFP2
VFP1
VFP0
VN[9:0]
This 10-bit register controls the total number of lines per field, which is equal to VN[9:0]+1.
Vertical Front Porch
Index
77h
Mnemonic
VFP
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
VFP5
VFP4
VFP3
VFP2
VFP1
VFP0
VN9
VN8
VFP[5:0]
This 6-bit register controls the vertical front porch in number of lines, which is equal to
VFP[5:0]+1.
Vertical Sync End
Index
78h
Mnemonic
VSYN
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
VSYN5
VSYN4
VSYN3
VSYN2
VSYN1
VSYN0
VSYN7
VSYN6
VSYN[7:0]
This register controls the end of vertical sync in number of lines, which is equal to
VSYN[7:0]+1.
Vertical Blanking End
Index
79h
Mnemonic
VBLK
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
VBLK5
VBLK4
VBLK3
VBLK2
VBLK1
VBLK0
VBLK7
VBLK6
VBLK[7:0]
This register has three functions:
1. It controls the vertical blank timing for VGA monitors, and for NTSC monitors if the
BLKALL Command
bit is set in the
register.
2. It defines line zero of the active display.
3. In conjunction with slt[1:0] it controls for which lines the MRQST signal will be asserted
for NTSC monitors.
PAGE 35 OF 50
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KS0119 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Characteristics
Supply voltage (measured to GND)
Digital input voltage
Symbol
VDD
VI
Value
Unit
-0.5 to +7.0
0.5 to (VDD+0.5)
-10 to +100
-60 to +150
150
V
V
Ambient operating temperature range
Storage temperature range
Ta
°C
°C
°C
°C
°C
Tstg
Tj
Junction temperature
Soldering temperature (5 sec., 1/4” from pin)
Vapor phase soldering (1 min.)
Tsol
Tvsol
300
220
Notes: 1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within
specified operating conditions.
2. Functional operation under any of these conditions is not implied.
3. Applied voltage must be current limited to a specified range.
RECOMMENDED OPERATING CONDITIONS
Characteristics
Supply voltage
Symbol
VDD
Min
Typ
Max
Unit
V
4.75
5
5.25
Reference voltage
Internal
External
Vref
V
1.235
1.235
Reference current
Iref
RL
Ta
11.56
37.5
mA
Ω
Analog output load
Ambient operating temperature range
0
70
°C
PAGE 36 OF 50
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KS0119 Data Sheet
DC ELECTRICAL CHARACTERISTICS
Characteristics
Digital input high voltage
Symbol
VIH
Min
2.0
Typ
Max
Unit
V
VDD+0.5
Digital input low voltage
VIL
GND-0.5
0.8
1
V
Digital input high current(VIN=2.4V)
Digital input low current(VIN=0.4V)
Digital input capacitance(f=1MHz,VIN=2.4V)
Digital output high voltage(IOH=-400µA)
Digital output low voltage(IOL=3.2mA)
Digital three-state current
IIH
µA
µA
pF
V
IIL
-1
7
CIN
VOH
VOL
2.4
0.4
50
7
V
IOZ
µA
pF
mA
Ω
Digital output capacitance
CDOUT
ICC
Supply current
150
10
Analog multiplexer ON resistance
Analog multiplexer OFF resistance
RAON
RAOFF
10
kΩ
PAGE 37 OF 50
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KS0119 Data Sheet
AC ELECTRICAL CHARACTERISTICS
Characteristics
CS or SCLK low
Symbol
tpwlC
tpwhC
tsR/W
thR/W
tsA
Min
50
4
Typ
Max
Unit
ns
CS or SCLK high
CK27/CKV
ns
R/W setup time
10
10
10
10
R/W hold time
ns
A[0:3] setup time
ns
A[0:3] hold time
thA
ns
CS or SCLK active to data valid
CS or SCLK inactive to data 3-state
Data setup time
tvalidD
t3-stateD
tsD
40
20
ns
ns
10
10
ns
Data hold time
thD
ns
SFRS setup time
tsFRM
thFRM
tsPIX
10
ns
SFRS hold time
10
ns
Setup time (P[0:31], DKY/R, AV, VBLK)
Hold time (P[0:31], DKY/R, AV, VBLK)
CKP to output delay
-9
ns
thPIX
tdPIX
tdNTSC
tdRGB
fCK27
fCKV
18.5
ns
9
ns
Video pipeline delay (NTSC output)
Video pipeline delay (RGB output)
CK27 clock rate
53
26.9999
7
54
CK27
CKV
MHz
MHz
ns
23
27
27.0001
Note1
12.5
CKV clock rate
CK27, CKV to CKP delay
32 for KS0119, 45 for KS0119Q2.
tdCKP
9
PAGE 38 OF 50
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KS0119 Data Sheet
Parallel Host Interface Timing
t
t
t
pwhC
pwlC
CS
t
sR/W
hR/W
R/W
t
t
sA
hA
A[0:3]
D[0:7]
t
t
hD
sD
INDEX
DATA 1
DATA 2
Figure 22. Parallel Host Interface Write Cycle
t
t
pwhC
pwlC
hR/W
hA
CS
t
sR/W
t
t
R/W
t
sA
A[0:3]
D[0:7]
t
t
t
t
3-stateD
sD
hD
validD
INDEX
DATA 1
DATA 2
Figure 23. Parallel Host Interface Read Cycle
t
t
C
pwlC
pwh
SCLK
t
hFRM
t
sFRM
SFRS
SDAT
t
sD
t
t
t
validD
3-stateD
hD
DATA WRITE (to slave)
DATA READ (to slave)
Figure 24. Serial Host Interface Detailed Timing
PAGE 39 OF 50
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KS0119 Data Sheet
CKV
t
dCKP
CKP
t
t
sPIX
hPIX
PD[0:31]
DKY/R
AV
VBLK
Figure 25. Pixel Data Setup and Hold Time
CKP
tdPIX
AV
VBLK
MRQST
F2
Figure 26. CKP to Output Delay
PAGE 40 OF 50
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KS0119 Data Sheet
DAC DC CHARACTERISTICS
Characteristics
Resolution
Symbol
Min
Typ
Max
Unit
RGB output
8
Bits
Bits
NTSC or Y/C output
Integral non-linearity error
Differential non-linearity error
Gray scale error
10
IL
0.15%
0.1%
5%
DL
0
Monotonicity
Guaranteed
Coding
Binary
mA
Analog outputs (NTSC)
Full scale current range
Output current
25.3
26.67
28
White level relative to black
Black level relative to blank
Blank level relative to sync
LSB size
16.74
17.62
1.44
7.62
26.1
2%
18.5
mA
mA
mA
µA
DAC to DAC matching
Output compliance
5%
1.5
VOC
RAOUT
CAOUT
Vref
-0.3
V
kΩ
Output impedance
10
15
Output capacitance (f=1MHz, IOUT=0mA)
Internal reference voltage
Voltage reference input current
DAC reference current
DAC reference resistor (VREF=Typ)
30
pF
1.17
1.235
10
1.296
V
IVref
µA
IREF
11.14
11.56
105
12.34
0.5
mA
Ω
RREF
PSRR
Power supply rejection ratio
%/∆VDD
(CCOMP=0.1 µF, f=1 KHz)
Test conditions: In NTSC operation, with DAC output = 1.0 VP-P, VREF = 1.235 V, RREF = 105 Ω, 75 Ω load.
PAGE 41 OF 50
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KS0119 Data Sheet
DAC AC CHARACTERISTICS
Characteristics
Differential gain
Symbol
DG
Min
Typ
±0.5%
±0.5
60
Max
1.5%
1
Unit
Differential phase
DP
Degree
dB
Signal to noise ratio
Analog output delay
Analog output rise/fall time
Analog settling time
Clock and data feedthrough
Glitch impulse
SNR
td
48
30
ns
tr/tf
3
20
-30
75
0
ns
tset
ns
FDTHR
GI
dB
pV-Sec
ns
Analog output skew
tskw
5
PAGE 42 OF 50
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KS0119 Data Sheet
NTSC DAC OUTPUT WAVEFORMS
Code
27.3 1024
mA
34 IRE
22.27
835
WHITE LEVEL (235)
3.58 MHz
COLOR BURST
(9 CYCLES)
100 IRE
9.92
7.68
6.64
372
BLACK LEVEL (16)
BLANK LEVEL
288
249
20 IRE
20 IRE
40 IRE
7.5 IRE
3.36
0.29
126
11
Note: 37.5 Ω load, VREF=1.235 V, and R
=105 Ω. RS-170A levels and tolerances are assumed.
REF
Figure 27. Composite NTSC Video Output Waveform
mA
Code
835
22.27
WHITE LEVEL
100 IRE
7.68
6.64
288
249
BLACK LEVEL
BLANK LEVEL
7.5 IRE
40 IRE
11
0.29
Note: 37.5 Ω load, VREF=1.235 V, and R
=105 Ω. RS-170A levels and tolerances are assumed.
REF
Figure 28. NTSC Y (Luminance) Video Output Waveform
PAGE 43 OF 50
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KS0119 Data Sheet
mA
Code
356
9.49
3.58 MHz
COLOR BURST
(9 CYCLES)
20 IRE
20 IRE
288
7.68
BLACK LEVEL
220
5.87
Note: 37.5 Ω load, VREF=1.235 V, and R
=105 Ω. RS-170A levels and tolerances are assumed.
REF
Figure 29. NTSC C (Chrominance) Video Output Waveform
PAGE 44 OF 50
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KS0119 Data Sheet
VDD
2k
30pF
(60pF for Fsmp)
Figure 30. Load Circuit for Timing Measurements. Digital Outputs
Equivalent Input Circuit
Equivalent Output Circuit
Figure 31. ESD Protection
PAGE 45 OF 50
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KS0119 Data Sheet
PACKAGE DIMENSION (Dimensions are in Millimeters)
80-QFP-1420C
23.90±0.30
20.00±0.20
3.00MAX
0.10MAX
2.65±0.10
#80
+0.10
0.15
#1
0.80
-0.05
0.35±0.10
0.80±0.20
0.80±0.2
PAGE 46 OF 50
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KS0119 Data Sheet
PACKAGE DIMENSION (Continued)
100-QPF-1420C
23.90±0.30
20.00±0.20
0.10MAX
#100
#1
0.30±0.10
0.00MIN
3.00MAX
0.65
(0.58)
0.10MAX
2.65±0.10
0.80±0.20
PAGE 47 OF 50
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KS0119 Data Sheet
NOTES:
PAGE 48 OF 50
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MULTIMEDIA VIDEO
KS0119 Data Sheet
NOTES:
PAGE 49 OF 50
070595
ELECTRONICS
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KS0119 Data Sheet
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NORTH CENTRAL
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TEL (508) 486-0700
FAX (508) 486-8209
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TEL (408) 954-7000
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FAX (708) 775-1058
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TECHNICAL SUPPORT HOT LINE
Phone: (714)-236-9507
Fax: (714)-236-9664
E-mail: video@sldc.com
Circuit diagrams utilizing SAMSUNG and/or SAMSUNG ELECTRONICS products are included as a means of illustrating typical
semiconductor applications; consequently, complete information sufficient for construction purposes is not necessarily given. The
information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for
inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described herein
any license under the patent rights of SAMSUNG and/or SAMSUNG ELECTRONICS, or others. SAMSUNG and/or SAMSUNG
ELECTRONICS, reserve the right to change device specifications.
LIFE SUPPORT APPLICATIONS
SAMSUNG and/or SAMSUNG ELECTRONICS products are not designed for use in life support applications, devices, or systems
where malfunction of a SAMSUNG product can reasonably be expected to result in a personal injury. SAMSUNG and/or
SAMSUNG ELECTRONICS’ customers using or selling SAMSUNG and/or SAMSUNG ELECTRONICS products for use in such
applications do so at their own risk and agree to fully indemnify SAMSUNG and/or SAMSUNG ELECTRONICS for any damages
resulting from such improper use or sale.
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