KS57C21132Q-XX [SAMSUNG]
Microcontroller, 4-Bit, MROM, 1.5MHz, CMOS, PQFP128, 14 X 20 MM, QFP-128;
| 型号： | KS57C21132Q-XX |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, MROM, 1.5MHz, CMOS, PQFP128, 14 X 20 MM, QFP-128 微控制器 |
| 文件： | 总38页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The KS57C21116/C21124/C21132 single-chip CMOS microcontroller has been designed for high performance
using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-1280-dot LCD direct drive capability, segment expandable circuit, 8-bit and 16-bit timer/counter,
and serial I/O, the KS57C21116/C21124/C21132 offers an excellent design solution for a wide variety of
applications which require LCD functions.
Up to 51 pins of the 128-pin QFP package can be dedicated to I/O. Nine vectored interrupts provide fast
response to internal and external events. In addition, the KS57C21116/C21124/C21132's advanced CMOS
technology provides for low power consumption and a wide operating voltage range.
OTP
The KS57C21116/C21124/C21132 microcontroller is also available in OTP (One Time Programmable) version,
KS57P21132. KS57P21132 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of
masked ROM. The KS57P21132 is comparable to KS57C21116/C21124/C21132, both in function and in pin
configuration except ROM size.
1-1
PRODUCT OVERVIEW
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
FEATURES SUMMARY
Memory
16-Bit Timer/Counter
Bit Sequential Carrier
•
•
•
Programmable 16-bit timer
External event counter
•
Supports 16-bit serial data
transfer in arbitrary format
•
•
3,584 ´ 4-bit RAM
(Excluding LCD Display
RAM)
Arbitrary clock frequency
output
Memory-Mapped I/O Structure
Data memory bank 15
16,384/24,576/32,768 ´
8-bit ROM
•
•
•
External clock signal divider
Configurable as two 8-bit
Timers
51 I/O Pins
Power-Down Modes
•
I/O: 47 pins (32 pins are
configurable as SEG pins)
•
•
•
Idle mode (only CPU clock
stops)
•
Serial I/O interface clock
generator
•
Input only: 4 pins
Stop mode (main system
clock stops)
Watch Timer
LCD Controller/Driver
Subsystem clock stop mode
•
•
•
Time interval generation:
0.5 s, 3.9 ms at 32,768 Hz
•
•
•
80 SEG ´ 16 COM, 88 SEG
´ 8 COM Terminals
Oscillation Sources
4 frequency outputs to BUZ
pin
Internal resistor circuit for
LCD bias
•
•
•
•
•
Crystal, Ceramic or RC for
main system clock
Clock source generation for
LCD
16 Level LCD contrast
control (software)
Crystal oscillator for
subsystem clock
•
•
Segment expandable circuit
Main system clock
frequency: 0.4–6 MHz
8-bit Serial I/O Interface
All dot can be switched
on/off
•
•
•
8-bit transmit/receive mode
8-bit receive mode
Subsystem clock frequency:
32.768 kHz
LSB-first or MSB-first
transmission selectable
8-bit Basic Timer
CPU clock divider circuit
(by 4, 8 or 64)
•
•
4 interval timer functions
Watch-dog timer
•
Internal or external clock
source
Instruction Execution Times
•
•
•
0.67, 1.33, 10.7 µs at 6
MHz
8-bit Timer/Counter
Comparator
•
•
•
Programmable 8-bit timer
External event counter
•
3 Channel mode: internal
0.95, 1.91, 15.3 µs at 4.19
MHz
reference (4-bit resolution)
Arbitrary clock frequency
output
•
2 Channel mode: external
reference
122 µs at 32.768 kHz
Operating Temperature
•
External clock signal divider
Interrupts
° °
– 40 C to 85 C
•
•
•
•
Five internal vectored
interrupts
Operating Voltage Range
1.8 V to 5.5 V
•
Four external vectored
interrupts
Package Type
128-pin QFP
Two quasi-interrupts
•
1-2
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU
All KS57-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical,
and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two
cycles.
CPU REGISTERS
Program Counter
A 15-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC
is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not
increment the PC is the 1-byte REF instruction which references instructions stored in a look-up table in the
ROM. Whenever a reset operation or an interrupt occurs, bits PC13 through PC0 are set to the vector address.
Stack Pointer
An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in general-purpose
data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logical zero.
During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the
service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction
is executed.
The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of
the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets
the first register of the stack area to data memory location 0FFH.
PROGRAM MEMORY
In its standard configuration, the 16,384/24,576/32,768 ´ 8-bit ROM is divided into four areas:
— 16-byte area for vector addresses
— 96-byte instruction reference area
— 16-byte general-purpose area (0010–001FH)
— 16,256/24,448/32,640-byte area for general-purpose program memory
The vector address area is used mostly during reset operations and interrupts. These 16 bytes can alternately be
used as general-purpose ROM.
The REF instruction references 2 x 1-byte or 2-byte instructions stored in reference area locations 0020H–
007FH. REF can also reference three-byte instructions such as JP or CALL. So that a REF instruction can
reference these instructions, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or
CALL is written to the reference area with the format TJP or TCALL instead of the normal instruction name.
Unused locations in the REF instruction look-up area can be allocated to general-purpose use.
1-3
PRODUCT OVERVIEW
DATA MEMORY
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
Overview
The 3,584-bit data memory has five areas:
— 32 ´ 4-bit working register area
— 224 ´ 4-bit general-purpose area in bank 0 which is also used as the stack area
— 256 ´ 4-bit general-purpose area in bank 1, bank 2,……, bank 13, respectively
— 256 ´ 5-bit area for LCD data in bank 14
— 128 ´ 4-bit area in bank 15 for memory-mapped I/O addresses
The data memory area is also organized as sixteen memory banks — bank 0, bank 1, ….., and bank 15. You use
the select memory bank instruction (SMB) to select one of the banks as working data memory.
Data stored in RAM locations are 1-, 4-, and 8-bit addressable. After a hardware reset, data memory initialization
values must be defined by program code.
Data Memory Addressing Modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, ….., or 15.
When the EMB flag is logical zero, only locations 00H–7FH of bank 0 and bank 15 can be accessed. When the
EMB flag is set to logical one, all sixteen data memory banks can be accessed based on the current SMB value.
Working Registers
The RAM's working register area in data memory bank 0 is also divided into four register banks. Each register
bank has eight 4-bit registers. Paired 4-bit registers are 8-bit addressable.
Register A can be used as a 4-bit accumulator and double register EA as an 8-bit extended accumulator; double
registers WX, WL and HL are used as address pointers for indirect addressing.
To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for
main programs and banks 1, 2, and 3 for interrupt service routines.
LCD Data Register Area
Bit values for LCD segment data are stored in data memory bank 14. Register locations that are not used to store
LCD data can be assigned to general-purpose use.
Bit Sequential Carrier
The bit sequential carrier (BSC) is a 16-bit general register that you can manipulate using 1-, 4-, and 8-bit RAM
control instructions.
Using the BSC register, addresses and bit locations can be specified sequentially using 1-bit indirect addressing
instructions. In this way, a program can generate 16-bit data output by moving the bit location sequentially,
incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data
in the BSC.
1-4
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
C
IS0
EMB
SC1
ERB
SC0
SC2
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0–SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit locations called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, ….., or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SRB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
Main system and subsystem oscillation circuits generate the internal clock signals for the CPU and peripheral
hardware. The main system clock can use a Crystal, Ceramic, or RC oscillation source, or an externally-
generated clock signal. The subsystem clock requires either a crystal oscillator or an external clock source.
Bit settings in the 4-bit power control and system clock mode registers select the oscillation source, the CPU
clock, and the clock used during power-down mode. The internal system clock signal (fxx) can be divided inter-
nally to produce four CPU clock frequencies — fx/4, fx/8, fx/64, or fxt/4.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, INT4, and INTK). There are two quasi-interrupts: INT2 and INTW.
INT2 detects rising or falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91
milliseconds. The following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
1-5
PRODUCT OVERVIEW
POWER DOWN
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode and the STOP instruction initiates stop mode.
In idle mode, only the CPU clock stops while peripherals and the oscillation source continue to operate normally.
Stop mode effects only the main system clock — a subsystem clock, if used, continues oscillating. In stop mode,
main system clock oscillation stops completely, halting all operations except for a few basic peripheral functions.
RESET or an interrupt can be used to terminate either idle or stop mode.
RESET
When a RESET signal occurs during normal operation or during power-down mode, the CPU enters idle mode
when the reset operation is initiated. When the standard oscillation stabilization interval (31.3 ms at 4.19 MHz)
has elapsed, normal CPU operation resumes.
I/O PORTS
The KS57C21116/C21124/C21132 has 13 I/O ports. Pin addresses for all I/O ports are mapped in bank 15 of the
RAM. There are 4 input pins and 47 configurable I/O pins for a total of 51 I/O pins. The contents of I/O port pin
latches can be read, written, or tested at the corresponding address using bit manipulation instructions.
TIMERS and TIMER/COUNTERS
The timer function has four main components: an 8-bit basic interval timer, an 8-bit timer/counter, a 16-bit
timer/counter and a watch timer. The 8-bit basic timer generates interrupt requests at precise intervals, based on
the selected clock frequency and has watch-dog timer function.
The programmable 8-bit and 16-bit timer/counters are used for external event counting, generation of arbitrary
clock frequencies for output, and dividing external clock signals. The 16-bit timer/counter is the source of the
clock signal that is required to drive the serial I/O interface and configurable as two 8-bit timer/counters.
The watch timer has an 8-bit watch timer mode register, a clock selector and a frequency divider circuit. Its
functions include real-time and watch-time measurement, clock generation for the LCD controller and frequency
outputs for buzzer sound.
LCD DRIVER/CONTROLLER
The KS57C21116/C21124/C21132 can directly drive an up-to-1,280-dot LCD panel. The LCD function block has
the following components:
— RAM area for storing display data
— 80 segment output pins (SEG0–SEG79)
— Segment expandable circuit
— 16 common output pins (COM0–COM15)
— 5 operating power supply pins (VLC1–VLC5
)
— Sixteen level LCD contrast control circuit (software)
Frame frequency, LCD clock, duty, and segment pins used for display output are controlled by bit settings in the
8-bit mode register, LMOD. You use the 4-bit LCD control register, LCON, to turn the LCD display on and off,
and to control current supplied to the dividing resistors. Segment data are output using a direct memory access
method synchronized with the LCD frame frequency (fLCD).
Using the main system clock, the LCD panel operates in idle mode; during stop mode, it is turned off. If a
subsystem clock is used as a clock source, the LCD panel will continue to operate during stop and idle modes.
1-6
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
SERIAL I/O INTERFACE
PRODUCT OVERVIEW
The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:
— 8-bit mode register
— Clock selector circuit
— 8-bit buffer register
— 3-bit serial clock counter
The serial I/O circuit can be set either to transmit-and-receive or to receive-only mode. MSB-first or LSB-first
transmission is also selectable. The serial interface operates with an internal or an external clock source, or using
the clock signal generated by the 16-bit timer/counter. To modify transmission frequency, the appropriate bits in
the serial I/O mode register (SMOD) must be manipulated.
COMPARATOR
Port 4 can be used as a analog input port for a comparator. The reference voltage for the 3-channel comparator
can be supplied either internally or externally at P4.2. The comparator module has the following components:
— Comparator
— Internal reference voltage generator (4-bit resolution)
— External reference voltage source at P4.2
— Comparator mode register (CMOD)
— Comparison result register (CMPREG)
1-7
PRODUCT OVERVIEW
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
BLOCK DIAGRAM
SCK
/K0/P0.0
SO/K1/P0.1
SI/K2/P0.2
BUZ/K3/P0.3
BASIC
TIMER
WATCH-DOG
TIMER
I/OPORT 0
Xin
Xout
RESET
XTin XTout
INT0/P1.0
INT1/P1.1
INT2/P1.2
INT4/P1.3
WATCH
TIMER
INPUT PORT 1
I/O PORT 2
INTERRUPT
CONTROL
BLOCK
M/P2.0
LCDFR/P2.1
CLO1/P2.2
CLO2/P2.3
STACK
POINTER
CLOCK
VLC1-VLC5
COM0-COM7
LCD
COM8-COM15/
SEG87-SEG80
SEG0-SEG47
DRIVER/
CONTROLLER
TCLO0/CL/P3.0
TCLO1/P3.1
TCL0/P3.2
I/O PORT 3
SEG48-SEG79/
PORT13-PORT6
TCL1/P3.3
INTERNAL
INTERRUPTS
CIN0/P4.0
CIN1/P4.1
CIN2/P4.2
PROGRAM
COUNTER
M/P2.0
LCDFR/P2.1
CL/P3.0/TCLO0
SEGMENT
EXPANDER
I/O PORT 4
SEG79/K4/P6.0
SEG78/K5/P6.1
SEG77/K6/P6.2
SEG76/K7/P6.3
SEG75-SEG72/
P7.0-P7.3
I/O PORT 6
I/O PORT 7
SCK
P0.0 /
/K0
SERIAL I/O
P0.1 / SO/K1
P0.2 / SI/K2
PROGRAM
STATUS
WORD
SEG71-SEG68/
P8.0–P8.3
SEG67-SEG64/
P9.0–P9.3
8-BIT
TIMER/
COUNTER0
I/O PORT 8
I/O PORT 9
INSTRUCTION DECODER
8-BIT TIMER/
COUNTER1A
16-BIT
TIMER/
COUNTER1
SEG63-SEG60/
P10.0–P10.3
SEG59-SEG56/
P11.0–P11.3
I/O PORT 10
I/O PORT 11
8-BIT TIMER/
COUNTER1B
ARITHMETIC
AND
FLAGS
LOGIC UNIT
SEG55-SEG52/
P12.0–P12.3
SEG51-SEG48/
P13.0–P13.3
I/O PORT 12
I/O PORT 13
COMPARATOR
3,584x 4-BIT
DATA
16/24/32 KBYTE
PROGRAM
MEMORY
MEMORY
Figure 1-1. KS57C21116/C21124/C21132 Simplified Block Diagram
1-8
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
PIN ASSIGNMENTS
COM9/SEG86
COM8/SEG87
COM7
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
COM6
COM5
COM4
COM3
COM2
COM1
COM0
VLC5
VLC4
VLC3
VLC2
VLC1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
P0.0/
/K0
SCK
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
KS57C21116/C21124/C21132
(128-QFP-1420)
V
DD
V
SS
X
OUT
X
IN
TEST
XT
IN
XT
OUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
SEG48/P13.3
SEG49/P13.2
SEG50/P13.1
SEG51/P13.0
SEG52/P12.3
SEG53/P12.2
SEG54/P12.1
SEG55/P12.0
SEG56/P11.3
SEG57/P11.2
P1.3/INT4
P2.0/M
P2.1/LCDFR
P2.2/CLO1
P2.3/CLO2
P3.0/TCLO0/CL
P3.1/TCLO1
P3.2/TCL0
Figure 1-2. KS57C21116/C21124/C21132 128-QFP Pin Assignment
1-9
PRODUCT OVERVIEW
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PIN DESCRIPTIONS
Table 1-1. KS57C21116/C21124/C21132 Pin Descriptions
Pin Type Description
Pin Name
P0.0
P0.1
P0.2
P0.3
Number
Share Pin
I/O
4-bit I/O port.
16
17
18
19
SCK/K0
SO/K1
SI/K2
1-bit and 4-bit read/write and test is possible.
4-bit unit pull-up resisters are assignable to input pins
by software and are automatically disabled for output
pins. Each bit pin can be allocated as input or output
(1-bit unit). The N-ch open drain or push-pull output
may be selected by software (1-bit unit).
BUZ/K3
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
28
29
30
31
INT0
INT1
INT2
INT4
1-bit and 4-bit read and test is possible.
4-bit unit pull-up resistors are assignable to input pins
by software.
P2.0
P2.1
P2.2
P2.3
I/O
I/O
4-bit I/O port. 1-bit and 4-bit read/write and test is
possible. I/O function is same as port 0.
32
33
34
35
M
LCDFR
CLO1
CLO2
P3.0
P3.1
P3.2
P3.3
4-bit I/O port. 1-bit and 4-bit read/write and test is
possible. I/O function is same as port 0.
36
37
38
39
TCLO0/CL
TCLO1
TCL0
TCL1
P4.0
P4.1
P4.2
I/O
I/O
3-bit I/O port. I/O function is same as port 0 except
that port 4 is 3-bit I/O port.
40
41
42
CIN0
CIN1
CIN2
P6.0
P6.1
P6.2
P6.3
4-bit I/O port. 1-, 4-bit and 8-bit read/write and test is
possible. 4-bit unit pull-up resisters are assignable to
input pins by software and are automatically disabled
for output pins. Each bit pin can be allocated as input
or output (1-bit unit). The N-ch open drain or push-
pull output may be selected by software (4-bit unit).
43
44
45
46
47–50
K4/SEG79
K5/SEG78
K6/SEG77
K7/SEG76
SEG75–72
P7.0–P7.3
P8.0–P8.3
P9.0–P9.3
I/O
I/O
I/O
4-bit I/O port. 1-, 4-bit and 8-bit read/write and test is
possible. I/O function is same as port 6, 7.
51–54
55–58
SEG71–68
SEG67–64
P10.0–P10.3
P11.0–P11.3
4-bit I/O port. 1-, 4-bit and 8-bit read/write and test is
possible. I/O function is same as port 6, 7.
59–62
63–66
SEG63–60
SEG59–56
P12.0–P12.3
P13.0–P13.3
4-bit I/O port. 1-, 4-bit and 8-bit read/write and test is
possible. I/O function is same as port 6, 7.
67–70
71–74
SEG55–52
SEG51–48
SCK
SO
SI
I/O
I/O
I/O
I/O
I/O
Serial I/O interface clock signal
Serial data output
16
17
18
19
P0.0
P0.1
P0.2
P0.3
Serial data input
BUZ
2, 4, 8, 16 kHz frequency output for buzzer sound
External interrupts with rising/falling edge detection
K0–K3
K4–K7
16–19
43–46
P0.0–P0.3
P6.0–P6.3
1-10
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
Table 1-1. KS57C21116/C21124/C21132 Pin Descriptions (Continued)
Pin Name
INT0
Pin Type
Description
Number
Share Pin
P1.0
I
I
I
External interrupts with rising/falling edge detection
External interrupts with rising/falling edge detection
28
29
30
INT1
INT2
P1.1
External quasi-interrupts with rising/falling edge
detection
P1.2
INT4
I
External interrupts with rising/falling edge detection
Alternated signal for SEG driver
31
32
33
34
35
36
36
37
38
39
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.0
P3.1
P3.2
P3.3
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LCDFR
CLO1
CLO2
CL
Synchronous frame signal for SEG driver
Clock output or operating clock for SEG driver
Clock output or operating clock for SEG driver
Data shift clock for SEG driver
TCLO0
TCLO1
TCL0
TCL1
CIN0–CIN2
Timer/counter0 clock output
Timer/counter1 clock output
External clock input for timer/counter 0
External clock input for timer/counter 1
CIN0,1: comparator input only
CIN2: comparator input or external reference input
40, 41
42
P4.0–P4.1
P4.2
SEG0–SEG47
O
O
LCD segment data output
LCD segment data output
122–75
74–43
–
SEG48–
SEG79
Port13–6
SEG80–
SEG87
O
LCD segment data output
2,1,
128–123
COM15–8
COM0–COM7
COM8–COM15
O
O
LCD common data output
LCD common data output
10–3
–
123–128
1, 2
SEG87–80
V –V
LC1 LC5
–
LCD power supply. Voltage dividing resistors are
fixed.
15–11
–
V
V
X
–
–
–
Main power supply
Ground
20
21
–
–
–
DD
SS
X
Crystal, Ceramic, or RC oscillator signal I/O for main
system clock.
23, 22
in, out
XT XT
in,
–
I
Crystal oscillator signal I/O for subsystem clock.
25, 26
24
–
–
–
out
TEST
Test signal input (must be connected to V
)
SS
RESET
I
Reset signal
27
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-11
PRODUCT OVERVIEW
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
Table 1-2. Overview of KS57C21116/C21124/C21132 Pin Data
Pin Names
P0.0–P0.3
P1.0–P1.3
P2.0–P2.3
P3.0–P3.1
P3.2–P3.3
P4.0–P4.2
P6.0–P6.3
P7.0–P7.3
P8.0–P8.3
Share Pins
SCK, SO, SI, BUZ/K0–K3
INT0–INT2, INT4
M, LCDFR, CLO1, CLO2
TCLO0/CL, TCLO1
TCL0, TCL1
I/O Type
I/O
Reset Value
Input
Circuit Type
E-2
A-3
E
I
Input
I/O
Input
I/O
Input
E
I/O
Input
E-1
F-4
H-15
CIN0–CIN2
I/O
Input
I/O
K4–K7/SEG79–SEG76
SEG75–SEG72
Input
I/O
I/O
Input
H-8
H-8
SEG71–SEG68
Input
P9.0–P9.3
SEG67–SEG64
SEG63–SEG60
SEG59–SEG56
SEG55–SEG52
SEG51–SEG48
–
I/O
I/O
Input
H-8
H-8
P10.0–P10.3
P11.0–P11.3
P12.0–P12.3
P13.0–P13.3
COM0–COM7
COM8–COM15
SEG0–SEG47
VLC1–VLC5
Input
I/O
I/O
Input
H-8
H-8
Input
I/O
O
O
O
–
Input
H-8
H-4
Low output
Low output
Low output
–
SEG87–SEG80
–
H-6
H-5
–
–
–
–
–
–
VDD
VSS
–
–
–
–
–
–
–
–
–
–
–
–
XIN
X
OUT
,
XTIN XT
,
OUT
RESET
TEST
–
–
I
I
–
–
B
–
1-12
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
V
DD
PULL-UP
RESISTOR
VDD
PNE
PULL-UP
RESISTOR
RESISTOR
ENABLE
P-CH
RESISTOR
ENABLE
P-CHANNEL
IN
DATA
I/O
N-CH
OUTPUT
DISABLE
SCHMITT TRIGGER
Figure 1-5. Pin Circuit Type E
Figure 1-3. Pin Circuit Type A-3
VDD
VDD
PULL-UP
RESISTOR
PNE
VDD
PULL-UP
RESISTOR
RESISTOR
ENABLE
P-CH
N-CH
DATA
I/O
IN
OUTPUT
DISABLE
SCHMITT TRIGGER
SCHMITT TRIGGER
Figure 1-6. Pin Circuit Type E-1
Figure 1-4. Pin Circuit Type B
1-13
PRODUCT OVERVIEW
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
VDD
VDD
PULL-UP
RESISTOR
PNE
RESISTOR
ENABLE
-
P CH
DATA
I/O
N-CH
OUTPUT
DISABLE
SCHMITT TRIGGER
Figure 1-7. Pin Circuit Type E-2
VDD
PULL-UP
RESISTOR
SCHMITT
TRIGGER
RESISTOR
ENABLE
DIGITAL IN
ANALOG IN
PNE
VDD
EXT-REF
(P4.2 only)
P-CH
+
-
COMPARATOR
DATA
I/O
N-CH
INT-REF
DIGITAL or ANALOG
OUTPUT
DISABLE
SELECTABLE by
SOFTWARE (P4MOD)
Figure 1-8. Pin Circuit Type F-4
1-14
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
PRODUCT OVERVIEW
V
V
LC1
V
V
LC1
LC2
LC2
V
LC3
OUT
SEG/COM
COM
OUT
V
V
V
LC4
V
LC5
LC5
V
SS
SS
Figure 1-11. Pin Circuit Type H-6
Figure 1-9. Pin Circuit Type H-4
V
V
LC1
V
LC1
LC3
LC3
V
SEG
OUT
SEG
OUT
OUTPUT
DISABLE
V
LC4
V
LC4
V
SS
V
SS
Figure 1-10. Pin Circuit Type H-5
Figure 1-12. Pin Circuit Type H-7
1-15
PRODUCT OVERVIEW
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
V
DD
PULL-UP
RESISTOR
VDD
PNE
RESISTOR
ENABLE
P-CH
N-CH
DATA
I/O
OUTPUT
DISABLE1
SEG
CIRCUIT
TYPE H-7
OUTPUT
DISABLE2
Figure 1-13. Pin Circuit Type H-8
VDD
PULL-UP
RESISTOR
VDD
PNE
RESISTOR
ENABLE
P-CH
DATA
I/O
-
N CH
OUTPUT
DISABLE1
SEG
CIRCUIT
TYPE H-7
OUTPUT
DISABLE2
SCHMITT TRIGGER
Figure 1-14. Pin Circuit Type H-15
1-16
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
ELECTRICAL DATA
15 ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C21116/C21124/C21132 electrical characteristics is presented as tables and
graphics. The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— Comparator electrical characteristics
— LCD contrast controller characteristics
— A.C. electrical characteristics
— Operating voltage range
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement points
— Clock timing measurement at X
in
— Clock timing measurement at XT
in
— TCL0/TCL1 timing
— Input timing for RESET signal
— Input timing for external interrupts and quasi-interrupts
— Serial data transfer timing
15-1
ELECTRICAL DATA
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
Table 15-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
Input Voltage
VDD
–
– 0.3 to + 6.5
V
VI
All I/O pins active
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 15
V
V
Output Voltage
Output Current High
VO
IOH
–
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 35
Output Current Low
IOL
+ 30 (Peak value)
mA
+ 15 *
Total for ports 0, 2–9
+ 100 (Peak value)
+ 60 *
Operating Temperature
Storage Temperature
TA
–
–
– 40 to + 85
°
°
C
Tstg
– 65 to + 150
C
* The values for Output Current Low ( IOL ) are calculated as Peak Value ´
Duty .
Table 15-2. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Voltage
VIH1
All input pins except those
specified below for VIH2–VIH3
0.7 VDD
–
VDD
V
VIH2
Ports 0, 1, 4, 6, P3.2, P3.3, and
RESET
0.8 VDD
VDD
VIH3
VIL1
Xin, Xout, XTin, and XTout
VDD – 0.1
–
VDD
Input Low
Voltage
All input pins except those
specified below for VIL2–VIL3
–
0.3 VDD
V
VIL2
Ports 0, 1, 4, 6, P3.2, P3.3, and
RESET
0.2 VDD
VIL3
VOH
Xin, Xout, XTin, and XTout
0.1
–
Output High
Voltage
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
Ports 0, 2, 3, 4, ports 6–13
VDD – 1.0
–
–
V
V
Output Low
Voltage
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
–
2.0
0.4
Ports 0, 2, 3, 4, ports 6–13
VDD = 1.8 V to 5.5 V
IOL = 1.6 mA
15-2
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Leakage
Current
ILIH1
VI = VDD
All input pins except those
specified below for ILIH2
–
–
3
µA
ILIH2
VI = VDD
20
Xin, Xout, XTin, and XTout
Input Low
Leakage
Current
ILIL1
VI = 0 V
–
–
– 3
µA
All input pins except RESET, Xin,
Xout, XTin, and XTout
ILIL2
VI = 0 V
– 20
3
RESET, Xin, Xout, XTin, and XTout
Output High
Leakage
Current
ILOH
VO = VDD
All output pins
–
–
–
–
µA
µA
kW
Output Low
Leakage
Current
ILOL
VO = 0 V
– 3
All output pins
Pull-Up
Resistor
RLI
VI = 0 V; VDD = 5 V
Ports 0–4, ports 6–13
25
50
100
VDD = 3 V
50
100
200
40
100
250
500
60
200
400
800
90
RL2
RLCD
VDC
V = 0 V; VDD = 5 V, RESET
I
VDD = 3 V
LCD Voltage
Dividing
Resistor
–
kW
V
– 15 µA per common pin
– 15 µA per segment pin
–
–
–
–
120
120
mV
|
LC1-COMi|
Voltage Drop
(i = 0–15)
V
VDS
|
LC1-SEGx|
Voltage Drop
(x = 0–79)
V
VLC2
VDD = 1.8 V to 5.5 V, 1/5 bias
LCD clock = 0 Hz, VLC1 = VDD
0.8 VDD– 0.2 0.8 VDD 0.8 VDD– 0.2
V
LC2 Output
Voltage
V
VLC3
VLC4
VLC5
0.6 VDD– 0.2 0.6 VDD 0.6 VDD– 0.2
0.4 VDD– 0.2 0.4 VDD 0.4 VDD– 0.2
0.2 VDD– 0.2 0.2 VDD 0.2 VDD– 0.2
LC3 Output
Voltage
V
LC4 Output
Voltage
V
LC5 Output
Voltage
15-3
ELECTRICAL DATA
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
Table 15-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
(2)
Supply
Current (1)
V
= 5 V ± 10%
6.0 MHz
4.19 MHz
–
3.9
2.9
8.0
5.5
mA
I
DD
DD1
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.8
1.3
4.0
3.0
(2)
Idle mode
= 5 V ± 10%
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
I
DD2
V
DD
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
(3)
(3)
V
= 3 V ± 10%
–
15.3
6.4
30
15
5
µA
I
I
DD
DD3
32 kHz crystal oscillator
Idle mode; V = 3 V ± 10%
DD
32 kHz crystal oscillator
DD4
I
Stop mode; SCMOD =
= 5 V ± 10%
2.5
DD5
V
0000B
XTin = 0V
DD
Stop mode;
0.5
3
V
DD
= 3 V ± 10%
V
= 5 V ± 10%
SCMOD =
0100B
0.2
0.1
3
2
DD
V
DD
= 3 V ± 10%
NOTES:
1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output
port drive currents.
2. Data includes power consumption for subsystem clock oscillation.
3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
15-4
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
ELECTRICAL DATA
Table 15-3. Main System Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Oscillato
r
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max Units
Oscillation frequency (1)
Ceramic
Oscillator
–
0.4
–
6.0
MHz
Xin Xout
C1
C2
Stabilization time (2)
Stabilization occurs
–
–
–
4
ms
when V
is equal to
DD
the minimum
oscillator voltage
range; V
= 3.0 V.
DD
Oscillation frequency (1)
Crystal
Oscillator
–
0.4
6.0
MHz
Xin
Xout
C1
C2
Stabilization time (2)
V
V
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
–
–
–
–
–
–
10
30
ms
DD
DD
X input frequency (1)
in
External
Clock
0.4
6.0
MHz
Xin
Xout
X input high and low
in
–
83.3
–
–
2
1250
–
ns
level width (t , t
)
XH XL
RC
Frequency
MHz
Xin
Xout
R = 20 kW,
= 5 V
Oscillator
V
DD
R
–
1
–
R = 39 kW,
= 3 V
V
DD
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
15-5
ELECTRICAL DATA
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
Table 15-4. Subsystem Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
DD
A
Oscillato
r
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
Oscillator
XTin XTout
Oscillation frequency
(1)
–
32
32.768
35
kHz
C1
C2
Stabilization time (2)
V
V
= 2.7 V to 5.5
–
–
1.0
–
2
s
DD
V
DD
V
= 1.8 V to 5.5
–
10
External
Clock
XT input frequency
in
(1)
32
–
100
kHz
XTin XTout
XT input high and
in
–
5
–
15
µs
low level width (t
,
XTL
t
)
XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
in
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
15-6
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
ELECTRICAL DATA
Table 15-5. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
CIN
f = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
Output
Capacitance
COUT
CIO
–
–
–
–
15
15
pF
pF
I/O Capacitance
Table 15-6. Comparator Electrical Characteristics
(TA = – 40 C + 85 C, VDD = 4.0 V to 5.5 V, VSS = 0 V)
°
°
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input Voltage Range
–
–
0
–
V
V
DD
DD
Reference Voltage Range
VREF
VCIN1
–
–
–
–
0
–
–
–
–
–
V
V
Internal
mV
mV
mA
± 150
± 150
3
Input Voltage
Accuracy
External
VCIN2
–
Input Leakage Current
ICIN, IREF
– 3
Table 15-7. LCD Contrast Controller Characteristics
(TA = – 40 C + 85 C, VDD = 4.5 V to 5.5 V)
°
°
Parameter
Resolution
Symbol
–
Condition
Min
–
Typ
–
Max
4
Units
Bits
LSB
V
–
Linearity
RLIN
VLPP
–
–
–
± 1.0
VLC1
Max Output Voltage
(LCNST = #8FH)
VLC1=VDD=5V
4.9
–
15-7
ELECTRICAL DATA
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
Table 15-8. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time (note)
tCY
VDD = 2.7 V to 5.5 V
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
0.95
0
64
TCL0, TCL1 Input
Frequency
fTI0, fTI1
–
–
1.5
MHz
µs
VDD = 1.8 V to 5.5 V
1
–
TCL0, TCL1 Input tTIH0, tTIL0 VDD = 2.7 V to 5.5 V
0.48
High, Low Width
tTIH1, tTIL1
VDD = 1.8 V to 5.5 V
1.8
SCK Cycle Time
tKCY
VDD = 2.7 V to 5.5 V; Input
800
–
–
–
–
ns
ns
Output
650
VDD = 1.8 V to 5.5 V; Input
3200
Output
3800
325
SCK High, Low
Width
tKH, tKL
VDD = 2.7 V to 5.5 V; Input
Output
tKCY/2 – 50
1600
VDD = 1.8 V to 5.5 V; Input
Output
tKCY/2 – 150
100
SI Setup Time to
SCK High
tSIK
VDD = 2.7 V to 5.5 V; Input
–
–
–
–
ns
ns
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 1.8 V to 5.5 V; Output
VDD = 2.7 V to 5.5 V; Input
150
150
500
400
SI Hold Time to
SCK High
t
KSI
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 1.8 V to 5.5 V; Output
400
600
500
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
15-8
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
ELECTRICAL DATA
Table 15-8. A.C. Electrical Characteristics (Continued)
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output Delay for
SCK to SO
tKSO
VDD = 2.7 V to 5.5 V; Input
–
–
300
ns
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 1.8 V to 5.5 V; Output
250
1000
1000
–
Interrupt Input
High, Low Width
tINTH, tINTL INT0, INT1, INT2, INT4,
K0–K7
10
10
–
–
µs
µs
RESET Input Low
Width
tRSL
Input
–
NOTE: Minimum value for INT0 is based on a clock of 2t
or 128 / fx as assigned by the IMOD0 register setting.
CY
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
15.6 kHz
4.2 MHz
1
2
3
4
5
6
7
1.8
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 15-1. Standard Operating Voltage Range
15-9
ELECTRICAL DATA
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
Table 15-9. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
VDDDR
–
1.8
–
5.5
V
Data retention supply current
IDDDR
VDDDR = 1.8 V
–
0.1
1
µA
Release signal set time
tSREL
tWAIT
–
0
–
–
–
–
µs
217 / fx
Oscillator stabilization wait
Released by RESET
ms
(1)
time
(2)
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-
up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
15-10
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
ELECTRICAL DATA
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 15-2. Stop Mode Release Timing When Initiated By RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request
15-11
ELECTRICAL DATA
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
0.8 VDD
0.2 VDD
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
Figure 15-4. A.C. Timing Measurement Points (Except for X and XT )
in in
1 / f
x
t
t
XH
XL
X
in
V
DD
– 0.1 V
0.1 V
Figure 15-5. Clock Timing Measurement at X
in
1 / f
xt
t
t
XTH
XTL
XT
in
V
DD
– 0.1 V
0.1 V
Figure 15-6. Clock Timing Measurement at XT
in
15-12
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
ELECTRICAL DATA
1 / f
TI
t
t
TIH
TIL
TCL0/TCL1
0.7 V
DD
0.3 V
DD
Figure 15-7. TCL0/TCL1 Timing
t
RSL
RESET
0.2 V
DD
Figure 15-8. Input Timing for RESET Signal
t
t
INTL
INTH
INT0, 1, 2, 4
K0 to K7
0.8V
0.2V
DD
DD
Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts
15-13
ELECTRICAL DATA
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
t
KCY
t
t
KH
KL
0.8 V
DD
SCK
0.2 V
DD
t
t
KSI
SIK
0.8 V
DD
INPUT DATA
SI
0.2 V
DD
t
KSO
SO
OUTPUT DATA
Figure 15-10. Serial Data Transfer Timing
15-14
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
MECHANICAL DATA
16 MECHANICAL DATA
22.00± 0.3
20.00± 0.2
0-8°
+0.10
- 0.05
0.15
128-QFP-1420
#128
#1
+0.10
- 0.05
0.05 MIN
2.10± 0.10
2.40 MAX
(0.75)
0.50
0.20
±
0.10 MAX
0.10 MAX
0.50± 0.20
: Dimensions are in millimeters.
NOTE
Figure 16-1. 128-QFP-1420 Package Dimensions
16-1
MECHANICAL DATA
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
NOTES
16-2
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
KS57P21132 OTP
17 KS57P21132 OTP
OVERVIEW
The KS57P21132 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS57C21116/C21124/C21132 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The
EPROM is accessed by serial data format.
The KS57P21132 is fully compatible with the KS57C21116/C21124/C21132, both in function and in pin
configuration except ROM size. Because of its simple programming requirements, the KS57P21132 is ideal for
use as an evaluation chip for the KS57C21116/C21124/C21132.
17-1
KS57P21132 OTP
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
COM9/SEG86
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
COM8/SEG87
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
VLC5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VLC4
VLC3
VLC2
VLC1
SCK
P0.0/
/K0
P0.1/SO/K1
SDAT/P0.2/SI/K2
SCLK/P0.3/BUZ/K3
KS57P21132
(128-QFP-1420C)
V
/V
DD DD
V
/V
SS SS
X
OUT
X
IN
TEST
/
V
PP
XT
IN
XT
OUT
RESET /RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
SEG48/P13.3
SEG49/P13.2
SEG50/P13.1
SEG51/P13.0
SEG52/P12.3
SEG53/P12.2
SEG54/P12.1
SEG55/P12.0
SEG56/P11.3
SEG57/P11.2
P2.0/M
P2.1/LCDFR
P2.2/CLO1
P2.3/CLO2
P3.0/TCLO0/CL
P3.1/TCLO1
P3.2/TCL0
NOTE: The bolds indicate an OTP pin name.
Figure 17-1. KS57P21132 Pin Assignments (128-QFP Package)
17-2
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
KS57P21132 OTP
Table 17-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
Pin Name
P0.2
During Programming
I/O
Pin Name
Pin No.
Function
SDAT
18
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P0.3
SCLK
19
24
I/O
I
Serial clock pin. Input only pin.
TEST
V
(TEST)
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
PP
RESET
RESET
VDD/VSS
27
I
I
Chip Initialization
VDD/VSS
20/21
Logic power supply pin. VDD should be tied to +5
V during programming.
Table 17-2. Comparison of KS57P21132 and KS57C21116/C21124/C21132 Features
Characteristic KS57P21132 KS57C21116/C21124/C21132
Program Memory 32-Kbyte EPROM
16/24/32-Kbyte mask ROM
1.8 V to 5.5 V
Operating Voltage (VDD
)
1.8 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (TEST) = 12.5V
Pin Configuration
128 QFP
128 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the KS57P21132, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 17-3. Operating Mode Selection Criteria
VPP
(TEST)
ADDRESS
(A15-A0)
V
DD
REG/
MEM
R/W
MODE
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
17-3
KS57P21132 OTP
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 17-2. OTP Programming Algorithm
17-4
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
KS57P21132 OTP
Table 17-4. D.C. Electrical Characteristics
°
°
(TA
= – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter Symbol Conditions
= 5 V ± 10%
Min
Typ
Max
Units
I
(2)
Supply
Current (1)
V
DD
6.0 MHz
4.19 MHz
–
3.9
2.9
8.0
5.5
mA
DD1
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
1.8
1.3
4.0
3.0
I
(2)
Idle mode
= 5 V ± 10%
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
DD2
V
DD
Crystal oscillator
C1 = C2 = 22 pF
V
DD
= 3 V ± 10%
6.0 MHz
4.19 MHz
0.5
0.44
1.5
1.0
I
I
(3)
(3)
V
= 3 V ± 10%
–
15.3
6.4
30
15
5
µA
DD
DD3
DD4
32 kHz crystal oscillator
Idle mode; V = 3 V ± 10%
DD
32 kHz crystal oscillator
I
Stop mode; SCMOD =
= 5 V ± 10%
2.5
DD5
V
0000B
DD
XTin = 0V
Stop mode;
0.5
3
V
DD
= 3 V ± 10%
V
= 5 V ± 10%
SCMOD =
0100B
0.2
0.1
3
2
DD
V
DD
= 3 V ± 10%
NOTES:
1. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output
port drive currents.
2. Data includes power consumption for subsystem clock oscillation.
3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
4. Every values in this table is measured when the power control register (PCON) is set to "0011B".
17-5
KS57P21132 OTP
KS57C21116/C21124/C21132/P21132 MICROCONTROLLER
Main Oscillator Frequency
(Divided by 4)
CPU CLOCK
1.5 MHz
6 MHz
1.05 MHz
15.6 kHz
4.2 MHz
1
2
3
4
5
6
7
1.8
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 17-3. Standard Operating Voltage Range
17-6
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