KS57C21516Q-XX_技术文档

KS57C21516/P21516 MICROCONTROLLER

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

OVERVIEW

The KS57C21516 single-chip CMOS microcontroller has been designed for high performance using Samsung's

newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With an up-to-896-dot LCD direct drive capability, 8-bit and 16-bit timer/counter, and serial I/O, the KS57C21516

offers an excellent design solution for a wide variety of applications which require LCD functions.

Up to 39 pins of the 100-pin QFP package can be dedicated to I/O. Eight vectored interrupts provide fast

response to internal and external events. In addition, the KS57C21516's advanced CMOS technology provides

for low power consumption and a wide operating voltage range.

OTP

The KS57C21516 microcontroller is also available in OTP (One Time Programmable) version, KS57P21516.

KS57P21516 microcontroller has an on-chip 16K-byte one-time-programable EPROM instead of masked ROM.

The KS57P21516 is comparable to KS57C21516, both in function and in pin configuration.

1–1

PRODUCT OVERVIEW

KS57C21516/P21516 MICROCONTROLLER

FEATURES SUMMARY

Memory

Watch Timer

•

Time interval generation: 0.5 s, 3.9 ms

at 32768 Hz

•

544 ´ 4-bit RAM (excluding LCD display RAM)

16,384 ´ 8-bit ROM

•

4 frequency outputs to BUZ pin

Clock source generation for LCD

39 I/O Pins

•

I/O: 35 pins

Interrupts

Input only: 4 pins

•

Four internal vectored interrupts

LCD Controller/Driver

Four external vectored interrupts

Two quasi-interrupts

•

56 segments and 16 common terminals

8 and 16 common selectable

Bit Sequential Carrier

Internal resistor circuit for LCD bias

All dot can be switched on/off

•

Supports 16-bit serial data transfer in arbitrary

format

8-bit Basic Timer

Power-Down Modes

•

4 interval timer functions

Watch-dog timer

•

Idle mode (only CPU clock stops)

Stop mode (main system oscillation stops)

Subsystem clock stop mode

8-bit Timer/Counter

•

Programmable 8-bit timer

Oscillation Sources

External event counter

•

Crystal, ceramic, or RC for main system clock

Crystal oscillator for subsystem clock

Arbitrary clock frequency output

External clock signal divider

Serial I/O interface clock generator

Main system clock frequency: 0.4 – 6 MHz

Subsystem clock frequency: 32.768 kHz

CPU clock divider circuit (by 4, 8, or 64)

16-Bit Timer/Counter

•

Programmable 16-bit timer

External event counter

Instruction Execution Times

•

0.67, 1.33, 10.7 µs at 6 MHz

0.95, 1.91, 15.3 µs at 4.19 MHz

122 µs at 32.768 kHz

Arbitrary clock frequency output

External clock signal divider

8-bit Serial I/O Interface

Operating Temperature

•

8-bit transmit/receive mode

° °

– 40 C to 85 C

•

8-bit receive mode

Operating Voltage Range

1.8 V to 5.5 V

LSB-first or MSB-first transmission selectable

Internal or external clock source

•

Package Type

100-pin QFP

Memory-Mapped I/O Structure

•

Data memory bank 15

1–2

KS57C21516/P21516 MICROCONTROLLER

PRODUCT OVERVIEW

BLOCK DIAGRAM

BASIC

TIMER

WATCH

TIMER

Xin

Xout

RESET

XTin XTout

P1.0-P1.3/

INT0-INT4

INPUT PORT 1

I/O PORT 2

VLC1-VLC5

COM0-COM7

P4.0-P5.3/

P2.0/CLO

P2.1/LCDCK

P2.2/LCDSY

INTERRUPT

CONTROL

BLOCK

INSTRUCTION

REGISTER

LCD

DRIVER/

CONTROLLER

CLOCK

COM8-COM15

P3.0/TCLO0

P3.1/TCLO1

P3.2/TCL0

P3.3/TCL1

SEG0-SEG39

PROGRAM

COUNTER

I/O PORT 3

P9.3-P6.0/

SEG40-SEG55

INTERNAL

INTERRUPTS

SERIAL I/O

P4.0–P4.3/

COM8-COM11

PROGRAM

STATUS

WORD

I/O PORT 4

I/O PORT 5

INSTRUCTION

P5.0–P5.3/

COM12-COM15

P0.0/SCK/K0

P0.1/SO/K1

P0.2/SI/K2

I/O

PORT 0

ARITHMETIC

AND

LOGIC UNIT

P6.0–P6.3/

SEG55-SEG52/

KS4–KS7

STACK

POINTER

P0.3/BUZ/K3

I/O PORT 6

I/O PORT 7

8-BIT

TIMER/

COUNTER

P7.0–P7.3/

SEG51-SEG48

16-BIT

TIMER/

COUNTER

P8.0–P8.3/

SEG47-SEG44

I/O PORT 8

I/O PORT 9

544 x 4-BIT

DATA

MEMORY

16 KBYTE

PROGRAM

MEMORY

P9.0–P9.3/

SEG43-SEG40

Figure 1-1. KS57C21516 Simplified Block Diagram

1–3

PRODUCT OVERVIEW

KS57C21516/P21516 MICROCONTROLLER

PIN ASSIGNMENTS

1

2

3

4

5

6

7

8

SEG4

SEG3

SEG2

SEG1

SEG0

VLC5

VLC4

VLC3

VLC2

VLC1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

P9.3/SEG40

P9.2/SEG41

P9.1/SEG42

P9.0/SEG43

P8.3/SEG44

P8.2/SEG45

P8.1/SEG46

P8.0/SEG47

P7.3/SEG48

P7.2/SEG49

P7.1/SEG50

P7.0/SEG51

P6.3/SEG52/K7

P6.2/SEG53/K6

P6.1/SEG54/K5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SCK

P0.0/

/K0

P0.1/SO/K1

P0.2/SI/K2

P0.3/BUZ/K3

VDD

KS57C21516

(100-QFP-1420C)

VSS

Xout

Xin

TEST

XTin

XTout

RESET

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

P2.0/CLO

P2.1/LCDCK

P2.2/LCDSY

P3.0/TCLO0

Figure 1-2. KS57C21516 100-QFP Pin Assignment Diagram

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KS57C21516/P21516 MICROCONTROLLER

PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1–1. KS57C21516 Pin Descriptions

Description

Pin Name

P0.0

P0.1

P0.2

P0.3

Pin Type

Number

Share Pin

I/O

4-bit I/O port.

11

12

13

14

SCK/K0

SO/K1

SI/K2

1-bit and 4-bit read/write and test are possible.

Individual pins are software configurable as input or

output.

BUZ/K3

Individual pins are software configurable as open-

drain or push-pull output.

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

P1.0

P1.1

P1.2

P1.3

I

4-bit input port.

1-bit and 4-bit read and test are possible.

4-bit pull-up resistors are assignable by software.

23

24

25

26

INT0

INT1

INT2

INT4

P2.0

P2.1

P2.2

I/O

Same as port 0 except that port 2 is 3-bit I/O port.

Same as port 0.

27

28

29

CLO

LCDCK

LCDSY

P3.0

P3.1

P3.2

P3.3

30

31

32

33

TCLO0

TCLO1

TCL0

TCL1

P4.0–P4.3

I/O

4-bit I/O ports.

42–45

COM8–

COM11

COM12–

COM15

1-, 4-bit or 8-bit read/write and test are possible.

Individual pins are software configurable as input or

output.

P5.0–P5.3

46–49

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

P6.0–P6.3

P7.0–P7.3

I/O

Same as P4, P5.

50–53

54–57

SEG55/K4–

SEG52/K7

SEG51–

SEG48

P8.0–P8.3

P9.0–P9.3

Same as P4, P5.

58–61

62–65

SEG47–

SEG44

SEG43–

SEG40

SCK

SO

SI

I/O

Serial I/O interface clock signal.

Serial data output.

11

12

13

14

P0.0/K0

P0.1/K1

P0.2/K2

P0.3/K3

Serial data input.

BUZ

2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for

buzzer signal.

INT0, INT1

I

External interrupts. The triggering edge for INT0 and

INT1 is selectable.

23, 24

P1.0, P1.1

1–5

PRODUCT OVERVIEW

KS57C21516/P21516 MICROCONTROLLER

Table 1–1. KS57C21516 Pin Descriptions (Continued)

Pin Name

Pin Type

Description

Number

Share Pin

INT2

I

Quasi-interrupt with detection of rising or

falling edges.

25

P1.2

INT4

I

External interrupt with detection of rising or

falling edges.

26

P1.3

CLO

I/O

Clock output .

27

28

29

P2.0

P2.1

P2.2

LCDCK

LCDSY

LCD clock output for display expansion.

LCD synchronization clock output for display

expansion.

TCLO0

I/O

O

Timer/counter 0 clock output.

30

31

P3.0

P3.1

TCLO1

Timer/counter 1 clock output.

TCL0

External clock input for timer/counter 0.

External clock input for timer/counter 1.

LCD common signal output.

32

P3.2

TCL1

33

P3.3

COM0–COM7

COM8–COM11

COM12–COM15

SEG0–SEG39

34–41

42–45

46–49

–

I/O

P4.0–P4.3

P5.0–P5.3

–

O

LCD segment signal output.

5–1,

100–66

SEG40–SEG43

SEG44–SEG47

SEG48–SEG51

SEG52–SEG55

K0–K3

I/O

65–62

61–58

57–54

53–50

11–14

P9.3–P9.0

P8.3–P8.0

P7.3–P7.0

P6.3/K7–P6.0/K4

P0.0–P0.3

I/O

External interrupt. The triggering edge is

selectable.

K4–K7

50–53

15

P6.0–P6.3

V

DD

V

SS

–

I

Main power supply.

Ground.

–

16

RESET

Reset signal.

22

V –V

LC1 LC5

–

LCD power supply.

10–6

18, 17

X

Crystal, Ceramic or RC oscillator pins for

system clock.

in, out

XT XT

in,

–

I

Crystal oscillator pins for subsystem clock.

20, 21

19

–

out

TEST

Test signal input. (must be connected to V )

SS

NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

1–6

KS57C21516/P21516 MICROCONTROLLER

PRODUCT OVERVIEW

Table 1–2. Overview of KS57C21516 Pin Data

Pin Names

P0.1, P0.3

Share Pins

SO/K1, BUZ/K3

SCK/K0, SI/K2

I/O Type

I/O

Reset Value

Input

Circuit Type

E-1

E-2

A-3

E

P0.0, P0.2

P1.0–P1.3

P2.0–P2.2

P3.0–P3.1

P3.2–P3.3

I/O

Input

INT0–INT2, INT4

CLO, LCDCK, LCDSY

TCLO0, TCLO1

TCL0, TCL1

I

Input

I/O

Input

I/O

Input

E

I/O

Input

E-1

H-13

P4.0–P4.3

P5.0–P5.3

COM8–COM11

COM12–COM15

I/O

Input

I/O

H-16

P6.0–P6.3

P7.0–P7.3

SEG55/K4–SEG52/K7

SEG51–SEG48

Input

I/O

H-13

P8.0–P8.3

P9.0–P9.3

SEG47–SEG44

SEG43–SEG40

COM0–COM7

SEG0–SEG39

–

O

–

I

High

H-3

High

H-15

V

DD

V

SS

–

B

–

RESET

V –V

LC1 LC5

–

I

X

in, out

XT XT

in,

out

TEST

1–7

KS57C21516/P21516 MICROCONTROLLER

PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

V

DD

V

DD

PULL-UP

RESISTOR

-

P CHANNEL

IN

N-CHANNEL

SCHMITT TRIGGER

Figure 1-3. Pin Circuit Type A

Figure 1-5. Pin Circuit Type B

V

DD

V

DD

PULL-UP

RESISTOR

P-CHANNEL

OUT

PULL-UP

RESISTOR

ENABLE

DATA

P-CHANNEL

N-CHANNEL

IN

OUTPUT

DISABLE

SCHMITT TRIGGER

Figure 1-4. Pin Circuit Type A-3

Figure 1-6. Pin Circuit Type C

1–8

KS57C21516/P21516 MICROCONTROLLER

PRODUCT OVERVIEW

VDD

PULL-UP

RESISTOR

PNE

RESISTOR

ENABLE

P-CH

I/O

DATA

N-CH

OUTPUT

DISABLE

CIRCUIT TYPE A

Figure 1-7. Pin Circuit Type E

VDD

PULL-UP

RESISTOR

PNE

RESISTOR

ENABLE

P-CH

N-CH

I/O

DATA

OUTPUT

DISABLE

SCHMITT TRIGGER

Figure 1-8. Pin Circuit Type E-1

1–9

PRODUCT OVERVIEW

KS57C21516/P21516 MICROCONTROLLER

VDD

PULL-UP

RESISTOR

PNE

RESISTOR

ENABLE

P-CH

I/O

DATA

N-CH

OUTPUT

DISABLE

SCHMITT TRIGGER

Figure 1-9. Pin Circuit Type E-2

1–10

KS57C21516/P21516 MICROCONTROLLER

PRODUCT OVERVIEW

V

DD

LC1

OUT

COM DATA

V

LC4

LC5

Figure 1-10. Pin Circuit Type H-3

V

DD

LC2

OUT

SEG DATA

V

LC3

LC5

Figure 1-11. Pin Circuit Type H-15

1–11

PRODUCT OVERVIEW

KS57C21516/P21516 MICROCONTROLLER

V

DD

PULL-UP

RESISTOR

P-CH

RESISTOR

ENABLE

COM/SEG

TYPE H-3

OUTPUT

DISABLE

DATA

I/O

TYPE C

CIRCUIT TYPE A

Figure 1-12. Pin Circuit Type H-13

V

DD

PULL-UP

RESISTOR

P-CH

RESISTOR

ENABLE

SEG

TYPE H-15

OUTPUT

DISABLE

DATA

TYPE C

I/O

SCHMITT TRIGGER

Figure 1-13. Pin Circuit Type H-16

1–12

KS57C21516/P21516 MICROCONTROLLER

ADDRESS SPACES

2

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

ROM maps for KS57C21516 devices are mask programmable at the factory. In its standard configuration, the

device's 16,384 ´ 8-bit program memory has three areas that are directly addressable by the program counter

(PC):

— 16-byte area for vector addresses

— 96-byte instruction reference area

— 16-byte general-purpose area

— 16,256-byte general-purpose area

General-purpose Program Memory

Two program memory areas are allocated for general-purpose use: One area is 16 bytes in size and the other is

16,256 bytes.

Vector Addresses

A 16-byte vector address area is used to store the vector addresses required to execute system resets and

interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the

enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the

corresponding service routines. The 16-byte area can be used alternately as general-purpose ROM.

REF Instructions

Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF

instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte

instructions, and one 3-byte instructions which are stored in the look-up table. Unused look-up table addresses

can be used as general-purpose ROM.

Table 2–1. Program Memory Address Ranges

ROM Area Function

Vector address area

Address Ranges

0000H–000FH

0010H–001FH

0020H–007FH

0080H–3FFFH

Area Size (in Bytes)

16

General-purpose program memory

REF instruction look-up table area

General-purpose program memory

96

16,256

2–1

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

GENERAL-PURPOSE MEMORY AREAS

The 16-byte area at ROM locations 0010H–001FH and the 16,256-byte area at ROM locations 0080H–3FFFH

are used as general-purpose program memory. Unused locations in the vector address area and REF instruction

look-up table areas can be used as general-purpose program memory. However, care must be taken not to

overwrite live data when writing programs that use special-purpose areas of the ROM.

VECTOR ADDRESS AREA

The 16-byte vector address area of the ROM is used to store the vector addresses for executing system resets

and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable

memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines.

16-byte vector addresses are organized as follows:

EMB

PC7

ERB

PC6

PC13

PC5

PC12

PC4

PC11

PC3

PC10

PC2

PC9

PC1

PC8

PC0

To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the

next page explain how to do this.

0000H

7

6

5

4

3

2

1

0

Vector Address Area

(16 bytes)

RESET

0000H

0002H

0004H

0006H

0008H

000AH

000CH

000EH

000FH

0010H

INTB/INT4

INT0

General Purpose Area

(16 bytes)

001FH

0020H

INT1

Instruction Reference Area

(96 bytes)

INTS

007FH

0080H

INTT0

INTT1

INTK

General Purpose Area

(16,256 bytes)

3FFFH

Figure 2–2. Vector Address Map

Figure 2–1. ROM Address Structure

2–2

KS57C21516/P21516 MICROCONTROLLER

ADDRESS SPACES

+

PROGRAMMING TIP — Defining Vectored Interrupts

The following examples show you several ways you can define the vectored interrupt and instruction reference

areas in program memory:

1. When all vector interrupts are used:

ORG

0000H

;

VENT0

VENT1

VENT2

VENT3

VENT4

VENT5

VENT6

VENT7

1,0,RESET

0,0,INTB

0,0,INT0

0,0,INT1

0,0,INTS

0,0,INTT0

0,0,INTT1

0,0,INTK

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address by RESET

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address by INTB

; EMB ¬ 0, ERB ¬ 0; Jump to INT0 address by INT0

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address by INT1

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address by INTS

; EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address by INTT0

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address by INTT1

; EMB ¬ 0, ERB ¬ 0; Jump to INTK address by INTK

2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations

must be skipped with the assembly instruction ORG so that jumps will address the correct locations:

ORG

0000H

;

VENT0

VENT1

ORG

1,0,RESET

0,0,INTB

0006H

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address by RESET

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address by INTB

; INT0 interrupt not used

VENT3

VENT4

0,0,INT1

0,0,INTS

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address by INT1

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address by INTS

;

ORG

000CH

; INTT0 interrupt not used

VENT6

VENT7

0,0,INTT1

0,0,INTK

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address by INTT1

; EMB ¬ 0, ERB ¬ 0; Jump to INTK address by INTK

;

ORG

0010H

2–3

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Defining Vectored Interrupts (Continued)

3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not

written by a ORG instruction as in Example 2, a CPU malfunction will occur:

ORG

0000H

;

VENT0

VENT1

VENT3

VENT4

VENT5

VENT6

VENT7

1,0,RESET

0,0,INTB

0,0,INT1

0,0,INTS

0,0,INTT0

0,0,INTT1

0,0,INTK

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address by RESET

; EMB ¬ 0, ERB ¬ 0; Jump to INTB address by INTB

; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address by INT0

; EMB ¬ 0, ERB ¬ 0; Jump to INTS address by INT1

; EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address by INTS

; EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address by INTT0

; EMB ¬ 0, ERB ¬ 0; Jump to INTK address by INTT1

;

ORG

0010H

General-purpose ROM area

In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but

VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU

malfunction to occur.

2–4

KS57C21516/P21516 MICROCONTROLLER

INSTRUCTION REFERENCE AREA

ADDRESS SPACES

Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in ad-

dresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or

look-up table. Locations in the REF look-up table may contain two 1-byte instructions, one 2-byte instruction, or

one 3-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are referencing

must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area

in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. In summary, there are three ways to the

REF instruction:

By using REF instructions you can execute instructions larger than one byte. In summary, there are three ways

you can use the REF instruction:

— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions,

— Branching to any location by referencing a branch instruction stored in the look-up table,

— Calling subroutines at any location by referencing a call instruction stored in the look-up table.

+

PROGRAMMING TIP — Using the REF Look-Up Table

Here is one example of how to use the REF instruction look-up table:

ORG

0020H

;

JMAIN

KEYCK

WATCH

INCHL

TJP

BTSF

TCALL

LD

INCS

•

MAIN

; 0, MAIN

; 1, KEYFG CHECK

; 2, Call CLOCK

KEYFG

CLOCK

@HL,A

HL

; 3, (HL) ¬

A

•

ABC

LD

ORG

EA,#00H

0080

; 47, EA ¬ #00H

;

MAIN

NOP

•

REF

KEYCK

JMAIN

WATCH

INCHL

; BTSF KEYFG (1-byte instruction)

; KEYFG = 1, jump to MAIN (1-byte instruction)

; KEYFG = 0, CALL CLOCK (1-byte instruction)

; LD @HL,A

; INCS HL

REF

ABC

; LD EA,#00H (1-byte instruction)

•

2–5

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

DATA MEMORY (RAM)

OVERVIEW

In its standard configuration, the 736 ´ 4-bit data memory has five areas:

— 32 ´ 4-bit working register area in bank 0

— 224 ´ 4-bit general-purpose area in bank 0 which is also used as the stack area

— 256 ´ 4-bit general-purpose area in bank 1

— 32 ´ 4-bit general-purpose area in bank 2

— 224 ´ 4-bit area for LCD data in bank 2

— 128 ´ 4-bit area in bank 15 for memory-mapped I/O addresses

To make it easier to reference, the data memory area has four memory banks — bank 0, bank 1, bank 2 and

bank 15. The select memory bank instruction (SMB) is used to select the bank you want to select as working data

memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable.

Initialization values for the data memory area are not defined by hardware and must therefore be initialized by

program software following power RESET. However, when RESET signal is generated in power-down mode, the

most of data memory contents are held.

000H

WORKING REGISTERS

(32 x 4 Bits)

01FH

020H

BANK 0

GENERAL-PURPOSE

REGISTERS AND

STACK AREA

(224 x 4 Bits)

0FFH

100H

GENERAL-PURPOSE

REGISTERS

BANK 1

BANK 2

(256 x 4 Bits)

1FFH

200H

LCD DATA REGISTERS

(224 x 4 Bits) and

GENERAL-PURPOSE

REGISTERS (32 x 4 Bits)

2FFH

F80H

~

MEMORY-MAPPED I/O

AEERESS REGISTERS

(128 x 4 Bits)

BANK 15

FFFH

Figure 2–3. Data Memory (RAM) Map

2–6

KS57C21516/P21516 MICROCONTROLLER

Memory Banks 0, 1, 2, and 15

ADDRESS SPACES

Bank 0

(000H–0FFH)

The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers;

the next 224 nibbles (020H–0FFH) can be used both as stack area and as

general-purpose data memory. Use the stack area for implementing subroutine

calls and returns, and for interrupt processing.

Bank 1

Bank 2

(100H–1FFH)

(200H–2FFH)

Bank 1 is used for general-purpose.

The 224 nibbles of bank 2 are for display registers or general-purpose use;

locations 2xE and 2xF (x = 0–F) are for general-purpose use in bank 2.

Detailed map on bank 2 is shown in Section 12 LCD Controller/Driver.

Bank 15

(F80H–FFFH)

The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed

RAM locations for each peripheral hardware address are mapped into this area.

Data Memory Addressing Modes

The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, 2, or 15. When

the EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or

indirect addressing is used. With direct addressing, you can access locations 000H–07FH of bank 0 and bank 15.

With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic one, all

four data memory banks can be accessed according to the current SMB value.

For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to

address RAM locations, remember to use the even-numbered register address as the instruction operand.

Working Registers

The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2,

and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable.

Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag

bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for

indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable

to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.

LCD Data Register Area

Bit values for LCD segment data are stored in data memory bank 2. Register locations in this area that are not

used to store LCD data can be assigned to general-purpose use.

2–7

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

Table 2–2. Data Memory Organization and Addressing

Addresses

000H–01FH

020H–0FFH

100H–1FFH

200H–2FFH

Register Areas

Working registers

Bank

EMB Value

SMB Value

0

0, 1

0

Stack and general-purpose registers

General-purpose registers

1

2

1

2

Display registers and general-purpose

registers

F80H–FFFH

I/O-mapped hardware registers

15

0, 1

15

+

PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1

Clear banks 0 and 1 of the data memory area:

RAMCLR

RMCL1

;

SMB

LD

INCS

JR

1

; RAM (100H–1FFH) clear

; RAM (010H–0FFH) clear

HL,#00H

A,#0H

@HL,A

HL

RMCL1

SMB

LD

INCS

JR

0

HL,#10H

@HL,A

HL

RMCL0

2–8

KS57C21516/P21516 MICROCONTROLLER

WORKING REGISTERS

ADDRESS SPACES

Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store

intermediate results during program execution, as well as pointer values used for indirect addressing. Unused

registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-

bit units or, using paired registers, as 8-bit units.

000H

A

001H

E

002H

L

003H

H

X

Working

Register

Bank 0

004H

005H

006H

W

Data

Memory

Bank 0

Z

Y

007H

008H

Register

Bank 1

A

Y

...

00FH

010H

Register

Bank 2

017H

018H

Register

Bank 3

01FH

Figure 2–4. Working Register Map

2–9

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

Working Register Banks

For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2,

and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection

instruction (SRB n) and by setting the status of the register bank enable flag (ERB).

Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou-

tines. Following this convention helps to prevent possible data corruption during program execution due to con-

tention in register bank addressing.

Table 2–3. Working Register Organization and Addressing

ERB Setting

SRB Settings

Selected Register Bank

3

0

2

0

1

x

0

1

0

x

0

1

0

1

0

1

Always set to bank 0

Bank 0

Bank 1

Bank 2

Bank 3

NOTE: 'x' means don't care.

Paired Working Registers

Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E and

A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data

manipulation.

The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z

always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit

registers or four 8-bit double registers in each of the four working register banks.

(MSB)

(LSB)

(MSB)

(LSB)

Y

Z

X

L

W

H

E

A

Figure 2–5. Register Pair Configuration

2–10

KS57C21516/P21516 MICROCONTROLLER

Special-Purpose Working Registers

ADDRESS SPACES

Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also

be used as a 1-bit accumulator.

8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register

serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working

registers as program loop counters by letting you transfer a value to the L register and increment or decrement it

using a single instruction.

1-BIT

ACCUMULATOR

C

4-BIT

ACCUMULATOR

A

8-BIT

ACCUMULATOR

EA

Figure 2–6. 1-Bit, 4-Bit, and 8-Bit Accumulator

Recommendation for Multiple Interrupt Processing

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

2–11

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Selecting the Working Register Area

The following examples show the correct programming method for selecting working register area:

1. When ERB = "0":

VENT2

1,0,INT0

; EMB ¬ 1, ERB ¬ 0, Jump to INT0 address

;

INT0

PUSH

SRB

PUSH

SMB

LD

INCS

LD

POP

IRET

SB

2

HL

WX

YZ

EA

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

EA

YZ

WX

HL

SB

; PUSH current SMB, SRB

; Instruction does not execute because ERB = "0"

; PUSH HL register contents to stack

; PUSH WX register contents to stack

; PUSH YZ register contents to stack

; PUSH EA register contents to stack

; POP EA register contents from stack

; POP YZ register contents from stack

; POP WX register contents from stack

; POP HL register contents from stack

; POP current SMB, SRB

The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an

interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and

SRB values, as shown in Example 2 below.

2. When ERB = "1":

VENT2

1,1,INT0

; EMB ¬ 1, ERB ¬ 1, Jump to INT0 address

;

INT0

PUSH

SRB

SMB

LD

INCS

LD

POP

IRET

SB

2

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

SB

; Store current SMB, SRB

; Select register bank 2 because of ERB = "1"

; Restore SMB, SRB

2–12

KS57C21516/P21516 MICROCONTROLLER

ADDRESS SPACES

STACK OPERATIONS

STACK POINTER (SP)

The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data

memory set aside for temporary storage of data and addresses. The SP can be read or written by 8-bit control

instructions. When addressing the SP, bit 0 must always remain cleared to logic zero.

F80H

F81H

SP3

SP7

SP2

SP6

SP1

SP5

"0"

SP4

There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack

(pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the

last data to be written to the stack.

The program counter contents and program status word are stored in the stack area prior to the execution of a

CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out)

type. The stack area is located in general-purpose data memory bank 0.

During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine

has completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed.

The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the en-

able memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register areas

can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s).

Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack

pointer by program code to location 00H. This sets the first register of the stack area to 0FFH.

NOTE

A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or

interrupt routines are used continuously, the stack area should be set in accordance with the maximum

number of subroutine levels. To do this, estimate the number of nibbles that will be used for the

subroutines or interrupts and set the stack area correspondingly.

+

PROGRAMMING TIP — Initializing the Stack Pointer

To initialize the stack pointer (SP):

1. When EMB = "1":

SMB

LD

15

EA,#00H

SP,EA

; Select memory bank 15

; Bit 0 of SP is always cleared to "0"

; Stack area initial address (0FFH) ¬ (SP) – 1

2. When EMB = "0":

LD

EA,#00H

SP,EA

; Memory addressing area (00H–7FH, F80H–FFFH)

2–13

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

PUSH OPERATIONS

Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the

stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number

determined by the type of push operation and then points to the next available stack location.

PUSH Instructions

A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are

referenced by the stack pointer: one for the upper register value and another for the lower register. After the

PUSH has executed, the SP is decremented by two and points to the next available stack location.

CALL Instructions

When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit

stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag

are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up

to the number of levels permitted in the stack.

Interrupt Routines

An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the

stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is

decremented by six and points to the next available stack location. During an interrupt sequence, subroutines

may be nested up to the number of levels which are permitted in the stack area.

INTERRUPT

(When INT is acknowledged,

SP SP – 6)

PUSH

(After PUSH, SP

CALL

(After CALL, SP

SP – 2)

SP – 6)

SP – 6

SP – 5

SP – 4

SP – 3

SP – 2

SP – 1

SP

SP – 6

SP – 5

SP – 4

SP – 3

SP – 2

SP – 1

SP

PC11– PC8

PC13 PC12

PC11– PC8

0

PC13–PC12

-

PC3 – PC0

PC7 – PC4

PC3 – PC0

PC7 – PC4

0

0 EMB ERB

PSW

IS1 IS0 EMB ERB

PSW

SP – 2

SP – 1

SP

LOWER REGISTER

UPPER REGISTER

0

C

SC2 SC1 SC0

Figure 2–7. Push-Type Stack Operations

2–14

KS57C21516/P21516 MICROCONTROLLER

POP OPERATIONS

ADDRESS SPACES

For each push operation there is a corresponding pop operation to write data from the stack back to the source

register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET;

for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined

by the type of operation and points to the next free stack location.

POP Instructions

A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and

SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register.

After the POP has executed, the SP is incremented by two and points to the next free stack location.

RET and SRET Instructions

The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP

to reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and

the ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack

location.

IRET Instructions

The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4-

bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has

executed, the SP is incremented by six and points to the next free stack location.

RET OR SRET

POP

SP + 2)

IRET

SP + 6)

(SP

PC11 – PC8

PC13–PC12

SP + 6)

(SP

PC11 – PC8

LOWER REGISTER

UPPER REGISTER

SP

0

PC13–PC12

SP + 1

SP + 2

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

PC3 – PC0

PC7 – PC4

PC3 – PC0

PC7 – PC4

0

0 EMB ERB

PSW

IS1 IS0 EMB ERB

PSW

0

C

SC2 SC1 SC0

Figure 2–8. Pop-Type Stack Operations

2–15

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

BIT SEQUENTIAL CARRIER (BSC)

The bit sequential carrier (BSC) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM

control instructions. RESET clears all BSC bit values to logic zero.

Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing

(memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit

data by moving the bit location sequentially and then incrementing or decrementing the value of the L register.

BSC data can also be manipulated using direct addressing. For 8-bit manipulations, the 4-bit register names

BSC0 and BSC2 must be specified and the upper and lower 8 bits manipulated separately.

If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L

register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3.

Table 2–4. BSC Register Organization

Name

BSC0

BSC1

BSC2

BSC3

Address

FC0H

Bit 3

Bit 2

Bit 1

Bit 0

BSC0.3

BSC1.3

BSC2.3

BSC3.3

BSC0.2

BSC1.2

BSC2.2

BSC3.2

BSC0.1

BSC1.1

BSC2.1

BSC3.1

BSC0.0

BSC1.0

BSC2.0

BSC3.0

FC1H

FC2H

FC3H

+

PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data

To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin:

BITS

SMB

LD

SMB

LD

LDB

INCS

JR

EMB

15

EA,#37H

BSC0,EA

EA,#59H

BSC2,EA

0

L,#0H

C,BSC0.@L

P3.0,C

L

;

; BSC0 ¬ A, BSC1 ¬

;

; BSC2 ¬ A, BSC3 ¬

E

;

AGN

; P3.0 ¬

C

AGN

RET

2–16

KS57C21516/P21516 MICROCONTROLLER

ADDRESS SPACES

PROGRAM COUNTER (PC)

A 14-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a

reset operation or an interrupt occurs, bits PC13 through PC0 are set to the vector address.

Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-

byte REF instruction which is used to reference instructions stored in the ROM.

PROGRAM STATUS WORD (PSW)

The program status word (PSW) is an 8-bit word that defines system status and program execution status and

which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW

values are mapped as follows:

(MSB)

IS1

(LSB)

ERB

SC0

FB0H

FB1H

IS0

EMB

SC1

C

SC2

The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific

bit or bits being addressed. The PSW can be addressed during program execution regardless of the current

value of the enable memory bank (EMB) flag.

Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the in-

terrupt has been processed, the PSW values are popped from the stack back to the PSW address.

When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the

carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all

cleared to logical zero.

Table 2–5. Program Status Word Bit Descriptions

PSW Bit Identifier

IS1, IS0

Description

Interrupt status flags

Enable memory bank flag

Enable register bank flag

Carry flag

Bit Addressing

Read/Write

R/W

1, 4

1

EMB

R/W

ERB

1

R/W

C

1

R/W

SC2, SC1, SC0

Program skip flags

8

R

2–17

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

INTERRUPT STATUS FLAGS (IS0, IS1)

PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1

flags directly using 1-bit RAM control instructions.

By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process

multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit

determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status

flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined

by the IPR.

When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically

incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET

instruction, IS0 and IS1 values are restored to the PSW. Table 2–6 shows the effects of IS0 and IS1 flag

settings.

Table 2–6. Interrupt Status Flag Bit Settings

IS1

Value

IS0

Value

Status of Currently

Executing Process

Effect of IS0 and IS1 Settings

on Interrupt Request Control

0

1

0

1

All interrupt requests are serviced.

Only high-priority interrupt(s) as determined in the

interrupt priority register (IPR) are serviced.

1

0

1

2

–

No more interrupt requests are serviced.

Not applicable; these bit settings are undefined.

Since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter-

rupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI in-

struction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI

instruction to re-enable interrupt processing.

+

PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing

The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:

INTB

DI

; Disable interrupt

BITR

BITS

EI

IS1

IS0

; IS1 ¬ 0

; Allow interrupts according to IPR priority level

; Enable interrupt

2–18

KS57C21516/P21516 MICROCONTROLLER

EMB FLAG (EMB)

ADDRESS SPACES

The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit

data memory addresses. In this way, it controls the addressing mode for data memory banks 0, 1, 2, or 15.

When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H–07FH of

memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", the general-purpose

areas of bank 0, 1, 2, and 15 can be accessed by using the appropriate SMB value.

+

PROGRAMMING TIP — Using the EMB Flag to Select Memory Banks

EMB flag settings for memory bank selection:

1. When EMB = "0":

SMB

LD

SMB

LD

SMB

LD

1

; Non-essential instruction since EMB = "0"

A,#9H

90H,A

34H,A

0

90H,A

34H,A

15

; (F90H) ¬ A, bank 15 is selected

; (034H) ¬ A, bank 0 is selected

; Non-essential instruction since EMB = "0"

; (F90H) ¬ A, bank 15 is selected

; (034H) ¬ A, bank 0 is selected

; Non-essential instruction, since EMB = "0"

; (020H) ¬ A, bank 0 is selected

; (F90H) ¬ A, bank 15 is selected

20H,A

90H,A

LD

2. When EMB = "1":

SMB

LD

SMB

LD

SMB

LD

1

; Select memory bank 1

A,#9H

90H,A

34H,A

0

90H,A

34H,A

15

; (190H) ¬ A, bank 1 is selected

; (134H) ¬ A, bank 1 is selected

; Select memory bank 0

; (090H) ¬ A, bank 0 is selected

; (034H) ¬ A, bank 0 is selected

; Select memory bank 15

20H,A

90H,A

; Program error, but assembler does not detect it

; (F90H) ¬ A, bank 15 is selected

LD

2–19

ADDRESS SPACES

ERB FLAG (ERB)

KS57C21516/P21516 MICROCONTROLLER

The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the

ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank

selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area,

regardless of the current value of the register bank selection register (SRB).

When an internal RESET is generated, bit 6 of program memory address 0000H is written to the ERB flag. This

automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in

program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is

executed.

During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW

bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored

interrupt are defined using VENTn instructions.

+

PROGRAMMING TIP — Using the ERB Flag to Select Register Banks

ERB flag settings for register bank selection:

1. When ERB = "0":

SRB

1

; Register bank 0 is selected (since ERB = "0", the

SRB is configured to bank 0)

; Bank 0 EA ¬ #34H

; Bank 0 HL ¬ EA

; Register bank 0 is selected

; Bank 0 YZ ¬ EA

LD

SRB

LD

SRB

LD

EA,#34H

HL,EA

2

YZ,EA

3

; Register bank 0 is selected

; Bank 0 WX ¬ EA

WX,EA

2. When ERB = "1":

SRB

LD

SRB

LD

SRB

LD

1

; Register bank 1 is selected

; Bank 1 EA ¬ #34H

EA,#34H

HL,EA

2

YZ,EA

3

; Bank 1 HL ¬ Bank 1 EA

; Register bank 2 is selected

; Bank 2 YZ ¬ BANK2 EA

; Register bank 3 is selected

; Bank 3 WX ¬ Bank 3 EA

WX,EA

2–20

KS57C21516/P21516 MICROCONTROLLER

SKIP CONDITION FLAGS (SC2, SC1, SC0)

ADDRESS SPACES

The skip condition flags SC2, SC1, and SC0 in the PSW indicate the current program skip conditions and are set

and reset automatically during program execution. Skip condition flags can only be addressed by 8-bit read

instructions. Direct manipulation of the SC2, SC1, and SC0 bits is not allowed.

CARRY FLAG (C)

The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving

a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations

involving bit-addressed data memory.

If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry

flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained

during power-down mode, but when normal operating mode resumes, its value is undefined.

The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other

bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2–7, affect the carry

flag.

Table 2–7. Valid Carry Flag Manipulation Instructions

Operation Type

Instructions

Carry Flag Manipulation

Set carry flag to "1".

Direct manipulation

SCF

RCF

CCF

Clear carry flag to "0" (reset carry flag).

Invert carry flag value (complement carry flag).

Test carry and skip if C = "1".

BTST C

(1)

Bit transfer

Load carry flag value to the specified bit.

Load contents of the specified bit to carry flag.

LDB (operand) ,C

(1)

LDB C,(operand)

(1)

Boolean manipulation

AND the specified bit with contents of carry flag and save

the result to the carry flag.

BAND C,(operand)

(1)

OR the specified bit with contents of carry flag and save

the result to the carry flag.

BOR C,(operand)

(1)

XOR the specified bit with contents of carry flag and save

the result to the carry flag.

BXOR C,(operand)

(2)

Interrupt routine

Save carry flag to stack with other PSW bits.

INTn

Return from interrupt

IRET

Restore carry flag from stack with other PSW bits.

NOTES:

1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b.

2. 'INTn' refers to the specific interrupt being executed and is not an instruction.

2–21

ADDRESS SPACES

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator

1. Set the carry flag to logic one:

SCF

; C ¬ 1

LD

ADC

EA,#0C3H

HL,#0AAH

EA,HL

; EA ¬ #0C3H

; HL ¬ #0AAH

; EA ¬ #0C3H + #0AAH + #1H, C ¬ 1

2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P5.0:

LD

H,#3H

; Set the upper four bits of the address to the H register

; value

LDB

BAND

LDB

C,@H+0FH.3

C,P3.3

P5.0,C

; C ¬ bit 3 of 3FH

; C ¬ C AND P3.3

; Output result from carry flag to P5.0

2–22

KS57C21516/P21516 MICROCONTROLLER

ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

The enable memory bank flag, EMB, controls the two addressing modes for data memory. When the EMB flag is

set to logic one, you can address the entire RAM area; when the EMB flag is cleared to logic zero, the

addressable area in the RAM is restricted to specific locations.

The EMB flag works in connection with the select memory bank instruction, SMBn. You will recall that the SMBn

instruction is used to select RAM bank 0, 1, 2, or 15. The SMB setting is always contained in the upper four bits

of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically

to the memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks

0, 1, 2, or 15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. Several RAM locations

are addressable at all times, regardless of the current EMB flag setting.

Here are a few guidelines to keep in mind regarding data memory addressing:

— When you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped

hardware component can be used as the operand in place of the actual address location.

— Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing.

— With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the

instruction specifies a register which contains the operand's address.

3–1

ADDRESSING MODES

KS57C21516/P21516 MICROCONTROLLER

ADDRESSING

MODE

DA

DA.b

@HL

@H + DA.b

@WX

@WL

mema.b memb.@L

RAM

EMB = 0

EMB = 1 EMB = 0

EMB = 1

X

AREAS

000H

WORKING

REGISTERS

01FH

020H

07FH

080H

SMB = 0

BANK 0

(GENERAL

REGISTERS

AND STACK)

0FFH

100H

BANK 1

(GENERAL

REGISTERS)

SMB =1

SMB = 1

1FFH

200H

BANK 2

(DISPLAY

REGISTERS and

GENERAL

SMB =2

SMB = 2

REGISTERS)

2FFH

F80H

FB0H

FBFH

FC0H

BANK 15

(PERIPHERAL

HARDWARE

REGISTERS)

SMB = 15

FF0H

FFFH

NOTES

1. 'X' means don't care.

2. Blank columns indicate RAM areas that are not addressable, given the addressing method

and enable memory bank (EMB) flag setting shown in the column headers.

Figure 3–1. RAM Address Structure

3–2

KS57C21516/P21516 MICROCONTROLLER

EMB AND ERB INITIALIZATION VALUES

ADDRESSING MODES

The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt

vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the

EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector

address table is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine.

When the interrupt is serviced, the EMB value is automatically saved to stack and then restored when the

interrupt routine has completed.

At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by

using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR)

despite the current SMB setting.

+

PROGRAMMING TIP — Initializing the EMB and ERB Flags

The following assembly instructions show how to initialize the EMB and ERB flag settings:

ORG

0000H

; ROM address assignment

VENT0 1,0,RESET

VENT1 0,1,INTB

VENT2 0,1,INT0

VENT3 0,1,INT1

VENT4 0,1,INTS

VENT5 0,1,INTT0

VENT6 0,1,INTT1

VENT7 0,1,INTK

; EMB ¬ 1, ERB ¬ 0; Jump to RESET address by RESET

; EMB ¬ 0, ERB ¬ 1; Jump to INTB address by INTB

; EMB ¬ 0, ERB ¬ 1; Jump to INT0 address by INT0

; EMB ¬ 0, ERB ¬ 1; Jump to INT1 address by INT1

; EMB ¬ 0, ERB ¬ 1; Jump to INTS address by INTS

; EMB ¬ 0, ERB ¬ 1; Jump to INTT0 address by INTT0

; EMB ¬ 0, ERB ¬ 1; Jump to INTT1 address by INTT1

; EMB ¬ 0, ERB ¬ 1; Jump to INTK address by INTK

•

RESET BITR

EMB

3–3

ADDRESSING MODES

KS57C21516/P21516 MICROCONTROLLER

ENABLE MEMORY BANK SETTINGS

EMB = "1"

When the enable memory bank flag EMB is set to logic one, you can address the data memory bank specified by

the select memory bank (SMB) value (0, 1, 2, or 15) using 1-, 4-, or 8-bit instructions. You can use both direct

and indirect addressing modes. The addressable RAM areas when EMB = "1" are as follows:

If SMB = 0,

If SMB = 1,

If SMB = 2,

If SMB = 15,

000H–0FFH

100H–1FFH

200H–2FFH

F80H–FFFH

EMB = "0"

When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of

the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is

used.

If EMB = "0", the addressable area is restricted to locations 000H–07FH in bank 0 and to locations F80H–FFFH

in bank 15 for direct addressing. For indirect addressing, only locations 000H–0FFH in bank 0 are addressable,

regardless of SMB value.

To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to

"1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of ROM

address 0000H.

EMB-Independent Addressing

At any time, several areas of the data memory can be addressed independent of the current status of the EMB

flag. These exceptions are described in Table 3–1.

Table 3–1. RAM Addressing Not Affected by the EMB Value

Address

Addressing Method

Affected Hardware

Program Examples

000H–0FFH

4-bit indirect addressing using WX

and WL register pairs;

Not applicable

LD

A,@WX

8-bit indirect addressing using SP

PUSH

POP

FB0H–FBFH

FF0H–FFFH

1-bit direct addressing

PSW, SCMOD,

IEx, IRQx, I/O

BITS EMB

BITR IE4

FC0H–FFFH

1-bit indirect addressing using the

L register

BSC, I/O

BTST FC3H.@L

BAND C,P3.@L

3–4

KS57C21516/P21516 MICROCONTROLLER

SELECT BANK REGISTER (SB)

ADDRESSING MODES

The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register con-

sists of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown

in Figure 3–2.

During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB

instruction. You later restore the value to the SB using the POP SB instruction.

SMB (F83H)

SMB 2 SMB 1

SRB (F82H)

SRB 1

SB

REGISTER

SMB 3

SMB 0

0

SRB 0

Figure 3–2. SMB and SRB Values in the SB Register

SELECT REGISTER BANK (SRB) INSTRUCTION

The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The

SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, 3.

One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set

using the 'SRB n' instruction. The current SRB value is retained until another register is requested by program

software. PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts

and subroutine calls. RESET clears the 4-bit SRB value to logic zero.

SELECT MEMORY BANK (SMB) INSTRUCTION

To select one of the four available data memory banks, you must execute an SMB n instruction specifying the

number of the memory bank you want (0, 1, 2, or 15). For example, the instruction 'SMB 1' selects bank 1 and

'SMB 15' selects bank 15. (And remember to enable the selected memory bank by making the appropriate EMB

flag setting).

The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not

specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB

value to logic zero.

The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack

area during interrupts and subroutine calls.

3–5

ADDRESSING MODES

KS57C21516/P21516 MICROCONTROLLER

DIRECT AND INDIRECT ADDRESSING

1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or

bit address as the instruction operand.

Indirect addressing specifies a memory location that contains the required direct address. The KS57 instruction

set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an even-numbered RAM

address must always be used as the instruction operand.

1-BIT ADDRESSING

Table 3–2. 1-Bit Direct and Indirect RAM Addressing

Operand

Notation

Addressing Mode

Description

EMB Flag Addressable

Memory

Bank

Hardware I/O

Mapping

Setting

Area

DA.b

Direct: bit is indicated by the

0

000H–07FH

F80H–FFFH

Bank 0

–

RAM address (DA), memory

bank selection, and specified

bit number (b).

Bank 15

All 1-bit

addressable

peripherals

(SMB = 15)

1

x

000H–FFFH

SMB = 0, 1,

2, 15

mema.b

Direct: bit is indicated by ad-

dressable area (mema) and

bit number (b).

FB0H–FBFH

FF0H–FFFH

Bank 15

IS0, IS1,

EMB, ERB, IEx,

IRQx, Pn.n

memb.@L

Indirect: address is indicated

by the upper 10 bits of RAM

area (memb) and the upper

two bits of register L, and bit is

indicated by the lower two bits

of register L.

x

FC0H–FFFH

Bank 15

BSCn.x

Pn.n

@H + DA.b

Indirect: bit is indicated by the

lower four bits of the address

(DA), memory bank selection,

and the H register identifier.

0

1

000H–0FFH

000H–FFFH

Bank 0

–

SMB = 0, 1,

2, 15

All 1-bit

addressable

peripherals

(SMB = 15)

NOTE: 'x' means don't care.

3–6

KS57C21516/P21516 MICROCONTROLLER

ADDRESSING MODES

+

PROGRAMMING TIP — 1-Bit Addressing Modes

1-Bit Direct Addressing

1. If EMB = "0":

AFLAG

BFLAG

CFLAG

EQU

SMB

BITS

BTST

BITS

34H.3

85H.3

0BAH.0

0

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

; 34H.3 ¬ 1

; F85H.3 ¬ 1

; If FBAH.0 = 1, skip

; Else if, FBAH.0 = 0, F85H.3 (BMOD.3) ¬

; FF3H.0 (P3.0) ¬

1

2. If EMB = "1":

AFLAG

BFLAG

CFLAG

EQU

34H.3

85H.3

0BAH.0

0

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

EQU

SMB

BITS

BTST

BITS

; 34H.3 ¬

; 85H.3 ¬

1

; If 0BAH.0 = 1, skip

; Else if 0BAH.0 = 0, 085H.3 ¬

1

; FF3H.0 (P3.0) ¬

1

3–7

ADDRESSING MODES

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — 1-Bit Addressing Modes (Continued)

1-Bit Indirect Addressing

1. If EMB = "0":

AFLAG

BFLAG

CFLAG

EQU

SMB

LD

34H.3

85H.3

0BAH.0

0

H,#0BH

@H+CFLAG

CFLAG

; H ¬ #0BH

; If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

; Else if 0BAH.0 = 0, FBAH.0 ¬

BTSTZ

BITS

1

2. If EMB = "1":

AFLAG

BFLAG

CFLAG

EQU

34H.3

85H.3

EQU

SMB

LD

BTSTZ

BITS

0BAH.0

0

H,#0BH

@H+CFLAG

CFLAG

; H ¬ #0BH

; If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

; Else if 0BAH.0 = 0, 0BAH.0 ¬

1

3–8

KS57C21516/P21516 MICROCONTROLLER

4-BIT ADDRESSING

ADDRESSING MODES

Table 3–3. 4-Bit Direct and Indirect RAM Addressing

Operand

Notation

Addressing Mode

Description

EMB Flag Addressable

Memory

Bank

Hardware I/O

Mapping

Setting

Area

0

DA

Direct: 4-bit address indicated

000H–07FH

F80H–FFFH

Bank 0

–

Bank 15

All 4-bit

addressable

peripherals

by the RAM address (DA) and

the memory bank selection

1

0

000H–FFFH

000H–0FFH

SMB = 0, 1,

2, 15

(SMB = 15)

Bank 0

–

@HL

Indirect: 4-bit address indi-

cated by the memory bank

selection and register HL

1

000H–FFFH

SMB = 0, 1,

2, 15

All 4-bit

addressable

peripherals

(SMB = 15)

x

000H–0FFH

Bank 0

–

@WX

@WL

Indirect: 4-bit address indi-

cated by register WX

Indirect: 4-bit address indi-

cated by register WL

NOTE: 'x' means don't care.

+

PROGRAMMING TIP — 4-Bit Addressing Modes

4-Bit Direct Addressing

1. If EMB = "0":

ADATA

BDATA

EQU

SMB

LD

SMB

LD

46H

8EH

15

A,P3

0

; Non-essential instruction, since EMB = "0"

; A ¬ (P3)

; Non-essential instruction, since EMB = "0"

ADATA,A

BDATA,A

; (046H) ¬

A

LD

; (F8EH (LCON)) ¬

A

2. If EMB = "1":

ADATA

BDATA

EQU

46H

8EH

15

A,P3

0

EQU

SMB

LD

SMB

LD

; A ¬ (P3)

ADATA,A

BDATA,A

; (046H) ¬

; (08EH) ¬

A

LD

3–9

ADDRESSING MODES

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — 4-Bit Addressing Modes (Continued)

4-Bit Indirect Addressing (Example 1)

1. If EMB = "0", compare bank 0 locations 040H–046H with bank 0 locations 060H–066H:

ADATA

BDATA

EQU

SMB

LD

CPSE

SRET

DECS

JR

46H

66H

1

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

; Non-essential instruction, since EMB = "0"

COMP

; A ¬ bank 0 (040H–046H)

; If bank 0 (060H–066H) = A, skip

L

COMP

RET

2. If EMB = "1", compare bank 0 locations 040H–046H to bank 1 locations 160H–166H:

ADATA

BDATA

EQU

SMB

LD

CPSE

SRET

DECS

JR

46H

66H

1

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

COMP

; A ¬ bank 0 (040H–046H)

; If bank 1 (160H–166H) = A, skip

L

COMP

RET

3–10

KS57C21516/P21516 MICROCONTROLLER

ADDRESSING MODES

+

PROGRAMMING TIP — 4-Bit Addressing Modes (Concluded)

4-Bit Indirect Addressing (Example 2)

1. If EMB = "0", exchange bank 0 locations 040H–046H with bank 0 locations 060H–066H:

ADATA

BDATA

EQU

SMB

LD

46H

66H

1

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

TRANS

; Non-essential instruction, since EMB = "0"

TRANS

; A ¬ bank 0 (040H–046H)

; Bank 0 (060H–066H) « A

XCHD

JR

2. If EMB = "1", exchange bank 0 locations 040H–046H to bank 1 locations 160H–166H:

ADATA

BDATA

EQU

SMB

LD

46H

66H

1

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

TRANS

; A ¬ bank 0 (040H–046H)

; Bank 1 (160H–166H) «

XCHD

JR

A

3–11

ADDRESSING MODES

8-BIT ADDRESSING

KS57C21516/P21516 MICROCONTROLLER

Table 3–4. 8-Bit Direct and Indirect RAM Addressing

Instruction

Notation

Addressing Mode

Description

EMB Flag

Setting

Addressable

Area

Memory

Bank

Hardware I/O

Mapping

DA

Direct: 8-bit address indicated

0

000H–07FH

F80H–FFFH

Bank 0

–

by the RAM address (DA =

even number) and memory

bank selection

Bank 15

All 8-bit

addressable

peripherals

1

0

000H–FFFH

000H–0FFH

SMB = 0, 1,

2, 15

(SMB = 15)

@HL

Indirect: the 8-bit address indi-

cated by the memory bank

selection and register HL; (the

4-bit L register value must be

an even number)

Bank 0

–

1

000H–FFFH

SMB = 0, 1,

2, 15

All 8-bit

addressable

peripherals

(SMB = 15)

+

PROGRAMMING TIP — 8-Bit Addressing Modes

8-Bit Direct Addressing

1. If EMB = "0":

ADATA

BDATA

EQU

SMB

LD

SMB

LD

46H

8EH

15

EA,P4

0

; Non-essential instruction, since EMB = "0"

; E ¬ (P5), A ¬ (P4)

ADATA,EA

BDATA,EA

; (046H) ¬ A, (047H) ¬

; (F8EH) ¬ A, (F8FH) ¬

E

LD

2. If EMB = "1":

ADATA

BDATA

EQU

46H

8EH

15

EA,P4

0

EQU

SMB

LD

SMB

LD

; E ¬ (P5), A ¬ (P4)

ADATA,EA

BDATA,EA

; (046H) ¬ A, (047H) ¬

; (08EH) ¬ A, (08FH) ¬

E

LD

3–12

KS57C21516/P21516 MICROCONTROLLER

ADDRESSING MODES

+

PROGRAMMING TIP — 8-Bit Addressing Modes (Continued)

8-Bit Indirect Addressing

1. If EMB = "0":

ADATA

EQU

SMB

LD

46H

1

HL,#ADATA

EA,@HL

; Non-essential instruction, since EMB = "0"

; A ¬ (046H), E ¬ (047H)

LD

2. If EMB = "1":

ADATA EQU

46H

SMB

LD

1

HL,#ADATA

EA,@HL

; A ¬ (146H), E ¬ (147H)

3–13

ADDRESSING MODES

KS57C21516/P21516 MICROCONTROLLER

NOTES

3–14

KS57C21516/P21516 MICROCONTROLLER

ADDRESSING MODES

3–15

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

4

MEMORY MAP

OVERVIEW

To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank

15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the

specific memory location.

Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank

flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the

current SMB value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless

of the current EMB value.

I/O MAP FOR HARDWARE REGISTERS

Table 4–1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations

F80H–FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map

gives you the following information:

— Register address

— Register name (mnemonic for program addressing)

— Bit values (both addressable and non-manipulable)

— Read-only, write-only, or read and write addressability

— 1-bit, 4-bit, or 8-bit data manipulation characteristics

4–1

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

Table 4–1. I/O Map for Memory Bank 15

Memory Bank 15

Addressing Mode

Address

F80H

Register

Bit 3

.3

Bit 2

.2

Bit 1

.1

Bit 0

"0"

R/W

1-Bit

4-Bit

8-Bit

SP

R/W

No

Yes

F81H

.7

.6

.5

.4

Locations F82H–F84H are not mapped.

F85H

F86H

F87H

F88H

F89H

BMOD

BCNT

.3

.2

.1

.0

W

R

.3

Yes

No

Yes

(1)

WMOD

.3

.7

.2

.1

.5

.0

.4

W

No

Yes

.3

"0"

Locations F8AH–F8BH are not mapped.

F8CH

F8DH

F8EH

LMOD

LCON

.3

.7

.2

.6

.2

.1

.5

.1

.0

.4

.0

W

No

.3

No

Yes

No

Yes

No

"0"

W

Locations F8FH is not mapped.

F90H

F91H

F92H

TMOD0

.3

"0"

.2

.6

"0"

.5

"0"

.4

W

Yes

No

TOE1

TOE0

"U"

"0"

R/W

R

Yes

No

.3

Yes

No

Locations F93H is not mapped.

F94H

F95H

F96H

F97H

F98H

F99H

F9AH

TCNT0

TREF0

Yes

No

W

No

WDMOD

.3

.7

.2

.6

.1

.5

.0

.4

W

No

(2)

WDTCF

"0"

W

Yes

No

WDFLAG

TMOD1

Locations F9BH–F9FH are not mapped.

FA0H

FA1H

.3

.2

.6

"0"

.5

"0"

.4

W

.3

Yes

"0"

Locations FA2H–FA3H are not mapped.

R

FA4H

FA5H

FA6H

FA7H

TCNT1A

TCNT1B

No

Yes

4–2

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

Table 4–1. I/O Map for Memory Bank 15 (Continued)

Memory Bank 15

Bit 3 Bit 2

Addressing Mode

Address

FA8H

Register

Bit 1

Bit 0

R/W

1-Bit

4-Bit

8-Bit

TREF1A

W

No

Yes

FA9H

FAAH

FABH

TREF1B

PSW

Locations FACH–FAFH are not mapped.

FB0H

FB1H

FB2H

FB3H

FB4H

FB5H

FB6H

FB7H

FB8H

IS1

(3)

IS0

SC2

.2

EMB

SC1

.1

ERB

SC0

.0

R/W

R

Yes

No

Yes

No

Yes

C

IPR

IME

.3

W

IME

No

Yes

No

PCON

IMOD0

IMOD1

IMODK

SCMOD

.2

.1

.0

W

"0"

.3

"0"

.2

.1

.0

W

No

"0"

.1

.0

W

No

.0

W

No

.2

"0"

IEB

.0

W

Yes

IE4

IRQ4

IRQB

R/W

Yes

Locations FB9H is not mapped.

FBAH

FBBH

FBCH

FBDH

FBEH

FBFH

FC0H

FC1H

FC2H

FC3H

"0"

IEK

"0"

IRQK

"0"

IEW

IET1

IET0

IES

IRQW

IRQT1

IRQT0

IRQS

IRQ0

R/W

Yes

No

"0"

IE1

"0"

IRQ1

"0"

IE0

IE2

IRQ2

BSC0

BSC1

BSC2

BSC3

R/W

Yes

Locations FC4H–FCFH are not mapped.

4–3

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

Table 4–1. I/O Map for Memory Bank 15 (Continued)

Memory Bank 15

Addressing Mode

Address

Register

Bit 3

Bit 2

Bit 1

Bit 0

R/W

1-Bit

4-Bit

8-Bit

FD0H

CLMOD

.3

"0"

.1

.0

W

No

.3

Yes

No

Yes

No

Locations FD1H–FD5H are not mapped.

FD6H

FD7H

FD8H

PNE1

PNE2

.3

"0"

.3

.2

.6

.2

.1

.5

.1

.0

.4

.0

W

No

Yes

No

Locations FD9H is not mapped.

"0" "0" .0

Locations FDBH is not mapped.

FDAH

IMOD2

PUMOD1

PUMOD2

SMOD

"0"

W

No

FDCH

FDDH

FDEH

PUR3

PUR7

"0"

PUR2

PUR6

"0"

PUR1

PUR5

PUR9

PUR0

PUR4

PUR8

Yes

No

Yes

No

Locations FDFH is not mapped.

FE0H

FE1H

.3

.7

.2

.6

.1

.5

.0

W

Yes

"0"

Locations FE2H–FE3H are not mapped.

R/W

FE4H

FE5H

FE6H

FE7H

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

FEEH

FEFH

SBUF

PMG1

PMG2

PMG3

PMG4

PMG5

No

Yes

PM0.3

"0"

PM0.2

PM2.2

PM3.2

"0"

PM0.1

PM2.1

PM3.1

"0"

PM0.0

PM2.0

PM3.0

"0"

W

PM3.3

"0"

PM4.3

PM5.3

PM6.3

PM7.3

PM8.3

PM9.3

PM4.2

PM5.2

PM6.2

PM7.2

PM8.2

PM9.2

PM4.1

PM5.1

PM6.1

PM7.1

PM8.1

PM9.1

PM4.0

PM5.0

PM6.0

PM7.0

PM8.0

PM9.0

4–4

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

Table 4–1. I/O Map for Memory Bank 15 (Concluded)

Memory Bank 15

Addressing Mode

Address

FF0H

FF1H

FF2H

FF3H

FF4H

FF5H

FF6H

FF7H

FF8H

FF9H

Register

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Bit 3

.3

Bit 2

.2

Bit 1

.1

Bit 0

.0

R/W

R

1-Bit

4-Bit

8-Bit

Yes

No

.3

.2

.1

.0

"0"

.2

.1

.0

R/W

.3

.2

.1

.0

.3

.2

.1

.0

Yes

.3 / .7

.3

.2 / .6

.2

.1 / .5

.1

.0 / .4

.0

R/W

.3 / .7

.3

.2 / .6

.2

.1 / .5

.1

.0 / .4

.0

.3 / .7

.2 / .6

.1 / .5

.0 / .4

NOTES:

1. Bit 3 in the WMOD register is read only.

2. F9AH.0, F9AH.1 and F9AH.2 are fixed to "0".

3. The carry flag can be read or written by specific bit manipulation instructions only.

4. The “U” means that the bit is undefined.

4–5

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

REGISTER DESCRIPTIONS

In this section, register descriptions are presented in a consistent format to familiarize you with the memory-

mapped I/O locations in bank 15 of the RAM. Figure 4–1 describes features of the register description format.

Register descriptions are arranged in alphabetical order. Programmers can use this section as a quick-reference

source when writing application programs.

Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are

not included in these descriptions. More detailed information about how these registers are used is included in

Part II of this manual, "Hardware Descriptions," in the context of the corresponding peripheral hardware module

descriptions.

4–6

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

Register and bit IDs

used for bit addressing

Name of individual

bit or related bits

Register location

Associated

in RAM bank 15

Register ID

hardware module

Register name

CPU

CLMOD Clock Output Mode Control Register

FD0H

-

Bit

3

2

1

0

Identifier

.3

.2

.1

.0

RESET

Value

0

W

4

0

W

4

0

W

4

0

W

4

Read/Write

Bit Addressing

CLMOD.3

Enable/Disable Clock Output Control Bit

0

1

Disable clock output at the CLO pin

Enable clock output at the CLO pin

CLMOD.2

Bit 2

Always logic zero

0

CLMOD.1 - .0

Clock Source and Frequency Selection Control Bits

0

1

0 Select CPU clock source fx/4, fx/8, fx/64 (1.05 MHz, 524kHz,or 65.5kHz), or fxt/4

1 Select system clock fxx/8 (524 kHz at 4.19 MHz)

Select system clock fxx/16 (262 kHz at 4.19 MHz)

0

1 Select system clock fxx/64 (65.5 kHz at 4.19 MHz)

R = Read-only

W = Write-only

Bit value immediately

RESET

Bit number in

MSB to LSB order

after a

R/W = Read/write

Type of addressing

that must be used to

address the bit

Description of the

effect of specific bit

settin gs

Bit identifier used

for bit addressing

(1-bit, 4-bit, or 8-bit)

Figure 4–1. Register Description Format

4–7

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

BMOD— Basic Timer Mode Register

BT

F85H

Bit

3

.3

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

0

W

1/4

W

4

W

4

W

4

BMOD.3

Basic Timer Restart Bit

Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero

1

BMOD.2 – .0

Input Clock Frequency and Interrupt Interval Time

12

0

1

0

1

0

1

0

1

Input clock frequency:

Interrupt interval time (wait time)

fxx / 2 (1.02 kHz)

2

20

/ fxx (250 ms)

9

Input clock frequency:

Interrupt interval time (wait time)

fxx / 2 (8.18 kHz)

17

2

/ fxx (31.3 ms)

7

Input clock frequency:

Interrupt interval time (wait time)

fxx / 2 (32.7 kHz)

15

2

/ fxx (7.82 ms)

5

Input clock frequency:

Interrupt interval time (wait time)

fxx / 2 (131 kHz)

13

2

/ fxx (1.95 ms)

NOTES:

1. When a RESET occurs, the oscillator stabilization wait time is 31.3 ms (2¹⁷/fxx) at 4.19 MHz.

2. 'fxx' is the system clock rate given a clock frequency of 4.19 MHz.

4–8

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

CLMOD — Clock Output Mode Register

CPU

FD0H

Bit

3

.3

0

2

"0"

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

W

4

CLMOD.3

Enable/Disable Clock Output Control Bit

0

1

Disable clock output at the CLO pin

Enable clock output at the CLO pin

CLMOD.2

Bit 2

0

Always logic zero

CLMOD.1 – .0

Clock Source and Frequency Selection Control Bits

0

Select CPU clock source fx/4, fx/8, fx/64 (1.05 MHz, 524 kHz, or 65.5

kHz) or fxt/4

0

1

0

1

Select system clock fxx/8 (524 kHz)

Select system clock fxx/16 (262 kHz)

Select system clock fxx/64 (65.5 kHz)

NOTE: 'fxx' is the system clock, given a clock frequency of 4.19 MHz.

4–9

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

IE0, 1, IRQ0, 1— INT0, 1 Interrupt Enable/Request Flags

CPU

FBEH

Bit

3

IE1

0

2

IRQ1

0

1

IE0

0

IRQ0

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

IE1

INT1 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT1 pin

Enable interrupt requests at the INT1 pin

IRQ1

IE0

INT1 Interrupt Request Flag

–

Generate INT1 interrupt (This bit is set and cleared by hardware when rising or

falling edge detected at INT1 pin.)

INT0 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT0 pin

Enable interrupt requests at the INT0 pin

IRQ0

INT0 Interrupt Request Flag

–

Generate INT0 interrupt (This bit is set and cleared automatically by hardware

when rising or falling edge detected at INT0 pin.)

4–10

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

IE2, IRQ2— INT2 Interrupt Enable/Request Flags

CPU

FBFH

Bit

3

"0"

0

2

"0"

0

1

IE2

0

IRQ2

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

.3 – .2

IE2

Bits 3–2

0

Always logic zero

INT2 Interrupt Enable Flag

0

1

Disable INT2 interrupt requests at the INT2 pin

Enable INT2 interrupt requests at the INT2 pin

IRQ2

INT2 Interrupt Request Flag

–

Generate INT2 quasi-interrupt (This bit is set and is not cleared automatically

by hardware when a rising or falling edge is detected at INT2. Since INT2 is a

quasi-interrupt, IRQ2 flag must be cleared by software.)

4–11

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

IE4, IRQ4— INT4 Interrupt Enable/Request Flags

IEB, IRQB— INTB Interrupt Enable/Request Flags

CPU

FB8H

Bit

3

IE4

0

2

IRQ4

0

1

IEB

0

IRQB

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

IE4

INT4 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT4 pin

Enable interrupt requests at the INT4 pin

IRQ4

IEB

INT4 Interrupt Request Flag

–

Generate INT4 interrupt (This bit is set and cleared automatically by hardware

when rising and falling signal edge detected at INT4 pin.)

INTB Interrupt Enable Flag

0

1

Disable INTB interrupt requests

Enable INTB interrupt requests

IRQB

INTB Interrupt Request Flag

–

Generate INTB interrupt (This bit is set and cleared automatically by hardware

when reference interval signal received from basic timer.)

4–12

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

IES, IRQS— INTS Interrupt Enable/Request Flags

CPU

FBDH

Bit

3

"0"

0

2

"0"

0

1

IES

0

IRQS

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

.3 – .2

IES

Bits 3–2

0

Always logic zero

INTS Interrupt Enable Flag

0

1

Disable INTS interrupt requests

Enable INTS interrupt requests

IRQS

INTS Interrupt Request Flag

–

Generate INTS interrupt (This bit is set and cleared automatically by hardware

when serial data transfer completion signal received from serial I/O interface.)

4–13

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

IET0, IRQT0— INTT0 Interrupt Enable/Request Flags

CPU

FBCH

Bit

3

"0"

0

2

"0"

0

1

IET0

0

IRQT0

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

.3 – .2

IET0

Bits 3–2

0

Always logic zero

INTT0 Interrupt Enable Flag

0

1

Disable INTT0 interrupt requests

Enable INTT0 interrupt requests

IRQT0

INTT0 Interrupt Request Flag

–

Generate INTT0 interrupt (This bit is set and cleared automatically by

hardware when contents of TCNT0 and TREF0 registers match.)

4–14

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

IET1, IRQT1— INTT1 Interrupt Enable/Request Flags

IEK, IRQK— INTK Interrupt Enable/Request Flags

CPU

FBBH

Bit

3

IEK

0

2

IRQK

0

1

IET1

0

IRQT1

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

IEK

INTK Interrupt Enable Flag

0

1

Disable interrupt requests at the K0–K7 pins

Enable interrupt requests at the K0–K7 pins

IRQK

IET1

INTK Interrupt Request Flag

–

Generate INTK interrupt (This bit is set and cleared automatically by hardware

when rising or falling edge detected at K0–K7 pins.)

INTT1 Interrupt Enable Flag

0

1

Disable INTT1 interrupt requests

Enable INTT1 interrupt requests

IRQT1

INTT1 Interrupt Request Flag

–

Generate INTT1 interrupt (This bit is set and cleared automatically by

hardware when contents of TCNT1 and TREF1 registers match.)

4–15

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

IEW, IRQW— INTW Interrupt Enable/Request Flags

CPU

FBAH

Bit

3

"0"

0

2

"0"

0

1

IEW

0

IRQW

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

.3 – .2

IEW

Bits 3–2

0

Always logic zero

INTW Interrupt Enable Flag

0

1

Disable INTW interrupt requests

Enable INTW interrupt requests

IRQW

INTW Interrupt Request Flag

–

Generate INTW interrupt (This bit is set when the timer interval is set to 0.5

seconds or 3.91 milliseconds.)

NOTE: Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software.

4–16

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

IMOD0— External Interrupt 0 (INT0) Mode Register

CPU

FB4H

Bit

3

"0"

0

2

"0"

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

W

4

IMOD0.3 – .2

IMOD0.1 – .0

Bits 3– 2

0

Always logic zero

External Interrupt Mode Control Bits

0

1

0

1

0

1

Interrupt request is triggered by a rising signal edge

Interrupt request is triggered by a falling signal edge

Interrupt request is triggered by both rising and falling signal edges

Interrupt request flag (IRQ0) cannot be set to logic one

4–17

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

IMOD1— External Interrupt 1 (INT1) Mode Register

CPU

FB5H

Bit

3

"0"

0

2

"0"

0

1

"0"

0

Identifier

IMOD1.0

RESET Value

Read/Write

Bit Addressing

0

W

4

W

4

W

4

W

4

IMOD1.3 – .1

IMOD1.0

Bits 3–1

0

Always logic zero

External Interrupt 1 Edge Detection Control Bit

0

1

Rising edge detection

Falling edge detection

4–18

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

IMOD2— External Interrupt 2 (INT2) Mode Register

CPU

FDAH

Bit

3

"0"

0

2

"0"

0

1

"0"

0

Identifier

IMOD2.0

RESET Value

Read/Write

Bit Addressing

0

W

4

W

4

W

4

W

4

IMOD2.3 – .1

IMOD2.0

Bits 3–1

0

Always logic zero

External Interrupt 2 Edge Detection Selection Bit

0

1

Interrupt request at INT2 pin trigged by rising edge

Interrupt request at INT2 pin trigged by falling edge

4–19

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

IMODK— External Key Interrupt Mode Register

CPU

FB6H

Bit

3

"0"

0

2

1

0

Identifier

IMODK.2 IMODK.1 IMODK.0

RESET Value

Read/Write

Bit Addressing

0

W

4

0

W

4

0

W

4

W

4

IMODK.3

IMODK.2

Bit 3

0

Always logic zero

External Key Interrupt Edge Detection Selection Bit

0

1

Falling edge detection

Rising edge detection

IMODK.1 – .0

External Key Interrupt Mode Control Bits

0

1

0

1

0

1

Disable key interrupt

Enable edge detection at K0–K3 pins

Enable edge detection at K4–K7 pins

Enable edge detection at K0–K7 pins

NOTES:

1. To generate a key interrupt, all of the selected pins must be configured to input mode. If any one of the selected pins

is configured to output mode, only falling edge can be detected.

2. To generate a key interrupt, all of the selected pins must be at input high state for falling edge detection, or all of the

selected pins must be at input low state for rising edge detection. If any one of them or more is at input low state or

input high state, the interrupt may be not occurred at falling edge or rising edge.

3. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select edge

detection and pins by setting IMODK register.

4–20

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

IPR— Interrupt Priority Register

CPU

FB2H

Bit

3

IME

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

1/4

IME

Interrupt Master Enable Bit

0

1

Disable all interrupt processing

Enable processing for all interrupt service requests

IPR.2 – .0

Interrupt Priority Assignment Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Process all interrupt requests at low priority

Only INTB and INT4 interrupts are at high priority

Only INT0 interrupt is at high priority

Only INT1 interrupt is at high priority

Only INTS interrupt is at high priority

Only INTT0 interrupt is at high priority

Only INTT1 interrupt is at high priority

Only INTK interrupt is at high priority

4–21

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

LCON— LCD Output Control Register

LCD

F8EH

Bit

3

"0"

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

W

4

LCON.3

LCON.2

Bit 3

0

Always logic zero

LCD Clock Output Disable/Enable Bit

0

1

Disable LCDCK and LCDSY signal outputs.

Enable LCDCK and LCDSY signal outputs.

LCON.1 – .0

LCD Output Control Bit

0

1

0

1

0

1

LCD display off; cut off current to dividing resistor

LCD display on; application without contrast control

LCD display on; application with contrast control

LCD dispaly on; application without contrast control

NOTES:

1. The function of LCON.0 is applied in case of using the internal GND for LCD power; the function of LCON.1

is used for contrast control application.

2. The table for LCON.1–LCON.0 also shows the case that internal bias resistors are built-in by mask option. For the

case that external bias resistors are configured by mask option, refer to Chapter 12.

4–22

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

LMOD— LCD Mode Register

LCD

F8DH, F8CH

Bit

3

.7

0

2

.6

0

1

.5

0

.4

0

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

LMOD.7 – .5

LCD Output Segment and Pin Configuration Bits

0

1

0

1

0

1

0

1

0

Segments 40–43, 44–47, 48–51 and 52–55

Segments 40–43, 44–47 and 48–51; normal I/O at port 6

Segments 40–43 and 44–47; normal I/O at port 6 and port 7

Segments 40–43; normal I/O at ports 6, 7 and 8

Normal I/O at ports 6, 7, 8 and 9

NOTE: Segment pins that also can used for normal I/O should be configured to output mode

when the SEG function is used.

LMOD.4 – .3

LCD Clock (LCDCK) Frequency Selection Bits

7

6

0

1

0

1

0

1

When 1/8 duty: fxx / 2 (256 Hz); when 1/16 duty: fxx / 2 (512 Hz)

6

5

When 1/8 duty: fxx/ 2 (512 Hz); when 1/16 duty: fxx / 2 (1024 Hz)

5

4

When 1/8 duty: fxx / 2 (1024 Hz); when 1/16 duty: fxx / 2 (2048 Hz)

4

3

When 1/8 duty: fxx / 2 (2048 Hz); when 1/16 duty: fxx / 2 (4096 Hz)

NOTE: LCDCK is supplied only when the watch timer operates. To use the LCD controller,

bit 2 in the watch mode register WMOD should be set to 1.

LMOD.2

LCD Duty and Selection Bits

0

1

1/8 duty (COM0–COM7 select)

1/16 duty (COM0–COM15 select)

NOTE: When 1/16 duty is selected, ports 4 and 5 should be configured as output mode;

when 1/8 duty is selected, ports 4 and 5 can be used as normal I/O ports.

LMOD.1 – .0

LCD Display Mode Selection Bits

0

1

0

1

All LCD dots off

All LCD dots on

Normal display

4–23

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

PCON— Power Control Register

CPU

FB3H

Bit

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

W

4

PCON.3 – .2

PCON.1 – .0

CPU Operating Mode Control Bits

0

1

0

1

0

Enable normal CPU operating mode

Initiate idle power-down mode

Initiate stop power-down mode

CPU Clock Frequency Selection Bits

0

1

0

1

If SCMOD.0 = "0", fx/64; if SCMOD.0 = "1", fxt/4

If SCMOD.0 = "0", fx/8; if SCMOD.0 = "1", fxt/4

If SCMOD.0 = "0", fx/4; if SCMOD.0 = "1", fxt/4

NOTE: 'fx' is the main system clock; 'fxt' is the subsystem clock.

4–24

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

PMG1 — Port I/O Mode Register 1 (Group 1: Ports 0, 2)

I/O

FE7H, FE6H

Bit

7

"0"

0

6

5

4

3

2

1

0

Identifier

PM2.2

PM2.1

PM2.0

PM0.3

PM0.2

PM0.1

PM0.0

RESET Value

Read/Write

Bit Addressing

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

W

8

.7

Bit 7

0

Always logic zero

PM2.2

P2.2 I/O Mode Selection Flag

0

1

Set P2.2 to input mode

Set P2.2 to output mode

PM2.1

PM2.0

PM0.3

PM0.2

PM0.1

PM0.0

P2.1 I/O Mode Selection Flag

0

1

Set P2.1 to input mode

Set P2.1 to output mode

P2.0 I/O Mode Selection Flag

0

1

Set P2.0 to input mode

Set P2.0 to output mode

P0.3 I/O Mode Selection Flag

0

1

Set P0.3 to input mode

Set P0.3 to output mode

P0.2 I/O Mode Selection Flag

0

1

Set P0.2 to input mode

Set P0.2 to output mode

P0.1 I/O Mode Selection Flag

0

1

Set P0.1 to input mode

Set P0.1 to output mode

P0.0 I/O Mode Selection Flag

0

1

Set P0.0 to input mode

Set P0.0 to output mode

4–25

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

PMG2 — Port I/O Mode Register 2 (Group 2: Port 3)

I/O

FE9H, FE8H

Bit

7

"0"

0

6

"0"

0

5

"0"

0

4

"0"

0

3

2

1

0

Identifier

PM3.3

PM3.2

PM3.1

PM3.0

RESET Value

Read/Write

Bit Addressing

0

W

8

0

W

8

0

W

8

0

W

8

W

8

W

8

W

8

W

8

.7 – .4

PM3.3

Bits 7 – 4

0

Always logic zero

P3.3 I/O Mode Selection Flag

0

1

Set P3.3 to input mode

Set P3.3 to output mode

PM3.2

PM3.1

PM3.0

P3.2 I/O Mode Selection Flag

0

1

Set P3.2 to input mode

Set P3.2 to output mode

P3.1 I/O Mode Selection Flag

0

1

Set P3.1 to input mode

Set P3.1 to output mode

P3.0 I/O Mode Selection Flag

0

1

Set P3.0 to input mode

Set P3.0 to output mode

4–26

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

PMG3 — Port I/O Mode Register 3 (Group 3: Ports 4, 5)

I/O

FEBH, FEAH

Bit

7

6

5

4

3

2

1

0

Identifier

PM5.3

PM5.2

PM5.1

PM5.0

PM4.3

PM4.2

PM4.1

PM4.0

RESET Value

Read/Write

Bit Addressing

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

PM5.3

P5.3 I/O Mode Selection Flag

0

1

Set P5.3 to input mode

Set P5.3 to output mode

PM5.2

PM5.1

P5.2 I/O Mode Selection Flag

0

1

Set P5.2 to input mode

Set P5.2 to output mode

P5.1 I/O Mode Selection Flag

0

1

Set P5.1 to input mode

Set P5.1 to output mode

PM5.0

PM4.3

PM4.2

PM4.1

PM4.0

P5.0 I/O Mode Selection Flag

0

1

Set P5.0 to input mode

Set P5.0 to output mode

P4.3 I/O Mode Selection Flag

0

1

Set P4.3 to input mode

Set P4.3 to output mode

P4.2 I/O Mode Selection Flag

0

1

Set P4.2 to input mode

Set P4.2 to output mode

P4.1 I/O Mode Selection Flag

0

1

Set P4.1 to input mode

Set P4.1 to output mode

P4.0 I/O Mode Selection Flag

0

1

Set P4.0 to input mode

Set P4.0 to output mode

4–27

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

PMG4 — Port I/O Mode Register 4 (Group 4: Ports 6, 7)

I/O

FEDH, FECH

Bit

7

6

5

4

3

2

1

0

Identifier

PM7.3

PM7.2

PM7.1

PM7.0

PM6.3

PM6.2

PM6.1

PM6.0

RESET Value

Read/Write

Bit Addressing

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

PM7.3

P7.3 I/O Mode Selection Flag

0

1

Set P7.3 to input mode

Set P7.3 to output mode

PM7.2

PM7.1

PM7.0

PM6.3

PM6.2

PM6.1

PM6.0

P7.2 I/O Mode Selection Flag

0

1

Set P7.2 to input mode

Set P7.2 to output mode

P7.1 I/O Mode Selection Flag

0

1

Set P7.1 to input mode

Set P7.1 to output mode

P7.0 I/O Mode Selection Flag

0

1

Set P7.0 to input mode

Set P7.0 to output mode

P6.3 I/O Mode Selection Flag

0

1

Set P6.3 to input mode

Set P6.3 to output mode

P6.2 I/O Mode Selection Flag

0

1

Set P6.2 to input mode

Set P6.2 to output mode

P6.1 I/O Mode Selection Flag

0

1

Set P6.1 to input mode

Set P6.1 to output mode

P6.0 I/O Mode Selection Flag

0

1

Set P6.0 to input mode

Set P6.0 to output mode

4–28

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

PMG5 — Port I/O Mode Register 5 (Group 5: Ports 8, 9)

I/O

FEFH, FEEH

Bit

7

6

5

4

3

2

1

0

Identifier

PM9.3

PM9.2

PM9.1

PM9.0

PM8.3

PM8.2

PM8.1

PM8.0

RESET Value

Read/Write

Bit Addressing

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

PM9.3

PM9.2

PM9.1

PM9.0

P9.3 I/O Mode Selection Flag

0

1

Set P9.3 to input mode

Set P9.3 to output mode

P9.2 I/O Mode Selection Flag

0

1

Set P9.2 to input mode

Set P9.2 to output mode

P9.1 I/O Mode Selection Flag

0

1

Set P9.1 to input mode

Set P9.1 to output mode

P9.0 I/O Mode Selection Flag

0

1

Set P9.0 to input mode

Set P9.0 to output mode

PM8.3

PM8.2

PM8.1

P8.3 I/O Mode Selection Flag

0

1

Set P8.3 to input mode

Set P8.3 to output mode

P8.2 I/O Mode Selection Flag

0

1

Set P8.2 to input mode

Set P8.2 to output mode

P8.1 I/O Mode Selection Flag

0

1

Set P8.1 to input mode

Set P8.1 to output mode

PM8.0

P8.0 I/O Mode Selection Flag

0

1

Set P8.0 to input mode

Set P8.0 to output mode

4–29

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

PNE1 — N-Channel Open-Drain Mode Register 1

I/O

FD7H, FD6H

Bit

7

"0"

0

6

5

4

3

2

1

0

Identifier

PNE1.6 PNE1.5 PNE1.4 PNE1.3 PNE1.2 PNE1.1 PNE1.0

RESET Value

Read/Write

Bit Addressing

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

W

8

.7

Bit 7

0

Always logic 0

PNE1.6

P2.2 N-Channel Open-Drain Configurable Bit

0

1

Configure P2.2 as a push-pull

Configure P2.2 as a n-channel open-drain

PNE1.5

P2.1 N-Channel Open-Drain Configurable Bit

0

1

Configure P2.1 as a push-pull

Configure P2.1 as a n-channel open-drain

PNE1.4

PNE1.3

PNE1.2

PNE1.1

PNE1.0

P2.0 N-Channel Open-Drain Configurable Bit

0

1

Configure P2.0 as a push-pull

Configure P2.0 as a n-channel open-drain

P0.3 N-Channel Open-Drain Configurable Bit

0

1

Configure P0.3 as a push-pull

Configure P0.3 as a n-channel open-drain

P0.2 N-Channel Open-Drain Configurable Bit

0

1

Configure P0.2 as a push-pull

Configure P0.2 as a n-channel open-drain

P0.1 N-Channel Open-Drain Configurable Bit

0

1

Configure P0.1 as a push-pull

Configure P0.1 as a n-channel open-drain

P0.0 N-Channel Open-Drain Configurable Bit

0

1

Configure P0.0 as a push-pull

Configure P0.0 as a n-channel open-drain

4–30

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

PNE2 — N-Channel Open-Drain Mode Register 2

I/O

FD8H

Bit

3

2

1

0

Identifier

PNE2.3 PNE2.2 PNE2.1 PNE2.0

RESET Value

Read/Write

Bit Addressing

0

W

4

0

W

4

0

W

4

0

W

4

PNE2.3

PNE2.2

PNE2.1

PNE2.0

P3.3 N-Channel Open-Drain Configurable Bit

0

1

Configure P3.3 as a push-pull

Configure P3.3 as a n-channel open-drain

P3.2 N-Channel Open-Drain Configurable Bit

0

1

Configure P3.2 as a push-pull

Configure P3.2 as a n-channel open-drain

P3.1 N-Channel Open-Drain Configurable Bit

0

1

Configure P3.1 as a push-pull

Configure P3.1 as a n-channel open-drain

P3.0 N-Channel Open-Drain Configurable Bit

0

1

Configure P3.0 as a push-pull

Configure P3.0 as a n-channel open-drain

4–31

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

PSW— Program Status Word

CPU

FB1H, FB0H

Bit

7

C

6

SC2

0

5

SC1

0

4

SC0

0

3

IS1

0

2

IS0

0

1

0

Identifier

EMB

0

ERB

0

RESET Value

Read/Write

Bit Addressing

(1)

R/W

(2)

R

R/W

1/4/8

R/W

1/4/8

R/W

1/4/8

R/W

1/4/8

8

C

Carry Flag

0

1

No overflow or borrow condition exists

An overflow or borrow condition does exist

SC2 – SC0

IS1, IS0

Skip Condition Flags

0

1

No skip condition exists; no direct manipulation of these bits is allowed

A skip condition exists; no direct manipulation of these bits is allowed

Interrupt Status Flags

0

1

Service all interrupt requests

Service only the high-priority interrupt(s) as determined in the interrupt

priority register (IPR)

1

0

1

Do not service any more interrupt requests

Undefined

EMB

ERB

Enable Data Memory Bank Flag

0

Restrict program access to data memory to bank 15 (F80H–FFFH) and to

the locations 000H–07FH in the bank 0 only

1

Enable full access to data memory banks 0, 1, 2, and 15

Enable Register Bank Flag

0

1

Select register bank 0 as working register area

Select register banks 0, 1, 2, or 3 as working register area in accordance with

the select register bank (SRB) instruction operand

NOTES:

1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during

power-down mode (IDLE or STOP), the current value of the carry flag is retained.

2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for

detailed information.

4–32

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

PUMOD1 — Pull-up Resistor Mode Register 1 I/O

FDDH, FDCH

Bit

7

PUR7

0

6

PUR6

0

5

PUR5

0

4

PUR4

0

3

PUR3

0

2

PUR2

0

1

0

Identifier

PUR1

PUR0

RESET Value

Read/Write

Bit Addressing

0

W

8

0

W

8

W

8

PUR7

PUR6

PUR5

PUR4

PUR3

PUR2

PUR1

PUR0

Connect/Disconnect Port 7 Pull-up Resistor Control Bit

0

1

Disconnect port 7 pull-up resistor

Connect port 7 pull-up resistor

Connect/Disconnect Port 6 Pull-up Resistor Control Bit

0

1

Disconnect port 6 pull-up resistor

Connect port 6 pull-up resistor

Connect/Disconnect Port 5 Pull-up Resistor Control Bit

0

1

Disconnect port 5 pull-up resistor

Connect port 5 pull-up resistor

Connect/Disconnect Port 4 Pull-up Resistor Control Bit

0

1

Disconnect port 4 pull-up resistor

Connect port 4 pull-up resistor

Connect/Disconnect Port 3 Pull-up Resistor Control Bit

0

1

Disconnect port 3 pull-up resistor

Connect port 3 pull-up resistor

Connect/Disconnect Port 2 Pull-up Resistor Control Bit

0

1

Disconnect port 2 pull-up resistor

Connect port 2 pull-up resistor

Connect/Disconnect Port 1 Pull-up Resistor Control Bit

0

1

Disconnect port 1 pull-up resistor

Connect port 1 pull-up resistor

Connect/Disconnect Port 0 Pull-up Resistor Control Bit

0

1

Disconnect port 0 pull-up resistor

Connect port 0 pull-up resistor

4–33

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

PUMOD2 — Pull-up Resistor Mode Register 2

I/O

FDEH

Bit

3

"0"

0

2

"0"

0

1

PUR9

0

PUR8

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

.3 – .2

PUR9

Bits 3 – 2

0

Always cleared to logic zero

Connect/Disconnect Port 9 Pull-up Resistor Control Bit

0

1

Disconnect port 9 pull-up resistor

Connect port 9 pull-up resistor

PUR8

Connect/Disconnect Port 8 Pull-up Resistor Control Bit

0

1

Disconnect port 8 pull-up resistor

Connect port 8 pull-up resistor

4–34

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

SCMOD— System Clock Mode Control Register

CPU

FB7H

Bit

3

.3

0

2

.2

0

1

"0"

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

1

W

1

W

1

W

1

SCMOD.3

Bit 3

0

1

Enable main system clock

Disable main system clock

SCMOD.2

Bit 2

0

1

Enable sub system clock

Disable sub system clock

SCMOD.1

SCMOD.0

Bit 1

0

Always logic zero

Bit 0

0

1

Select main system clock

Select sub system clock

NOTES:

1. Sub-oscillation goes into stop mode only by SCMOD.2. PCON which revokes stop mode cannot stop the sub-

oscillation.

2. You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed):

Main operation ® sub-operation ® sub-idle (LCD on, after a few minutes later without any external input) ® sub-

operation ® main operation ® SCMOD.2 = 1 ® main stop mode (LCD off).

3. SCMOD bits 3–0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by

separate 1-bit instructions.

4–35

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

SMOD — Serial I/O Mode Register

SIO

FE1H, FE0H

Bit

7

.7

0

6

.6

0

5

.5

0

4

"0"

0

3

.3

2

1

.1

0

.0

0

Identifier

.2

0

RESET Value

Read/Write

Bit Addressing

0

W

8

W

8

W

8

W

8

W

1/8

W

8

W

8

W

8

SMOD.7 – .5

Serial I/O Clock Selection and SBUF R/W Status Control Bits

Use an external clock at the SCK pin;

Enable SBUF when SIO operation is halted or when SCK goes high

0

1

0

1

x

Use the TOL0 clock from timer/counter 0;

Enable SBUF when SIO operation is halted or when SCK goes high

Use the selected CPU clock (fxx/4, 8, or 64; 'fxx' is the system clock)

then, enable SBUF read/write operation. 'x' means 'don't care.'

10

1

0

1

0

1

4.09 kHz clock (fxx/2

)

4

262 kHz clock (fxx/2 ); Note: You cannot select a fxx/2 clock fre-

quency if you have selected a CPU clock of fxx/64

NOTE: All kHz frequency ratings assume a system clock of 4.19 MHz.

SMOD.4

SMOD.3

Bit 4

0

Always logic zero

Initiate Serial I/O Operation Bit

1

Clear IRQS flag and 3-bit clock counter to logic zero; then initiate serial trans-

mission. When SIO transmission starts, this bit is cleared by hardware to logic

zero

SMOD.2

Enable/Disable SIO Data Shifter and Clock Counter Bit

0

Disable the data shifter and clock counter; the contents of IRQS flag is retained

when serial transmission is completed

1

Enable the data shifter and clock counter; The IRQS flag is set to logic one when

serial transmission is completed

SMOD.1

SMOD.0

Serial I/O Transmission Mode Selection Bit

0

1

Receive-only mode

Transmit-and-receive mode

LSB/MSB Transmission Mode Selection Bit

0

1

Transmit the most significant bit (MSB) first

Transmit the least significant bit (LSB) first

4–36

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

TMOD0— Timer/Counter 0 Mode Register

T/C0

F91H, F90H

Bit

7

"0"

0

6

.6

0

5

.5

0

4

.4

0

3

.3

2

.2

0

1

"0"

0

"0"

0

Identifier

RESET Value

Read/Write

Bit Addressing

0

W

8

W

8

W

8

W

8

W

1/8

W

8

W

8

W

8

TMOD0.7

Bit 7

0

Always logic zero

TMOD0.6 – .4

Timer/Counter 0 Input Clock Selection Bits

0

1

0

1

0

1

0

1

0

1

External clock input at TCL0 pin on rising edge

External clock input at TCL0 pin on falling edge

10

fxx/2 (4.09 kHz)

6

fxx/2 (65.5 kHz)

4

fxx/2 (262 kHz)

fxx (4.19 MHz)

NOTE: “fxx” is selected system clock of 4.19 MHz

TMOD0.3

TMOD0.2

Clear Counter and Resume Counting Control Bit

1

Clear TCNT0, IRQT0, and TOL0 and resume counting immediately

(This bit is cleared automatically when counting starts.)

Enable/Disable Timer/Counter 0 Bit

0

1

Disable timer/counter 0; retain TCNT0 contents

Enable timer/counter 0

TMOD0.1

TMOD0.0

Bit 1

0

Always logic zero

Bit 0

0

4–37

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

TMOD1— Timer/Counter 1 Mode Register

T/C

FA1H, FA0H

Bit

3

"0"

0

2

.6

0

1

.5

0

.4

0

3

.3

2

.2

0

1

"0"

0

"0"

0

Identifier

RESET Value

Read/Write

Bit Addressing

0

W

8

W

8

W

8

W

8

W

1/8

W

8

W

8

W

8

TMOD1.7

Bit 7

0

Always logic zero

TMOD1.6 – .4

Timer/Counter 1 Input Clock Selection Bit

0

1

0

1

0

1

0

1

0

1

External clock input at TCL1 pin on rising edge

External clock input at TCL1 pin on falling edge

10

fxx/2 (4.09 kHz)

8

fxx/2 (16.4 kHz)

6

fxx/2 (65.5 kHz)

4

fxx/2 (262 kHz)

NOTE: “fxx” is selected system clock of 4.19 MHz

TMOD1.3

TMOD1.2

Clear Counter and Resume Counting Control Bit

1

Clear TCNT1, IRQT1, and TOL1 and resume counting immediately

(This bit is cleared automatically when counting starts.)

Enable/Disable Timer/Counter 1 Bit

0

1

Disable timer/counter 1; retain TCNT1 contents

Enable timer/counter 1

TMOD1.1

TMOD1.0

Bit 1

0

Always logic zero

Bit 0

0

4–38

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

TOE— Timer Output Enable Flag Register

T/C

F92H

Bit

3

TOE1

0

2

TOE0

0

1

"U"

U

0

"0"

0

Identifier

RESET Value

Read/Write

Bit Addressing

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

TOE1

Timer/Counter 1 Output Enable Flag

0

1

Disable timer/counter 1 clock output at the TCLO1 pin

Enable timer/counter 1 clock output at the TCLO1 pin

TOE0

Timer/Counter 0 Output Enable Flag

0

1

Disable timer/counter 0 clock output at the TCLO0 pin

Enable timer/counter 0 clock output at the TCLO0 pin

.1

.0

Bits 1

U

This bit is undefined

Bits 0

0

Always logic zero

4–39

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

WDFLAG — Watch-Dog Timer's Counter Clear Flag

WT

F9AH.3

Bit

3

WDTCF

0

2

"0"

0

1

"0"

0

"0"

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

1/4

WDTCF

Watch-dog Timer's Counter Clear Bit

0

–

1

Clear the WDT's counter to zero and restart the WDT's counter

WDFLAG.2 – .0

Bit2 – 0

Always logic zero

0

4–40

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

WDMOD — Watch-Dog Timer Mode Control Register

WT

F99H, F98H

Bit

3

.7

1

2

.6

0

1

.5

1

0

.4

0

3

.3

0

2

.2

1

.1

0

.0

1

Identifier

RESET Value

Read/Write

Bit Addressing

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

WMOD.7 – .0

Watch-Dog Timer Enable/Disable Control

0

1

0

1

0

1

0

Disable watch-dog timer function

Enable watch-dog timer function

Other Values

4–41

MEMORY MAP

KS57C21516/P21516 MICROCONTROLLER

WMOD — Watch Timer Mode Register

WT

F89H, F88H

Bit

7

.7

0

6

"0"

0

5

.5

0

4

.4

0

3

.3

2

.2

0

1

.1

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

(note)

R

W

8

W

8

W

8

W

8

W

8

W

8

W

8

1

WMOD.7

Enable/Disable Buzzer Output Bit

0

1

Disable buzzer (BUZ) signal output at the BUZ pin

Enable buzzer (BUZ) signal output at the BUZ pin

WMOD.6

Bit 6

0

Always logic zero

WMOD.5 – .4

Output Buzzer Frequency Selection Bits

0

1

0

1

0

1

2 kHz buzzer (BUZ) signal output

4 kHz buzzer (BUZ) signal output

8 kHz buzzer (BUZ) signal output

16 kHz buzzer (BUZ) signal output

XT Input Level Control Bit

in

WMOD.3

Input level to XT pin is low; 1-bit read-only addressable for tests

in

0

1

Input level to XT pin is high; 1-bit read-only addressable for tests

in

WMOD.2

WMOD.1

WMOD.0

Enable/Disable Watch Timer Bit

0

1

Disable watch timer and clear frequency dividing circuits

Enable watch timer

Watch Timer Speed Control Bit

0

1

Normal speed; set IRQW to 0.5 seconds

High-speed operation; set IRQW to 3.91 ms

Watch Timer Clock Selection Bit

0

1

Select main system clock (fx)/128 as the watch timer clock

Select a subsystem clock as the watch timer clock

NOTE: RESET sets WMOD.3 to the current input level of the subsystem clock, XTin. If the input level is high, WMOD.3

is set to logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register.

4–42

KS57C21516/P21516 MICROCONTROLLER

MEMORY MAP

4–43

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

5

SAM47 INSTRUCTION SET

OVERVIEW

The SAM47 instruction set is specifically designed to support the large register files typically founded in most

KS57-series microcontrollers. The SAM47 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data

manipulation, logical and arithmetic operations, program control, and CPU control. I/O instructions for peripheral

hardware devices are flexible and easy to use. Symbolic hardware names can be substituted as the instruction

operand in place of the actual address. Other important features of the SAM47 instruction set include:

— 1-byte referencing of long instructions (REF instruction)

— Redundant instruction reduction (string effect)

— Skip feature for ADC and SBC instructions

Instruction operands conform to the operand format defined for each instruction. Several instructions have

multiple operand formats.

Predefined values or labels can be used as instruction operands when addressing immediate data. Many of the

symbols for specific registers and flags may also be substituted as labels for operations such DA, mema, memb,

b, and so on. Using instruction labels can greatly simplify programming and debugging tasks.

INSTRUCTION SET FEATURES

In this section, the following SAM47 instruction set features are described in detail:

— Instruction reference area

— Instruction redundancy reduction

— Flexible bit manipulation

— ADC and SBC instruction skip condition

NOTES:

1. The ROM size accessed by instruction may change for different devices in the SAM47 product family (JP, JPS, CALL,

and CALLS).

2. The number of memory bank selected by SMB may change for different devices in the SAM47 product family.

3. The port names used in the instruction set may change for different devices in the SAM4 product family.

4. The interrupt names and the interrupt numbers used in the instruction set may change for different devices in the SAM

47 product family.

5–1

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

INSTRUCTION REFERENCE AREA

Using the 1-byte REF (Reference) instruction, you can reference instructions stored in addresses 0020H–007FH

of program memory (the REF instruction look-up table). The location referenced by REF may contain either two

1-byte instructions or a single 2-byte instruction. The starting address of the instruction being referenced must

always be an even number.

3-byte instructions such as JP or CALL may also be referenced using REF. To reference these 3-byte

instructions, the 2-byte pseudo commands TJP and TCALL must be written in the reference instead of JP and

CALL.

The PC is not incremented when a REF instruction is executed. After it executes, the program's instruction

execution sequence resumes at the address immediately following the REF instruction. By using REF instructions

to execute instructions larger than one byte, as well as branches and subroutines, you can reduce program size.

To summarize, the REF instruction can be used in three ways:

— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions;

— Branching to any location by referencing a branch address that is stored in the look-up table;

— Calling subroutines at any location by referencing a call address that is stored in the look-up table.

If necessary, a REF instruction can be circumvented by means of a skip operation prior to the REF in the

execution sequence. In addition, the instruction immediately following a REF can also be skipped by using an

appropriate reference instruction or instructions.

Two-byte instruction can be referenced by using a REF instruction (An exception is XCH A, DA). If the MSB

value of the first one-byte instruction in the reference area is “0”, the instruction cannot be referenced by a REF

instruction. Therefore, if you use REF to reference two 1-byte instruction stored in the reference area, specific

combinations must be used for the first and second 1-byte instruction.

These combination examples are described in Table 5-1.

Table 5-1. Valid 1-Byte Instruction Combinations for REF Look-Ups

First 1-Byte Instruction

Instruction Operand

Second 1-Byte Instruction

Instruction Operand

INCS ^(note)

LD

A, #im

R

INCS

DECS ^(note)

RRb

R

INCS ^(note)

INCS

DECS ^(note)

A, @RRa

@HL, A

R

RRb

R

INCS ^(note)

INCS

DECS ^(note)

R

RRb

R

NOTE:

The MSB value of the instruction is “0”.

5–2

KS57C21516/P21516 MICROCONTROLLER

REDUCING INSTRUCTION REDUNDANCY

SAM47 INSTRUCTION SET

When redundant instructions such as LD A,#im and LD EA,#imm are used consecutively in a program sequence,

only the first instruction is executed. The redundant instructions which follow are ignored, that is, they are handled

like a NOP instruction. When LD HL,#imm instructions are used consecutively, redundant instructions are also

ignored.

In the following example, only the 'LD A, #im' instruction will be executed. The 8-bit load instruction which follows

it is interpreted as redundant and is ignored:

LD

A,#im

EA,#imm

; Load 4-bit immediate data (#im) to accumulator

; Load 8-bit immediate data (#imm) to extended

; accumulator

In this example, the statements 'LD A,#2H' and 'LD A,#3H' are ignored:

BITR

LD

EMB

A,#1H

A,#2H

A,#3H

23H,A

; Execute instruction

; Ignore, redundant instruction

; Execute instruction, 023H ¬ #1H

If consecutive LD HL, #imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, HL) are

detected, only the first LD is executed and the LDs which immediately follow are ignored. For example,

LD

HL,#10H

HL,#20H

A,#3H

EA,#35H

@HL,A

; HL ¬ 10H

; Ignore, redundant instruction

; A ¬ 3H

; Ignore, redundant instruction

; (10H) ¬ 3H

If an instruction reference with a REF instruction has a redundancy effect, the following conditions apply:

— If the instruction preceding the REF has a redundancy effect, this effect is cancelled and the referenced

instruction is not skipped.

— If the instruction following the REF has a redundancy effect, the instruction following the REF is skipped.

+

PROGRAMMING TIP — Example of the Instruction Redundancy Effect

ORG 0020H

ABC

LD

EA,#30H

;

STORED IN REF INSTRUCTION REFERENCE AREA

ORG 0080H

•

LD

REF

•

EA,#40H

ABC

;

REDUNDANCY EFFECT IS ENCOUNTERED

NO SKIP (EA ¬ #30H)

•

REF

LD

ABC

EA,#50H

;

EA ¬ #30H

SKIP

5-3

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

FLEXIBLE BIT MANIPULATION

In addition to normal bit manipulation instructions like set and clear, the SAM47 instruction set can also perform

bit tests, bit transfers, and bit Boolean operations. Bits can also be addressed and manipulated by special bit

addressing modes. Three types of bit addressing are supported:

— mema.b

— memb.@L

— @H+DA.b

The parameters of these bit addressing modes are described in more detail in Table 5-2.

Table 5-2. Bit Addressing Modes and Parameters

Addressing Mode

Addressable Peripherals

ERB, EMB, IS1, IS0, IEx, IRQx

Ports

Address Range

mema.b

FB0H–FBFH

FF0H–FFFH

FC0H–FFFH

memb.@L

@H+DA.b

BSCx, Ports

All bit-manipulatable peripheral hardware

All bits of the memory bank specified by

EMB and SMB that are bit-manipulatable

NOTE: Some devices in the SAM47 product family don’t have BSC.

INSTRUCTIONS WHICH HAVE SKIP CONDITIONS

The following instructions have a skip function when an overflow or borrow occurs:

XCHI

XCHD

LDI

INCS

DECS

ADS

LDD

SBS

If there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a

skip is executed. However, the carry flag value is unaffected.

The instructions BTST, BTSF, and CPSE also generate a skip signal and execute a skip when they meet a skip

condition, and the carry flag value is also unaffected.

5-4

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

INSTRUCTIONS WHICH AFFECT THE CARRY FLAG

The only instructions which do not generate a skip signal, but which do affect the carry flag are as follows:

ADC

SBC

SCF

RCF

CCF

RRC

LDB

C,(operand)

BAND

BOR

BXOR

IRET

ADC AND SBC INSTRUCTION SKIP CONDITIONS

The instructions 'ADC A,@HL' and 'SBC A,@HL' can generate a skip signal, and set or clear the carry flag,

when they are executed in combination with the instruction 'ADS A,#im'.

If an 'ADS A,#im' instruction immediately follows an 'ADC A,@HL' or 'SBC A,@HL' instruction in a program

sequence, the ADS instruction does not skip the instruction following ADS, even if it has a skip function. If,

however, an 'ADC A,@HL' or 'SBC A,@HL' instruction is immediately followed by an 'ADS A,#im' instruction,

the ADC (or SBC) skips on overflow (or if there is no borrow) to the instruction immediately following the ADS,

and program execution continues. Table 5-3 contains additional information and examples of the 'ADC A,@HL'

and 'SBC A,@HL' skip feature.

Table 5-3. Skip Conditions for ADC and SBC Instructions

Sample

Instruction Sequences

If the result of

instruction 1 is:

Then, the execution

sequence is:

Reason

ADC A,@HL

ADS A,#im

xxx

1

2

3

4

Overflow

1, 3, 4

ADS cannot skip

instruction 3, even if it

has a skip function.

No overflow

1, 2, 3, 4

xxx

SBC A,@HL

ADS A,#im

xxx

1

2

3

4

Borrow

1, 2, 3, 4

1, 3, 4

ADS cannot skip

instruction 3, even if it

has a skip function.

No borrow

xxx

5-5

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

Table 5-6. Instruction Operand Notation

SYMBOLS and CONVENTIONS

Table 5-4. Data Type Symbols

Symbol

Definition

Direct address

Symbol

Data Type

Immediate data

DA

d

a

b

r

@

Indirect address prefix

Source operand

Address data

src

Bit data

dst

Destination operand

Contents of register R

Bit location

Register data

(R)

f

Flag data

.b

i

Indirect addressing data

memc ´ 0.5 immediate data

im

4-bit immediate data (number)

8-bit immediate data (number)

Immediate data prefix

000H–3FFFH immediate address

'n' bit address

t

imm

#

Table 5-5. Register Identifiers

ADR

ADRn

R

Full Register Name

4-bit accumulator

ID

A, E, L, H, X, W, Z, Y

E, L, H, X, W, Z, Y

EA, HL, WX, YZ

A

Ra

4-bit working registers

E, L, H, X, W,

Z, Y

RR

8-bit extended accumulator

8-bit memory pointer

8-bit working registers

Select register bank 'n'

Select memory bank 'n'

Carry flag

EA

RRa

RRb

RRc

mema

memb

memc

HL, WX, WL

HL

HL, WX, YZ

WX, YZ, WL

SRB n

SMB n

C

WX, WL

FB0H–FBFH, FF0H–FFFH

FC0H–FFFH

Code direct addressing:

0020H–007FH

Program status word

Port 'n'

PSW

Pn

SB

Select bank register (8 bits)

Logical exclusive-OR

Logical OR

XOR

OR

'm'-th bit of port 'n'

Pn.m

IPR

Interrupt priority register

Enable memory bank flag

Enable register bank flag

AND

[(RR)]

Logical AND

EMB

ERB

Contents addressed by RR

5-6

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

OPCODE DEFINITIONS

Table 5-8. Opcode Definitions (Indirect)

Table 5-7. Opcode Definitions (Direct)

Register

@HL

i2

1

i1

0

i0

1

Register

r2

0

1

0

1

r1

0

1

0

1

0

1

0

1

r0

0

1

0

1

0

1

0

1

0

A

E

@WX

@WL

1

0

1

L

H

i = Immediate data for indirect addressing

X

W

Z

Y

EA

HL

WX

YZ

r = Immediate data for register

CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS

A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected

using the PCON register.

In this document, the letter 'S' is used in tables when describing the number of additional machine cycles required

for an instruction to execute, given that the instruction has a skip function ('S' = skip). The addition number of

machine cycles that will be required to perform the skip usually depends on the size of the instruction being

skipped — whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also executed for SMB and SRB

instructions.

The values in additional machine cycles for 'S' for the three cases in which skip conditions occur are as follows:

Case 1:No skip

S = 0 cycles

S = 1 cycle

S = 2 cycles

Case 2:Skip is 1-byte or 2-byte instruction

Case 3: Skip is 3-byte instruction

NOTE: REF instructions are skipped in one machine cycle.

5-7

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

HIGH-LEVEL SUMMARY

This section contains a high-level summary of the SAM47 instruction set in table format. The tables are designed

to familiarize you with the range of instructions that are available in each instruction category.

These tables are a useful quick-reference resource when writing application programs.

If you are reading this user's manual for the first time, however, you may want to scan this detailed information

briefly, and then return to it later on. The following information is provided for each instruction:

— Instruction name

— Operand(s)

— Brief operation description

— Number of bytes of the instruction and operand(s)

— Number of machine cycles required to execute the instruction

The tables in this section are arranged according to the following instruction categories:

— CPU control instructions

— Program control instructions

— Data transfer instructions

— Logic instructions

— Arithmetic instructions

— Bit manipulation instructions

5-8

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

Table 5-9. CPU Control Instructions — High-Level Summary

Operand Operation Description

Set carry flag to logic one

Name

SCF

Bytes

Cycles

1

2

1

2

1

2

1

2

1

2

1

2

RCF

CCF

EI

Reset carry flag to logic zero

Complement carry flag

Enable all interrupts

Disable all interrupts

Engage CPU idle mode

Engage CPU stop mode

No operation

DI

IDLE

STOP

NOP

SMB

SRB

REF

VENTn

n

Select memory bank

Select register bank

Reference code

memc

EMB (0,1)

ERB (0,1)

ADR

Load enable memory bank flag (EMB) and the enable

register bank flag (ERB) and program counter to vector

address, then branch to the corresponding location

Table 5-10. Program Control Instructions — High-Level Summary

Name

Operand

R,#im

Operation Description

Compare and skip if register equals #im

Compare and skip if indirect data memory equals #im

Compare and skip if A equals R

Compare and skip if A equals indirect data memory

Compare and skip if EA equals indirect data memory

Compare and skip if EA equals RR

Jump to direct address (14 bits)

Jump direct in page (12 bits)

Bytes

Cycles

CPSE

2

1

2

3

2

1

2

3

2

1

2 + S

@HL,#im

A,R

2 + S

A,@HL

EA,@HL

EA,RR

ADR

#im

1 + S

2 + S

JP

3

JPS

JR

2

Jump to immediate address

2

@WX

@EA

ADR

–

Branch relative to WX register

3

Branch relative to EA

3

CALL

CALLS

RET

Call direct in page (14 bits)

4

Call direct in page (11 bits)

3

Return from subroutine

IRET

–

Return from interrupt

3

SRET

–

Return from subroutine and skip

3 + S

5-9

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

Table 5-11. Data Transfer Instructions — High-Level Summary

Name

XCH

Operand

A,DA

Operation Description

Exchange A and direct data memory contents

Exchange A and register (Ra) contents

Bytes

Cycles

2

1

2

1

2

A,Ra

1

A,@RRa

EA,DA

Exchange A and indirect data memory

1

Exchange EA and direct data memory contents

Exchange EA and register pair (RRb) contents

Exchange EA and indirect data memory contents

2

EA,RRb

EA,@HL

A,@HL

2

XCHI

XCHD

LD

Exchange A and indirect data memory contents;

increment contents of register L and skip on carry

2 + S

A,@HL

Exchange A and indirect data memory contents;

decrement contents of register L and skip on carry

1

2 + S

A,#im

Load 4-bit immediate data to A

1

2

1

2

1

A,@RRa

A,DA

Load indirect data memory contents to A

Load direct data memory contents to A

Load register contents to A

1

2

A,Ra

2

Ra,#im

RR,#imm

DA,A

Load 4-bit immediate data to register

Load 8-bit immediate data to register

Load contents of A to direct data memory

Load contents of A to register

2

Ra,A

2

EA,@HL

EA,DA

EA,RRb

@HL,A

DA,EA

RRb,EA

@HL,EA

A,@HL

Load indirect data memory contents to EA

Load direct data memory contents to EA

Load register contents to EA

2

Load contents of A to indirect data memory

Load contents of EA to data memory

Load contents of EA to register

1

2

Load contents of EA to indirect data memory

2

LDI

Load indirect data memory to A; increment register L

contents and skip on carry

2 + S

LDD

LDC

A,@HL

Load indirect data memory contents to A; decrement

register L contents and skip on carry

1

2 + S

EA,@WX

EA,@EA

A

Load code byte from WX to EA

Load code byte from EA to EA

Rotate right through carry bit

1

2

1

2

3

1

2

1

2

RRC

PUSH

RR

Push register pair onto stack

SB

Push SMB and SRB values onto stack

Pop to register pair from stack

Pop SMB and SRB values from stack

POP

RR

SB

5-10

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

Table 5-12. Logic Instructions — High-Level Summary

Name

AND

Operand

A,#im

Operation Description

Logical-AND A immediate data to A

Logical-AND A indirect data memory to A

Logical-AND register pair (RR) to EA

Logical-AND EA to register pair (RRb)

Logical-OR immediate data to A

Bytes

Cycles

2

1

2

1

2

1

2

1

2

1

2

1

2

A,@HL

EA,RR

RRb,EA

A, #im

A, @HL

EA,RR

RRb,EA

A,#im

OR

Logical-OR indirect data memory contents to A

Logical-OR double register to EA

Logical-OR EA to double register

XOR

COM

Exclusive-OR immediate data to A

Exclusive-OR indirect data memory to A

Exclusive-OR register pair (RR) to EA

Exclusive-OR register pair (RRb) to EA

Complement accumulator (A)

A,@HL

EA,RR

RRb,EA

A

Table 5-13. Arithmetic Instructions — High-Level Summary

Name

Operand

Operation Description

Bytes

Cycles

1

ADC

A,@HL

EA,RR

RRb,EA

A, #im

EA,#imm

A,@HL

EA,RR

RRb,EA

A,@HL

EA,RR

RRb,EA

A,@HL

EA,RR

RRb,EA

R

Add indirect data memory to A with carry

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

Add register pair (RR) to EA with carry

2

Add EA to register pair (RRb) with carry

2

ADS

Add 4-bit immediate data to A and skip on carry

Add 8-bit immediate data to EA and skip on carry

Add indirect data memory to A and skip on carry

Add register pair (RR) contents to EA and skip on carry

Add EA to register pair (RRb) and skip on carry

Subtract indirect data memory from A with carry

Subtract register pair (RR) from EA with carry

Subtract EA from register pair (RRb) with carry

Subtract indirect data memory from A; skip on borrow

Subtract register pair (RR) from EA; skip on borrow

Subtract EA from register pair (RRb); skip on borrow

Decrement register (R); skip on borrow

1 + S

2 + S

1 + S

2 + S

1

SBC

SBS

2

1 + S

2 + S

1 + S

2 + S

1 + S

2 + S

1 + S

DECS

INCS

RR

Decrement register pair (RR); skip on borrow

Increment register (R); skip on carry

R

DA

Increment direct data memory; skip on carry

Increment indirect data memory; skip on carry

Increment register pair (RRb); skip on carry

@HL

RRb

5-11

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

Table 5-14. Bit Manipulation Instructions — High-Level Summary

Name

BTST

Operand

Operation Description

Test specified bit and skip if carry flag is set

Test specified bit and skip if memory bit is set

Bytes

Cycles

1 + S

C

1

2

DA.b

2 + S

mema.b

memb.@L

@H+DA.b

DA.b

BTSF

Test specified memory bit and skip if bit equals "0"

mema.b

memb.@L

@H+DA.b

mema.b

BTSTZ

BITS

Test specified bit; skip and clear if memory bit is set

Set specified memory bit

memb.@L

@H+DA.b

DA.b

2

mema.b

memb.@L

@H+DA.b

DA.b

BITR

Clear specified memory bit to logic zero

mema.b

memb.@L

@H+DA.b

C,mema.b

C,memb.@L

C,@H+DA.b

C,mema.b

C,memb.@L

C,@H+DA.b

C,mema.b

C,memb.@L

C,@H+DA.b

mema.b,C

BAND

BOR

Logical-AND carry flag with specified memory bit

Logical-OR carry with specified memory bit

Exclusive-OR carry with specified memory bit

Load carry bit to a specified memory bit

BXOR

LDB

memb.@L,C Load carry bit to a specified indirect memory bit

@H+DA.b,C

C,mema.b

Load specified memory bit to carry bit

C,memb.@L Load specified indirect memory bit to carry bit

C,@H+DA.b

5-12

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BINARY CODE SUMMARY

This section contains binary code values and operation notation for each instruction in the SAM47 instruction set

in an easy-to-read, tabular format. It is intended to be used as a quick-reference source for programmers who are

experienced with the SAM47 instruction set. The same binary values and notation are also included in the

detailed descriptions of individual instructions later in Section 5.

If you are reading this user's manual for the first time, please just scan this very detailed information briefly. Most

of the general information you will need to write application programs can be found in the high-level summary

tables in the previous section. The following information is provided for each instruction:

— Instruction name

— Operand(s)

— Binary values

— Operation notation

The tables in this section are arranged according to the following instruction categories:

— CPU control instructions

— Program control instructions

— Data transfer instructions

— Logic instructions

— Arithmetic instructions

— Bit manipulation instructions

5-13

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

Table 5-15. CPU Control Instructions — Binary Code Summary

Operand Binary Code Operation Notation

Name

SCF

1

0

1

0

t7

1

0

1

0

1

0

1

0

1

t6

1

0

1

0

t5

0

1

0

1

0

1

0

1

t4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C ¬ 1

RCF

CCF

EI

C ¬ 0

C ¬ C

0

1

IME ¬ 1

0

DI

1

IME ¬ 0

0

IDLE

STOP

1

PCON.2 ¬ 1

PCON.3 ¬ 1

0

1

0

NOP

SMB

0

No operation

n

1

SMB ¬ n (n = 0, … ,15)

d3

1

d2 d1 d0

SRB

1

0

1

SRB ¬ n (n = 0, 1, 2, 3)

0

d1 d0

t1 t0

REF

memc

t3

t2

PC13–0 ¬ memc.5–0 + (memc + 1).7–

0

VENTn

EMB (0,1)

ERB (0,1)

ADR

E

M

B

E

R

B

a13 a12 a11 a10 a9 a8

ROM (2 x n) 7–6 ® EMB, ERB

ROM (2 x n) 5–4 ® PC13–12

ROM (2 x n) 3–0 ® PC11–8

ROM (2 x n + 1) 7–0 ® PC7–0

(n = 0, 1, 2, 3, 4, 5, 6, 7)

a7 a6 a5 a4 a3

a2 a1 a0

5-14

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

Table 5-16. Program Control Instructions — Binary Code Summary

Operand Binary Code Operation Notation

R,#im Skip if R = im

Name

CPSE

1

d3

1

d2

1

0

d1

0

1

d0

1

0

r2

1

0

r1

0

1

r0

1

@HL,#im

A,R

1

Skip if (HL) = im

Skip if A = R

0

1

d3

1

d2

1

d1

0

d0

1

0

1

0

1

0

1

r2

0

r1

0

r0

0

A,@HL

0

1

Skip if A = (HL)

EA,@HL

1

0

1

0

Skip if A = (HL), E = (HL+1)

0

1

0

1

EA,RR

ADR

1

0

1

0

Skip if EA = RR

1

0

1

r2

0

r1

1

0

JP

1

0

1

PC13–0 ¬ ADR13–0

0

a13 a12 a11 a10 a9

a8

a0

a8

a0

a7

1

a6

0

a5

0

a4

1

a3

a2

a1

JPS

JR

ADR

a11 a10 a9

PC13–0 ¬ PC13–12 + ADR11–0

a7

a6

a5

a4

a3

a2

a1

PC13–0 ¬ ADR (PC–15 to PC+16)

PC13–0 ¬ PC13–8 + (WX)

#im *

@WX

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

@EA

ADR

1

PC13–0 ¬ PC13–8 + (EA)

0

1

0

CALL

1

[(SP–1) (SP–2)] ¬ EMB, ERB

[(SP–3) (SP–4)] ¬ PC7–0

[(SP–5) (SP–6)] ¬ PC13–8

[(SP–1) (SP–2)] ¬ EMB, ERB

[(SP–3) (SP–4)] ¬ PC7–0

[(SP–5) (SP–6)] ¬ PC14–8

0

1

a13 a12 a11 a10 a9

a8

a0

a8

a0

a7

1

a6

1

a5

1

a4

0

a3

1

a2

a10 a9

a2 a1

a1

CALLS

ADR

a7

a6

a5

a4

a3

First Byte

Condition

0

1

0

a3

a2

a1

a0

PC ¬ PC+2 to PC+16

PC ¬ PC–1 to PC–15

* JR #im

5-15

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

Table 5-16. Program Control Instructions — Binary Code Summary (Continued)

Name

RET

Operand

Binary Code

Operation Notation

PC13–8 ¬ (SP + 1) (SP)

PC7–0 ¬ (SP + 3) (SP + 2)

EMB,ERB ¬ (SP + 4)

SP ¬ SP + 6

–

1

0

1

0

1

0

1

0

1

IRET

–

PC13–8 ¬ (SP + 1) (SP)

PC7–0 ¬ (SP + 3) (SP + 2)

PSW ¬ (SP + 5) (SP + 4)

SP ¬ SP + 6

SRET

PC13–8 ¬ (SP + 1) (SP)

PC7–0 ¬ (SP + 3) (SP + 2)

EMB,ERB ¬ (SP + 4)

SP ¬ SP + 6

Table 5-17. Data Transfer Instructions — Binary Code Summary

Operand Binary Code Operation Notation

Name

XCH

A,DA

0

a7

0

1

a6

1

a5

1

a4

0

1

a3

1

0

a2

r2

i2

1

0

a1

r1

i1

1

a0

r0

i0

1

A « DA

A,Ra

A « Ra

A,@RRa

EA,DA

0

1

A « (RRa)

1

0

1

A « DA,E « DA + 1

a7

1

a6

1

a5

0

a4

1

a3

1

a2

1

a1

0

a0

0

EA,RRb

EA,@HL

EA « RRb

1

0

r2

1

r1

0

1

0

1

0

A « (HL), E « (HL + 1)

0

1

XCHI

XCHD

LD

A,@HL

0

1

0

1

0

A « (HL), then L ¬ L+1;

skip if L = 0H

0

1

0

1

A « (HL), then L ¬ L-1;

skip if L = 0FH

A,#im

1

0

1

0

1

0

d3

1

d2

i2

1

d1

i1

0

d0

i0

0

A ¬ im

A,@RRa

A,DA

A ¬ (RRa)

A ¬ DA

1

0

1

a7

1

a6

1

a5

0

a4

1

a3

1

a2

1

a1

0

a0

1

A,Ra

A ¬ Ra

0

1

r2

r1

r0

5-16

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

Table 5-17. Data Transfer Instructions — Binary Code Summary (Continued)

Operand Binary Code Operation Notation

Ra,#im

Name

LD

1

d3

1

d2

0

d1

0

1

d0

0

1

0

r2

d2

0

r1

d1

0

1

r0

1

Ra ¬ im

RR,#imm

DA,A

0

RR ¬ imm

DA ¬ A

d7

1

d6

0

d5

0

d4

0

d3

1

d0

1

a7

1

a6

1

a5

0

a4

1

a3

1

a2

1

a1

0

a0

1

Ra,A

Ra ¬ A

0

r2

1

r1

0

r0

0

EA,@HL

EA,DA

EA,RRb

1

0

1

A ¬ (HL), E ¬ (HL + 1)

A ¬ DA, E ¬ DA + 1

EA ¬ RRb

0

1

0

1

0

1

0

a7

1

a6

1

a5

0

a4

1

a3

1

a2

1

a1

0

a0

0

1

r2

1

r1

0

@HL,A

DA,EA

1

0

(HL) ¬ A

1

0

1

0

1

DA ¬ A, DA + 1 ¬ E

a7

1

a6

1

a5

0

a4

1

a3

1

a2

1

a1

0

a0

0

RRb,EA

@HL,EA

RRb ¬ EA

1

0

r2

1

r1

0

1

0

1

0

(HL) ¬ A, (HL + 1) ¬ E

0

LDI

A,@HL

1

0

1

0

1

0

A ¬ (HL), then L ¬ L+1;

skip if L = 0H

LDD

LDC

1

0

1

0

1

A ¬ (HL), then L ¬ L–1;

skip if L = 0FH

EA,@WX

EA,@EA

A

1

0

1

0

EA ¬ [PC12–8 + (WX)]

EA ¬ [PC12–8 + (EA)]

RRC

C ¬ A.0, A3 ¬ C

A.n–1 ¬ A.n (n = 1, 2, 3)

PUSH

RR

SB

0

1

0

1

0

1

0

1

0

1

0

r2

1

r1

0

1

((SP–1)) ((SP–2)) ¬ (RR),

(SP) ¬ (SP)–2

((SP–1)) ¬ (SMB), ((SP–2)) ¬ (SRB),

(SP) ¬ (SP)–2

1

5-17

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

Table 5-17. Data Transfer Instructions — Binary Code Summary (Concluded)

Operand Binary Code Operation Notation

RR

Name

POP

0

1

0

1

r2

r1

0

RR ¬ (SP), RR ¬ (SP + 1)

L

H

SP ¬ SP + 2

SB

1

0

1

0

1

0

1

0

1

0

1

0

(SRB) ¬ (SP), SMB ¬ (SP + 1),

SP ¬ SP + 2

Table 5-18. Logic Instructions — Binary Code Summary

Operand Binary Code Operation Notation

Name

AND

A,#im

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

d3

1

d2

0

d1

0

1

d0

1

A ¬ A AND im

A,@HL

EA,RR

A ¬ A AND (HL)

1

0

EA ¬ EA AND RR

1

r2

1

r1

0

RRb,EA

A, #im

1

0

RRb ¬ RRb AND EA

A ¬ A OR im

0

r2

1

r1

0

OR

1

d3

1

d2

0

d1

1

d0

0

A, @HL

EA,RR

A ¬ A OR (HL)

1

0

EA ¬ EA OR RR

1

r2

1

r1

0

RRb,EA

A,#im

1

0

RRb ¬ RRb OR EA

A ¬ A XOR im

0

r2

1

r1

0

XOR

1

d3

1

d2

0

d1

1

d0

1

A,@HL

EA,RR

A ¬ A XOR (HL)

1

0

EA ¬ EA XOR (RR)

0

r2

1

r1

0

RRb,EA

A

1

0

RRb ¬ RRb XOR EA

A ¬ A

0

r2

1

r1

0

COM

1

5-18

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

Table 5-19. Arithmetic Instructions — Binary Code Summary

Binary Code Operation Notation

C, A ¬ A + (HL) + C

Name

ADC

Operand

A,@HL

0

1

d7

0

1

0

1

0

1

0

1

0

1

a7

1

0

1

0

1

0

1

0

1

d6

0

1

0

1

0

1

0

1

0

1

0

1

a6

1

0

1

0

1

0

1

0

d5

1

0

1

0

1

0

1

0

1

0

a5

0

1

0

1

0

1

0

d4

1

0

1

0

1

0

1

0

a4

1

0

1

0

EA,RR

C, EA ¬ EA + RR + C

1

r2

1

r1

0

RRb,EA

1

0

C, RRb ¬ RRb + EA + C

0

r2

d2

0

r1

d1

0

ADS

A, #im

d3

1

d0

1

A ¬ A + im; skip on carry

EA,#imm

EA ¬ EA + imm; skip on carry

d3

1

d2

1

d1

1

d0

1

A,@HL

EA,RR

A ¬ A+ (HL); skip on carry

EA ¬ EA + RR; skip on carry

1

0

1

r2

1

r1

0

RRb,EA

1

0

RRb ¬ RRb + EA; skip on carry

0

r2

1

r1

0

SBC

SBS

A,@HL

EA,RR

1

0

C,A ¬ A–(HL)–C

1

0

C, EA ¬ EA–RR–C

1

r2

1

r1

0

RRb,EA

1

0

C,RRb ¬ RRb–EA–C

0

r2

1

r1

0

A,@HL

EA,RR

1

A ¬ A–(HL); skip on borrow

EA ¬ EA–RR; skip on borrow

1

0

1

r2

1

r1

0

RRb,EA

1

0

RRb ¬ RRb–EA; skip on borrow

0

r2

1

r1

0

DECS

INCS

R

1

r0

0

R ¬ R–1; skip on borrow

RR

1

RR ¬ RR–1; skip on borrow

1

r2

0

r1

1

0

R

1

r0

0

R ¬ R+1; skip on carry

DA

1

DA ¬ DA+1; skip on carry

a3

1

a2

1

a1

0

a0

1

@HL

RRb

(HL) ¬ (HL)+1; skip on carry

RRb ¬ RRb+1; skip on carry

0

1

0

r2

r1

0

5-19

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

Table 5-20. Bit Manipulation Instructions — Binary Code Summary

Operand Binary Code Operation Notation

Skip if C = 1

Name

BTST

C

1

0

1

0

1

0

1

DA.b

b1 b0

Skip if DA.b = 1

a7 a6 a5 a4 a3

a2 a1 a0

1

0

1

Skip if mema.b = 1

mema.b *

memb.@L

@H+DA.b

DA.b

1

0

1

0

1

0

1

0

1

0

1

a5

1

Skip if [memb.7–2 + L.3–2].[L.1–0] = 1

Skip if [H + DA.3–0].b = 1

Skip if DA.b = 0

a4 a3 a2

0

1

b1 b0 a3

b1 b0

a2 a1 a0

BTSF

0

1

0

a7 a6 a5 a4 a3

a2 a1 a0

1

0

Skip if mema.b = 0

mema.b *

memb.@L

@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

a5

1

Skip if [memb.7–2 + L.3–2].[L.1–0] = 0

Skip if [H + DA.3–0].b = 0

a4 a3 a2

0

b1 b0 a3

a2 a1 a0

BTSTZ

1

0

1

Skip if mema.b = 1 and clear

mema.b *

memb.@L

1

Skip if [memb.7–2 + L.3–2].

[L.1–0] = 1 and clear

0

1

0

1

0

1

0

1

0

1

a5

1

a4 a3 a2

@H+DA.b

DA.b

1

0

1

Skip if [H + DA.3–0].b =1 and clear

DA.b ¬ 1

b1 b0 a3

b1 b0

a2 a1 a0

BITS

0

1

a7 a6 a5 a4 a3

a2 a1 a0

1

mema.b ¬ 1

mema.b *

memb.@L

@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

a5

1

[memb.7–2 + L.3–2].[L.1–0] ¬ 1

[H + DA.3–0].b ¬ 1

a4 a3 a2

1

b1 b0 a3

a2 a1 a0

5-20

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

Table 5-20. Bit Manipulation Instructions — Binary Code Summary (Continued)

Operand Binary Code Operation Notation

DA.b

Name

BITR

1

a7

1

a6

1

b1

a5

1

b0

a4

1

0

a3

1

0

a2

1

0

a1

1

0

a0

0

DA.b ¬ 0

mema.b ¬ 0

mema.b *

memb.@L

@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

a5

1

a4

1

a3

1

0

a2

0

[memb.7–2 + L3–2].[L.1–0] ¬ 0

[H + DA.3–0].b ¬ 0

1

b1

1

b0

1

a3

0

a2

1

a1

0

a0

1

BAND

C ¬ C AND mema.b

C,mema.b *

C,memb.@L

1

0

1

0

1

C ¬ C AND [memb.7–2 + L.3–2].

[L.1–0]

0

1

0

1

0

1

0

1

0

1

a5

0

a4

1

a3

0

a2

1

C,@H+DA.b

C,mema.b *

C,memb.@L

C ¬ C AND [H + DA.3–0].b

C ¬ C OR mema.b

b1

1

b0

1

a3

0

a2

1

a1

1

a0

0

BOR

1

0

1

0

C ¬ C OR [memb.7–2 + L.3–2].

[L.1–0]

0

1

0

1

0

1

0

1

0

1

a5

0

a4

1

a3

1

a2

0

C,@H+DA.b

C,mema.b *

C,memb.@L

C ¬ C OR [H + DA.3–0].b

C ¬ C XOR mema.b

b1

1

b0

1

a3

0

a2

1

a1

1

a0

1

BXOR

1

0

1

C ¬ C XOR [memb.7–2 + L.3–2].

[L.1–0]

0

1

0

1

0

1

0

1

a5

0

a4

1

a3

1

a2

1

C,@H+DA.b

C ¬ C XOR [H + DA.3–0].b

b1

b0

a3

a2

a1

a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

5-21

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

Table 5-20. Bit Manipulation Instructions — Binary Code Summary (Concluded)

Name

LDB

Operand

Binary Code

Operation Notation

mema.b ¬ C

1

0

mema.b,C *

memb.@L,C

@H+DA.b,C

1

0

1

0

1

0

1

0

1

0

1

a5

1

a4

1

0

a3

0

a2

0

memb.7–2 + [L.3–2]. [L.1–0] ¬ C

H+[DA.3–0].b ¬ (C)

1

b1

1

b0

1

a3

0

a2

1

a1

0

a0

0

C ¬ mema.b

C,mema.b *

C,memb.@L

C,@H+DA.b

1

0

1

0

1

0

1

0

1

0

a5

0

1

a4

1

0

a3

0

a2

0

C ¬ memb.7–2+[L.3–2] . [L.1–0]

C ¬ [H + DA.3–0].b

1

b1

b0

a3

a2

a1

a0

Second Byte

Bit Addresses

1

0

1

b1

b0

a3

a2

a1

a0

FB0H–FBFH

* mema.b

FF0H–FFFH

5-22

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction of the SAM47

instruction set. Information is arranged in a consistent format to improve readability and for use as a quick-

reference resource for application programmers.

If you are reading this user's manual for the first time, please just scan this very detailed information briefly in

order to acquaint yourself with the basic features of the instruction set. The information elements of the

instruction description format are as follows:

— Instruction name (mnemonic)

— Full instruction name

— Source/destination format of the instruction operand

— Operation overview (from the "High-Level Summary" table)

— Textual description of the instruction's effect

— Binary code overview (from the "Binary Code Summary" table)

— Programming example(s) to show how the instruction is used

5-23

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

ADC — Add with Carry

ADC

dst,src

Operation:

Operand

Operation Summary

Add indirect data memory to A with carry

Add register pair (RR) to EA with carry

Add EA to register pair (RRb) with carry

Bytes

Cycles

A,@HL

EA,RR

RRb,EA

1

2

1

2

Description: The source operand, along with the setting of the carry flag, is added to the destination operand

and the sum is stored in the destination. The contents of the source are unaffected. If there is an

overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag

is cleared.

If 'ADC A,@HL' is followed by an 'ADS A,#im' instruction in a program, ADC skips the ADS

instruction if an overflow occurs. If there is no overflow, the ADS instruction is executed normally.

(This condition is valid only for 'ADC A,@HL' instructions. If an overflow occurs following an

'ADS A,#im' instruction, the next instruction will not be skipped.)

Operand

A,@HL

Binary Code

Operation Notation

C, A ¬ A + (HL) + C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

EA,RR

C, EA ¬ EA + RR + C

r2 r1

RRb,EA

1

0

C, RRb ¬ RRb + EA + C

r2 r1

Examples:

1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag is set to "1":

SCF

ADC

JPS

; C ¬ "1"

EA,HL

XXX

; EA ¬ 0C3H + 0AAH + 1H = 6EH, C ¬ "1"

; Jump to XXX;no skip after ADC

2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag is cleared to "0":

RCF

ADC

JPS

; C ¬ "0"

EA,HL

XXX

; EA ¬ 0C3H + 0AAH + 0H = 6DH, C ¬ "1"

; Jump to XXX; no skip after ADC

5-24

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

ADC — Add with Carry

ADC

(Continued)

Examples:

3. If ADC A,@HL is followed by an ADS A,#im, the ADC skips on carry to the instruction

immediately after the ADS. An ADS instruction immediately after the ADC does not skip

even if an overflow occurs. This function is useful for decimal adjustment operations.

a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H):

RCF

LD

ADS

ADC

ADS

JPS

; C ¬ "0"

; A ¬ 8H

A,#8H

A,#6H

A,@HL

A,#0AH

XXX

; A ¬ 8H + 6H = 0EH

; A ¬ 0EH + 9H + C(0), C ¬ "1"

; Skip this instruction because C = "1" after ADC result

b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H):

RCF

LD

; C ¬ "0"

; A ¬ 3H

A,#3H

ADS

ADC

ADS

A,#6H

A,@HL

A,#0AH

; A ¬ 3H + 6H = 9H

; A ¬ 9H + 4H + C(0) = 0DH

; No skip. A ¬ 0DH + 0AH = 7H

; (The skip function for 'ADS A,#im' is inhibited after an

; 'ADC A,@HL' instruction even if an overflow occurs.)

JPS

XXX

5-25

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

ADS — Add and Skip on Overflow

ADS

dst,src

Operation:

Operand

Operation Summary

Bytes

Cycles

1 + S

2 + S

1 + S

2 + S

A, #im

Add 4-bit immediate data to A and skip on overflow

Add 8-bit immediate data to EA and skip on overflow

Add indirect data memory to A and skip on overflow

1

2

1

2

EA, #imm

A,@HL

EA,RR

Add register pair (RR) contents to EA and skip on

overflow

RRb, EA

Add EA to register pair (RRb) and skip on overflow

2

2 + S

Description: The source operand is added to the destination operand and the sum is stored in the destination.

The contents of the source are unaffected. If there is an overflow from the most significant bit of

the result, the skip signal is generated and a skip is executed, but the carry flag value is

unaffected.

If 'ADS A,#im' follows an 'ADC A,@HL' instruction in a program, ADC skips the ADS instruction

if an overflow occurs. If there is no overflow, the ADS instruction is executed normally. This skip

condition is valid only for 'ADC A,@HL' instructions, however. If an overflow occurs following an

ADS instruction, the next instruction is not skipped.

Operand

A, #im

Binary Code

Operation Notation

A ¬ A + im; skip on overflow

EA ¬ EA + imm; skip on overflow

1

0

1

0

d3 d2 d1 d0

EA,#imm

1

0

1

d7 d6 d5 d4 d3 d2 d1 d0

A,@HL

EA,RR

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A ¬ A + (HL); skip on overflow

EA ¬ EA + RR; skip on overflow

r2 r1

RRb,EA

1

0

RRb ¬ RRb + EA; skip on overflow

r2 r1

Examples:

1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag = "0":

ADS

EA,HL

; EA ¬ 0C3H + 0AAH = 6DH

; ADS skips on overflow, but carry flag value is not

; affected.

JPS

XXX

YYY

; This instruction is skipped since ADS had an overflow.

; Jump to YYY.

5-26

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

ADS — Add and Skip on Overflow

ADS

(Continued)

Examples:

2. If the extended accumulator contains the value 0C3H, register pair HL the value 12H, and

the carry flag = "0":

ADS

JPS

EA,HL

XXX

; EA ¬ 0C3H + 12H = 0D5H

; Jump to XXX; no skip after ADS.

3. If 'ADC A,@HL' is followed by an 'ADS A,#im', the ADC skips on overflow to the instruction

mmediately after the ADS. An 'ADS A,#im' instruction immediately after the 'ADC A,@HL'

does not skip even if overflow occurs. This function is useful for decimal adjustment

operations.

a. 8 + 9 decimal addition (the contents of the address specified by the HL register is 9H):

RCF

LD

ADS

ADC

ADS

JPS

; C ¬ "0"

; A ¬ 8H

A,#8H

A,#6H

A,@HL

A,#0AH

XXX

; A ¬ 8H + 6H = 0EH

; A ¬ 0EH + 9H + C(0) = 7H, C ¬ "1"

; Skip this instruction because C = "1" after ADC result.

b. 3 + 4 decimal addition (the contents of the address specified by the HL register is 4H):

RCF

LD

; C ¬ "0"

; A ¬ 3H

A,#3H

ADS

ADC

ADS

A,#6H

A,@HL

A,#0AH

; A ¬ 3H + 6H = 9H

; A ¬ 9H + 4H + C(0) = 0DH, C ¬ "0"

; No skip. A ¬ 0DH + 0AH = 7H

; (The skip function for 'ADS A,#im' is inhibited after an

; 'ADC A,@HL' instruction even if an overflow occurs.)

JPS

XXX

5-27

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

AND — Logical AND

AND

dst,src

Operation:

Operand

Operation Summary

Logical-AND A immediate data to A

Logical-AND A indirect data memory to A

Logical-AND register pair (RR) to EA

Logical-AND EA to register pair (RRb)

Bytes

Cycles

A,#im

2

1

2

1

2

A,@HL

EA,RR

RRb,EA

Description: The source operand is logically ANDed with the destination operand. The result is stored in the

destination. The logical AND operation results in a "1" whenever the corresponding bits in the two

operands are both "1"; otherwise a "0" is stored in the corresponding destination bit. The contents

of the source are unaffected.

Operand

A,#im

Binary Code

Operation Notation

A ¬ A AND im

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

d3 d2 d1 d0

A,@HL

EA,RR

1

0

1

0

1

0

A ¬ A AND (HL)

EA ¬ EA AND RR

r2 r1

RRb,EA

1

0

RRb ¬ RRb AND EA

r2 r1

Example:

If the extended accumulator contains the value 0C3H (11000011B) and register pair HL the value

55H (01010101B), the instruction

AND

EA,HL

leaves the value 41H (01000001B) in the extended accumulator EA .

5-28

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BAND — Bit Logical AND

BAND

C,src.b

Operation:

Operand

Operation Summary

Bytes

Cycles

C,mema.b

Logical-AND carry flag with memory bit

2

C,memb.@L

C,@H+DA.b

Description: The specified bit of the source is logically ANDed with the carry flag bit value. If the Boolean

value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry

flag setting is left unaltered. The bit value of the source operand is not affected.

Operand

Binary Code

Operation Notation

C ¬ C AND mema.b

1

0

1

0

1

C,mema.b *

C,memb.@L

C,@H+DA.b

1

0

C ¬ C AND [memb.7–2 + L.3–2].

[L.1–0]

0

1

0

1

0

1

0

1

a5 a4 a3 a2

0

1

0

1

C ¬ C AND [H + DA.3–0].b

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

Examples:

1. The following instructions set the carry flag if P1.0 (port 1.0) is equal to "1" (and assuming

the carry flag is already set to "1"):

SMB

15

; C ¬ "1"

BAND

C,P1.0

; If P1.0 = "1", C ¬ "1"

; If P1.0 = "0", C ¬ "0"

2. Assume the P1 address is FF1H and the value for register L is 5H (0101B). The address

(memb.7–2) is 111100B; (L.3–2) is 01B. The resulting address is 11110001B or FF1H,

specifying P1. The bit value for the BAND instruction, (L.1–0) is 01B which specifies bit 1.

Therefore, P1.@L = P1.1:

LD

L,#5H

BAND

C,P1.@L

; P1.@L is specified as P1.1

; C AND P1.1

5-29

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

BAND — Bit Logical AND

BAND

(Continued)

Examples:

3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and

FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BAND

instruction is 3. Therefore, @H+FLAG = 20H.3:

FLAG

LD

EQU

H,#2H

20H.3

BAND

C,@H+FLAG

; C AND FLAG (20H.3)

5-30

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BITR — Bit Reset

BITR

dst.b

Operation:

Operand

Operation Summary

Bytes

Cycles

DA.b

Clear specified memory bit to logic zero

2

mema.b

memb.@L

@H+DA.b

Description: A BITR instruction clears to logic zero (resets) the specified bit within the destination operand. No

other bits in the destination are affected.

Operand

DA.b

Binary Code

b1 b0

a7 a6 a5 a4 a3 a2 a1 a0

Operation Notation

DA.b ¬ 0

1

0

1

0

mema.b ¬ 0

mema.b *

memb.@L

@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

[memb.7–2 + L3–2].[L.1–0] ¬ 0

[H + DA.3–0].b ¬ 0

a5 a4 a3 a2

1

0

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

Examples:

1. If the Bit location 30H.2 in the RAM has a current value of "1". The following instruction

clears the third bit of location 30H to "0":

BITR

2. You can use BITR in the same way to manipulate a port address bit:

BITR P0.0 ; P0.0 ¬ "0"

30H.2

; 30H.2 ¬ "0"

5-31

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

BITR — Bit Reset

BITR

(Continued)

Examples:

3. For clearing P0.2, P0.3, and P1.0–P1.3 to "0":

LD

L,#2H

BP2

BITR

P0.@L

; First, P0.@2H = P0.2

; (111100B) + 00B.10B = 0F0H.2

INCS

CPSE

JR

L

L,#8H

BP2

4. If bank 0, location 0A0H.0 is cleared (and regardless of whether the EMB value is logic

zero), BITR has the following effect:

FLAG

EQU

0A0H.0

•

BITR

EMB

•

LD

BITR

H,#0AH

@H+FLAG

;

Bank 0 (AH + 0H).0 = 0A0H.0 ¬ "0”

NOTE: Since the BITR instruction is used for output functions, the pin names used in the examples above may change for

different devices in the SAM47 product family.

5-32

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BITS — Bit Set

BITS

dst.b

Operation:

Operand

Operation Summary

Set specified memory bit

Bytes

Cycles

DA.b

2

mema.b

memb.@L

@H+DA.b

Description: This instruction sets the specified bit within the destination without affecting any other bits in the

destination. BITS can manipulate any bit that is addressable using direct or indirect addressing

modes.

Operand

DA.b

Binary Code

b1 b0

a7 a6 a5 a4 a3 a2 a1 a0

Operation Notation

DA.b ¬ 1

1

0

1

mema.b ¬ 1

mema.b *

memb.@L

@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

[memb.7–2 + L.3–2].b [L.1–0] ¬ 1

[H + DA.3–0].b ¬ 1

a5 a4 a3 a2

1

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

Examples:

1. If the bit location 30H.2 in the RAM has a current value of "0", the following instruction sets

the second bit of location 30H to "1".

BITS

2. You can use BITS in the same way to manipulate a port address bit:

BITS P0.0 ; P0.0 ¬ "1"

30H.2

; 30H.2 ¬ "1"

5-33

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

BITS — Bit Set

BITS

(Continued)

Examples:

3. For setting P0.2, P0.3, and P1.0–P1.3 to "1":

LD

L,#2H

BP2

BITS

P0.@L

; First, P0.@02H = P0.2

; (111100B) + 00B.10B = 0F0H.2

INCS

CPSE

JR

L

L,#8H

BP2

4. If bank 0, location 0A0H.0, is set to "1" and the EMB = "0", BITS has the following effect:

FLAG

EQU

•

0A0H.0

EMB

BITR

•

LD

BITS

H,#0AH

@H+FLAG ; Bank 0 (AH + 0H).0 = 0A0H.0 ¬ "1"

NOTE: Since the BITS instruction is used for output functions, pin names used in the examples above may change for

different devices in the SAM47 product family.

5-34

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BOR — Bit Logical OR

BOR

C,src.b

Operation:

Operand

Operation Summary

Bytes

Cycles

C,mema.b

Logical-OR carry with specified memory bit

2

C,memb.@L

C,@H+DA.b

Description: The specified bit of the source is logically ORed with the carry flag bit value. The value of the

source is unaffected.

Operand

Binary Code

Operation Notation

C ¬ C OR mema.b

1

0

1

0

C,mema.b *

C,memb.@L

C,@H+DA.b

1

0

C ¬ C OR [memb.7–2 + L.3–2].

[L.1–0]

0

1

0

1

0

1

0

1

a5 a4 a3 a2

0

1

0

C ¬ C OR [H + DA.3–0].b

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

Examples:

1. The carry flag is logically ORed with the P1.0 value:

RCF

BOR

; C ¬ "0"

C,P1.0

; If P1.0 = "1", then C ¬ "1"; if P1.0 = "0", then C ¬ "0"

2. The P1 address is FF1H and register L contains the value 1H (0001B). The address

(memb.7–2) is 111100B and (L.3–2) = 00B. The resulting address is 11110000B or FF0H,

specifying P0. The bit value for the BOR instruction, (L.1–0) is 01B which specifies bit 1.

Therefore, P1.@L = P0.1:

LD

L,#1H

BOR

C,P1.@L

; P1.@L is specified as P0.1; C OR P0.1

5-35

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

BOR — Bit Logical OR

BOR

(Continued)

Examples:

3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and

FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR

instruction is 3. Therefore, @H+FLAG = 20H.3:

FLAG

LD

EQU

H,#2H

20H.3

BOR

C,@H+FLAG

; C OR FLAG (20H.3)

5-36

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BTSF — Bit Test and Skip on False

BTSF

dst.b

Operation:

Operand

Operation Summary

Bytes

Cycles

2 + S

DA.b

Test specified memory bit and skip if bit equals "0"

2

mema.b

memb.@L

@H+DA.b

Description: The specified bit within the destination operand is tested. If it is a "0", the BTSF instruction skips

the instruction which immediately follows it; otherwise the instruction following the BTSF is

executed. The destination bit value is not affected.

Operand

DA.b

Binary Code

b1 b0

a7 a6 a5 a4 a3 a2 a1 a0

Operation Notation

Skip if DA.b = 0

1

0

1

0

1

0

Skip if mema.b = 0

mema.b *

memb.@L

Skip if [memb.7–2 + L.3-2].

[L.1–0] = 0

0

1

0

1

0

1

0

1

a5 a4 a3 a2

@H + DA.b

1

0

Skip if [H + DA.3–0].b = 0

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FF0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

Examples:

1. If RAM bit location 30H.2 is set to “0”, the following instruction sequence will cause the

program to continue execution from the instruction identifed as LABEL2:

BTSF

RET

JP

30H.2

; If 30H.2 = "0", then skip

; If 30H.2 = "1", return

LABEL2

2. You can use BTSF in the same way to test a port pin address bit:

BTSF

RET

JP

P1.0

; If P1.0 = "0", then skip

; If P1.0 = "1", then return

LABEL3

5-37

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

BTSF — Bit Test and Skip on False

BTSF

(Continued)

Examples:

3. P0.2, P0.3 and P1.0–P1.3 are tested:

LD

L,#2H

BP2

BTSF

P0.@L

; First, P1.@02H = P0.2

; (111100B) + 00B.10B = 0F0H.2

RET

INCS

CPSE

JR

L

L,#8H

BP2

4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTSF has the

following effect:

FLAG

EQU

0A0H.0

•

BITR

EMB

•

LD

H,#0AH

BTSF

@H+FLAG

;

If bank 0 (AH + 0H).0 = 0A0H.0 = "0", then skip

RET

•

5-38

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BTST — Bit Test and Skip on True

BTST

dst.b

Operation:

Operand

Operation Summary

Bytes

Cycles

1 + S

2 + S

C

Test carry bit and skip if set (= "1")

1

2

DA.b

Test specified bit and skip if memory bit is set

mema.b

memb.@L

@H+DA.b

Description: The specified bit within the destination operand is tested. If it is "1", the instruction that

immediately follows the BTST instruction is skipped; otherwise the instruction following the BTST

instruction is executed. The destination bit value is not affected.

Operand

Binary Code

Operation Notation

Skip if C = 1

C

1

0

1

0

1

0

1

DA.b

b1 b0

Skip if DA.b = 1

a7 a6 a5 a4 a3 a2 a1 a0

1

0

1

Skip if mema.b = 1

mema.b *

memb.@L

Skip if [memb.7–2 + L.3–2].

[L.1–0] = 1

0

1

0

1

0

1

0

1

a5 a4 a3 a2

@H+DA.b

* mema.b

1

0

1

Skip if [H + DA.3–0].b = 1

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

Examples:

1. If RAM bit location 30H.2 is set to “0”, the following instruction sequence will execute the

RET instruction:

BTST

RET

JP

30H.2

; If 30H.2 = "1", then skip

; If 30H.2 = "0", return

LABEL2

5-39

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

BTST — Bit Test and Skip on True

BTST

(Continued)

2. You can use BTST in the same way to test a port pin address bit:

Examples:

BTST

RET

JP

P1.0

; If P1.0 = "1", then skip

; If P1.0 = "0", then return

LABEL3

3. P0.2, P0.3 and P1.0–P1.3 are tested:

LD

L,#2H

BP2

BTST

P0.@L

; First, P0.@02H = P0.2

; (111100B) + 00B.10B = 0F0H.2

RET

INCS

CPSE

JR

L

L,#8H

BP2

4. Bank 0, location 0A0H.0, is tested and (regardless of the current EMB value) BTST has the

following effect:

FLAG

EQU

0A0H.0

•

BITR

EMB

•

LD

H,#0AH

BTST

@H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", then skip

RET

•

5-40

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BTSTZ — Bit Test and Skip on True; Clear Bit

BTSTZ

dst.b

Operation:

Operand

Operation Summary

Bytes

Cycles

2 + S

mema.b

Test specified bit; skip and clear if memory bit is set

2

memb.@L

@H+DA.b

Description: The specified bit within the destination operand is tested. If it is a "1", the instruction immediately

following the BTSTZ instruction is skipped; otherwise the instruction following the BTSTZ is

executed. The destination bit value is cleared.

Operand

Binary Code

Operation Notation

1

0

1

Skip if mema.b = 1 and clear

mema.b *

memb.@L

@H+DA.b

1

Skip if [memb.7–2 + L.3–2].

[L.1–0] = 1 and clear

0

1

0

1

0

1

0

1

a5 a4 a3 a2

1

0

1

Skip if [H + DA.3–0].b =1 and clear

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

Examples:

1. Port pin P0.0 is toggled by checking the P0.0 value (level):

BTSTZ

BITS

JP

P0.0

LABEL3

; If P0.0 = "1", then P0.0 ¬ "0" and skip

; If P0.0 = "0", then P0.0 ¬ "1"

2. For toggling P2.2, P2.3, and P3.0–P3.3:

LD

BTSTZ

L,#0AH

P2.@L

BP2

; First, P2.@0AH = P2.2

; (111100B) + 10B.10B = 0F2H.2

BITS

INCS

JR

P2.@L

L

BP2

5-41

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

BTSTZ — Bit Test and Skip on True; Clear Bit

BTSTZ

(Continued)

Examples:

3. Bank 0, location 0A0H.0, is tested and EMB = "0":

FLAG

EQU

0A0H.0

•

BITR

EMB

•

LD

H,#0AH

BTSTZ

BITS

@H+FLAG ; If bank 0 (AH + 0H).0 = 0A0H.0 = "1", clear and skip

@H+FLAG ; If 0A0H.0 = "0", then 0A0H.0 ¬ "1"

5-42

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

BXOR — Bit Exclusive OR

BXOR

C,src.b

Operation:

Operand

Operation Summary

Bytes

Cycles

C,mema.b

Exclusive-OR carry with memory bit

2

C,memb.@L

C,@H+DA.b

Description: The specified bit of the source is logically XORed with the carry bit value. The resultant bit is

written to the carry flag. The source value is unaffected.

Operand

Binary Code

Operation Notation

C ¬ C XOR mema.b

1

0

1

C,mema.b *

C,memb.@L

C,@H+DA.b

1

0

C ¬ C XOR [memb.7–2 + L.3-2].

[L.1–0]

0

1

0

1

0

1

0

1

a5 a4 a3 a2

0

1

C ¬ C XOR [H + DA.3–0].b

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

Examples:

1. The carry flag is logically XORed with the P1.0 value:

RCF

; C ¬ "0"

BXOR

C,P1.0

; If P1.0 = "1", then C ¬ "1"; if P1.0 = "0", then C ¬ "0"

2. The P1 address is FF1H and register L contains the value 1H (0001B). The address

(memb.7–2) is 111100B and (L.3–2) = 00B. The resulting address is 11110000B or FF0H,

specifying P0. The bit value for the BXOR instruction, (L.1–0) is 01B which specifies bit 1.

Therefore, P1.@L = P0.1:

LD

BXOR

L,#0001B

C,P0.@L

; P1.@L is specified as P0.1; C XOR P0.1

5-43

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

BXOR — Bit Exclusive OR

BXOR

(Continued)

Examples:

3. Register H contains the value 2H and FLAG = 20H.3. The address of H is 0010B and

FLAG(3–0) is 0000B. The resulting address is 00100000B or 20H. The bit value for the BOR

instruction is 3. Therefore, @H+FLAG = 20H.3:

FLAG

LD

EQU

H,#2H

20H.3

BXOR

C,@H+FLAG

; C XOR FLAG (20H.3)

5-44

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

CALL — Call Procedure

CALL

dst

Operation:

Operand

ADR

Operation Summary

Call direct in page (14 bits)

Bytes

Cycles

3

4

Description: CALL calls a subroutine located at the destination address. The instruction adds three to the

program counter to generate the return address and then pushes the result onto the stack,

decreasing the stack pointer by six. The EMB and ERB are also pushed to the stack. Program

execution continues with the instruction at this address. The subroutine may therefore begin

anywhere in the full 16 K byte program memory address space.

Operand

ADR

Binary Code

Operation Notation

[(SP–1) (SP–2)] ¬ EMB, ERB

[(SP–3) (SP–4)] ¬ PC7–0

[(SP–5) (SP–6)] ¬ PC13–8

1

0

1

0

1

0

1

a13 a12 a11 a10 a9 a8

a7 a6 a5 a4 a3 a2 a1 a0

Example:

The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location

0E3FH. Executing the instruction

CALL PLAY

at location 0123H will generate the following values:

SP

0FFH

0FEH

=

0FAH

0H

EMB, ERB

0FDH = 2H

0FCH = 3H

0FBH

0FAH

PC

=

0H

1H

0E3FH

Data is written to stack locations 0FFH–0FAH as follows:

SP - 6

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP ®

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(00H)

PC11 – PC8

0

PC13 PC12

PC3 – PC0

PC7 – PC4

0

EMB ERB

0

5-45

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

CALLS — Call Procedure (Short)

CALLS

dst

Operation:

Operand

ADR

Operation Summary

Call direct in page (11 bits)

Bytes

Cycles

2

3

Description: The CALLS instruction unconditionally calls a subroutine located at the indicated address. The

instruction increments the PC twice to obtain the address of the following instruction. Then, it

pushes the result onto the stack, decreasing the stack pointer six times. The higher bits of the

PC, with the exception of the lower 11 bits, are cleared. The CALLS instruction can be used in

the all range (0000H–3FFFH), but the subroutine call must therefore be located within the 2 K

byte block (0000H–07FFH) of program memory.

Operand

ADR

Binary Code

Operation Notation

[(SP–1) (SP–2)] ¬ EMB, ERB

[(SP–3) (SP–4)] ¬ PC7–0

[(SP–5) (SP–6)] ¬ PC14–8

1

0

1

a10 a9 a8

a7 a6 a5 a4 a3 a2 a1 a0

Example:

The stack pointer value is 00H and the label 'PLAY' is assigned to program memory location

0345H. Executing the instruction

CALLS

PLAY

at location 0123H will generate the following values:

SP

0FFH

0FEH

=

0FAH

0H

EMB, ERB

0FDH = 2H

0FCH = 3H

0FBH

0FAH

PC

=

0H

1H

0345H

Data is written to stack locations 0FFH–0FAH as follows:

SP - 6

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP ®

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(00H)

PC11 – PC8

PC14 PC13 PC12

PC3 – PC0

0

PC7 – PC4

0

EMB ERB

0

5-46

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

CCF — Complement Carry Flag

CCF

Operation:

Operand

Operation Summary

Complement carry flag

Bytes

Cycles

–

1

Description: The carry flag is complemented; if C = "1" it is changed to C = "0" and vice-versa.

Operand

Binary Code

Operation Notation

–

1

0

1

0

1

0

C ¬ C

Example:

If the carry flag is logic zero, the instruction

CCF

changes the value to logic one.

5-47

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

COM — Complement Accumulator

COM

A

Operation:

Operand

Operation Summary

Complement accumulator (A)

Bytes

Cycles

A

2

Description: The accumulator value is complemented; if the bit value of A is "1", it is changed to "0" and vice

versa.

Operand

Binary Code

Operation Notation

A

1

0

1

0

1

0

1

A ¬ A

Example:

If the accumulator contains the value 4H (0100B), the instruction

COM

leaves the value 0BH (1011B) in the accumulator.

A

5-48

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

CPSE — Compare and Skip if Equal

CPSE

dst,src

Operation:

Operand

Operation Summary

Bytes

Cycles

2 + S

1 + S

2 + S

R,#im

Compare and skip if register equals #im

Compare and skip if indirect data memory equals #im

Compare and skip if A equals R

2

1

2

@HL,#im

A,R

A,@HL

EA,@HL

EA,RR

Compare and skip if A equals indirect data memory

Compare and skip if EA equals indirect data memory

Compare and skip if EA equals RR

Description: CPSE compares the source operand (subtracts it from) the destination operand, and skips the

next instruction if the values are equal. Neither operand is affected by the comparison.

Operand

R,#im

Binary Code

Operation Notation

Skip if R = im

1

0

1

0

1

0

1

d3 d2 d1 d0

r2 r1 r0

@HL,#im

A,R

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Skip if (HL) = im

Skip if A = R

d3 d2 d1 d0

1

0

1

r2 r1 r0

A,@HL

0

1

0

1

0

1

0

Skip if A = (HL)

EA,@HL

Skip if A = (HL), E = (HL+1)

EA,RR

Skip if EA = RR

r2 r1

Example:

The extended accumulator contains the value 34H and register pair HL contains 56H. The

second instruction (RET) in the instruction sequence

CPSE

RET

EA,HL

is not skipped. That is, the subroutine returns since the result of the comparison is 'not equal.'

5-49

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

DECS — Decrement and Skip on Borrow

DECS

dst

Operation:

Operand

Operation Summary

Decrement register (R); skip on borrow

Decrement register pair (RR); skip on borrow

Bytes

Cycles

1 + S

R

1

2

RR

2 + S

Description: The destination is decremented by one. An original value of 00H will underflow to 0FFH. If a

borrow occurs, a skip is executed. The carry flag value is unaffected.

Operand

Binary Code

Operation Notation

R ¬ R–1; skip on borrow

RR ¬ RR–1; skip on borrow

R

0

1

0

1

r2 r1 r0

RR

1

0

r2 r1

Examples:

1. Register pair HL contains the value 7FH (01111111B). The following instruction leaves the

value 7EH in register pair HL:

DECS

HL

2. Register A contains the value 0H. The following instruction sequence leaves the value 0FFH

in register A. Since a "borrow" occurs, the 'CALL PLAY1' instruction is skipped and the 'CALL

PLAY2' instruction is executed:

DECS

CALL

A

; "Borrow" occurs

; Skipped

; Executed

PLAY1

PLAY2

5-50

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

DI — Disable Interrupts

DI

Operation:

Operand

Operation Summary

Disable all interrupts

Bytes

Cycles

–

2

Description: Bit 3 of the interrupt priority register IPR, IME, is cleared to logic zero, disabling all interrupts.

Interrupts can still set their respective interrupt status latches, but the CPU will not directly

service them.

Operand

Binary Code

Operation Notation

IME ¬ 0

–

1

0

1

0

1

0

1

0

Example:

If the IME bit (bit 3 of the IPR) is logic one (e.g., all instructions are enabled), the instruction

DI

sets the IME bit to logic zero, disabling all interrupts.

5-51

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

EI — Enable Interrupts

EI

Operation:

Operand

Operation Summary

Enable all interrupts

Bytes

Cycles

–

2

Description: Bit 3 of the interrupt priority register IPR (IME) is set to logic one. This allows all interrupts to be

serviced when they occur, assuming they are enabled. If an interrupt's status latch was

previously enabled by an interrupt, this interrupt can also be serviced.

Operand

Binary Code

Operation Notation

–

1

0

1

0

1

0

1

0

IM ¬ 1

Example:

If the IME bit (bit 3 of the IPR) is logic zero (e.g., all instructions are disabled), the instruction

EI

sets the IME bit to logic one, enabling all interrupts.

5-52

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

IDLE — Idle Operation

IDLE

Operation:

Operand

Operation Summary

Engage CPU idle mode

Bytes

Cycles

–

2

Description: IDLE causes the CPU clock to stop while the system clock continues oscillating by setting bit 2 of

the power control register (PCON). After an IDLE instruction has been executed, peripheral hard-

ware remains operative.

In application programs, an IDLE instruction must be immediately followed by at least three NOP

instructions. This ensures an adequate time interval for the clock to stabilize before the next

instruction is executed. If three or more NOP instructions are not used after IDLE instruction,

leakage current could be flown because of the floating state in the internal bus.

Operand

Binary Code

Operation Notation

PCON.2 ¬ 1

–

1

0

1

0

1

0

1

0

1

Example:

The instruction sequence

IDLE

NOP

sets bit 2 of the PCON register to logic one, stopping the CPU clock. The three NOP instructions

provide the necessary timing delay for clock stabilization before the next instruction in the

program sequence is executed.

5-53

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

INCS — Increment and Skip on Carry

INCS

dst

Operation:

Operand

Operation Summary

Increment register (R); skip on carry

Bytes

Cycles

1 + S

2 + S

1 + S

R

1

2

1

DA

Increment direct data memory; skip on carry

Increment indirect data memory; skip on carry

Increment register pair (RRb); skip on carry

@HL

RRb

Description: The instruction INCS increments the value of the destination operand by one. An original value

of 0FH will, for example, overflow to 00H. If a carry occurs, the next instruction is skipped. The

carry flag value is unaffected.

Operand

Binary Code

Operation Notation

R ¬ R + 1; skip on carry

DA ¬ DA + 1; skip on carry

R

0

1

0

1

0

1

r2 r1 r0

DA

0

1

0

a7 a6 a5 a4 a3 a2 a1 a0

@HL

RRb

1

0

1

0

1

0

1

0

1

0

1

0

1

0

(HL) ¬ (HL) + 1; skip on carry

RRb ¬ RRb + 1; skip on carry

r2 r1

Example:

Register pair HL contains the value 7EH (01111110B). RAM location 7EH contains 0FH. The

instruction sequence

INCS

@HL

HL

@HL

; 7EH ¬ "0"

; Skip

; 7EH ¬ "1"

leaves the register pair HL with the value 7EH and RAM location 7EH with the value 1H. Since a

carry occurred, the second instruction is skipped. The carry flag value remains unchanged.

5-54

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

IRET — Return from Interrupt

IRET

Operation:

Operand

Operation Summary

Return from interrupt

Bytes

Cycles

–

1

3

Description: IRET is used at the end of an interrupt service routine. It pops the PC values successively from

the stack and restores them to the program counter. The stack pointer is incremented by six and

the PSW, enable memory bank (EMB) bit, and enable register bank (ERB) bit are also

automatically restored to their pre-interrupt values. Program execution continues from the

resulting address, which is generally the instruction immediately after the point at which the

interrupt request was detected. If a lower-level or same-level interrupt was pending when the

IRET was executed, IRET will be executed before the pending interrupt is processed.

Since the 'a14' bit of an interrupt return address is not stored in the stack, this bit location is

always interpreted as a logic zero. The starting address in the ROM must for this reason be

located in 0000H–3FFFH.

Operand

Binary Code

Operation Notation

–

1

0

1

0

1

0

1

PC13–8 ¬ (SP + 1) (SP)

PC7–0 ¬ (SP + 3) (SP + 2)

PSW ¬ (SP + 5) (SP + 4)

SP ¬ SP + 6

Example:

The stack pointer contains the value 0FAH. An interrupt is detected in the instruction at location

0123H. RAM locations 0FDH, 0FCH, and 0FAH contain the values 2H, 3H, and 1H, respectively.

The instruction

IRET

leaves the stack pointer with the value 00H and the program returns to continue execution at

location 0123H.

During a return from interrupt, data is popped from the stack to the program counter. The data in

stack locations 0FFH–0FAH is organized as follows:

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(00H)

PC11 – PC8

SP ®

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

0

PC13 PC12

PC3 – PC0

PC7 – PC4

IS1

C

IS0

EMB ERB

SC1 SC0

SC2

5-55

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

JP — Jump

JP

dst

Operation:

Operand

ADR

Operation Summary

Jump to direct address (14 bits)

Bytes

Cycles

3

Description: JP causes an unconditional branch to the indicated address by replacing the contents of the

program counter with the address specified in the destination operand. The destination can be

anywhere in the 16 K byte program memory address space.

Operand

ADR

Binary Code

Operation Notation

1

0

1

0

1

0

1

PC13–0 ¬ ADR13–0

a13 a12 a11 a10 a9 a8

a7 a6 a5 a4 a3 a2 a1 a0

Example:

The label 'SYSCON' is assigned to the instruction at program location 07FFH. The instruction

JP SYSCON

at location 0123H will load the program counter with the value 07FFH.

5-56

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

JPS — Jump (Short)

JPS

dst

Operation:

Operand

ADR

Operation Summary

Jump direct in page (12 bits)

Bytes

Cycles

2

Description: JPS causes an unconditional branch to the indicated address with the 4 K byte program memory

address space. Bits 0–11 of the program counter are replaced with the directly specified address.

The destination address for this jump is specified to the assembler by a label or by an actual

address in program memory.

Operand

ADR

Binary Code

a11 a10 a9 a8

a7 a6 a5 a4 a3 a2 a1 a0

Operation Notation

1

0

1

PC13–0 ¬ PC13–12+ADR11–0

Example:

The label 'SUB' is assigned to the instruction at program memory location 00FFH. The instruction

JPS SUB

at location 0EABH will load the program counter with the value 00FFH. Normally, the JPS

instruction jumps to the address in the block in which the instruction is located. If the first byte of

the instruction code is located at address xFFEH or xFFFH, the instruction will jump to the next

block. If the instruction 'JPS SUB' were located instead at program memory address 0FFEH or

0FFFH, the instruction 'JPS SUB' would load the PC with the value 10FFH, causing a program

malfunction.

5-57

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

JR — Jump Relative (Very Short)

JR

dst

Operation:

Operand

Operation Summary

Branch to relative immediate address

Branch relative to contents of WX register

Branch relative to contents of EA

Bytes

Cycles

#im

1

2

3

@WX

@EA

Description: JR causes the relative address to be added to the program counter and passes control to the

instruction whose address is now in the PC. The range of the relative address is current PC – 15

to current PC + 16. The destination address for this jump is specified to the assembler by a label,

an actual address, or by immediate data using a plus sign (+) or a minus sign (–).

For immediate addressing, the (+) range is from 2 to 16 and the (–) range is from –1 to –15. If a

0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an

error.

For JR @WX and JR @EA branch relative instructions, the valid range for the relative address is

0H–0FFH. The destination address for these jumps can be specified to the assembler by a label

that lies anywhere within the current 256-byte block.

Normally, the 'JR @WX' and 'JR @EA' instructions jump to the address in the page in which the

instruction is located. However, if the first byte of the instruction code is located at address

xxFEH or xxFFH, the instruction will jump to the next page.

Operand

#im *

Binary Code

Operation Notation

PC13–0 ¬ ADR (PC–15 to

PC+16)

@WX

@EA

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

PC13–0 ¬ PC13–8 + (WX)

PC13–0 ¬ PC13–8 + (EA)

First Byte

Condition

PC ¬ PC+2 to PC+16

PC ¬ PC–1 to PC–15

0

1

0

a3 a2 a1 a0

* JR #im

5-58

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

JR — Jump Relative (Very Short)

JR

(Continued)

Examples:

1. A short form for a relative jump to label 'KK' is the instruction

JR

KK

where 'KK' must be within the allowed range of current PC–15 to current PC+16. The JR

instruction has in this case the effect of an unconditional JP instruction.

2. In the following instruction sequence, if the instruction 'LD WX, #02H' were to be executed in

place of 'LD WX,#00H', the program would jump to 1004H and 'JPS CCC' would be

executed. If 'LD WX,#03H' were to be executed, the jump would be to1006H and 'JPS DDD'

would be executed.

ORG

1000H

JPS

LD

AAA

BBB

CCC

DDD

XXX

WX,#00H ; WX ¬ 00H

LD

EA,WX

ADS

JR

WX,EA

@WX

; WX ¬ (WX) + (EA)

; Current PC12–8 (10H) + WX (00H) = 1000H

; Jump to address 1000H and execute JPS AAA

3. Here is another example:

ORG

1100H

LD

JPS

A,#0H

A,#1H

A,#2H

A,#3H

30H,A

YYY

; Address 30H ¬ A

XXX

LD EA,#00H

JR

; EA ¬ 00H

; Jump to address 1100H

; Address 30H ¬ 00H

@EA

If 'LD EA,#01H' were to be executed in place of 'LD EA,#00H', the program would jump to

1101H and address 30H would contain the value 1H. If 'LD EA,#02H' were to be executed,

the jump would be to 1102H and address 30H would contain the value 2H.

5-59

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

LD — Load

LD

dst,src

Operand

Operation:

Operation Summary

Load 4-bit immediate data to A

Bytes

Cycles

A,#im

1

2

1

2

1

2

1

2

A,@RRa

A,DA

Load indirect data memory contents to A

Load direct data memory contents to A

Load register contents to A

A,Ra

Ra,#im

RR,#imm

DA,A

Load 4-bit immediate data to register

Load 8-bit immediate data to register

Load contents of A to direct data memory

Load contents of A to register

Ra,A

EA,@HL

EA,DA

EA,RRb

@HL,A

DA,EA

RRb,EA

@HL,EA

Load indirect data memory contents to EA

Load direct data memory contents to EA

Load register contents to EA

Load contents of A to indirect data memory

Load contents of EA to data memory

Load contents of EA to register

Load contents of EA to indirect data memory

Description: The contents of the source are loaded into the destination. The source's contents are unaffected.

If an instruction such as 'LD A,#im' (LD EA,#imm) or 'LD HL,#imm' is written more than two

times in succession, only the first LD will be executed; the other similar instructions that

immediately follow the first LD will be treated like a NOP. This is called the 'redundancy effect'

(see examples below).

Operand

A,#im

Binary Code

Operation Notation

1

0

1

0

1

0

d3 d2 d1 d0

A ¬ im

A,@RRa

A,DA

1

i2

1

i1

0

i0

0

A ¬ (RRa)

A ¬ DA

a7 a6 a5 a4 a3 a2 a1 a0

A,Ra

1

0

1

0

1

0

1

0

1

0

1

A ¬ Ra

r2 r1 r0

Ra,#im

0

1

Ra ¬ im

d3 d2 d1 d0

r2 r1 r0

5-60

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

LD — Load

LD

(Continued)

Description:

Operand

Binary Code

Operation Notation

RR ¬ imm

RR,#imm

1

0

r2 r1

1

d7 d6 d5 d4 d3 d2 d1 d0

DA,A

1

0

1

0

1

DA ¬ A

a7 a6 a5 a4 a3 a2 a1 a0

Ra,A

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Ra ¬ A

r2 r1 r0

EA,@HL

EA,DA

EA,RRb

1

0

1

0

1

0

A ¬ (HL), E ¬ (HL + 1)

A ¬ DA, E ¬ DA + 1

EA ¬ RRb

a7 a6 a5 a4 a3 a2 a1 a0

1

0

1

0

1

0

1

0

1

0

1

r2 r1

@HL,A

DA,EA

1

0

(HL) ¬ A

DA ¬ A, DA + 1 ¬ E

a7 a6 a5 a4 a3 a2 a1 a0

RRb,EA

@HL,EA

1

0

1

0

1

0

1

0

1

0

1

0

1

0

RRb ¬ EA

r2 r1

1

0

(HL) ¬ A, (HL + 1) ¬ E

Examples:

1. RAM location 30H contains the value 4H. The RAM location values are 40H, 41H and 0AH,

3H respectively. The following instruction sequence leaves the value 40H in point pair HL,

0AH in the accumulator and in RAM location 40H, and 3H in register E.

LD

HL,#30H

A,@HL

HL,#40H

EA,@HL

@HL,A

; HL ¬ 30H

; A ¬ 4H

; HL ¬ 40H

; A ¬ 0AH, E ¬ 3H

; RAM (40H) ¬ 0AH

5-61

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

LD — Load

LD

(Continued)

Examples:

2. If an instruction such as LD A,#im (LD EA,#imm) or LD HL,#imm is written more than two

times in succession, only the first LD is executed; the next instructions are treated as NOPs.

Here are two examples of this 'redundancy effect':

LD

A,#1H

EA,#2H

A,#3H

23H,A

; A ¬ 1H

; NOP

; (23H) ¬ 1H

LD

HL,#10H

HL,#20H

A,#3H

EA,#35

@HL,A

; HL ¬ 10H

; NOP

; A ¬ 3H

; NOP

; (10H) ¬ 3H

The following table contains descriptions of special characteristics of the LD instruction when

used in different addressing modes:

Instruction

Operation Description and Guidelines

LD A,#im

Since the 'redundancy effect' occurs with instructions like LD EA,#imm, if this

instruction is used consecutively, the second and additional instructions of the

same type will be treated like NOPs.

LD A,@RRa Load the data memory contents pointed to by 8-bit RRa register pairs (HL, WX,

WL) to the A register.

LD A,DA

LD A,Ra

LD Ra,#im

Load direct data memory contents to the A register.

Load 4-bit register Ra (E, L, H, X, W, Z, Y) to the A register.

Load 4-bit immediate data into the Ra register (E, L, H, X, W, Y, Z).

LD RR,#imm Load 8-bit immediate data into the Ra register (EA, HL, WX, YZ). There is a

redundancy effect if the operation addresses the HL or EA registers.

LD DA,A

LD Ra,A

Load contents of register A to direct data memory address.

Load contents of register A to 4-bit Ra register (E, L, H, X, W, Z, Y).

5-62

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

LD — Load

LD

(Concluded)

Examples:

Instruction

Operation Description and Guidelines

LD EA,@HL Load data memory contents pointed to by 8-bit register HL to the A register,

and the contents of HL+1 to the E register. The contents of register L must be

an even number. If the number is odd, the LSB of register L is recognized as a

logic zero (an even number), and it is not replaced with the true value. For

example, 'LD HL,#36H' loads immediate 36H to HL and the next instruction

'LD EA,@HL' loads the contents of 36H to register A and the contents of 37H

to register E.

LD EA,DA

Load direct data memory contents of DA to the A register, and the next direct

data memory contents of DA + 1 to the E register. The DA value must be an

even number. If it is an odd number, the LSB of DA is recognized as a logic

zero (an even number), and it is not replaced with the true value. For example,

'LD EA,37H' loads the contents of 36H to the A register and the contents of

37H to the E register.

LD EA,RRb Load 8-bit RRb register (HL, WX, YZ) to the EA register. H, W, and Y register

values are loaded into the E register, and the L, X, and Z values into the A

register.

LD @HL,A

LD DA,EA

Load A register contents to data memory location pointed to by the 8-bit HL

register value.

Load the A register contents to direct data memory and the E register contents

to the next direct data memory location. The DA value must be an even

number. If it is an odd number, the LSB of the DA value is recognized as logic

zero (an even number), and is not replaced with the true value.

LD RRb,EA Load contents of EA to the 8-bit RRb register (HL, WX, YZ). The E register is

loaded into the H, W, and Y register and the A register into the L, X, and Z

register.

LD @HL,EA Load the A register to data memory location pointed to by the 8-bit HL register,

and the E register contents to the next location, HL + 1. The contents of the L

register must be an even number. If the number is odd, the LSB of the L

register is recognized as logic zero (an even number), and is not replaced with

the true value. For example, 'LD HL,#36H' loads immediate 36H to register

HL; the instruction 'LD @HL,EA' loads the contents of A into address 36H and

the contents of E into address 37H.

5-63

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

LDB — Load Bit

LDB

dst,src.b

dst.b,src

Operation:

Operand

mema.b,C

Operation Summary

Bytes

Cycles

Load carry bit to a specified memory bit

2

memb.@L,C Load carry bit to a specified indirect memory bit

@H+DA.b,C

C,mema.b

Load memory bit to a specified carry bit

C,memb.@L Load indirect memory bit to a specified carry bit

C,@H+DA.b

Description: The Boolean variable indicated by the first or second operand is copied into the location specified

by the second or first operand. One of the operands must be the carry flag; the other may be any

directly or indirectly addressable bit. The source is unaffected.

Operand

Binary Code

Operation Notation

mema.b ¬ C

1

0

mema.b,C *

memb.@L,C

@H+DA.b,C

C,mema.b*

C,memb.@L

C,@H+DA.b

1

0

1

0

1

0

1

0

1

0

1

memb.7–2 + [L.3–2]. [L.1–0] ¬ C

H + [DA.3–0].b ¬ (C)

a5 a4 a3 a2

1

0

b1 b0 a3 a2 a1 a0

1

0

1

0

C ¬ mema.b

1

0

1

0

1

0

1

0

1

0

1

0

1

0

C ¬ memb.7–2 + [L.3–2] . [L.1–0]

C ¬ [H + DA.3–0].b

a5 a4 a3 a2

0

1

0

b1 b0 a3 a2 a1 a0

Second Byte

Bit Addresses

1

0

1

b1 b0 a3 a2 a1 a0 FB0H–FBFH

b1 b0 a3 a2 a1 a0 FF0H–FFFH

* mema.b

5-64

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

LDB — Load Bit

LDB

(Continued)

Examples:

1. The carry flag is set and the data value at input pin P1.0 is logic zero. The following

instruction clears the carry flag to logic zero.

LDB

C,P1.0

2. The P1 address is FF1H and the L register contains the value 1H (0001B). The address

(memb.7–2) is 111100B and (L.3–2) is 00B. The resulting address is 11110000B or FF0H

and P0 is addressed. The bit value (L.1–0) is specified as 01B (bit 1).

LD

LDB

L,#0001B

C,P1.@L

; P1.@L specifies P0.1 and C ¬ P0.1

3. The H register contains the value 2H and FLAG = 20H.3. The address for H is 0010B and for

FLAG(3–0) the address is 0000B. The resulting address is 00100000B or 20H. The bit value

is 3. Therefore, @H+FLAG = 20H.3.

FLAG

LD

EQU

H,#2H

20H.3

LDB

C,@H+FLAG

; C ¬ FLAG (20H.3)

4. The following instruction sequence sets the carry flag and the loads the "1" data value to the

output pin P1.0, setting it to output mode:

SCF

LDB

; C ¬ "1"

; P1.0 ¬ "1"

P1.0,C

5. The P1 address is FF1H and L = 01H (0001B). The address (memb.7–2) is 111100B and

(L.3–2) is 00B. The resulting address, 11110000B specifies P0. The bit value (L.1–0) is

specified as 01B (bit 1). Therefore, P1.@L = P0.1.

SCF

LD

LDB

; C ¬ "1"

L,# 0001B

P1.@L,C

; P1.@L specifies P0.1

; P0.1 ¬ "1"

6. In this example, H = 2H and FLAG = 20H.3 and the address 20H is specified. Since the bit

value is 3, @H+FLAG = 20H.3:

FLAG

RCF

LD

EQU

20H.3

; C ¬ "0"

H,#2H

LDB

@H+FLAG,C

; FLAG(20H.3) ¬ "0"

NOTE: Port pin names used in examples 4 and 5 may vary with different SAM47 devices.

5-65

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

LDC — Load Code Byte

LDC

dst,src

Operation:

Operand

Operation Summary

Load code byte from WX to EA

Load code byte from EA to EA

Bytes

Cycles

EA,@WX

EA,@EA

1

3

Description: This instruction is used to load a byte from program memory into an extended accumulator. The

address of the byte fetched is the six highest bit values in the program counter and the contents

of an 8-bit working register (either WX or EA). The contents of the source are unaffected.

Operand

EA,@WX

EA,@EA

Binary Code

Operation Notation

EA ¬ [PC13–8 + (WX)]

EA ¬ [PC13–8 + (EA)]

1

0

1

0

Examples:

1. The following instructions will load one of four values defined by the define byte (DB)

directive to the extended accumulator:

LD

CALL

JPS

EA,#00H

DISPLAY

MAIN

ORG

0500H

DB

66H

77H

88H

99H

DISPLAY LDC

RET

EA,@EA ; EA ¬ address 0500H = 66H

If the instruction 'LD EA,#01H' is executed in place of 'LD EA,#00H', The content of 0501H

(77H) is loaded to the EA register. If 'LD EA,#02H' is executed, the content of address 0502H

(88H) is loaded to EA.

5-66

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

LDC — Load Code Byte

LDC

(Continued)

Examples:

2. The following instructions will load one of four values defined by the define byte (DB)

directive to the extended accumulator:

ORG

0500H

DB

66H

77H

88H

99H

DISPLAY LD

WX,#00H

LDC

RET

EA,@WX ; EA ¬ address 0500H = 66H

If the instruction 'LD WX,#01H' is executed in place of 'LD WX,#00H', then

EA ¬ address 0501H = 77H.

If the instruction 'LD WX,#02H' is executed in place of 'LD WX,#00H', then

EA ¬ address 0502H = 88H.

3. Normally, the LDC EA, @EA and the LDC EA, @WX instructions reference the table data

on the page on which the instruction is located. If, however, the instruction is located at

address xxFFH, it will reference table data on the next page. In this example, the upper 4 bits

of the address at location 0200H is loaded into register E and the lower 4 bits into register A:

ORG

LD

LDC

01FDH

WX,#00H

01FDH

01FFH

EA,@WX ; E ¬ upper 4 bits of 0200H address

; A ¬ lower 4 bits of 0200H address

4. Here is another example of page referencing with the LDC instruction:

ORG

DB

0100H

67H

SMB

LD

0

HL,#30H ; Even number

WX,#00H

LDC

EA,@WX ; E ¬ upper 4 bits of 0100H address

; A ¬ lower 4 bits of 0100H address

@HL,EA ; RAM (30H) ¬ 7, RAM (31H) ¬ 6

LD

5-67

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

LDD — Load Data Memory and Decrement

LDD

dst

Operation:

Operand

A,@HL

Operation Summary

Bytes

Cycles

Load indirect data memory contents to A; decrement

register L contents and skip on borrow

1

2 + S

Description: The contents of a data memory location are loaded into the accumulator, and the contents of the

register L are decreased by one. If a "borrow" occurs (e.g., if the resulting value in register L is

0FH), the next instruction is skipped. The contents of data memory and the carry flag value are

not affected.

Operand

A,@HL

Binary Code

Operation Notation

1

0

1

0

1

A ¬ (HL), then L ¬ L–1;

skip if L = 0FH

Example:

In this example, assume that register pair HL contains 20H and internal RAM location 20H

contains the value 0FH:

LD

HL,#20H

A,@HL

XXX

LDD

JPS

; A ¬ (HL) and L ¬ L–1

; Skip

; H ¬ 2H and L ¬ 0FH

YYY

The instruction 'JPS XXX' is skipped since a "borrow" occurred after the 'LDD A,@HL' and

instruction 'JPS YYY' is executed.

5-68

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

LDI — Load Data Memory and Increment

LDI

dst,src

Operation:

Operand

A,@HL

Operation Summary

Bytes

Cycles

Load indirect data memory to A; increment register L

contents and skip on overflow

1

2 + S

Description: The contents of a data memory location are loaded into the accumulator, and the contents of the

register L are incremented by one. If an overflow occurs (e.g., if the resulting value in register L

is 0H), the next instruction is skipped. The contents of data memory and the carry flag value are

unaffected.

Operand

A,@HL

Binary Code

Operation Notation

1

0

1

0

1

0

A ¬ (HL), then L ¬ L+1;

skip if L = 0H

Example:

Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains

the value 0FH:

LD

HL,#2FH

A,@HL

XXX

LDI

JPS

; A ¬ (HL) and L ¬ L+1

; Skip

; H ¬ 2H and L ¬ 0H

YYY

The instruction 'JPS XXX' is skipped since an overflow occurred after the 'LDI A,@HL' and the

instruction 'JPS YYY' is executed.

5-69

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

NOP — No Operation

NOP

Operation:

Operand

Operation Summary

Bytes

Cycles

–

No operation

1

Description: No operation is performed by a NOP instruction. It is typically used for timing delays.

One NOP causes a 1-cycle delay: with a 1 µs cycle time, five NOPs would therefore cause a 5 µs

delay. Program execution continues with the instruction immediately following the NOP. Only the

PC is affected. At least three NOP instructions should follow a STOP or IDLE instruction.

Operand

Binary Code

Operation Notation

No operation

–

1

0

1

0

Example:

Three NOP instructions follow the STOP instruction to provide a short interval for clock

stabilization before power-down mode is initiated:

STOP

NOP

5-70

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

OR — Logical OR

OR

dst,src

Operation:

Operand

Operation Summary

Logical-OR immediate data to A

Bytes

Cycles

A, #im

2

1

2

1

2

A, @HL

EA,RR

RRb,EA

Logical-OR indirect data memory contents to A

Logical-OR double register to EA

Logical-OR EA to double register

Description: The source operand is logically ORed with the destination operand. The result is stored in the

destination. The contents of the source are unaffected.

Operand

A, #im

Binary Code

Operation Notation

A ¬ A OR im

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

d3 d2 d1 d0

A, @HL

EA,RR

1

0

1

0

A ¬ A OR (HL)

EA ¬ EA OR RR

r2 r1

RRb,EA

1

0

RRb ¬ RRb OR EA

r2 r1

Example:

If the accumulator contains the value 0C3H (11000011B) and register pair HL the value 55H

(01010101B), the instruction

OR

EA,@HL

leaves the value 0D7H (11010111B) in the accumulator .

5-71

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

POP — Pop from Stack

POP

dst

Operation:

Operand

Operation Summary

Pop to register pair from stack

Pop SMB and SRB values from stack

Bytes

Cycles

RR

SB

1

2

1

2

Description: The contents of the RAM location addressed by the stack pointer is read, and the SP is

incremented by two. The value read is then transferred to the variable indicated by the

destination operand.

Operand

RR

Binary Code

Operation Notation

0

1

0

1

r2 r1

0

RR ¬ (SP), RR ¬ (SP+1)

L

H

SP ¬ SP+2

SB

1

0

1

0

1

0

1

0

1

0

1

0

(SRB) ¬ (SP), SMB ¬ (SP+1),

SP ¬ SP+2

Example:

The SP value is equal to 0EDH, and RAM locations 0EFH through 0EDH contain the values 2H,

3H, and 4H, respectively. The instruction

POP

HL

leaves the stack pointer set to 0EFH and the data pointer pair HL set to 34H.

5-72

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

PUSH — Push Onto Stack

PUSH

src

Operation:

Operand

Operation Summary

Push register pair onto stack

Push SMB and SRB values onto stack

Bytes

Cycles

RR

SB

1

2

1

2

Description: The SP is then decreased by two and the contents of the source operand are copied into the

RAM location addressed by the stack pointer, thereby adding a new element to the top of the

stack.

Operand

RR

Binary Code

Operation Notation

0

1

0

1

r2 r1

1

(SP–1) ¬ RR , (SP–2) ¬ RR

H

L

SP ¬ SP–2

SB

1

0

1

0

1

0

1

0

1

0

1

(SP–1) ¬ SMB, (SP–2) ¬ SRB;

(SP) ¬ SP–2

Example:

As an interrupt service routine begins, the stack pointer contains the value 0FAH and the data

pointer register pair HL contains the value 20H. The instruction

PUSH

HL

leaves the stack pointer set to 0F8H and stores the values 2H and 0H in RAM locations 0F9H

and 0F8H, respectively.

5-73

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

RCF — Reset Carry Flag

RCF

Operation:

Operand

Operation Summary

Reset carry flag to logic zero

Bytes

Cycles

–

1

Description: The carry flag is cleared to logic zero, regardless of its previous value.

Operand

Binary Code

Operation Notation

–

1

0

1

0

C ¬ 0

Example:

Assuming the carry flag is set to logic one, the instruction

RCF

resets (clears) the carry flag to logic zero.

5-74

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

REF — Reference Instruction

REF

dst

Operation:

Operand

memc

NOTE: The instruction referenced by REF determines instruction cycles.

Operation Summary

Bytes

Cycles

1 ^(note)

Reference code

1

Description: The REF instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or

two 1-byte instructions) stored in the REF instruction reference area in program memory. REF

reduces the number of program memory accesses for a program.

Operand

memc

Binary Code

t4 t3

Operation Notation

t7

t6

t5

t2

t1

t0

PC13–0 ¬ memc.5–0 + (memc +

1).7–0

TJP and TCALL are 2-byte pseudo-instructions that are used only to specify the reference area:

1. When the reference area is specified by the TJP instruction,

memc.7–6 = 00

PC13–0 ¬ memc.5–0 + (memc + 1).7–0

2. When the reference area is specified by the TCALL instruction,

memc.7–6 = 01

(SP–4) (SP–1) (SP–2) ¬ PC11–0

SP–3 ¬ EMB, ERB, PC13–12

PC13–0 ¬ memc.5–0 + (memc + 1).7–0

SP ¬ SP–4

When the reference area is specified by any other instruction, the 'memc' and 'memc + 1'

instructions are executed.

Instructions referenced by REF occupy 2 bytes of memory space (for two 1-byte instructions or

one 2-byte instruction) and must be written as an even number from 0020H to 007FH in ROM. In

addition, the destination address of the TJP and TCALL instructions must be located with the

3FFFH address. TJP and TCALL are reference instructions for JP/JPS and CALL/CALLS.

If the instruction following a REF is subject to the 'redundancy effect', the redundant instruction is

skipped. If, however, the REF follows a redundant instruction, it is executed.

On the other hand, the binary code of a REF instruction is 1 byte. The upper 4 bits become the

higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction

becomes the lower address, producing a total of 8 bits or 1 byte (see Example 3 below).

NOTE: If the MSB value of the first one-byte binary code in instruction is “0”, the instruction cannot be referenced by a REF

instruction.

5-75

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

REF — Reference Instruction

REF

(Continued)

1. Instructions can be executed efficiently using REF, as shown in the following example:

Examples:

ORG

LD

TCALL

TJP

•

0020H

AAA

BBB

CCC

DDD

HL,#00H

EA,#FFH

SUB1

SUB2

•

ORG

REF

0080H

AAA

BBB

CCC

DDD

; LD

; CALL SUB1

; JP SUB2

HL,#00H

EA,#FFH

2. The following example shows how the REF instruction is executed in relation to LD

instructions that have a 'redundancy effect':

ORG

0020H

AAA

LD

EA,#40H

•

ORG

LD

REF

•

0100H

EA,#30H

AAA

; Not skipped

•

REF

LD

SRB

AAA

EA,#50H ; Skipped

2

5-76

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

REF — Reference Instruction

REF

(Concluded)

Examples:

3. In this example the binary code of 'REF A1' at locations 20H–21H is 20H, for 'REF A2' at

locations 22H–23H, it is 21H, and for 'REF A3' at 24H–25H, the binary code is 22H :

Opcode Symbol Instruction

ORG

0020H

83 00

83 03

83 05

83 10

83 26

83 08

83 0F

83 F0

83 67

41 0B

01 0D

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

LD

TCALL

TJP

•

HL,#00H

HL,#03H

HL,#05H

HL,#10H

HL,#26H

HL,#08H

HL,#0FH

HL,#0F0H

HL,#067H

SUB1

SUB2

•

ORG

0100H

20

21

22

23

24

25

26

27

30

31

32

REF

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

; LD

; CALL

; JP

HL,#00H

HL,#03H

HL,#05H

HL,#10H

HL,#26H

HL,#08H

HL,#0FH

HL,#0F0H

HL,#067H

SUB1

SUB2

5-77

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

RET — Return from Subroutine

RET

Operation:

Operand

Operation Summary

Return from subroutine

Bytes

Cycles

–

1

3

Description: RET pops the PC values successively from the stack, incrementing the stack pointer by six.

Program execution continues from the resulting address, generally the instruction immediately

following a CALL or CALLS.

Operand

Binary Code

Operation Notation

–

1

0

1

0

1

PC13–8 ¬ (SP+1) (SP)

PC7–0 ¬ (SP+3) (SP+2)

EMB,ERB ¬ (SP+4)

SP ¬ SP+6

Example:

The stack pointer contains the value 0FAH. RAM locations 0FAH, 0FBH, 0FCH, and 0FDH

contain 1H, 0H, 5H, and 2H, respectively. The instruction

RET

leaves the stack pointer with the new value of 00H and program execution continues from

location 0125H.

During a return from subroutine, PC values are popped from stack locations as follows:

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(000H)

PC11 – PC8

SP ®

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

0

PC13 PC12

PC3 – PC0

PC7 – PC4

0

EMB ERB

0

5-78

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

RRC — Rotate Accumulator Right through Carry

RRC

A

Operation:

Operand

Operation Summary

Rotate right through carry bit

Bytes

Cycles

A

1

Description: The four bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0

moves into the carry flag and the original carry value moves into the bit 3 accumulator position.

3

0

C

Operand

Binary Code

Operation Notation

C ¬ A.0, A3 ¬ C

A.n–1 ¬ A.n (n = 1, 2, 3)

A

1

0

1

0

Example:

The accumulator contains the value 5H (0101B) and the carry flag is cleared to logic zero. The

instruction

RRC

A

leaves the accumulator with the value 2H (0010B) and the carry flag set to logic one.

5-79

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

SBC — Subtract with Carry

SBC

dst,src

Operation:

Operand

Operation Summary

Bytes

Cycles

A,@HL

EA,RR

RRb,EA

Subtract indirect data memory from A with carry

Subtract register pair (RR) from EA with carry

Subtract EA from register pair (RRb) with carry

1

2

1

2

Description: SBC subtracts the source and carry flag value from the destination operand, leaving the result in

the destination. SBC sets the carry flag if a borrow is needed for the most significant bit;

otherwise it clears the carry flag. The contents of the source are unaffected.

If the carry flag was set before the SBC instruction was executed, a borrow was needed for the

previous step in multiple precision subtraction. In this case, the carry bit is subtracted from the

destination along with the source operand.

Operand

A,@HL

Binary Code

Operation Notation

C,A ¬ A – (HL) – C

0

1

0

1

0

1

0

1

0

1

0

1

0

EA,RR

C, EA ¬ EA –RR – C

r2 r1

RRb,EA

1

0

C,RRb ¬ RRb – EA – C

r2 r1

Examples:

1. The extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag is set to "1":

SCF

SBC

JPS

; C ¬ "1"

; EA ¬ 0C3H – 0AAH – 1H, C ¬ "0"

; Jump to XXX; no skip after SBC

EA,HL

XXX

2. If the extended accumulator contains the value 0C3H, register pair HL the value 0AAH, and

the carry flag is cleared to "0":

RCF

SBC

JPS

; C ¬ "0"

EA,HL

XXX

; EA ¬ 0C3H – 0AAH – 0H = 19H, C ¬ "0"

; Jump to XXX; no skip after SBC

5-80

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

SBC — Subtract with Carry

SBC

(Continued)

Examples:

3. If SBC A,@HL is followed by an ADS A,#im, the SBC skips on 'no borrow' to the instruction

immediately after the ADS. An 'ADS A,#im' instruction immediately after the 'SBC A,@HL'

instruction does not skip even if an overflow occurs. This function is useful for decimal

adjustment operations.

a. 8 – 6 decimal addition (the contents of the address specified by the HL register is 6H):

RCF

LD

SBC

ADS

JPS

; C ¬ "0"

; A ¬ 8H

A,#8H

A,@HL

A,#0AH

XXX

; A ¬ 8H – 6H – C(0) = 2H, C ¬ "0"

; Skip this instruction because no borrow after SBC result

b. 3 – 4 decimal addition (the contents of the address specified by the HL register is 4H):

RCF

LD

; C ¬ "0"

; A ¬ 3H

A,#3H

SBC

ADS

A,@HL

A,#0AH

; A ¬ 3H – 4H – C(0) = 0FH, C ¬ "1"

; No skip. A ¬ 0FH + 0AH = 9H

; (The skip function of 'ADS A,#im' is inhibited after a

; 'SBC A,@HL' instruction even if an overflow occurs.)

JPS

XXX

5-81

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

SBS — Subtract

SBS

dst,src

Operation:

Operand

Operation Summary

Bytes

Cycles

1 + S

2 + S

A,@HL

EA,RR

RRb,EA

Subtract indirect data memory from A; skip on borrow

Subtract register pair (RR) from EA; skip on borrow

Subtract EA from register pair (RRb); skip on borrow

1

2

Description: The source operand is subtracted from the destination operand and the result is stored in the

destination. The contents of the source are unaffected. A skip is executed if a borrow occurs. The

value of the carry flag is not affected.

Operand

A,@HL

Binary Code

Operation Notation

A ¬ A – (HL); skip on borrow

EA ¬ EA – RR; skip on borrow

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

EA,RR

r2 r1

RRb,EA

1

0

RRb ¬ RRb – EA; skip on borrow

r2 r1

Examples:

1. The accumulator contains the value 0C3H, register pair HL contains the value 0C7H, and the

carry flag is cleared to logic zero:

RCF

SBS

; C ¬ "0"

; EA ¬ 0C3H – 0C7H

EA,HL

; SBS instruction skips on borrow,

; but carry flag value is not affected

; Skip because a borrow occurred

; Jump to YYY is executed

JPS

XXX

YYY

2. The accumulator contains the value 0AFH, register pair HL contains the value 0AAH, and the

carry flag is set to logic one:

SCF

SBS

JPS

; C ¬ "1"

; EA ¬ 0AFH – 0AAH

; Jump to XXX

EA,HL

XXX

; JPS was not skipped since no "borrow" occurred after

; SBS

5-82

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

SCF — Set Carry Flag

SCF

Operation:

Operand

Operation Summary

Set carry flag to logic one

Bytes

Cycles

–

1

Description: The SCF instruction sets the carry flag to logic one, regardless of its previous value.

Operand

Binary Code

Operation Notation

–

1

0

1

C ¬ 1

Example:

If the carry flag is cleared to logic zero, the instruction

SCF

sets the carry flag to logic one.

5-83

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

SMB — Select Memory Bank

SMB

n

Operation:

Operand

Operation Summary

Select memory bank

Bytes

Cycles

n

2

Description: The SMB instruction sets the upper four bits of a 12-bit data memory address to select a specific

memory bank. The constants 0, n, and 15 are usually used as the SMB operand to select the

corresponding memory bank. All references to data memory addresses fall within the following

address ranges:

Please note that since data memory spaces differ for various devices in the SAM4 product

family, the 'n' value of the SMB instruction will also vary.

Addresses

000H–01FH

Register Areas

Working registers

Bank

SMB

0

020H–0FFH

n00H–nFFH

Stack and general-purpose registers

General-purpose registers

n

(n = 1–14) (n = 1–14)

F80H–FFFH

I/O-mapped hardware registers

15 15

The enable memory bank (EMB) flag must always be set to "1" in order for the SMB instruction

to execute successfully for memory banks 0–15.

Format

Binary Code

Operation Notation

SMB ¬ n (n = 0-15)

n

1

0

1

0

1

0

1

0

1

d3 d2 d1 d0

Example:

If the EMB flag is set, the instruction

SMB

selects the data memory address range for bank 0 (000H–0FFH) as the working memory bank.

0

NOTE: The number of memory balk selected by SMB may change for different devices in the SAM47 product family.

5-84

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

SRB— Select Register Bank

SRB

n

Operation:

Operand

Operation Summary

Select register bank

Bytes

Cycles

n

2

Description: The SRB instruction selects one of four register banks in the working register memory area. The

constant value used with SRB is 0, 1, 2, or 3. The following table shows the effect of SRB

settings:

ERB Setting

SRB Settings

Selected Register Bank

3

2

1

x

0

1

0

x

0

1

0

1

0

1

0

Always set to bank 0

Bank 0

0

Bank 1

Bank 2

Bank 3

NOTE: 'x' = not applicable.

The enable register bank flag (ERB) must always be set for the SRB instruction to execute

successfully for register banks 0, 1, 2, and 3. In addition, if the ERB value is logic zero, register

bank 0 is always selected, regardless of the SRB value.

Operand

Binary Code

Operation Notation

n

1

0

1

0

1

0

1

0

1

SRB ¬ n (n = 0, 1, 2, 3)

d1 d0

Example:

If the ERB flag is set, the instruction

SRB

selects register bank 3 (018H–01FH) as the working memory register bank.

3

5-85

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

SRET — Return from Subroutine and Skip

SRET

Operation:

Operand

Operation Summary

Return from subroutine and skip

Bytes

Cycles

–

1

3 + S

Description: SRET is normally used to return to the previously executing procedure at the end of a subroutine

that was initiated by a CALL or CALLS instruction. SRET skips the resulting address, which is

generally the instruction immediately after the point at which the subroutine was called. Then,

program execution continues from the resulting address and the contents of the location

addressed by the stack pointer are popped into the program counter.

Operand

Binary Code

Operation Notation

–

1

0

1

0

1

PC13–8 ¬ (SP + 1) (SP)

PC7–0 ¬ (SP + 3) (SP + 2)

EMB,ERB ¬ (SP + 4)

SP ¬ SP + 6

Example:

If the stack pointer contains the value 0FAH and RAM locations 0FAH, 0FBH, 0FCH, and 0FDH

contain the values 1H, 0H, 5H, and 2H, respectively, the instruction

SRET

leaves the stack pointer with the value 00H and the program returns to continue execution at

location 0125H, then skips unconditionally.

During a return from subroutine, data is popped from the stack to the PC as follows:

(0FAH)

(0FBH)

(0FCH)

(0FDH)

(0FEH)

(0FFH)

(000H)

PC11 – PC8

SP ®

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

0

PC13 PC12

PC3 – PC0

PC7 – PC4

0

EMB ERB

0

5-86

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

STOP — Stop Operation

STOP

Operation:

Operand

Operation Summary

Engage CPU stop mode

Bytes

Cycles

–

2

Description: The STOP instruction stops the system clock by setting bit 3 of the power control register

(PCON) to logic one. When STOP executes, all system operations are halted with the exception

of some peripheral hardware with special power-down mode operating conditions.

In application programs, a STOP instruction must be immediately followed by at least three NOP

instructions. This ensures an adequate time interval for the clock to stabilize before the next

instruction is executed. If three or more NOP instructions are not used after STOP instruction,

leakage current could be flown because of the floating state in the internal bus.

Operand

Binary Code

Operation Notation

PCON.3 ¬ 1

–

1

0

1

0

1

0

1

Example:

Given that bit 3 of the PCON register is cleared to logic zero, and all systems are operational, the

instruction sequence

STOP

NOP

sets bit 3 of the PCON register to logic one, stopping all controller operations (with the exception

of some peripheral hardware). The three NOP instructions provide the necessary timing delay for

clock stabilization before the next instruction in the program sequence is executed.

5-87

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

VENT — Load EMB, ERB, and Vector Address

VENTn

dst

Operation:

Operand

Operation Summary

Bytes

Cycles

EMB (0,1)

ERB (0,1)

ADR

Load enable memory bank flag (EMB) and the enable

register bank flag (ERB) and program counter to

vector address, then branch to the corresponding

location.

2

Description: The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable

register bank flag (ERB) into the respective vector addresses. It then points the interrupt service

routine to the corresponding branching locations. The program counter is loaded automatically

with the respective vector addresses which indicate the starting address of the respective vector

interrupt service routines.

The EMB and ERB flags should be modified using VENT before the vector interrupts are

acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous

routine are automatically pushed onto the stack and then popped back when the routine is

completed.

After the return from interrupt (IRET) you do not need to set the EMB and ERB values again.

Instead, use BITR and BITS to clear these values in your program routine.

The starting addresses for vector interrupts and reset operations are pointed to by the VENTn

instruction. These starting addresses must be located in ROM ranges 0000H–3FFFH. Generally,

the VENTn instructions are coded starting at location 0000H.

The format for VENT instructions is as follows:

VENTn

d1,d2,ADDR

EMB ¬ d1 ("0" or "1")

ERB ¬ d2 ("0" or "1")

PC ¬ ADDR (address to branch

n = device-specific module address code (n = 0–n)

Operand

Binary Code

Operation Notation

EMB (0,1)

ERB (0,1)

ADR

E

M

B

E

R

B

a13 a12 a11 a10 a9 a8

ROM (2 x n) 7–6 ® EMB, ERB

ROM (2 x n) 5–4 ® PC13–12

ROM (2 x n) 3–0 ® PC11–8

ROM (2 x n + 1) 7–0 ® PC7–0

(n = 0, 1, 2, 3, 4, 5, 6, 7)

a7 a6 a5 a4 a3 a2 a1 a0

5-88

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

VENT — Load EMB, ERB, and Vector Address

VENTn

(Continued)

Example:

The instruction sequence

ORG

0000H

VENT0

VENT1

VENT2

VENT3

VENT4

VENT6

VENT7

1,0,RESET

0,1,INTA

0,1,INTB

0,1,INTC

0,1,INTD

0,1,INTE

0,1,INTF

causes the program sequence to branch to the RESET routine labeled 'RESET', setting EMB to

"1" and ERB to "0" when RESET is activated. When a basic timer interrupt is generated, VENT1

causes the program to branch to the basic timer's interrupt service routine, INTA, and to set the

EMB value to "0" and the ERB value to "1". VENT2 then branches to INTB, VENT3 to INTC, and

so on, setting the appropriate EMB and ERB values.

NOTE: The number of VENTn interrupt names used in the examples above may change for different devices in the SAM47

product family.

5-89

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

XCH — Exchange A or EA with Nibble or Byte

XCH

dst,src

Operation:

Operand

Operation Summary

Bytes

Cycles

A,DA

Exchange A and data memory contents

Exchange A and register (Ra) contents

Exchange A and indirect data memory

2

1

2

1

2

A,Ra

A,@RRa

EA,DA

EA,RRb

EA,@HL

Exchange EA and direct data memory contents

Exchange EA and register pair (RRb) contents

Exchange EA and indirect data memory contents

Description: The instruction XCH loads the accumulator with the contents of the indicated destination variable

and writes the original contents of the accumulator to the source.

Operand

A,DA

Binary Code

Operation Notation

A « DA

0

1

0

1

a7 a6 a5 a4 a3 a2 a1 a0

A,Ra

0

1

0

1

0

1

r2 r1 r0

A « Ra

A,@RRa

EA,DA

i2

1

i1

1

i0

1

A « (RRa)

A « DA,E « DA + 1

a7 a6 a5 a4 a3 a2 a1 a0

EA,RRb

EA,@HL

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EA « RRb

r2 r1

1

0

A « (HL), E « (HL + 1)

Example:

Double register HL contains the address 20H. The accumulator contains the value 3FH

(00111111B) and internal RAM location 20H the value 75H (01110101B). The instruction

XCH

EA,@HL

leaves RAM location 20H with the value 3FH (00111111B) and the extended accumulator with

the value 75H (01110101B).

5-90

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

XCHD — Exchange and Decrement

XCHD

dst,src

Operation:

Operand

A,@HL

Operation Summary

Bytes

Cycles

Exchange A and data memory contents; decrement

contents of register L and skip on borrow

1

2 + S

Description: The instruction XCHD exchanges the contents of the accumulator with the RAM location

addressed by register pair HL and then decrements the contents of register L. If the content of

register L is 0FH, the next instruction is skipped. The value of the carry flag is unaffected.

Operand

A,@HL

Binary Code

Operation Notation

0

1

0

1

A « (HL), then L ¬ L–1;

skip if L = 0FH

Example:

Register pair HL contains the address 20H and internal RAM location 20H contains the value

0FH:

LD

HL,#20H

A,#0H

A,@HL

XXX

YYY

A,@HL

XCHD

JPS

XCHD

•

; A ¬ 0FH and L ¬ L – 1, (HL) ¬ "0"

; Skipped since a borrow occurred

; H ¬ 2H, L ¬ 0FH

YYY

; (2FH) ¬ 0FH, A ¬ (2FH), L ¬ L – 1 = 0EH

•

The 'JPS YYY' instruction is executed since a skip occurs after the XCHD instruction.

5-91

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

XCHI — Exchange and Increment

XCHI

dst,src

Operation:

Operand

A,@HL

Operation Summary

Bytes

Cycles

Exchange A and data memory contents; increment

contents of register L and skip on overflow

1

2 + S

Description: The instruction XCHI exchanges the contents of the accumulator with the RAM location

addressed by register pair HL and then increments the contents of register L. If the content of

register L is 0H, a skip is executed. The value of the carry flag is unaffected.

Operand

A,@HL

Binary Code

Operation Notation

0

1

0

1

0

A « (HL), then L ¬ L+1;

skip if L = 0H

Example:

Register pair HL contains the address 2FH and internal RAM location 2FH contains 0FH:

LD

XCHI

JPS

XCHI

•

HL,#2FH

A,#0H

A,@HL

XXX

YYY

A,@HL

; A ¬ 0FH and L ¬ L + 1 = 0, (HL) ¬ "0"

; Skipped since an overflow occurred

; H ¬ 2H, L ¬ 0H

YYY

; (20H) ¬ 0FH, A ¬ (20H), L ¬ L + 1 = 1H

•

The 'JPS YYY' instruction is executed since a skip occurs after the XCHI instruction.

5-92

KS57C21516/P21516 MICROCONTROLLER

SAM47 INSTRUCTION SET

XOR — Logical Exclusive OR

XOR

dst,src

Operation:

Operand

Operation Summary

Exclusive-OR immediate data to A

Exclusive-OR indirect data memory to A

Exclusive-OR register pair (RR) to EA

Exclusive-OR register pair (RRb) to EA

Bytes

Cycles

A,#im

2

1

2

1

2

A,@HL

EA,RR

RRb,EA

Description: XOR performs a bitwise logical XOR operation between the source and destination variables and

stores the result in the destination. The source contents are unaffected.

Operand

A,#im

Binary Code

Operation Notation

A ¬ A XOR im

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

d3 d2 d1 d0

A,@HL

EA,RR

1

0

1

0

1

0

1

0

A ¬ A XOR (HL)

EA ¬ EA XOR (RR)

r2 r1

RRb,EA

1

0

RRb ¬ RRb XOR EA

r2 r1

Example:

If the extended accumulator contains 0C3H (11000011B) and register pair HL contains 55H

(01010101B), the instruction

XOR

EA,HL

leaves the value 96H (10010110B) in the extended accumulator.

5-93

SAM47 INSTRUCTION SET

KS57C21516/P21516 MICROCONTROLLER

NOTES

5-94

Oscillator Circuits

Interrupts

Power-Down

RESET

I/O Ports

Timers and Timer/Counters

LCD Controller/Driver

Serial I/O Interface

Electrical Data

Mechanical Data

KS57P21516 OTP

Development Tools

KS57C21516/P21516 MICROCONTROLLER

OSCILLATOR CIRCUITS

6

OSCILLATOR CIRCUITS

OVERVIEW

The KS57C21516 microcontroller have two oscillator circuits: a main system clock circuit, and a subsystem clock

circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits.

Specifically, a clock pulse is required by the following peripheral modules:

— LCD controller

— Basic timer

— Timer/counters 0 and 1

— Watch timer

— Serial I/O interface

— Clock output circuit

CPU Clock Notation

In this document, the following notation is used for descriptions of the CPU clock:

fx

Main system clock

Subsystem clock

fxt

fxx

Selected system clock

Clock Control Registers

When the system clock mode register, SCMOD, and the power control register, PCON, are both cleared to zero

after RESET, the normal CPU operating mode is enabled, a main system clock is selected as fx/64, and main

system clock oscillation is initiated.

The PCON is used to select normal CPU operating mode or one of two power down mode-stop or idle. Bits 3 and

2 of the PCON register can be manipulated by STOP of IDLE instruction to engage stop or idle power down

mode.

The SCMOD, lets you select the main system clock (fx) or a subsystem clock (fxt) as the CPU clock and start (or

stop) main/sub system clock oscillation. The resulting clock source, either main system clock or subsystem clock,

is referred to the selected system clock (fxx).

The main system clock is selected and oscillation started when all SCMOD bits are cleared to “0”. By setting

SCMOD.3, SCMOD.2 and SCMOD.0 to different values, you can select a subsystem clock source and start or

stop main/sub system clock oscillation. To stop main system clock oscillation, you must use the STOP instruction

(assuming the main system clock is selected) or manipulate SCMOD.3 to (assuming the sub system clock is

selected).

The main system clock frequencies can be divided by 4, 8, or 64 and a subsystem clock frequencies can only be

divided by 4. By manipulating PCON bits 1 and 0, you select one of the following frequencies as the CPU clock.

fx/4, fxt/4, fx/8, fx/64

6–1

OSCILLATOR CIRCUITS

KS57C21516/P21516 MICROCONTROLLER

Using a Subsystem Clock

If a subsystem clock is being used as the selected system clock, the idle power-down mode can be initiated by

executing an IDLE instruction.

The watch timer, buzzer and LCD display operate normally with a subsystem clock source, since they operate at

very low speed (as low as 122 µs at 32.768 kHz) and with very low power consumption.

Watch Timer

LCD Controller

Main-system

Oscillator

Circuit

Sub-system

Oscillator

Circuit

fx

fxt

Oscillator

stop

Selector

Xin

Xout

XTin

XTout

fxx

1/1 - 1/4096

Basic Timer

Timer/Counter

Watch Timer

LCD Controller

Clock Output Circuit

Oscillator

stop

Frequency

Dividing

Circuit

1/2 1/16

SCMOD.3

Selector

SCMOD.0

SCMOD.2

fx/1,2,16

fxt

Selector

1 / 4

CPU stop signal

(IDLE mode)

PCON.0

PCON.1

PCON.2

PCON.3

CPU clock

Wait release signal

RESET

signal

IDLE

STOP

Oscillator

Control

Circuit

Internal

Power down release signal

fx : Main-system clock

PCON.3, .2 clear

fxt : Sub-system clock

fxx : System clock

Figure 6-1. Clock Circuit Diagram

6–2

KS57C21516/P21516 MICROCONTROLLER

MAIN SYSTEM OSCILLATOR CIRCUITS

OSCILLATOR CIRCUITS

SUB SYSTEM OSCILLATOR CIRCUITS

XTin

XTout

32.768 kHz

Figure 6-2. Crystal/Ceramic Oscillator (fx)

Figure 6-5. Crystal/Ceramic Oscillator (fxt)

XTin

Xin

External

Clock

XTout

Xout

Figure 6-6. External Oscillator (fxt)

Figure 6-3. External Oscillator (fx)

Xin

R

Xout

Figure 6-4. RC Oscillator (fx)

6–3

OSCILLATOR CIRCUITS

KS57C21516/P21516 MICROCONTROLLER

POWER CONTROL REGISTER (PCON)

The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control

CPU operating and power-down modes. PCON can be addressed directly by 4-bit write instructions or indirectly

by the instructions IDLE and STOP.

FB3H

PCON.3

PCON.2

PCON.1

PCON.0

PCON bits 3 and 2 are addressed by the STOP and IDLE instructions, respectively, to engage the idle and stop

power-down modes. Idle and stop modes can be initiated by these instruction despite the current value of the

enable memory bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency. There

are two basic choices:

— Main system clock (fx) or subsystem clock (fxt);

— Divided fx/4, 8, 64 or fxt/4 clock frequency.

PCON.1 and PCON.0 settings are also connected with the system clock mode control register, SCMOD. If

SCMOD.0 = "0" the main system clock is always selected by the PCON.1 and PCON.0 setting; if SCMOD.0 =

"1" the subsystem clock is selected.

RESET sets PCON register values (and SCMOD) to logic zero: SCMOD.3 and SCMOD.0 select the main system

clock (fx) and start clock oscillation; PCON.1 and PCON.0 divide the selected fx frequency by 64, and PCON.3

and PCON.2 enable normal CPU operating mode.

Table 6-1. Power Control Register (PCON) Organization

PCON Bit Settings

Resulting CPU Operating Mode

PCON.3

PCON.2

0

1

0

1

0

Normal CPU operating mode

Idle power-down mode

Stop power-down mode

PCON Bit Settings

Resulting CPU Clock Frequency

PCON.1

PCON.0

If SCMOD.0 = "0"

If SCMOD.0 = "1"

0

1

0

1

fx/64

fx/8

fxt/4

fx/4

+

PROGRAMMING TIP — Setting the CPU Clock

To set the CPU clock to 0.95 µs at 4.19 MHz:

BITS

SMB

LD

EMB

15

A,#3H

PCON,A

LD

6–4

KS57C21516/P21516 MICROCONTROLLER

INSTRUCTION CYCLE TIMES

OSCILLATOR CIRCUITS

The unit of time that equals one machine cycle varies depending on whether the main system clock (fx) or a

subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). Table 6-2 shows

corresponding cycle times in microseconds.

Table 6-2. Instruction Cycle Times for CPU Clock Rates

Selected

CPU Clock

Resulting Frequency

Oscillation

Source

Cycle Time (µsec)

fx/64

fx/8

65.5 kHz

524.0 kHz

1.05 MHz

8.19 kHz

15.3

fx = 4.19 MHz

1.91

0.95

122.0

fx/4

fxt/4

fxt = 32.768 kHz

6–5

OSCILLATOR CIRCUITS

KS57C21516/P21516 MICROCONTROLLER

SYSTEM CLOCK MODE REGISTER (SCMOD)

The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control

main and sub-system clock oscillation. The SCMOD is mapped to the RAM address FB7H.

The main clock oscillation is stopped by setting SCMOD.3 when the clock source is subsystem clock and

subsystem clock can be stopped by setting SCMOD.2 when the clock source is main system clock. SCMOD.0,

SCMOD.3 cannot be simultaneously modified.

The subsystem clock is stopped only by setting SCMOD.2, and PCON which revokes stop mode cannot stop the

subsystem clock. The stop of subsystem clock is released by RESET when the selected system clock is main

system clock or subsystem clock and is released by setting SCMOD.2 when the selected system clock is main

system clock.

RESET clears all SCMOD values to logic zero, selecting the main system clock (fx) as the CPU clock and starting

clock oscillation. The reset value of the SCMOD is “0”

SCMOD.0, SCMOD.2, and SCMOD.3 bits can be manipulated by 1-bit write instructions (In other words,

SCMOD.0, SCMOD.2, and SCMOD.3 cannot be modified simultaneously by a 4-bit write).

Bit 1 is always logic zero.

FB7H

SCMOD.3 SCMOD.2

"0"

SCMOD.0

A subsystem clock (fxt) can be selected as the system clock by manipulating the SCMOD.3 and SCMOD.0 bit

settings. If SCMOD.3 = "0" and SCMOD.0 = "1", the subsystem clock is selected and main system clock

oscillation continues. If SCMOD.3 = "1" and SCMOD.0 = "1", fxt is selected, but main system clock oscillation

stops.

Even if you have selected fx as the CPU clock, setting SCMOD.3 to "1" will stop main system clock oscillation,

and malfunction may be occured. To operate safely, main system clock should be stopped by a stop instruction

is main system clock mode.

Table 6-3. System Clock Mode Register (SCMOD) Organization

SCMOD Register Bit Settings

Resulting Clock Selection

CPU Clock Source fx Oscillation

fx On

SCMOD.3

SCMOD.0

0

1

0

1

fxt

On

Off

SCMOD.2

Sub-oscillation on/off

Enable sub system clock

Disable sub system clock

0

1

NOTE: You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed):

Main operation ® sub-operation ® sub-idle (LCD on, after a few minutes later without any external

input) ® sub-operation ® main operation ® SCMOD.2 = 1 ® main stop mode (LCD off).

6–6

KS57C21516/P21516 MICROCONTROLLER

OSCILLATOR CIRCUITS

Table 6-4. Main/Sub Oscillation Stop Mode

Osc Stop Release Source ⁽²⁾

Mode

Main

Oscillation

STOP Mode (stops).

System clock is the

Condition

Method to issue Osc Stop

Main oscillator runs.

Sub oscillator runs

STOP instruction:

Interrupt and RESET:

Main oscillator stops.

CPU is in idle mode.

Sub oscillator still runs

After releasing stop mode, main

oscillation starts and oscillation

stabilization time is elapsed. And then

the CPU operates.

main oscillation clock. (stops).

Oscillation stabilization time is

1/ {256 x BT clock (fx)}.

When SCMOD.3 is set to “1”

RESET:

(1),

main oscillator stops,

Interrupt can’t start the main

oscillation. Therefore, the CPU

operation can never be restarted.

halting the CPU operation.

Sub oscillator still runs

(stops).

Main oscillator runs.

Sub oscillator runs.

System clock is the

sub oscillation clock.

STOP instruction:

Main oscillator stops.

CPU is in idle mode.

Sub oscillator still runs

(stops).

BT overflow, interrupt, and RESET:

After the overflow of basic timer [1/

{256 x BT clock (fxt)}], CPU operation

and main oscillation automatically

start.

Sub oscillator still runs.

When SCMOD.3 is set to

“1”, main oscillator stops.

The CPU, however, would

still operate.

Set SCMOD.3 to “0” or RESET

Sub oscillator still runs.

Sub

Oscillation

STOP Mode System clock is the

Main oscillator runs.

Sub oscillator runs.

When SCMOD.2 to “1”, sub

oscillator stops, while main

oscillator and the CPU would

Set SCMOD.2 to “0” or RESET

main oscillation clock. still operate.

Main oscillator runs

(stops).

Sub oscillator runs.

System clock is the

sub oscillation clock.

When SCMOD.2 to “1”, sub

oscillator stops, halting the

CPU operation.

Main oscillator still runs

(stops).

RESET

NOTES:

1. This mode must not be used.

2. Oscillation stabilization time by interrupt is 1/ (256 x BT clocks). Oscillation stabilization time by a reset is

31.3ms at 4.19Mhz, main oscillation clock.

6–7

OSCILLATOR CIRCUITS

KS57C21516/P21516 MICROCONTROLLER

SWITCHING THE CPU CLOCK

Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD,

determine whether a main system or a subsystem clock is selected as the CPU clock, and also how this

frequency is to be divided. This makes it possible to switch dynamically between main and subsystem clocks and

to modify operating frequencies.

SCMOD.3, SCMOD.2, and SCMOD.0 select the main system clock (fx) or a subsystem clock (fxt) and start or

stop main system clock oscillation. PCON.1 and PCON.0 control the frequency divider circuit, and divide the

selected fx clock by 4, 8, or 64,or fxt clock by 4.

NOTE

A clock switch operation does not go into effect immediately when you make the SCMOD and PCON

register modifications — the previously selected clock continues to run for a certain number of machine

cycles.

For example, you are using the default CPU clock (normal operating mode and a main system clock of fx/64)

and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. To do this, you

first need to set SCMOD.0 to "1". This switches the clock from fx to fxt but allows main system clock oscillation

to continue. Before the switch actually goes into effect, a certain number of machine cycles must elapse. After

this time interval, you can then disable main system clock oscillation by setting SCMOD.3 to "1".

This same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first,

clear SCMOD.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles

has elapsed, select the main system clock by clearing all SCMOD values to logic zero.

Following a RESET, CPU operation starts with the lowest main system clock frequency of 15.3 µs at 4.19 MHz

after the standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6-4 details the number of

machine cycles that must elapse before a CPU clock switch modification goes into effect.

Table 6-5. Elapsed Machine Cycles During CPU Clock Switch

AFTER

SCMOD.0 = 0

PCON.1 = 1 PCON.0 = 0

SCMOD.0 = 1

BEFORE

PCON.1 = 0

PCON.0 = 0

PCON.1 = 1 PCON.0 = 1

PCON.1 = 0

PCON.0 = 0

PCON.1 = 1

PCON.0 = 0

PCON.1 = 1

PCON.0 = 1

N/A

1 MACHINE CYCLE

N/A

SCMOD.0 = 0

8 MACHINE CYCLES

16 MACHINE CYCLES

N/A

1 MACHINE CYCLES

N/A

1 MACHINE CYCLES

N/A

fx / 4fxt

N/A

SCMOD.0 = 1

1MACHINE CYCLES

NOTES:

1. Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered.

2. Since the X input is connected internally to V to avoid current leakage due to the crystal oscillator in stop mode, do

SS

IN

not set SCMOD.3 to "1" or do not use stop instruction when an external clock is used as the main system clock.

3. When the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur

during the time intervals shown in Table 6-4.

4. 'N/A' means 'not available'.

5. fx: Main-system clock, fxt: Sub-system clock. When fx is 4.19 MHz, and fxt is 32.768 kHz.

6–8

KS57C21516/P21516 MICROCONTROLLER

OSCILLATOR CIRCUITS

+

PROGRAMMING TIP — Switching Between Main System and Subsystem Clock

1. Switch from the main system clock to the subsystem clock:

MA2SUB

BITS

CALL

BITS

RET

LD

NOP

DECS

JR

SCMOD.0

DLY80

SCMOD.3

; Switches to subsystem clock

; Delay 80 machine cycles

; Stop the main system clock

DLY80

DEL1

A,#0FH

A

DEL1

RET

2. Switch from the subsystem clock to the main system clock:

SUB2MA

BITR

CALL

BITR

RET

SCMOD.3

DLY80

; Start main system clock oscillation

; Delay 160 machine cycles

SCMOD.0

; Switch to main system clock

6–9

OSCILLATOR CIRCUITS

KS57C21516/P21516 MICROCONTROLLER

CLOCK OUTPUT MODE REGISTER (CLMOD)

The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the

CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4-bit write instructions

only.

FD0H

CLMOD.3

"0"

CLMOD.1

CLMOD.0

RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without

initiating clock oscillation), and disables clock output.

CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four

possible clock sources and frequencies: normal CPU clock, fxx/8, fxx/16, or fxx/64.

Table 6-6. Clock Output Mode Register (CLMOD) Organization

CLMOD Bit Settings

Resulting Clock Output

CLMOD.1

CLMOD.0

Clock Source

Frequency

0

1

0

1

0

1

CPU clock (fx/4, fx/8, fx/64, fxt/4)

1.05 MHz, 524 kHz, 65.5 kHz, 8.2 kHz

fxx/8

524 kHz

262 kHz

65.5 kHz

fxx/16

fxx/64

CLMOD.3

Result of CLMOD.3 Setting

0

1

Disable clock output at the CLO pin

Enable clock output at the CLO pin

NOTE: Frequencies assume that fxx, fx = 4.19 MHz and fxt = 32.768 kHz.

6–10

KS57C21516/P21516 MICROCONTROLLER

CLOCK OUTPUT CIRCUIT

OSCILLATOR CIRCUITS

The clock output circuit, used to output clock pulses to the CLO pin, has the following components:

— 4-bit clock output mode register (CLMOD)

— Clock selector

— Output latch

— Port mode flag

— CLO output pin (P2.0)

CLMOD.3

CLO

CLMOD.2

4

CLMOD.1

Clock

P2.0 OUTPUT LATCH

PM 2

Selector

CLMOD.0

clocks

(fxx/8, fxx/16, fxx/64, CPU clock)

Figure 6-7. CLO Output Pin Circuit Diagram

CLOCK OUTPUT PROCEDURE

The procedure for outputting clock pulses to the CLO pin may be summarized as follows:

1. Disable clock output by clearing CLMOD.3 to logic zero.

2. Set the clock output frequency (CLMOD.1, CLMOD.0).

3. Load a "0" to the output latch of the CLO pin (P2.0).

4. Set the P2.0 mode flag (PM2.0) to output mode.

5. Enable clock output by setting CLMOD.3 to logic one.

+

PROGRAMMING TIP — CPU Clock Output to the CLO Pin

To output the CPU clock to the CLO pin:

BITS

SMB

LD

BITR

LD

EMB

15

EA,#10H

PMG1,EA

P2.0

A,#9H

CLMOD,A

; P2.0 ¬ Output mode

; Clear P2.0 output latch

LD

6–11

OSCILLATOR CIRCUITS

KS57C21516/P21516 MICROCONTROLLER

NOTES

6–12

KS57C21516/P21516 MICROCONTROLLER

INTERRUPTS

7

INTERRUPTS

OVERVIEW

The KS57C21516 interrupt control circuit has five functional components:

— Interrupt enable flags (IEx)

— Interrupt request flags (IRQx)

— Interrupt master enable register (IME)

— Interrupt priority register (IPR)

— Power-down release signal circuit

Three kinds of interrupts are supported:

— Internal interrupts generated by on-chip processes

— External interrupts generated by external peripheral devices

— Quasi-interrupts used for edge detection and as clock sources

Table 7–1. Interrupt Types and Corresponding Port Pin(s)

Interrupt Type

External interrupts

Interrupt Name

INT0, INT1, INT4, INTK

INTB, INTT0, INTT1, INTS

INT2

Corresponding Port Pins

P1.0, P1.1, P1.3, K0–K7

Not applicable

P1.2

Internal interrupts

Quasi-interrupts

INTW

Not applicable

7–1

INTERRUPTS

KS57C21516/P21516 MICROCONTROLLER

Vectored Interrupts

Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program

software. A vectored interrupt is generated when the following flags and register settings, corresponding to the

specific interrupt (INTn) are set to logic one:

— Interrupt enable flag (IEx)

— Interrupt master enable flag (IME)

— Interrupt request flag (IRQx)

— Interrupt status flags (IS0, IS1)

— Interrupt priority register (IPR)

If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is

loaded into the program counter and the program starts executing the service routine from this address.

EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM

during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction.

The initial flag values determine the vectors for resets and interrupts. Enable flag values are saved during the

main routine, as well as during service routines. Any changes that are made to enable flag values during a

service routine are not stored in the vector address.

When an interrupt occurs, the EMB and the ERB flags before the interrupt is initiated are saved along with the

program status word (PSW), and the EMB and the ERB flag for the interrupt is fetched from the respective vector

address. Then, if necessary, you can modify the enable flags during the interrupt service routine. When the

interrupt service routine is returned to the main routine by the IRET instruction, the original values saved in the

stack are restored and the main program continues program execution with these values.

Software-Generated Interrupts

To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the

interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met,

and the service routine can be initiated.

Multiple Interrupts

By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and

thereby process multiple interrupts simultaneously.

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

Power-Down Mode Release

An interrupt can be used to release power-down mode (stop or idle). Interrupts for power-down mode release are

initiated by setting the corresponding interrupt enable flag. Even if the IME flag is cleared to zero, power-down

mode will be released by an interrupt request signal when the interrupt enable flag has been set. In such cases,

the interrupt routine will not be executed since IME = "0".

7–2

KS57C21516/P21516 MICROCONTROLLER

INTERRUPTS

Interrupt is generated (INT xx)

Request flag (IRQx) <-- 1

NO

IEx = 1?

YES

Retain value until IEx = 1

Generate corresponding vector interrupt

and release power-down mode

NO

IME = 1?

Retain value until IME = 1

YES

Retain value until interrupt

service routine is completed

IS1,0 = 0,0?

NO

IS1,0 = 0,1 ?

YES

NO

High-priority interrupt?

YES

IS1,0 = 0,1

IS1,0 = 1,0

Store contents of PC and PSW in the stack area;

set PC contents to corresponding vector address

Are both interrupt sources

YES

of shared vector address used?

IRQx flag value remains 1

NO

Reset corresponding IRQx flag

Jump to interrupt start address

Verify interrupt source and clear

IRQx with a BTSTZ instruction

Figure 7–1. Interrupt Execution Flowchart

7–3

INTERRUPTS

KS57C21516/P21516 MICROCONTROLLER

IE2 IEW IETK IET1 IET0 IES IE1 IE0 IE4 IEB

IMOD1

IMOD0

INTB

IRQB

IRQ4

IRQ0

IRQ1

IRQS

IRQT0

IRQT1

IRQK

IRQW

IRQ2

INT4

INT0

INT1

@

INTS

INTT0

INTT1

K0-K7

INT2

@

INTW

IMODK

@

IMOD2

POWER-DOWN

MODE

RELEASE SIGNAL

IME

IPR

INTERRUPT CONTROL UNIT

IS1 IS0

VECTOR INTERRUPT

GENERATOR

@ = EDGE DETECTION CIRCUIT

Figure 7–2. Interrupt Control Circuit Diagram

7–4

KS57C21516/P21516 MICROCONTROLLER

INTERRUPTS

Multiple Interrupts

The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter-

rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service

routine for a lower-priority request is accepted during the execution of a higher priority routine.

Two-Level Interrupt Handling

Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits

of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all

interrupt requests are serviced (see Figure 7–3).

Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one and the values are stored in the

stack along with the other PSW bits. After the interrupt routine has been serviced, the modified IS1 and IS0

values are automatically restored from the stack by an IRET instruction.

IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable

memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable

interrupt processing with a DI instruction.

When IS1 = "0" and IS0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt

currently defined by the interrupt priority register (IPR).

NORMAL PROGRAM

PROCESSING

(STATUS 0)

HIGH OR LOW LEVEL

INTERRUPT PROCESSING

(STATUS 1)

HIGH LEVEL INTERRUPT

PROCESSING

(STATUS 2)

INT DISABLE

SET IPR

INT ENABLE

LOW OR

HIGH LEVEL

INTERRUPT

GENERATED

HIGH-LEVEL

INTERRUPT

GENERATED

Figure 7–3. Two-Level Interrupt Handling

7–5

INTERRUPTS

KS57C21516/P21516 MICROCONTROLLER

Multi-Level Interrupt Handling

With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt

is being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1 (see Table 7–2).

When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1"

and "0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority

request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority

level can be serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7–4).

Table 7–2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling

Process Status

Before INT

IS1 IS0

Effect of ISx Bit Setting

After INT ACK

IS1

0

IS0

1

0

1

0

All interrupt requests are serviced.

0

1

Only high-priority interrupts as determined by the

current settings in the IPR register are serviced.

1

0

2

–

1

0

1

No additional interrupt requests will be serviced.

Value undefined

–

NORMAL PROGRAM

PROCESSING

(STATUS 0)

SINGLE

INTERRUPT

2-LEVEL

INTERRUPT

INT DISABLE

SET IPR

3-LEVEL

INTERRUPT

INT DISABLE

STATUS 1

INT ENABLE

MODIFY STATUS

INT ENABLE

LOW OR

HIGH LEVEL

INTERRUPT

GENERATED

STATUS 0

HIGH-LEVEL

INTERRUPT

GENERATED

LOW OR HIGH

LEVEL

STATUS 1 STATUS 2

INTERRUPT

GENERATED

STATUS 0

Figure 7–4. Multi-Level Interrupt Handling

7–6

KS57C21516/P21516 MICROCONTROLLER

INTERRUPT PRIORITY REGISTER (IPR)

INTERRUPTS

The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic

zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI

instruction.

FB2H

IME

IPR.2

IPR.1

IPR.0

By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or

you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by

a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by

any other interrupt source.

Table 7–3. Standard Interrupt Priorities

Interrupt

INTB, INT4

INT0

Default Priority

1

2

3

4

5

6

7

INT1

INTS

INTT0

INTT1

INTK

The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if

an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the

IME flag is set to logic one. The IME flag can be directly manipulated by EI and DI instructions, regardless of the

current enable memory bank (EMB) value.

Table 7–4. Interrupt Priority Register Settings

IPR.2

IPR.1

IPR.0

Result of IPR Bit Setting

(NOTE)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Process all interrupt requests at low priority

Only INTB and INT4 interrupts are at high priority

Only INT0 interrupts is at high priority

Only INT1 interrupts is at high priority

Only INTS interrupts is at high priority

Only INTT0 interrupts is at high priority

Only INTT1 interrupts is at high priority

Only INTK interrupts is at high priority

NOTE: When all interrupts are low priority (the lower three bits of the IPR register are logic zero), the interrupt requested

first will have high priority. Therefore, the first-request interrupt cannot be superceded by any other interrupt. If two

or more interrupt requests are received simultaneously, the priority level is determined according to the standard

interrupt priorities in Table 7–3 (the default priority assigned by hardware when the lower three IPR bits = "0"). In

this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then, when the high-

priority interrupt is returned from its service routine by an IRET instruction, the inhibited service routine is started.

7–7

INTERRUPTS

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Setting the INT Interrupt Priority

The following instruction sequence sets the INT1 interrupt to high priority:

BITS

SMB

DI

LD

EMB

15

; IPR.3 (IME) ¬

0

1

A,#3H

IPR,A

EI

EXTERNAL INTERRUPT 0, 1 AND 2 MODE REGISTERS (IMOD0, IMOD1 AND IMOD2)

The following components are used to process external interrupts at the INT0, INT1 and INT2 pins:

— Edge detection circuit

— Three mode registers, IMOD0, IMOD1 and IMOD2

The mode registers are used to control the triggering edge of the input signal. IMOD0, IMOD1 and IMOD2

settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The

INT4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling

edges. Since INT2 is a qusi-interrupt, the interrupt request flag (IRQ2) must be cleared by software.

FB4H

FB5H

"0"

IMOD0.1

"0"

IMOD0.0

IMOD1.0

FDAH

"0"

IMOD2.0

IMOD0, IMOD1 and IMOD2 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic

zero, selecting rising edges as the trigger for incoming interrupt requests.

Table 7–5. IMOD0, 1 and 2 Register Organization

IMOD0

0

IMOD0.1

IMOD0.0

Effect of IMOD0 Settings

Rising edge detection

0

1

0

1

0

1

Falling edge detection

Both rising and falling edge detection

IRQ0 flag cannot be set to "1"

IMOD1

IMOD2

0

IMOD1.0

IMOD2.0

Effect of IMOD1 and IMOD2 Settings

0

1

Rising edge detection

Falling edge detection

7–8

KS57C21516/P21516 MICROCONTROLLER

INTERRUPTS

EXTERNAL INTERRUPT 0, 1 and 2 MODE REGISTERS (Continued)

IMOD0

2

EDGE DETECTION

IRQ0

IRQ1

IRQ2

INT0

INT1

INT2

EDGE DETECTION

IMOD2

IMOD1

P1.2

P1.1

P1.0

Figure 7–5. Circuit Diagram for INT0, INT1 and INT2 Pins

When modifying the IMOD registers, it is possible to accidentally set an interrupt request flag. To avoid unwanted

interrupts, take these precautions when writing your programs:

1. Disable all interrupts with a DI instruction.

2. Modify the IMOD register.

3. Clear all relevant interrupt request flags.

4. Enable the interrupt by setting the appropriate IEx flag.

5. Enable all interrupts with an EI instructions.

7–9

INTERRUPTS

KS57C21516/P21516 MICROCONTROLLER

EXTERNAL KEY INTERRUPT MODE REGISTER (IMODK)

The mode register for external key interrupts at the K0–K7 pins, IMODK, is addressable only by 4-bit write

instructions. RESET clears all IMODK bits to logic zero.

FB6H

"0"

IMODK.2

IMODK.1

IMODK.0

Rising or falling edge can be detected by bit IMODK.2 settings. If a rising or falling edge is detected at any one of

the selected K pin by the IMODK register, the IRQK flag is set to logic one and a release signal for power-down

mode is generated.

Table 7–6. IMODK Register Bit Settings

IMODK

0

IMODK.2

IMODK.1

IMODK.0

Effect of IMODK Settings

Disable key interrupt

0, 1

0

1

0

1

0

1

Enable edge detection at the K0–K3 pins

Enable edge detection at the K4–K7 pins

Enable edge detection at the K0–K7 pins

IMODK.2

NOTES:

0

1

Falling edge detection

Rising edge detection

1. To generate a key interrupt, the selected pins must be configured to input mode. If any one pin of the selected pins is

configured to output mode, only falling edge can be detected.

2. To generate a key interrupt, all of the selected pins must be at input high state for falling edge detection, or all of the

selected pins must be at input low state for rising edge detection. If any one of them or more is at input low state or input

high state, the interrupt may be not occurred at falling edge or rising edge.

3. To generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. And then, select edge

detection and pins by setting IMODK register.

7–10

KS57C21516/P21516 MICROCONTROLLER

INTERRUPTS

P6.3/K7

P6.2/K6

P6.1/K5

P6.0/K4

P0.3/K3

P0.2/K2

P0.1/K1

P0.0/K0

ENABLE/

DISABLE

RISING/

FALLING

EDGE

IRQK

SELECTOR

ENABLE/

DISABLE

IMODK

Figure 7–6. Circuit Diagram for INTK

7–11

INTERRUPTS

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Using INTK as a Key Input Interrupt

When the key interrupt is used, the selected key interrupt source pin must be set to input:

1. When K0–K7 are selected (eight pins):

BITS

SMB

LD

EMB

15

A,#3H

LD

IMODK,A

EA,#00H

PMG1,EA

PMG4,EA

EA,#41H

PUMOD1,EA

; (IMODK) ¬ #3H, K0–K7 falling edge select

; P0 ¬ input mode

; P6 ¬ input mode

; Enable P0 and P6 pull-up resistors

2. When K0–K3 are selected (four pins):

BITS

SMB

LD

EMB

15

A,#1H

LD

IMODK,A

EA,#00H

PMG1,EA

EA,#1H

PUMOD1,EA

; (IMODK) ¬ #1H, K0–K3 falling edge select

; P0 ¬ input mode

LD

; Enable P0 pull-up resistors

7–12

KS57C21516/P21516 MICROCONTROLLER

INTERRUPT FLAGS

INTERRUPTS

There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in-

terrupt, the interrupt master enable flag, which enables or disables all interrupt processing.

Interrupt Master Enable Flag (IME)

The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an

IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the

IME flag is set to logic one.

The IME flag is located in the IPR register (IPR.3). It can be directly be manipulated by EI and DI instructions,

regardless of the current value of the enable memory bank flag (EMB).

IME

0

IPR.2

IPR.1

IPR.0

Effect of Bit Settings

Inhibit all interrupts

Enable all interrupts

1

Interrupt Enable Flags (IEx)

IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request

flag is set to logical one, an interrupt will not be serviced until its corresponding IEx flag is also enabled.

Interrupt enable flags can be read, written, or tested directly by 1-bit instructions. IEx flags can be addressed

directly at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag.

Table 7–7. Interrupt Enable and Interrupt Request Flag Addresses

Address

FB8H

Bit 3

IE4

0

Bit 2

IRQ4

0

Bit 1

IEB

Bit 0

IRQB

IRQW

IRQT1

IRQT0

IRQS

IRQ0

FBAH

FBBH

FBCH

FBDH

FBEH

FBFH

IEW

IET1

IET0

IES

IEK

0

IRQK

0

IE1

0

IRQ1

0

IE0

IE2

IRQ2

NOTES:

1.

2.

3.

4.

IEx refers to all interrupt enable flags.

IRQx refers to all interrupt request flags.

IEx = 0 is interrupt disable mode.

IEx = 1 is interrupt enable mode.

7–13

INTERRUPTS

KS57C21516/P21516 MICROCONTROLLER

Interrupt Request Flags (IRQx)

Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions.IRQx flags can be addressed

directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag.

When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then

automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt

request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt

service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary,

follow these guidelines for using IRQx flags:

1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.

2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the

exception of IRQW and IRQ2).

3. When IRQx is set to "1" by software, an interrupt is generated.

When two interrupts share the same service routine start address, interrupt processing may occur in one of two

ways:

— When only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been

serviced.

— When two interrupts are enabled, the request flag is not automatically cleared so that the user has an

opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared

manually using a BTSTZ instruction.

Table 7–8. Interrupt Request Flag Conditions and Priorities

Interrupt

Source

Internal /

External

Pre-condition for IRQx Flag Setting

Interrupt

Priority

IRQ Flag

Name

INTB

I

Reference time interval signal from basic

timer

1

IRQB

INT4

INT0

INT1

INTS

E

I

Both rising and falling edges detected at INT4

Rising or falling edge detected at INT0 pin

Rising or falling edge detected at INT1 pin

1

2

3

4

IRQ4

IRQ0

IRQ1

IRQS

Completion signal for serial transmit-and-re-

ceive or receive-only operation

INTT0

INTT1

INTK

I

Signals for TCNT0 and TREF0 registers

match

5

6

7

IRQT0

IRQT1

IRQK

Signals for TCNT1 and TREF1 registers

match

E

When a rising or falling edge detected at any

one of the K0–K7 pins

INT2

E

I

Rising or falling edge detected at INT2

Time interval of 0.5 secs or 3.19 msecs

–

IRQ2

INTW

IRQW

7–14

KS57C21516/P21516 MICROCONTROLLER

INTERRUPTS

+

PROGRAMMING TIP — Enabling the INTB and INT4 Interrupts

To simultaneously enable INTB and INT4 interrupts:

INTB

DI

BTSTZ

JR

IRQB

INT4

; IRQB = 1 ?

; If no, INT4 interrupt; if yes, INTB interrupt is processed

•

EI

IRET

;

INT4

BITR

IRQ4

; INT4 is processed

•

EI

IRET

7–15

INTERRUPTS

KS57C21516/P21516 MICROCONTROLLER

NOTES

7–16

KS57C21516/P21516 MICROCONTROLLER

POWER-DOWN

8

POWER-DOWN

OVERVIEW

The KS57C21516 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle

mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must

always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals

and the oscillation source continue to operate normally.

When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and the

CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has

elapsed, normal CPU operation resumes.

In stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hard-

ware components are powered-down. The effect of stop mode on specific peripheral hardware components —

CPU, basic timer, serial I/O, timer/ counters 0 and 1, watch timer, and LCD controller — and on external interrupt

requests, is detailed in Table 8–1.

Idle or stop modes are terminated either by a RESET, or by an interrupt which is enabled by the corresponding

interrupt enable flag, IEx. When power-down mode is terminated by RESET, a normal reset operation is

executed. Assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down

mode is released immediately upon entering power-down mode.

When an interrupt is used to release power-down mode, the operation differs depending on the value of the

interrupt master enable flag (IME):

— If the IME flag = “0”; If the power down mode release signal is generated, after releasing the power-down

mode, program execution starts immediately under the instruction to enter power down mode without

execution of interrupt service routine. The interrupt request flag remains set to logic one.

— If the IME flag = "1"; If the power down mode release signal is generated, after releasing the power down

mode, two instructions following the instruction to enter power down mode are executed first and the interrupt

service routine is executed, finally program is resumed.

However, when the release signal is caused by INT2 or INTW, the operation is identical to the IME = “0”

condition because INT2 and INTW are a quasi-interrupt.

NOTE

Do not use stop mode if you are using an external clock source because X_INinput must be restricted

internally to V_SSto reduce current leakage.

8–1

POWER-DOWN

KS57C21516/P21516 MICROCONTROLLER

Table 8–1. Hardware Operation During Power-Down Modes

Operation

Stop Mode (STOP)

Idle Mode (IDLE)

System clock status

STOP mode can be used only if the

Idle mode can be used if the main

main system clock is selected as system system clock or subsystem clock is

clock

selected as system clock (CPU clock)

(CPU clock)

Clock oscillator

Basic timer

Main system clock oscillation stops

Basic timer stops

CPU clock oscillation stops (main and

subsystem clock oscillation continues)

Basic timer operates (with IRQB set at

each reference interval)

Serial I/O interface

Timer/counter 0

Timer/counter 1

Watch timer

Operates only if external SCK input is

selected as the serial I/O clock

Operates if a clock other than the CPU

clock is selected as the serial I/O clock

Operates only if TCL0 is selected as the Timer/counter 0 operates

counter clock

Operates only if TCL1 is selected as the Timer/counter 1 operates

counter clock

Operates only if subsystem clock (fxt) is Watch timer operates

selected as the counter clock

LCD controller

External interrupts

Operates only if a subsystem clock is se- LCD controller operates

lected as LCDCK

INTO, INT1, INT2, INT4, and INTK are

acknowledged

INT0, INT1, INT2, INT4 and INTK are

acknowledged

CPU

All CPU operations are disabled

Mode release signal

Interrupt request signals are enabled by

an interrupt enable flag or by RESET

input

Interrupt request signals are enabled by

an interrupt enable flag or by RESET

input

8–2

KS57C21516/P21516 MICROCONTROLLER

POWER-DOWN

Table 8-2. System Operating Mode Comparison

Mode

Condition

STOP/IDLE Mode Start

Method

Current Consumption

Main operating

mode

Main oscillator runs.

Sub oscillator runs (stops).

System clock is the main

oscillation clock.

–

IDLE instruction

STOP instruction

–

A

B

D

C

Main Idle mode Main oscillator runs.

Sub oscillator runs (stops).

System clock is the main

oscillation clock.

Main Stop

mode

Main oscillator runs.

Sub oscillator runs.

System clock is the main

oscillation clock.

Sub operating

mode

Main oscillator is stopped by

SCMOD.3.

Sub oscillator runs.

System clock is the sub

oscillation clock.

Sub ldle Mode

Main oscillator is stopped by IDLE instruction

SCMOD.3.

Sub oscillator runs.

System clock is the sub

oscillation clock.

D

E

Sub Stop mode Main oscillator is stopped by Setting SCMOD.2 to “1”:

SCMOD.3.

This mode can be released

only by an external RESET.

Sub oscillator runs.

System clock is the sub

oscillation clock.

Main/Sub Stop

mode

Main oscillator runs.

Sub oscillator is stopped by

SCMOD.2.

STOP instruction:

This mode can be released by

an interrupt and RESET.

System clock is the main

oscillation clock.

NOTE: The current consumption is: A > B > C > D > E.

8–3

POWER-DOWN

KS57C21516/P21516 MICROCONTROLLER

IDLE MODE TIMING DIAGRAMS

OSCILLATOR

STABILIZATION WAIT TIME

(31.3 ms / 4.19 MHz)

IDLE

INSTRUCTION

RESET

NORMAL MODE

IDLE MODE

NORMAL MODE

NORMAL OSCILLATION

CLOCK

SIGNAL

Figure 8–1. Timing When Idle Mode is Released by RESET

IDLE

INSTRUCTION

MODE

RELEASE

SIGNAL

INTERRUPT ACKNOWLEDGE (IME = 1)

NORMAL MODE

IDLE MODE

NORMAL OSCILLATION

CLOCK

SIGNAL

Figure 8–2. Timing When Idle Mode is Released by an Interrupt

8–4

KS57C21516/P21516 MICROCONTROLLER

STOP MODE TIMING DIAGRAMS

POWER-DOWN

OSCILLATOR

STABILIZATION WAIT TIME

(31.3 ms / 4.19 MHz)

STOP

INSTRUCTION

RESET

NORMAL MODE

STOP MODE

IDLE MODE

NORMAL MODE

OSCILLATION

STOPS

OSCILLATION RESUMES

CLOCK

SIGNAL

Figure 8–3. Timing When Stop Mode is Released by RESET

OSCILLATOR

STABILIZATION WAIT TIME

(BMOD SETTING)

STOP

INSTRUCTION

MODE

RELEASE

SIGNAL

INT ACK (IME = 1)

NORMAL MODE

STOP MODE

IDLE MODE

NORMAL MODE

OSCILLATION

STOPS

OSCILLATION RESUMES

CLOCK

SIGNAL

Figure 8–4. Timing When Stop Mode is Released by an Interrupt

8–5

POWER-DOWN

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Reducing Power Consumption for Key Input Interrupt Processing

The following code shows real-time clock and interrupt processing for key inputs to reduce power consumption.

In this example, the system clock source is switched from the main system clock to a subsystem clock and the

LCD display is turned on:

KEYCLK

DI

CALL

SMB

LD

MA2SUB

15

; Main system ® clock subsystem clock switch subroutine

EA,#00H

P4,EA

A,#3H

IMODK,A

0

IRQW

IRQK

IEW

IEK

WATDIS

IRQK

CIDLE

SUB2MA

; All key strobe outputs to low level

; Select K0–K7 enable

LD

SMB

BITR

BITS

CALL

BTSTZ

JR

CLKS1

; Execute clock and display changing subroutine

CALL

; Subsystem clock ® main system clock switch

subroutine

CIDLE

EI

RET

IDLE

NOP

JPS

; Engage idle mode

CLKS1

8–6

KS57C21516/P21516 MICROCONTROLLER

POWER-DOWN

RECOMMENDED CONNECTIONS FOR UNUSED PINS

To reduce overall power consumption, please configure unused pins according to the guidelines described in

Table 8–2.

Table 8-3. Unused Pin Connections for Reducing Power Consumption

Pin/Share Pin Names

Recommended Connection

Input mode: Connect to V

P0.0 / SCK / K0

P0.1 / SO / K1

P0.2 / SI / K2

DD

Output mode: No connection

P0.3 / BUZ / K3

Connect to V

DD

P1.0 / INT0 – P1.2 / INT2

P1.3 / INT4

Connect to V

DD

Input mode: Connect to V

DD

P2.0 / CLO

P2.1 / LCDCK

Output mode: No connection

P2.2 / LCDSY

P3.0 / TCLO0

P3.1 / TCLO1

P3.2 / TCL0

P3.3 / TCL1

P4.0 / COM8–P4.3 / COM11

P5.0 / COM12–P5.3 / COM15

P6.0 / SEG55 / K4 – P6.3 /

SEG52 / K7

P7.0 / SEG51–P7.3 / SEG48

P8.0 / SEG47–P8.3 / SEG44

P9.0 / SEG43–P9.3 / SEG40

SEG0–SEG39

COM0–COM7

No connection

V –V

LC1 LC5

No connection

(note)

Stop sub-oscillator by setting the SCMOD.2 to logic “1”

No connection

XT

in

out

Connect to V

SS

TEST

NOTE: You can stop the sub-oscillator by setting the SCMOD.2 to one.

8–7

POWER-DOWN

KS57C21516/P21516 MICROCONTROLLER

NOTES

8–8

KS57C21516/P21516 MICROCONTROLLER

RESET

9

RESET

OVERVIEW

When a RESET signal is input during normal operation or power-down mode, a hardware reset operation is

initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at

4.19 MHz has elapsed, normal system operation resumes.

Regardless of when the RESET occurs — during normal operating mode or during a power-down mode — most

hardware register values are set to the reset values described in Table 9–1. The current status of several register

values is, however, always retained when a RESET occurs during idle or stop mode; If a RESET occurs during

normal operating mode, their values are undefined. Current values that are retained in this case are as follows:

— Carry flag

— Data memory values

— General-purpose registers E, A, L, H, X, W, Z, and Y

— Serial I/O buffer register (SBUF)

OSCILLATOR

STABILIZATION WAIT TIME

(31.3 ms / 4.19 MHz)

RESET

INPUT

NORMAL MODE

IDLE MODE

NORMAL MODE

OR

POWER-DOWN

MODE

RESET

OPERATION

Figure 9–1. Timing for Oscillation Stabilization after RESET

HARDWARE REGISTER VALUES AFTER RESET

Table 9–1 gives you detailed information about hardware register values after a RESET occurs during power-

down mode or during normal operation.

9–1

RESET

KS57C21516/P21516 MICROCONTROLLER

Table 9–1. Hardware Register Values After RESET

Hardware Component

or Subcomponent

If RESET Occurs During

Power-Down Mode

If RESET Occurs During

Normal Operation

Program counter (PC)

Lower six bits of address 0000H Lower six bits of address 0000H

are transferred to PC13–8, and are transferred to PC13–8, and

the contents of 0001H to PC7–0. the contents of 0001H to PC7–0.

Program Status Word (PSW):

Carry flag (C)

Retained

Undefined

Skip flag (SC0–SC2)

0

Interrupt status flags (IS0, IS1)

Bank enable flags (EMB, ERB)

Bit 6 of address 0000H in

program memory is transferred

to the ERB flag, and bit 7 of the

address to the EMB flag.

program memory is transferred

to the ERB flag, and bit 7 of the

address to the EMB flag.

Stack pointer (SP)

Undefined

Data Memory (RAM):

General registers E, A, L, H, X, W, Z, Y

General-purpose registers

Values retained

Undefined

0, 0

(note)

Values retained

Bank selection registers (SMB, SRB)

BSC register (BSC0–BSC3)

0, 0

0

Clocks:

Power control register (PCON)

0

Clock output mode register (CLMOD)

System clock mode register (SCMOD)

Interrupts:

Interrupt request flags (IRQx)

Interrupt enable flags (IEx)

Interrupt priority flag (IPR)

0

Interrupt master enable flag (IME)

INT0 mode register (IMOD0)

INT1 mode register (IMOD1)

INT2 mode register (IMOD2)

INTK mode register (IMODK)

NOTE: The values of the 0F8H–0FDH are not retained when a RESET signal is input.

9–2

KS57C21516/P21516 MICROCONTROLLER

RESET

Table 9–1. Hardware Register Values After RESET (Continued)

Hardware Component

or Subcomponent

If RESET Occurs During

Power-Down Mode

If RESET Occurs During

Normal Operation

I/O Ports:

Output buffers

Off

0

Off

0

Output latches

Port mode flags (PM)

Pull-up resistor mode reg (PUMOD1/2)

0

Basic Timer:

Count register (BCNT)

Mode register (BMOD)

Mode register (WDMOD)

Counter clear flag (WDTCF)

Undefined

0

A5H

0

A5H

0

Timer/Counters 0 and 1:

Count registers (TCNT0/1)

Reference registers (TREF0/1)

Mode registers (TMOD0/1)

Output enable flags (TOE0/1)

0

FFH, FFFFH

0

Watch Timer:

Watch timer mode register (WMOD)

LCD Driver/Controller:

0

LCD mode register (LMOD)

LCD control register (LCON)

Display data memory

Output buffers

0

Values retained

Off

0

Undefined

Off

Serial I/O Interface:

SIO mode register (SMOD)

SIO interface buffer (SBUF)

0

Values retained

Undefined

N-Channel Open-Drain Mode Register

PNE0/3

0

9–3

RESET

KS57C21516/P21516 MICROCONTROLLER

NOTES

9–4

KS57C21516/P21516 MICROCONTROLLER

I/O PORTS

10 I/O PORTS

OVERVIEW

The KS57C21516 has 10 ports. There are total of 4 input pins and 35 configurable I/O pins, for a maximum

number of 39 pins.

Pin addresses for all ports are mapped to bank 15 of the RAM. The contents of I/O port pin latches can be read,

written, or tested at the corresponding address using bit manipulation instructions.

Port Mode Flags

Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the

corresponding I/O buffer.

Pull-up Resistor Mode Register (PUMOD)

The pull-up register mode registers (PUMOD1, 2) are used to assign internal pull-up resistors by software to

specific ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is

automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.

10–1

I/O PORTS

KS57C21516/P21516 MICROCONTROLLER

Function Description

Table 10–1. I/O Port Overview

Port

I/O

Pins

Pin Names

P0.0–P0.3

Address

0

I/O

4

FF0H

4-bit I/O port.

1-bit and 4-bit read/write and test is possible.

Individual pins are software configurable as

input or output.

Individual pins are software configurable as

open-drain or push-pull output.

4-bit pull-up resistors are software assignable;

pull-up resistors are automatically disabled for

output pins.

1

2

I

4

3

P1.0–P1.3

FF1H

4-bit input port.

1-bit and 4-bit read and test is possible.

4-bit pull-up resistors are assignable.

I/O

P2.0–P2.2

P3.0–P3.3

FF2H

FF3H

Same as port 0 except that port 2 is 3-bit I/O

port.

3

I/O

4

8

Same as port 0.

4, 5

P4.0–P4.3

P5.0–P5.3

FF4H

FF5H

4-bit I/O ports.

1-, 4-bit or 8-bit read/write and test is possible.

Individual pins are software configurable as

input or output.

4-bit pull-up resistors are software assignable;

pull-up resistors are automatically disabled for

output pins.

6, 7

8, 9

I/O

8

P6.0–P6.3

P7.0–P7.3

FF6H

FF7H

Same as P4 and P5.

P8.0–P8.3

P9.0–P9.3

FF8H

FF9H

Same as P4 and P5.

Table 10–2. Port Pin Status During Instruction Execution

Instruction Type

Example

Input Mode Status

Output Mode Status

1-bit test

BTST P0.1

Input or test data at each pin

Input or test data at output latch

1-bit input

4-bit input

8-bit input

LDB

LD

C,P1.3

A,P7

EA,P4

1-bit output

BITR P2.3

Output latch contents undefined

Output pin status is modified

4-bit output

8-bit output

LD

P2,A

P6,EA

Transfer accumulator data to the

output latch

Transfer accumulator data to the

output pin

10–2

KS57C21516/P21516 MICROCONTROLLER

PORT MODE FLAGS (PM FLAGS)

I/O PORTS

Port mode flags (PM) are used to configure I/O ports to input or output mode by setting or clearing the

corresponding I/O buffer.

For convenient program reference, PM flags are organized into five groups — PMG1, PMG2, PMG3, PMG4 and

PMG5 as shown in Table 10–3. They are addressable by 8-bit write instructions only.

When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. RESET clears all

port mode flags to logical zero, automatically configuring the corresponding I/O ports to input mode.

Table 10–3. Port Mode Group Flags

PM Group ID

Address

FE6H

FE7H

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

FEEH

FEFH

Bit 3

PM0.3

"0"

Bit 2

PM0.2

PM2.2

PM3.2

"0"

Bit 1

PM0.1

PM2.1

PM3.1

"0"

Bit 0

PM0.0

PM2.0

PM3.0

"0"

PMG1

PMG2

PMG3

PMG4

PMG5

PM3.3

"0"

PM4.3

PM5.3

PM6.3

PM7.3

PM8.3

PM9.3

PM4.2

PM5.2

PM6.2

PM7.2

PM8.2

PM9.2

PM4.1

PM5.1

PM6.1

PM7.1

PM8.1

PM9.1

PM4.0

PM5.0

PM6.0

PM7.0

PM8.0

PM9.0

NOTE: If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode: PM0.0 for

P0.0, PM0.1 for P0.1, etc,. All flags are cleared to "0" following RESET.

+

PROGRAMMING TIP — Configuring I/O Ports to Input or Output

Configure ports 0 and 2 as an output port:

BITS

SMB

LD

EMB

15

EA,#7FH

PMG1,EA

LD

; P0 and P2 ¬ Output

10–3

I/O PORTS

KS57C21516/P21516 MICROCONTROLLER

PULL-UP RESISTOR MODE REGISTER (PUMOD)

The pull-up resistor mode registers (PUMOD1 and PUMOD2) are used to assign internal pull-up resistors by soft-

ware to specific ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is

automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.

PUMOD1 is addressable by 8-bit write instructions only, and PUMOD2 by 4-bit write instruction only. RESET

clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up

resistors.

Table 10–4. Pull-Up Resistor Mode Register (PUMOD) Organization

PUMOD ID

Address

FDCH

Bit 3

PUR3

PUR7

"0"

Bit 2

PUR2

PUR6

"0"

Bit 1

PUR1

PUR5

PUR9

Bit 0

PUR0

PUR4

PUR8

PUMOD1

FDDH

PUMOD2

FDEH

NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2,

and so on.

+

PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors

P6 and P7 enable pull-up resistors.

BITS

SMB

LD

EMB

15

EA,#0C0H

PUMOD1,EA

LD

; P6 and P7 enable

N-CHANNEL OPEN-DRAIN MODE REGISTER (PNE)

The n-channel, open-drain mode register (PNE) is used to configure ports 0, 2 and 3 to n-channel, open-drain or

as push-pull outputs. When a bit in the PNE register is set to "1", the corresponding output pin is configured to n-

channel, open-drain; when set to "0", the output pin is configured to push-pull. The PNE register consists of an 8-

bit register and a 4-bit register; PNE0 can be addressed by 8-bit write instructions only and PNE3 by 4-bit write

instructions only.

FD6H

FD7H

PNE0.3

PNE2.3

PNE0.2

PNE2.2

PNE0.1

PNE2.1

PNE0.0

PNE2.0

PNE1

FD8H

PNE3.3

PNE3.2

PNE3.1

PNE3.0

PNE2

10–4

KS57C21516/P21516 MICROCONTROLLER

PORT 0 CIRCUIT DIAGRAM

I/O PORTS

V

DD

PUR0

PM0.3

PM0.2

PM0.1

PM0.0

SCK

P0.0/

Type B

SO

P0.1/SO

P0.2/SI

Type B

OUTPUT

LATCH

1, 4

Type B

BUZ

Type B

P0.3/BUZ

CMOS PUSH -PULL,

N-CHANNEL

Type B

V_DD

PNE0.x

OPEN-DRAIN

P-CH

M

U

X

PM0.0

PM0.2

Output

Data

SCK

1, 4

Input

Data

N-CH

PM0.x

SI

x = 0-3

NOTE:

When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the

port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (PUMOD).

Figure 10–1. Port 0 Circuit Diagram

10–5

I/O PORTS

KS57C21516/P21516 MICROCONTROLLER

PORT 1 CIRCUIT DIAGRAM

VDD

INT0 INT1 INT2

INT4

PUMOD.1

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

N/R = Noise Reduction

Figure 10–2. Port 1 Circuit Diagram

10–6

KS57C21516/P21516 MICROCONTROLLER

PORT 2 CIRCUIT DIAGRAM

I/O PORTS

V

DD

PUR2

PM2.2

PM2.1

PM2.0

CLO

Type B

P2.0/CLO

LCDCK

Type B

P2.1/LCDCK

OUTPUT

LATCH

1, 4

LCDSY

Type B

P2.2/LCDSY

Type B

CMOS PUSH-PULL,

N-CHANNEL

V

DD

PNE2.x

OPEN-DRAIN

P-CH

Output

Data

PM2.0

PM2.1

PM2.2

M

U

X

1, 4

Input

Data

N-CH

PM2.x

x = 0-2

NOTE: When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the

port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

Figure 10–3. Port 2 Circuit Diagram

10–7

I/O PORTS

KS57C21516/P21516 MICROCONTROLLER

PORT 3 CIRCUIT DIAGRAM

V

DD

PUR3

PM3.3

PM3.2

PM3.1

PM3.0

TCLO0

Type B

P3.0/TCLO0

P3.1/TCLO1

P3.2/TCL0

P3.3/TCL1

Type B

TCLO1

Type B

OUTPUT

LATCH

1, 4

Type B

CMOS PUSH-PULL,

N-CHANNEL

V

DD

PNE3.x

OPEN-DRAIN

P-CH

Output

Data

N-CH

M

U

X

PM3.0

PM3.1

1, 4

Input

Data

PM3.x

x = 0-3

TCL0

TCL1

NOTE:

When a port pin serves as an output, its pull-up resistor is automatically disabled, even though the

port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (PUMOD).

Figure 10–4. Port 3 Circuit Diagram

10–8

KS57C21516/P21516 MICROCONTROLLER

PORT 4, 5, 6, 7, 8, 9 CIRCUIT DIAGRAM

I/O PORTS

V

DD

x = port number (4, 5, 6, 7, 8, 9)

PURx

PMx.3

PMx.2

PMx.1

PMx.0

Px.0

Px.1

Px.2

Px.3

OUTPUT

LATCH

1, 4, 8

PMx.0

PMx.1

PMx.2

PMx.3

M

U

X

1, 4, 8

When a port pin serves as an output, its pull-up resistor is automatically disabled, even though

the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

Port 6 is a schmitt trigger input.

NOTE:

Figure 10–5. Ports 4, 5, 6, 7, 8, and 9 Circuit Diagram

10–9

I/O PORTS

KS57C21516/P21516 MICROCONTROLLER

NOTES

10–10

KS57C21516/P21516 MICROCONTROLLER

I/O PORTS

10–11

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

11 TIMERS and TIMER/COUNTERS

OVERVIEW

The KS57C21516 microcontroller has four timer and timer/counter modules:

— 8-bit basic timer (BT)

— 8-bit timer/counter (TC0)

— 16-bit timer/counter (TC1)

— Watch timer (WT)

The 8-bit basic timer (BT) is the microcontroller's main interval timer and watch-dog timer. It generates an

interrupt request at a fixed time interval when the appropriate modification is made to its mode register. The

basic timer is also used to determine clock oscillation stabilization time when stop mode is released by an

interrupt and after a RESET.

The 8-bit timer/counter (TC0) and the 16-bit timer/counter (TC1) are programmable timer/counters that are used

primarily for event counting and for clock frequency modification and output. In addition, TC0 generates a clock

signal that can be used by the serial I/O interface.

The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency

divider circuit. Watch timer functions include real-time and watch-time measurement, main and subsystem clock

interval timing, buzzer output generation. It also generates a clock signal for the LCD controller.

11–1

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

BASIC TIMER (BT)

OVERVIEW

The 8-bit basic timer (BT) has six functional components:

— Clock selector logic

— 4-bit mode register (BMOD)

— 8-bit counter register (BCNT)

— 8-bit watchdog timer mode register (WDMOD)

— Watchdog timer counter clear flag (WDTCF)

The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.

You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize

clock oscillation when stop mode is released by an interrupt and following RESET. Bit settings in the basic timer

mode register BMOD turns the BT module on and off, selects the input clock frequency, and controls interrupt or

stabilization intervals.

Interval Timer Function

The basic timer's primary function is to measure elapsed time intervals. The standard time interval is equal to

256 basic timer clock pulses.

To restart the basic timer, one bit setting is required: bit 3 of the mode register BMOD should be set to logic one.

The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit

values to BMOD.2–BMOD.0.

The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the

frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs (³

255). An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated

time interval has elapsed. An interrupt request is than generated, BCNT is cleared to logic zero, and counting

continues from 00H.

Watchdog Timer Function

The basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation

error. For this purpose, instruction that clear the watchdog timer (BITS WDTCF) should be executed at proper

points in a program within given period. If an instruction that clears the watchdog timer is not executed within the

given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset

status. An operation of watchdog timer is as follows:

— Write some values (except #5AH) to watchdog timer mode register, WDMOD.

— If WDCNT overflows, system reset is generated.

11–2

KS57C21516/P21516 MICROCONTROLLER

Oscillation Stabilization Interval Control

TIMERS and TIMER/COUNTERS

Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also

determines the time interval (also referred to as ‘wait time’) required to stabilize clock signal oscillation when stop

mode is released by an interrupt. When a RESET signal is inputted, the standard stabilization interval for system

clock oscillation following the RESET is 31.3 ms at 4.19 MHz.

Table 11-1. Basic Timer Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

BMOD

Control

Controls the clock frequency (mode) 4-bit

of the basic timer; also, the

oscillation stabilization interval after

stop mode release or RESET

F85H

4-bit write-only; “0”

BMOD.3: 1-bit

writeable

U^(note)

BCNT

Counter Counts clock pulses matching the

BMOD frequency setting

8-bit

F86H–F87H

8-bit read-only

WDMOD Control

WDTCF Control

Controls watchdog timer operation.

F98H–F99H

F9AH.3

8-bit write-only A5H

1-, 4-bit write “0”

Clears the watchdog timer’s counter. 1-bit

NOTE: 'U' means the value is undetermined after a RESET.

11–3

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

"CLEAR" SIGNAL

CLEAR

BCNT

CLEAR

IRQB

BITS

INSTRUCTION

BMOD.3

BMOD.2

BMOD.1

BMOD.0

INTERRUPT

REQUEST

OVERFLOW

CLOCK

4

BCNT

8

IRQB

SELECTOR

1-BIT R/W

CPU CLOCK

START SIGNAL

(POWER-DOWN RELEASE)

CLOCK INPUT

8

1 pulse period=BT input clock 2 (1/2 duty)

3-BIT COUNTER

OVERFLOW

WDCNT

RESET SIGNAL

GENERATION

RESET

Clear

WDMOD

8

WDTCF

BITS

DELAY

Clear

(note)

STOP

WAIT

RESET

INSTRUCTION

NOTES:

RESET

1. WAIT means stabilization time after

2. The

or stabilization time after STOP mode release.

RESET

signal can be generated if the WDMOD is toggled for 8 times where “toggle”

means change from 5AH to other value and vice versa.

3.

When the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared

to “0”, the BCNT value is not cleared but increased continuously.

As a result, the 3-bit counter of the watchdog timer (WDCNT) can be increased by 1.

For example, when the BMOD value is x000B and the watchdog timer is enabled,

3

12

8

3

12

8

the watchdog timer interval time is either 2 x 2 x 2 /fxx or (2 -1) x 2 x 2 /fxx.

Figure 11-1. Basic Timer Circuit Diagram

11–4

KS57C21516/P21516 MICROCONTROLLER

BASIC TIMER MODE REGISTER (BMOD)

TIMERS and TIMER/COUNTERS

The basic timer mode register, BMOD, is a 4-bit write-only register. Bit 3, the basic timer start control bit, is also

1-bit addressable. All BMOD values are set to logic zero following RESET and interrupt request signal generation

is set to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following

effects:

— Restart the basic timer;

— Control the frequency of clock signal input to the basic timer;

— Determine time interval required for clock oscillation to stabilize following the release of stop mode by an

interrupt.

By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency

12

5

during program execution. Four BT frequencies, ranging from fxx/2 to fxx/2 , are selectable. Since BMOD's

12

reset value is logic zero, the default clock frequency setting is fxx/2

.

The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set

to logic one by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt

request flag (IRQB) are both cleared to logic zero, and timer operation restarts.

The combination of bit settings in the remaining three registers — BMOD.2, BMOD.1, and BMOD.0 — determine

the clock input frequency and oscillation stabilization interval.

Table 11-2. Basic Timer Mode Register (BMOD) Organization

BMOD.3

Basic Timer Start Control Bit

1

Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0"

BMOD.2

BMOD.1

BMOD.0

Basic Timer Input Clock

Interrupt Interval Time

(Wait Time)

12

20

0

1

0

1

0

1

0

1

fxx/2 (1.02 kHz)

2

/fxx (250 ms)

/fxx (31.3 ms)

/fxx (7.82 ms)

/fxx (1.95 ms)

9

17

fxx/2 (8.18 kHz)

2

7

15

13

fxx/2 (32.7 kHz)

5

fxx/2 (131 kHz)

NOTES

1. Clock frequencies and interrupt interval time assume a system oscillator clock frequency (fxx) of 4.19 MHz.

2. fxx = system clock frequency.

3. Wait time is the time required to stabilize clock signal oscillation after stop mode is released. The

data in the table column "Interrupt Interval Time" can also be interpreted as "Oscillation Stabilization."

4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.

11–5

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

BASIC TIMER COUNTER (BCNT)

BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions. RESET leaves the

BCNT counter value undetermined. BCNT is automatically cleared to logic zero whenever the BMOD register

control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock pulse of the

frequency determined by the current BMOD bit settings is detected.

When BCNT has incrementing to hexadecimal ‘FFH’ (³ 255 clock pulses), it is cleared to ‘00H’ and an overflow is

generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt

request is generated, BCNT immediately resumes counting incoming clock signals.

NOTE

Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while

the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the

latter value as valid data. Until the results of the consecutive reads match, however, the read operation

must be repeated until the validation condition is met.

BASIC TIMER OPERATION SEQUENCE

The basic timer's sequence of operations may be summarized as follows:

1. Set BMOD.3 to logic one to restart the basic timer.

2. BCNT is then incremented by one after each clock pulse corresponding to BMOD selection.

3. BCNT overflows if BCNT = 255 (BCNT = FFH).

4. When an overflow occurs, the IRQB flag is set by hardware to logic one.

5. The interrupt request is generated.

6. BCNT is then cleared by hardware to logic zero.

7. Basic timer resumes counting clock pulses.

11–6

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Using the Basic Timer

1. To read the basic timer count register (BCNT):

BITS

SMB

LD

EMB

15

BCNTR

EA,BCNT

YZ,EA

EA,BCNT

EA,YZ

BCNTR

CPSE

JR

2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms:

BITS

SMB

LD

EMB

15

A,#0BH

BMOD,A

LD

; Wait time is 31.3 ms

NOP

STOP

NOP

; Set stop power-down mode

NORMAL OPERATING

MODE

NORMAL OPERATING

STOP MODE

IDLE MODE

(31.3 ms)

MODE

CPU

OPERATION

STOP

INSTRUCTION

STOP MODE IS

RELEASED BY

INTERRUPT

3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz):

BITS

SMB

LD

EMB

15

A,#0FH

BMOD,A

LD

EI

BITS

IEB

; Basic timer interrupt enable flag is set to "1"

4. Clear BCNT and the IRQB flag and restart the basic timer:

BITS

SMB

BITS

EMB

15

BMOD.3

11–7

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

WATCHDOG TIMER MODE REGISTER (WDMOD)

The watchdog timer mode register, WDMOD, is a 8-bit write-only register. WDMOD register controls to enable or

disable the watchdog function. WDMOD values are set to logic “A5H” following RESET and this value enables the

watchdog timer. Watchdog timer is set to the longest interval because BT overflow signal is generated with the

longest interval.

WDMOD

Watchdog Timer Enable/Disable Control

Disable watchdog timer function

Enable watchdog timer function

5AH

Any other value

WATCHDOG TIMER COUNTER (WDCNT)

The watchdog timer counter, WDCNT, is a 3-bit counter. WDCNT is automatically cleared to logic zero, and

restarts whenever the WDTCF register control bit is set to “1”. RESET, stop, and wait signal clears the WDCNT to

logic zero also.

WDCNT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit

setting is generated. When WDCNT has incremented to hexadecimal ‘07H’, it is cleared to ‘00H’ and an overflow

is generated. The overflow causes the system RESET. When the interrupt request is generated, BCNT

immediately resumes counting incoming clock signals.

WATCHDOG TIMER COUNTER CLEAR FLAG (WDTCF)

The watchdog timer counter clear flag, WDTCF, is a 1-bit write instruction. When WDTCF is set to one, it clears

the WDCNT to zero and restarts the WDCNT. WDTCF register bits 2–0 are always logic zero.

Table 11-3. Watchdog Timer Interval Time

WDT Interval Time ⁽³⁾

2³´ 2¹²´ 2⁸/fxx or (2³–1) ´ 2¹²´ 2⁸/fxx

2³´ 2⁹´ 2⁸/fxx or (2³–1) ´ 2⁹´ 2⁸/fxx

2³´ 2⁷´ 2⁸/fxx or (2³–1) ´ 2⁷´ 2⁸/fxx

2³´ 2⁵´ 2⁸/fxx or (2³–1) ´ 2⁵´ 2⁸/fxx

BMOD

x000b

x011b

x101b

x111b

BT Input Clock

fxx/2¹²

1.75–2.0 sec

218.7–250 ms

54.6–62.5ms

13.6–15.6 ms

fxx/2⁹

fxx/2⁷

fxx/2⁵

NOTES:

1. Clock frequencies assume a system oscillator clock frequency (fx) of 4.19 MHz

2. fxx = system clock frequency.

3. When the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to “0”, the BCNT value is not

cleared but increased continuously. As a result, the 3-bit counter of the watchdog timer (WDCNT) can be increased

by 1. For example, when the BMOD value is x000b and the watchdog timer is enabled, the watchdog timer interval time

3

12

8

3

12

8

is either 2 ´ 2 ´ 2 /fxx or (2 –1) ´ 2 ´ 2 /fxx.

11–8

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Using the Watchdog Timer

RESET

DI

LD

EA,#00H

SP,EA

·

LD

A,#0DH

; WDCNT input clock is 7.82 ms

LD

BMOD,A

·

MAIN

BITS

·

WDTCF

MAIN

; Main routine operation period must be shorter than

; watchdog-timer’s period

JP

11–9

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

8-BIT TIMER/COUNTER 0 (TC0)

OVERVIEW

Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of

incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has

elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter

value with the reference register value, TC0 can be used to measure specific time intervals.

TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write

the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by

counter logic.

An 8-bit mode register, TMOD0, is used to activate the timer/counter and to select the basic clock frequency to

be used for timer/counter operations. To dynamically modify the basic frequency, new values can be loaded into

the TMOD0 register during program execution.

TC0 FUNCTION SUMMARY

8-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock fre-

quency.

Counts various system "events" based on edge detection of external clock sig-

nals at the TC0 input pin, TCL0. To start the event counting operation,

TMOD0.2 is set to "1" and TMOD0.6 is cleared to "0".

Arbitrary frequency output

External signal divider

Outputs selectable clock frequencies to the TC0 output pin, TCLO0.

Divides the frequency of an incoming external clock signal according to a

modifiable reference value (TREF0), and outputs the modified frequency to the

TCLO0 pin.

Serial I/O clock source

Outputs a modifiable clock signal for use as the SCK clock source.

11–10

KS57C21516/P21516 MICROCONTROLLER

TC0 COMPONENT SUMMARY

TIMERS and TIMER/COUNTERS

Mode register (TMOD0)

Reference register (TREF0)

Counter register (TCNT0)

Clock selector circuit

Activates the timer/counter and selects the internal clock frequency or the

external clock source at the TCL0 pin.

Stores the reference value for the desired number of clock pulses between in-

terrupt requests.

Counts internal or external clock pulses based on the bit settings in TMOD0

and TREF0.

Together with the mode register (TMOD0), lets you select one of four internal

clock frequencies or an external clock.

8-bit comparator

Determines when to generate an interrupt by comparing the current value of

the counter register (TCNT0) with the reference value previously programmed

into the reference register (TREF0).

Output latch (TOL0)

Where a clock pulse is stored pending output to the serial I/O circuit or to the

TC0 output pin, TCLO0.

When the contents of the TCNT0 and TREF0 registers coincide, the

timer/counter interrupt request flag (IRQT0) is set to "1", the status of TOL0 is

inverted, and an interrupt is generated.

Output enable flag (TOE0)

Must be set to logic one before the contents of the TOL0 latch can be output to

TCLO0.

Interrupt request flag (IRQT0) Cleared when TC0 operation starts and the TC0 interrupt service routine is

executed and set to 1 whenever the counter value and reference value

coincide.

Interrupt enable flag (IET0)

Must be set to logic one before the interrupt requests generated by

timer/counter 0 can be processed.

Table 11–4. TC0 Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

TMOD0

Control

Controls TC0 enable/disable

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and clock frequency

(bits 6–4)

8-bit

F90H–F91H

8-bit write-

only;

(TMOD0.3 is

also 1-bit

writeable)

"0"

TCNT0

TREF0

TOE0

Counter

Counts clock pulses matching

the TMOD0 frequency setting

8-bit

1-bit

F94H–F95H

F96H–F97H

F92H.2

8-bit

read-only

"0"

FFH

"0"

Reference Stores reference value for the

timer/counter 0 interval setting

8-bit

write-only

Flag

Controls timer/counter 0 output

to the TCLO0 pin

1/4-bit

read/write

11–11

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

CLOCKS

10

4

6

(fxx/2 , fxx/2 , fxx/2 , fxx)

TCL0

8

TMOD0.7

TMOD0.6

8-BIT

TREF0

TCNT0

COMPARATOR

CLOCK

SELECTOR

TMOD0.5

8

TMOD0.4

CLEAR

TMOD0.3

TMOD0.2

TMOD0.1

TMOD0.0

INVERTED

CLEAR

SET

IRQT0

CLEAR

TOL0

SERIAL I/O

TCLO0

P3.0 LATCH

PM3.0

TOE0

Figure 11–2. TC0 Circuit Diagram

TC0 ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 0

— Set TMOD0.2 to logic one.

— Set the TC0 interrupt enable flag IET0 to logic one.

— Set TMOD0.3 to logic one.

TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter 0

— Set TMOD0.2 to logic zero.

Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read

if necessary.

11–12

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected

system clock frequency. Its 8-bit TC0 mode register TMOD0 is used to activate the timer/counter and to select

the clock frequency. The reference register TREF0 stores the value for the number of clock pulses to be

generated between interrupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are

compared to the TREF0 value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt

request is generated.

To program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock

frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF0 register.

TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency

specified by TMOD0.4–TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag

(IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0

is then cleared to 00H and TC0 continues counting. The interrupt request mechanism for TC0 includes an

interrupt enable flag (IET0) and an interrupt request flag (IRQT0).

TC0 OPERATION SEQUENCE

The general sequence of operations for using TC0 can be summarized as follows:

1. Set TMOD0.2 to "1" to enable TC0.

2. Set TMOD0.6 to "1" to enable the system clock (fxx) input.

n

3. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fxx/2 ).

4. Load a value to TREF0 to specify the interval between interrupt requests.

5. Set the TC0 interrupt enable flag (IET0) to "1".

6. Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting.

7. TCNT0 increments with each internal clock pulse.

8. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1" and an interrupt request is

generated.

9. Output latch (TOL0) logic toggles high or low.

10. TCNT0 is cleared to 00H and counting resumes.

11. Programmable timer/counter operation continues until TMOD0.2 is cleared to "0".

11–13

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

TC0 EVENT COUNTER FUNCTION

Timer/counter 0 can monitor or detect system 'events' by using the external clock input at the TCL0 pin as the

counter source. The TC0 mode register selects rising or falling edge detection for incoming clock signals. The

counter register TCNT0 is incremented each time the selected state transition of the external clock signal occurs.

With the exception of the different TMOD0.4–TMOD0.6 settings, the operation sequence for TC0's event counter

function is identical to its programmable timer/counter function. To activate the TC0 event counter function,

— Set TMOD0.2 to "1" to enable TC0.

— Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin.

— Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5

and TMOD0.4.

— P3.2 must be set to input mode.

Table 11–5. TMOD0 Settings for TCL0 Edge Detection

TMOD0.5

TMOD0.4

TCL0 Edge Detection

Rising edges

0

1

Falling edges

11–14

KS57C21516/P21516 MICROCONTROLLER

TC0 CLOCK FREQUENCY OUTPUT

TIMERS and TIMER/COUNTERS

Using timer/counter 0, a modifiable clock frequency can be output to the TC0 clock output pin, TCLO0. To select

the clock frequency, load the appropriate values to the TC0 mode register, TMOD0. The clock interval is selected

by loading the desired reference value into the reference register TREF0. To enable the output to the TCLO0 pin,

the following conditions must be met:

— TC0 output enable flag TOE0 must be set to "1".

— I/O mode flag for P3.0 (PM3.0) must be set to output mode ("1").

— Output latch value for P3.0 must be set to "0".

In summary, the operational sequence required to output a TC0-generated clock signal to the TCLO0 pin is as

follows:

1. Load a reference value to TREF0.

2. Set the internal clock frequency in TMOD0.

3. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1").

4. Set P3.0 mode flag (PM3.0) to "1".

5. Set P3.0 output latch to "0".

6. Set TOE0 flag to "1".

Each time TCNT0 overflows and an interrupt request is generated, the state of the output latch TOL0 is inverted

and the TC0-generated clock signal is output to the TCLO0 pin.

+

PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin

Output a 30 ms pulse width signal to the TCLO0 pin:

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#79H

TREF0,EA

EA,#4CH

TMOD0,EA

EA,#01H

PMG2,EA

P3.0

; P3.0 ¬ output mode

; P3.0 clear

TOE0

11–15

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

TC0 SERIAL I/O CLOCK GENERATION

Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter

and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register,

SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface.

Use TMOD0 and TREF0 register settings to select the frequency and interval of the TC0 clock signals to be used

as SCK input to the serial interface. The generated clock signal is then sent directly to the serial I/O clock

selector circuit (the TOE0 flag may be disabled).

TC0 EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you

can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the

TCLO0 pin. The sequence of operations used to divide external clock input can be summarized as follows:

1. Load a signal divider value to the TREF0 register.

2. Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin.

3. Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection.

4. Set port 3.0 mode flag (PM3.0) to output ("1").

5. Set P3.0 output latch to "0".

6. Set TOE0 flag to "1" to enable output of the divided frequency to the TCLO0 pin.

+

PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin

Output external TCL0 clock pulse to the TCLO0 pin (divided by four):

EXTERNAL (TCL0)

CLOCK PULSE

TCLO0

OUTPUT

PULSE

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#01H

TREF0,EA

EA,#0CH

TMOD0,EA

EA,#01H

PMG2,EA

P3.0

; P3.0 ¬ output mode

; P3.0 clear

TOE0

11–16

KS57C21516/P21516 MICROCONTROLLER

TC0 MODE REGISTER (TMOD0)

TIMERS and TIMER/COUNTERS

TMOD0 is the 8-bit mode control register for timer/counter 0. It is addressable by 8-bit write instructions. One bit,

TMOD0.3, is also 1-bit writeable. RESET clears all TMOD0 bits to logic zero and disables TC0 operations.

F90H

F91H

TMOD0.3

"0"

TMOD0.2

TMOD0.6

"0"

TMOD0.5

TMOD0.4

TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0,

IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal

TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register TCNT0 are

retained until TC0 is re-enabled.

The TMOD0.6, TMOD0.5, and TMOD0.4 bit settings are used together to select the TC0 clock source. This

selection involves two variables:

— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal

input at the TCL0 pin, and

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC0 operation.

Table 11–6. TC0 Mode Register (TMOD0) Organization

Bit Name

TMOD0.7

TMOD0.6

TMOD0.5

TMOD0.4

TMOD0.3

Setting

Resulting TC0 Function

Address

0

Always logic zero

F91H

0,1

Specify input clock edge and internal frequency

1

Clear TCNT0, IRQT0, and TOL0 and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes.)

F90H

TMOD0.2

0

1

0

Disable timer/counter 0; retain TCNT0 contents

Enable timer/counter 0

TMOD0.1

TMOD0.0

Always logic zero

11–17

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

Table 11–7. TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings

TMOD0.6

TMOD0.5

TMOD0.4

Resulting Counter Source and Clock Frequency

External clock input (TCL0) on rising edges

0

1

0

1

0

1

0

1

0

1

External clock input (TCL0) on falling edges

10

fxx/2 (4.09 kHz)

6

fxx /2 (65.5 kHz)

4

fxx/2 (262 kHz)

fxx (4.19 MHz)

NOTE: 'fxx' = selected system clock of 4.19 MHz.

PROGRAMMING TIP — Restarting TC0 Counting Operation

1. Set TC0 timer interval to 4.09 kHz:

+

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD0,EA

LD

EI

BITS

IET0

2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation:

BITS

SMB

BITS

EMB

15

TMOD0.3

11–18

KS57C21516/P21516 MICROCONTROLLER

TC0 COUNTER REGISTER (TCNT0)

TIMERS and TIMER/COUNTERS

The 8-bit counter register for timer/counter 0, TCNT0, is read-only and can be addressed by 8-bit RAM control

instructions. RESET sets all TCNT0 register values to logic zero (00H).

Whenever TMOD0.3 is enabled, TCNT0 is cleared to logic zero and counting resumes. The TCNT0 register

value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency

setting of the TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4).

Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 refer-ence

buffer, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag,

IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter

interval has elapsed.

COUNT

CLOCK

TREF0

TCNT0

REFERENCE VALUE = n

0

1

2

n-1

n

0

1

2

n-1

n

0

1

2

3

MATCH

TOL0

INTERVAL TIME

TIMER START INSTRUCTION

(TMOD0.3 IS SET)

IRQT0 SET

Figure 11–3. TC0 Timing Diagram

11–19

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

TC0 REFERENCE REGISTER (TREF0)

The TC0 reference register TREF0 is an 8-bit write-only register. It is addressable by 8-bit RAM control

instructions. RESET initializes the TREF0 value to 'FFH'.

TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify

an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used

to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output

source.

During timer/counter operation, the value loaded into the reference register is compared to the TCNT0 value.

When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal

the interval or event. The TREF0 value, together with the TMOD0 clock frequency selection, determines the

specific TC0 timer interval. Use the following formula to calculate the correct value to load to the TREF0

reference register:

1

TC0 timer interval = (TREF0 value + 1) ´

TMOD0 frequency setting

(TREF0 value ¹ 0)

TC0 OUTPUT ENABLE FLAG (TOE0)

The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0

is addressable by 1-bit read and write instructions.

(MSB)

TOE1

(LSB)

"0"

TOE0

F92H

"U"

NOTE: The “U” means that the bit is undefined.

When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a RESET

occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled,

timer/counter 0 can continue to output an internally-generated clock frequency, via TOL0, to the serial I/O clock

selector circuit.

TC0 OUTPUT LATCH (TOL0)

TOL0 is the output latch for timer/counter 0. When the 8-bit comparator detects a correspondence between the

value of the counter register TCNT0 and the reference value stored in the TREF0 register, the TOL0 value is

inverted — the latch toggles high-to-low or low-to-high. Whenever the state of TOL0 is switched, the TC0 signal

is output. TC0 output may be directed to the TCLO0 pin, or it can be output directly to the serial I/O clock selector

circuit as the SCK signal.

Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero,

along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately.

When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if

necessary.

11–20

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Setting a TC0 Timer Interval

To set a 30 ms timer interval for TC0, given fxx = 4.19 MHz, follow these steps.

1. Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter

10

clock = fxx/2 , and TREF0 is set to FFH):

2. Calculate the TREF0 value:

TREF0 value + 1

30 ms =

4.09 kHz

30 ms

244 µs

TREF0 + 1 =

= 122.9 = 7AH

TREF0 value = 7AH – 1 = 79H

3. Load the value 79H to the TREF0 register:

BITS

SMB

LD

EMB

15

EA,#79H

TREF0,EA

EA,#4CH

TMOD0,EA

LD

11–21

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

16-BIT TIMER/COUNTER

OVERVIEW

Timer/counter 1 (TC1) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of

incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has

elapsed, TC1 generates an interrupt request. By counting signal transitions, it can be used to measure time inter-

vals. The TC1 circuit also has 16-bit comparator logic.

TC1 has a reloadable counter that consists of two parts: a 16-bit reference register (TREF1) into which you can

write data for use as a reference value, and a 16-bit counter register (TCNT1) whose contents are automatically

incremented by counter logic.

The 8-bit mode register, TMOD1, is used to activate the timer/counter and to select the basic clock frequency to

be used for timer/counter operations. You can modify the basic frequency dynamically by loading new values into

TMOD1 during program execution.

The only functional differences between TC0 and TC1 are the size of the counter and reference value registers

(8-bit versus 16-bit), and the fact that only TC0 can generate a clock signal for the serial I/O interface.

TIMER/COUNTER 1 FUNCTION SUMMARY

16-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock

frequency.

Counts various system "events" based on edge detection of external clock

signals at the TC1 input pin, TCL1.

Arbitrary frequency output

External signal divider

Outputs selectable clock frequencies to the TC1 output pin, TCLO1.

Divides the frequency of an incoming external clock signal according to the

modifiable reference value (TREF1), and outputs the modified frequency to

the TCLO1 pin.

11–22

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

TIMER/COUNTER 1 COMPONENT SUMMARY

Mode register (TMOD1)

Reference register (TREF1)

Counter register (TCNT1)

Clock selector circuit

Activates the timer/counter and selects the internal clock frequency or the

external clock source at the TCL1 pin.

Stores the reference value for the desired number of clock pulses between in-

terrupt requests.

Counts internal clock pulses that are generated based on bit settings in the

mode register and reference register.

Together with the mode register (TMOD1), lets you select one of four internal

clock frequencies, or the external system clock source.

16-bit comparator

Determines when to generate an interrupt by comparing the current value of

the counter (TCNT1) with the reference value previously programmed into the

reference register (TREF1).

Output latch (TOL1)

Where a TC1 clock pulse is stored pending output to the TC1 output pin,

TCLO1. When the contents of the TCNT1 and TREF1 registers coincide, the

timer/counter interrupt request flag (IRQT1) is set to "1", the status of TOL1 is

inverted, and an interrupt is generated.

Output enable flag (TOE1)

Must be set to logic one before the contents of the TOL1 latch can be output to

TCLO1.

Interrupt request flag (IRQT1) Cleared when TC1 operation starts and set to logic one whenever the counter

value and reference value match.

Interrupt enable flag (IET1)

Must be set to logic one before the interrupt requests generated by

timer/counter 1 can be processed.

Table 11–8. TC1 Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

TMOD1

Control

Controls TC1 enable/disable

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and the clock

frequency (bits 6–4)

8-bit

FA0H–FA1H

8-bit write-

only;

(TMOD1.3 is

also 1-bit

writeable)

"0"

TCNT1

TREF1

TOE1

Counter

Counts clock pulses matching

the TMOD1 frequency setting

16-bit FA4H–FA5H,

FA6H–FA7H

8-bit

read-only

"0"

FFFFH

"0"

Reference Stores reference value for TC1 16-bit FA8H–FA9H,

8-bit

write-only

interval setting

FAAH–FABH

Flag

Controls TC1 output to the

TCLO1 pin

1-bit

F92H.3

1/4-bit

read/write

11–23

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

CLOCKS

8

10

6 4

, fxx )

(fxx/2

, fxx/2

TCL1

16

TMOD1.7

TMOD1.6

TMOD1.5

TMOD1.4

TMOD1.3

TMOD1.2

TMOD1.1

TMOD1.0

16-BIT

TREF1

TCNT1

COMPARATOR

CLOCK

SELECTOR

8

CLEAR

INVERTED

CLEAR

SET

CLEAR

IRQT1

TOL1

TCLO1

P3.1 LATCH

PM3.1

TOE1

Figure 11–4. TC1 Circuit Diagram

TC1 ENABLE/DISABLE PROCEDURE

Enable Timer/Counter 1

— Set the TC1 interrupt enable flag IET1 to logic one.

— Set TMOD1.3 to logic one.

TCNT1, IRQT1, and TOL1 are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter 1

— Set TMOD1.2 to logic zero.

Clock signal input to the counter register TCNT1 is halted. The current TCNT1 value is retained and can be read

if necessary.

11–24

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

TC1 PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counter 1 can be programmed to generate interrupt requests at variable intervals, based on the system

clock frequency you select. The 8-bit TC1 mode register, TMOD1, is used to activate the timer/counter and to

select the clock frequency; the 16-bit reference register, TREF1, is used to store the value for the desired

number of clock pulses between interrupt requests. The 16-bit counter register, TCNT1, counts the incoming

clock pulses, which are compared to the TREF1 value. When there is a match, an interrupt request is generated.

To program timer/counter 1 to generate interrupt requests at specific intervals, select one of the four internal

clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the TREF1 register.

TCNT1 is incremented each time an internal counter pulse is detected with the reference clock frequency

specified by TMOD1.4–TMOD1.6 settings. To generate an interrupt request, the TC1 interrupt request flag

(IRQT1) is set to logic one, the status of TOL1 is inverted, and the interrupt is output. The content of TCNT1 is

then cleared to 0000H, and TC1 continues counting. The interrupt request mechanism for TC1 includes an

interrupt enable flag (IET1) and an interrupt request flag (IRQT1).

TC1 TIMER/COUNTER OPERATION SEQUENCE

The general sequence of operations for using TC1 can be summarized as follows:

1. Set TMOD1.2 to "1" to enable TC1.

2. Set TMOD1.6 to "1" to enable the system clock (fxx) input.

n

3. Set TMOD1.5 and TMOD1.4 bits to desired internal frequency (fxx/2 ).

4. Load a value to TREF1 to specify the interval between interrupt requests.

5. Set the TC1 interrupt enable flag (IET1) to "1".

6. Set TMOD1.3 bit to "1" to clear TCNT1, IRQT1, and TOL1, and start counting.

7. TCNT1 increments with each internal clock pulse.

8. When the comparator shows TCNT1 = TREF1, the IRQT1 flag is set to "1" and an interrupt request is

generated.

9. Output latch (TOL1) logic toggles high or low.

10. TCNT1 is cleared to 0000H and counting resumes.

11. Programmable timer/counter operation continues until TMOD1.2 is cleared to "0".

11–25

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

TC1 EVENT COUNTER FUNCTION

Timer/counter 1 can monitor system 'events' by using the external clock input at the TCL1 pin as the counter

source. The TC1 mode register selects rising or falling edge detection for incoming clock signals. The counter

register TCNT1 is incremented each time the selected state transition of the external clock signal occurs.

With the exception of the different TMOD1.4–TMOD1.6 settings, the operation sequence for TC1's event counter

function is identical to its programmable timer/counter function. To activate the TC1 event counter function,

— Set TMOD1.2 to "1" to enable TC1.

— Clear TMOD1.6 to "0" to select the external clock source at the TCL1 pin.

— Select TCL1 edge detection for rising or falling signal edges by loading the appropriate values to TMOD1.5

and TMOD1.4.

— Pin P3.3 must be set to input mode.

Table 11–9. TMOD1 Settings for TCL1 Edge Detection

TMOD1.5

TMOD1.4

TCL1 Edge Detection

Rising edges

0

1

Falling edges

11–26

KS57C21516/P21516 MICROCONTROLLER

TC1 CLOCK FREQUENCY OUTPUT

TIMERS and TIMER/COUNTERS

Using timer/counter 1, a modifiable clock frequency can be output to the TC1 clock output pin, TCLO1. To select

the clock frequency, load the appropriate values to the TC1 mode register, TMOD1. The clock interval is

selected by loading the desired reference value into the 16-bit reference register TREF1. To enable the output to

the TCLO1 pin at I/O port 3.1, the following conditions must be met:

— TC1 output enable flag TOE1 must be set to "1".

— I/O mode flag for P3.1 (PM3.1) must be set to output mode ("1").

— P3.1 output latch must be cleared to "0".

In summary, the operational sequence required to output a TC1-generated clock signal to the TCLO1 pin is as

follows:

1. Load your reference value to TREF1.

2. Set the internal clock frequency in TMOD1.

3. Initiate TC1 clock output to TCLO1 (TMOD1.2 = "1").

4. Set port 3.1 mode flag (PM3.1) to "1".

5. Clear the P3.1 output latch.

6. Set TOE1 flag to "1".

Each time TCNT1 overflows and an interrupt request is generated, the state of the output latch TOL1 is inverted

and the TC1-generated clock signal is output to the TCLO1 pin.

+

PROGRAMMING TIP — TC1 Signal Output to the TCLO1 Pin

Output a 30 ms pulse width signal to the TCLO1 pin:

BITS

SMB

LD

EMB

15

EA,#79H

TREF1A,EA

EA,#00H

TREF1B,EA

EA,#4CH

TMOD1,EA

EA,#02H

PMG2,EA

P3.1

LD

BITR

BITS

; P3.1 ¬ output mode

; P3.1 clear

TOE1

11–27

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

TC1 EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC1 reference register, TREF1, you

can divide the incoming clock signal by the TREF1 value and then output this modified clock frequency to the

TCLO1 pin. The sequence of operations used to divide external clock input and output the signals to the TCLO1

pin can be summarized as follows:

1. Load a signal divider value to the TREF1 register.

2. Clear TMOD1.6 to "0" to enable external clock input at the TCLO1 pin.

3. Set TMOD1.5 and TMOD1.4 to desired TCL signal edge detection.

4. Set P3.1 mode flag (PM3.1) to output ("1").

5. Clear the P3.1 output latch.

6. Set TOE1 flag to "1" to enable output of the divided frequency.

+

PROGRAMMING TIP — External TCL1 Clock Output to the TCLO1 Pin

Output the external TCL1 clock source to the TCLO1 pin (divide by four):

EXTERNAL (TCL1)

CLOCK PULSE

TCLO1

OUTPUT

PULSE

BITS

SMB

LD

EMB

15

EA,#01H

TREF1A,EA

EA,#00H

TREF1B,EA

EA,#0CH

TMOD1,EA

EA,#02H

PMG2,EA

P3.1

LD

BITR

BITS

; P3.1 ¬ output mode

; P3.1 clear

TOE1

11–28

KS57C21516/P21516 MICROCONTROLLER

TC1 MODE REGISTER (TMOD1)

TIMERS and TIMER/COUNTERS

TMOD1 is the 8-bit mode register for timer/counter 1. It is addressable by 8-bit write instructions. The TMOD1.3

bit is also 1-bit write addressable. RESET clears all TMOD1 bits to logic zero. Following a RESET, timer/counter 1

is disabled.

FA0H

FA1H

TMOD1.3

"0"

TMOD1.2

TMOD1.6

"0"

TMOD1.5

TMOD1.4

TMOD1.2 is the enable/disable bit for timer/counter 1. When TMOD1.3 is set to "1", the contents of TCNT1,

IRQT1, and TOL1 are cleared, counting starts from 0000H, and TMOD1.3 is automatically reset to "0" for normal

TC1 operation. When TC1 operation stops (TMOD1.2 = "0"), the contents of the TC1 counter register, TCNT1,

are retained until TC1 is re-enabled.

The TMOD1.6, TMOD1.5, and TMOD1.4 bit settings are used together to select the TC1 clock source. This

selection involves two variables:

— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal

input at the TCL1 pin, and

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC1 operations.

Table 11–10. TC1 Mode Register (TMOD1) Organization

Bit Name

TMOD1.7

TMOD1.6

TMOD1.5

TMOD1.4

TMOD1.3

Setting

Resulting TC1 Function

Address

0

Always logic zero

0,1

Specify input clock edge and internal frequency

FA1H

1

Clear TCNT1, IRQT1, and TOL1 and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes).

FA0H

TMOD1.2

0

1

0

Disable timer/counter 1; retain TCNT1 contents

Enable timer/counter 1

TMOD1.1

TMOD1.0

Always logic zero

11–29

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

Table 11–11. TMOD1.6, TMOD1.5, and TMOD1.4 Bit Settings

TMOD1.6

TMOD1.5

TMOD1.4

Resulting Counter Source and Clock Frequency

External clock input (TCL1) on rising edges

0

1

0

1

0

1

0

1

0

1

External clock input (TCL1) on falling edges

10

fxx/2 (4.09 kHz)

8

fxx/2 (16.4 kHz)

6

fxx/2 (65.5 kHz)

4

fxx/2 (262 kHz)

NOTE: 'fxx' = selected system clock of 4.19 MHz.

+

PROGRAMMING TIP — Restarting TC1 Counting Operation

1. Set TC1 timer interval to 4.09 kHz:

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD1,EA

LD

EI

BITS

IET1

2. Clear TCNT1, IRQT1, and TOL1 and restart TC1 counting operation:

SBITS

SMB

EMB

15

BITS

TMOD1.3

11–30

KS57C21516/P21516 MICROCONTROLLER

TC1 COUNTER REGISTER (TCNT1)

TIMERS and TIMER/COUNTERS

The 16-bit counter register for timer/counter 1, TCNT1, is mapped to RAM addresses FA5H–FA4H (TCNT1A)

and FA7H–FA6H (TCNT1B). The two 8-bit registers are read-only and can be addressed by 8-bit RAM control in-

structions. RESET sets all TCNT1 register values to logic zero (00H).

Whenever TMOD1.2 and TMOD1.3 are enabled, TCNT1 is cleared to logic zero and counting begins. The

TCNT1 register value is incremented each time an incoming clock signal is detected that matches the signal

edge and frequency setting of the TMOD1 register (specifically, TMOD1.6, TMOD1.5, and TMOD1.4).

Each time TCNT1 is incremented, the new value is compared to the reference value stored in the TC1 reference

register, TREF1. When TCNT1 = TREF1, an overflow occurs in the TCNT1 register, the interrupt request flag,

IRQT1, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter

interval has elapsed.

COUNT

CLOCK

TREF1

TCNT1

REFERENCE VALUE = n

0

1

2

n-1

n

0

1

2

n-1

n

0

1

2

3

MATCH

TOL1

INTERVAL TIME

TIMER START INSTRUCTION

(TMOD1.3 IS SET)

IRQT1 SET

Figure 11–5. TC1 Timing Diagram

11–31

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

TC1 REFERENCE REGISTER (TREF1)

The TC1 reference register TREF1 is a 16-bit write-only register that is mapped to RAM locations FA9H–FA8H

(TREF1A) and FABH–FAAH (TREF1B). It is addressable by 8-bit RAM control instructions. RESET clears the

TREF1 value to 'FFFFH'.

TREF1 is used to store a reference value to be compared to the incrementing TCNT1 register in order to identify

an elapsed time interval. Reference values will differ depending upon the specific function that TC1 is being used

to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output

source.

During timer/counter operation, the value loaded into the reference register compared to the TCNT1 value.

When TCNT1 = TREF1, the TC1 output latch (TOL1) is inverted and an interrupt request is generated to signal

the interval or event. The TREF1 value, together with the TMOD1 clock frequency selection, determines the

specific TC1 timer interval. Use the following formula to calculate the correct value to load to the TREF1

reference register:

1

TC1 timer interval = (TREF1 value + 1) ´

TMOD1 frequency setting

(TREF1 value ¹ 0)

TC1 OUTPUT ENABLE FLAG (TOE1)

The 1-bit timer/counter 1 output enable flag TOE1 flag controls output from timer/counter 1 to the TCLO1 pin.

TOE1 is addressable by 1-bit read and write instructions.

Bit 3

Bit 2

Bit 1

"U"

Bit 0

"0"

TOE1

F92H

TOE0

NOTE: The “U” means that the bit is undefined.

When you set the TOE1 flag to "1", the contents of TOL1 can be output to the TCLO1 pin. Whenever a RESET

occurs, TOE1 is automatically set to logic zero, disabling all TC1 output.

TC1 OUTPUT LATCH (TOL1)

TOL1 is the output latch for timer/counter 1. When the 16-bit comparator detects a correspondence between the

value of the counter register TCNT1 and the reference value stored in the TREF1 register, the TOL1 logic

toggles high-to-low or low-to-high. Whenever the state of TOL1 is switched, the TC1 signal exits the latch for

output. TC1 output is directed (if TOE1 = "1") to the TCLO1 pin at I/O port 3.1.

When timer/counter 1 is started, (TMOD1.3 = "0"), the contents of the output latch are cleared automatically.

However, when TC1 is disabled (TMOD1.2 = "0"), the contents of the TOL1 latch are retained and can be read, if

necessary.

11–32

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Setting a TC1 Timer Interval

To set a 30 ms timer interval for TC1, given fxx = 4.19 MHz, follow these steps:

1. Select the timer/counter 1 mode register with a maximum setup time of 16 seconds;

10

assume the TC1 counter clock = fxx/2 and TREF1 is set to FFFFH.

2. Calculate the TREF1 value:

TREF1 value + 1

30 ms =

4.09 kHz

30 ms

244 µs

TREF1 + 1 =

= 122.9 = 7AH

TREF1 value = 7AH – 1 = 79H

3. Load the value 79H to the TREF1 register:

BITS

SMB

LD

EMB

15

EA,#79H

TREF1A,EA

EA,#00H

TREF1B,EA

EA,#4CH

TMOD1,EA

11–33

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

WATCH TIMER

OVERVIEW

The watch timer is a multi-purpose timer which consists of three basic components:

— 8-bit watch timer mode register (WMOD)

— Clock selector

— Frequency divider circuit

Watch timer functions include real-time and watch-time measurement and interval timing for the main and sub-

system clock. It is also used as a clock source for the LCD controller and for generating buzzer (BUZ) output.

Real-Time and Watch-Time Measurement

To start watch timer operation, set bit 2 of the watch timer mode register (WMOD.2) to logic one. The watch

timer starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence

in 0.5-second intervals.

Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be

cleared to logic zero by program software as soon as a requested interrupt service routine has been executed.

Using a Main System or Subsystem Clock Source

The watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock.

When the zero bit of the WMOD register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its

source; if WMOD.0 = "0", the main system clock (fx) is used as the signal source, according to the following

formula:

Main system clock (fx)

Watch timer clock (fw) =

= 32.768 kHz (fx = 4.19 MHz)

128

This feature is useful for controlling timer-related operations during stop mode. When stop mode is engaged, the

main system clock (fx) is halted, but the subsystem clock continues to oscillate. By using the subsystem clock as

the oscillation source during stop mode, the watch timer can set the interrupt request flag IRQW to "1", thereby

releasing stop mode.

Clock Source Generation for LCD Controller

The watch timer supplies the clock frequency for the LCD controller (f ). Therefore, if the watch timer is dis-

LCD

abled, the LCD controller does not operate.

11–34

KS57C21516/P21516 MICROCONTROLLER

Buzzer Output Frequency Generator

TIMERS and TIMER/COUNTERS

The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the

desired BUZ frequency , load the appropriate value to the WMOD register. This output can then be used to

actuate an external buzzer sound. To generate a BUZ signal, three conditions must be met:

— The WMOD.7 register bit is set to "1"

— The output latch for I/O port 0.3 is cleared to "0"

— The port 0.3 output mode flag (PM0.3) set to 'output' mode

Timing Tests in High-Speed Mode

By setting WMOD.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91

ms. At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5 seconds. High-

speed mode is useful for timing events for program debugging sequences.

Check Subsystem Clock Level Feature

The watch timer can also check the input level of the subsystem clock by testing WMOD.3. If WMOD.3 is "1", the

input level at the XT pin is high; if WMOD.3 is "0", the input level at the XT pin is low.

in in

11–35

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

P0.3 LATCH

PM0.3

WMOD.7

WMOD.6

WMOD.5

BUZ

MUX

8

WMOD.4

WMOD.3

WMOD.2

WMOD.1

WMOD.0

fw/2

(16 kHz)

fw/4

(8 kHz)

DISABLE

ENABLE /

fw/8

(4 kHz)

SELECTOR

CIRCUIT

fw/16

(2 kHz)

IRQW

7

fw/2

14

fw/2 (2Hz)

FREQUENCY

DIVIDING

CIRCUIT

fw

CLOCK

SELECTOR (32.768 kHz)

3

f

fw/2 (4096 Hz)

LCD

fx = Main system clock

fxt = Subsystem clock

fw = Watch timer frequency

fxt

fx/128

Figure 11–6. Watch Timer Circuit Diagram

11–36

KS57C21516/P21516 MICROCONTROLLER

WATCH TIMER MODE REGISTER (WMOD)

TIMERS and TIMER/COUNTERS

The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only

addressable. An exception is WMOD bit 3 (the XT input level control bit) which is 1-bit read-only addressable.

in

A RESET automatically sets WMOD.3 to the current input level of the subsystem clock, XT (high, if logic one;

in

low, if logic zero), and all other WMOD bits to logic zero.

F88H

F89H

WMOD.3

WMOD.7

WMOD.2

"0"

WMOD.1

WMOD.5

WMOD.0

WMOD.4

In summary, WMOD settings control the following watch timer functions:

— Watch timer clock selection

— Watch timer speed control

— Enable/disable watch timer

(WMOD.0)

(WMOD.1)

(WMOD.2)

(WMOD.3)

— XT input level control

in

— Buzzer frequency selection

— Enable/disable buzzer output

(WMOD.4 and WMOD.5)

(WMOD.7)

Table 11–12. Watch Timer Mode Register (WMOD) Organization

Bit Name

Values

Function

Address

WMOD.7

0

1

Disable buzzer (BUZ) signal output at the BUZ pin

Enable buzzer (BUZ) signal output at the BUZ pin

F89H

WMOD.6

0

Always logic zero

WMOD.5 – .4

0

1

0

1

2 kHz buzzer (BUZ) signal output

4 kHz buzzer (BUZ) signal output

8 kHz buzzer (BUZ) signal output

16 kHz buzzer (BUZ) signal output

0

1

Input level to XT pin is low

in

WMOD.3

0

1

0

1

0

1

0

1

F88H

Input level to XT pin is high

in

WMOD.2

WMOD.1

WMOD.0

Disable watch timer; clear frequency dividing circuits

Enable watch timer

Normal mode; sets IRQW to 0.5 seconds

High-speed mode; sets IRQW to 3.91 ms

Select (fx/128 ) as the watch timer clock (fw)

Select subsystem clock as watch timer clock (fw)

NOTE: Main system clock frequency (fx) is assumed to be 4.19 MHz; subsystem clock (fxt) is assumed to be 32.768 kHz.

11–37

TIMERS and TIMER/COUNTERS

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Using the Watch Timer

1. Select a subsystem clock as the LCD display clock, a 0.5 second interrupt, and 2 kHz buzzer enable:

BITS

SMB

LD

BITR

LD

EMB

15

EA,#8H

PMG1,EA

P0.3

EA,#85H

WMOD,EA

IEW

; P0.3 ¬ output mode

LD

BITS

2. Sample real-time clock processing method:

CLOCK

BTSTZ

IRQW

; 0.5 second check

RET

; No, return

•

; Yes, 0.5 second interrupt generation

; Increment HOUR, MINUTE, SECOND

11–38

KS57C21516/P21516 MICROCONTROLLER

TIMERS and TIMER/COUNTERS

11–39

KS57C21516/P21516 MICROCONTROLLER

LCD CONTROLLER/DRIVER

12 LCD CONTROLLER/DRIVER

OVERVIEW

The KS57C21516 microcontroller can directly drive an up-to-896-dot (56 segments x 16 commons) LCD panel.

Its LCD block has the following components:

— LCD controller/driver

— Display RAM for storing display data

— 56 segment output pins (SEG0–SEG55)

— 16 common output pins (COM0–COM15)

— Five LCD operating power supply pins (V )

–V

pin for controlling the driver and bias voltage

LC1 LC5

— V

LC5

To use the LCD controller, bit 2 in the watch mode register WMOD must be set to 1, because LCDCK is supplied

by the watch timer.

The frame frequency, duty and bias, and the segment pins used for display output, are determined by bit settings

in the LCD mode register, LMOD.

The LCD control register, LCON, is used to turn the LCD display on and off, to switch current to the dividing

resistors for the LCD display, and to output LCD clock (LCDCK) and synchronizing signal (LCDSY) for LCD

display expansion. Data written to the LCD display RAM can be transferred to the segment signal pins

automatically without program control.

When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even during main

clock stop and idle modes.

V

–V

LC5

LC1

5

8

COM0–COM7

LCD

CONTROLLER /

DRIVER

COM8-COM15/

P4.0-P5.3

8

SEG0–SEG39

40

16

SEG40–SEG55/

P9.3–P6.0

Figure 12–1. LCD Function Diagram

12–1

LCD CONTROLLER/DRIVER

KS57C21516/P21516 MICROCONTROLLER

PORT

LATCH

16

SEG55/P6.0

SEG54/P6.1

DISPLAY

RAM

SEG40/P9.3

SELECTOR

224

MUX

56

(BANK 2)

SEG0

f

LCD

PORT

LATCH

8

COM15/P5.3

COM14/P5.2

COM

TIMING

LMOD

CONTROL

COM0

CONTROLLER

VCL5

LCD

VOLTAGE

CONTROL

VCL1

LCON

LCDSY

LCDCK

P2.1 LATCH

P2.2 LATCH

PM2.1

PM2.2

Figure 12–2. LCD Circuit Diagram

12–2

KS57C21516/P21516 MICROCONTROLLER

LCD RAM ADDRESS AREA

LCD CONTROLLER/DRIVER

RAM addresses of bank 2 are used as LCD data memory. These locations can be addressed by 1-bit, 4-bit, or 8-

bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value

is "0", the display is turned off.

Display RAM data are sent out through segment pins SEG0–SEG55 using a direct memory access (DMA)

method that is synchronized with the f

signal. RAM addresses in this location that are not used for LCD

LCD

display can be allocated to general-purpose use.

S

E

S

E

S

E

S

E

S

E

G

4

S

E

G G

S

E

S

E

G

7

S

E

G G

S

E

S

E

G

S

E

G

S

E

G

S

E

G G

S

E

S

E

G

G G G G

0

1

2

3

5

6

8

9 10 11

52 53 54 55

b0 b1 b2 b3 b0 b1 b2 b3 b0 b1 b2 b3

b0 b1 b2 b3

20DH

COM0

COM1

COM2

COM3

200H

210H

220H

230H

201H

211H

221H

231H

202H

212H

222H

232H

21DH

22DH

23DH

COM12

COM13

COM14

COM15

2C0H

2D0H

2E0H

2F0H

2C1H

2D1H

2E1H

2F1H

2C2H

2D2H

2E2H

2F2H

2CDH

2DDH

2EDH

2FDH

Figure 12–3. LCD Display Data RAM Organization

Table 12–1. Common and Segment Pins per Duty Cycle

Duty

Common Pins

COM0–COM15

COM0–COM7

Segment Pins

Dot Number

1/16

1/8

40 pins–56 pins

640 dots–896 dots

320 dots–448 dots

NOTE: When 1/8 duty is selected, COM8–COM15 (P4.0–P5.3) can be used for normal I/O pins.

12–3

LCD CONTROLLER/DRIVER

KS57C21516/P21516 MICROCONTROLLER

LCD CONTROL REGISTER (LCON)

The LCD control register (LCON) is used to turn the LCD display on and off, to output LCD clock (LCDCK) and

synchronizing signal (LCDSY) for LCD display expansion, and to control the flow of current to dividing resistors in

the LCD circuit. Following a RESET, all LCON values are cleared to "0". This turns the LCD display off and stops

the flow of current to the dividing resistors.

F8EH

“0”

LCON.2

LCON.1

LCON.0

The effect of the LCON.0 setting is dependent upon the current setting of bits LMOD.0 and LMOD.1. Bit 1 in the

LCON is used for contrast control application.

Table 12–2. LCD Control Register (LCON) Organization

LCON Bit

LCON.3

LCON.2

Setting

Description

0

1

Always logic zero.

Disable LCDCK and LCDSY signal outputs.

Enable LCDCK and LCDSY signal outputs.

LCON.1

LCON.0

0

1

0

1

LCD display off; cut off current to dividing resistor

LCD display on; application without contrast control

LCD display on; application with contrast control

LCD display on; application without contrast control

0

1

NOTE: The function of LCON.0 is applied in case of using the internal GND for LCD power; the function of LCON1 is used

for contrast control application.

Table 12–3. LMOD.1–0 Bits Settings

LMOD.1–0

COM0–COM15

SEG0–SEG55

SEG40/P9.3–SEG55/P6.0

Power Supply to the

Dividing Resistor

0, 0

0, 1

All of the LCD dots off

All of the LCD dots on

Normal I/O port function

On

1, 1

Common and segment signal output

corresponds to display data (normal

display mode)

NOTE: 'x' means 'don't care.'

12–4

KS57C21516/P21516 MICROCONTROLLER

LCD MODE REGISTER (LMOD)

LCD CONTROLLER/DRIVER

The LCD mode control register LMOD is used to control display mode; LCD clock, segment or port output, and

display on/off. LMOD can be manipulated using 8-bit write instructions.

F8CH

F8DH

LMOD.3

LMOD.7

LMOD.2

LMOD.6

LMOD.1

LMOD.5

LMOD.0

LMOD.4

The LCD clock signal, LCDCK, determines the frequency of COM signal scanning of each segment output. This

is also referred to as the 'frame frequency. Since LCDCK is generated by dividing the watch timer clock (fw), the

watch timer must be enabled when the LCD display is turned on. RESET clears the LMOD register values to logic

zero.

The LCD display can continue to operate during idle and stop modes if a subsystem clock is used as the watch

timer source. The LCD mode register LMOD controls the output mode of the 16 pins used for normal outputs

(P9.3–P6.0). Bits LMOD.7–5 define the segment output and normal bit output configuration.

Table 12–4. LCD Clock Signal (LCDCK) Frame Frequency

LCDCK

256 Hz

512 Hz

1024 Hz

2048 Hz

4096 Hz

Display Duty Cycle

1/8

32

–

64

32

128

64

256

128

–

1/16

256

NOTE:

COM0

1 FRAME

12–5

LCD CONTROLLER/DRIVER

KS57C21516/P21516 MICROCONTROLLER

Table 12–5. LCD Mode Register (LMOD) Organization

Segment/Port Output Selection Bits

LMOD.7 LMOD.6 LMOD.5 SEG40–43

SEG44–47

SEG48–51

SEG52–55

Total Number

of Segment

0

1

0

1

0

1

0

1

0

SEG port

Normal port

56

52

48

44

40

SEG port

Normal port

Normal port Normal port

NOTE: Segment pins that also can used for normal I/O should be configured to output mode when the SEG function is

used.

LCD Clock Selection Bits

LMOD.4

LMOD.3

LCD Clock (LCDCK)

1/8 duty (COM0–COM7)

1/16 duty (COM0–COM15)

7

6

0

1

0

1

0

1

fxx / 2 (256 Hz)

fxx / 2 (512 Hz)

6

5

fxx/ 2 (512 Hz)

fxx / 2 (1024 Hz)

5

4

fxx / 2 (1024 Hz)

fxx / 2 (2048 Hz)

4

3

fxx / 2 (2048 Hz)

fxx / 2 (4096 Hz)

NOTE: LCDCK is supplied only when the watch timer is operating. To use the LCD controller, you must set bit 2 in the

watch mode register WMOD to “1”.

Duty Selection Bits

LMOD.2

Duty

0

1

1/8 duty (COM0–COM7 select)

1/16 duty (COM0–COM15 select)

NOTE: When 1/16 duty is selected, ports 4 and 5 should be configured as output mode; when 1/8 duty is selected, ports 4

and 5 can be used as normal I/O ports.

Display Mode Selection Bits

LMOD.1

LMOD.0

Function

0

1

0

1

All LCD dots off

All LCD dots on

Normal display

12–6

KS57C21516/P21516 MICROCONTROLLER

LCD CONTROLLER/DRIVER

LCD VOLTAGE DIVIDING RESISTORS

On-chip voltage dividing resistors for the LCD drive power supply are fixed to the V –V pins. Power can be

LC1 LC5

supplied without an external dividing resistor. Figure 12–4 shows the bias connections for the KS57C21516 LCD

drive power supply. To cut off the flow of current through the dividing resistor, clear bits 0 and 1 of the LCON

register.

1/4 Bias

1/5 Bias

KS57C21516

V

LC1

V

LC2

LC3

LC2

LC3

V

LC4

LC5

LC4

LC5

Figure 12–4. LCD Bias Circuit Connection

12–7

LCD CONTROLLER/DRIVER

KS57C21516/P21516 MICROCONTROLLER

Application Without Contrast Control

Application With Contrast Control

KS57C21516

V_DD

Fixed

V_LC1

V_LC2

V_LC3

V_LC4

V_LC5

V_LC1

V_LC2

V_LC3

V_LC4

V_LC5

LCON.0 (OFF)

LCON.1 (ON)

LCON.0 (ON)

LCON.1

(DON’T CARE)

V_SS

NOTES:

1.

2.

When the LCD module is turned off, clear LCON.0 and LCON.1 to “0” to reduce power consumption.

If an external variable resistor is used to connect V

the variable resistor.

to ground, you can control LCD contrast using

LC5

Figure 12–5. Internal Voltage Dividing Resistor Connection (1/5 Bias, Display On)

12–8

KS57C21516/P21516 MICROCONTROLLER

COMMON (COM) SIGNALS

LCD CONTROLLER/DRIVER

The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.

— In 1/8 duty mode, COM0–COM7 pins are selected.

— In 1/16 duty mode, COM0–COM15 pins are selected.

When 1/8 duty is selected by clearing LMOD.2 to zero, COM8–COM15 (P4.0–P5.3) can be used for normal I/O

port.

SEGMENT (SEG) SIGNALS

The 56 LCD segment signal pins are connected to corresponding display RAM locations at bank 2. Bits of the

display RAM are synchronized with the common signal output pins.

When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin.

When the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin.

12–9

LCD CONTROLLER/DRIVER

KS57C21516/P21516 MICROCONTROLLER

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

0 1 2 3

15 0 1 2 3

15

V

DD

SS

FR

1 FRAME

V

DD

V

LC1

LC2

LC3

LC4

COM0

COM8

COM9

COM10

COM11

COM12

COM13

COM14

LC5

V

DD

LC1

COM15

LC2

LC3

COM1

COM2

SEG0

S S S S S

E E E E E

G G G G G

0 1 2 3 4

LC4

LC5

V

DD

LC1

LC2

LC3

LC4

LC5

V

DD

LC1

LC2

LC3

LC4

LC5

Figure 12–6. LCD Signal Waveforms (1/16 Duty, 1/5 Bias)

12–10

KS57C21516/P21516 MICROCONTROLLER

LCD CONTROLLER/DRIVER

0 1 2 3

15 0 1 2 3

15

V

DD

SS

FR

1 FRAME

V

DD

V

LC1

LC2

SEG1

LC3

LC4

LC5

V

DD

V

LC1

V

LC2

LC3

LC4

LC5

SEG0 COM0

-

V

-

LC4

LC3

LC2

LC1

V

-

DD

V

DD

V

LC1

LC2

LC3

LC4

LC5

SEG1 COM0

-

V

-

LC4

LC3

LC2

LC1

V

-

DD

Figure 12–6. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) (Continued)

12–11

LCD CONTROLLER/DRIVER

KS57C21516/P21516 MICROCONTROLLER

COM0

COM1

COM2

0

1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

V

DD

SS

FR

COM3

COM4

1 FRAME

COM5

COM6

COM7

V

DD

LC1

V

(

)

LC2 LC3

S S S S S

COM0

COM1

COM2

SEG0

E E E E E

G G G G G

0 1 2 3 4

LC4

LC5

V

DD

LC1

V

(

)

LC2 LC3

LC4

LC5

V

DD

LC1

V

(

)

LC2 LC3

LC4

LC5

V

DD

LC1

V

(

)

LC2 LC3

LC4

LC5

V

DD

LC1

V

(

)

LC2 LC3

LC4

SEG0 COM0

-

LC5

V

-

LC4

LC2

LC1

V

(

)

-

LC3

DD

Figure 12–7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)

12–12

KS57C21516/P21516 MICROCONTROLLER

LCD CONTROLLER/DRIVER

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

V

DD

FR

SS

1 FRAME

V

DD

LC1

V

(

)

LC2 LC3

SEG1

LC4

LC5

V

DD

LC1

V

(

)

LC2 LC3

LC4

LC5

SEG0 COM0

-

V

-

LC4

V

(

)

LC2 LC3

LC1

DD

Figure 12–7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued)

12–13

LCD CONTROLLER/DRIVER

KS57C21516/P21516 MICROCONTROLLER

NOTES

12–14

KS57C21516/P21516 MICROCONTROLLER

SERIAL I/O INTERFACE

13 SERIAL I/O INTERFACE

OVERVIEW

The serial I/O interface (SIO) has the following functional components:

— 8-bit mode register (SMOD)

— Clock selector circuit

— 8-bit buffer register (SBUF)

— 3-bit serial clock counter

Using the serial I/O interface, 8-bit data can be exchanged with an external device. The transmission frequency

is controlled by making the appropriate bit settings to the SMOD register.

The serial interface can run off an internal or an external clock source, or the TOL0 signal that is generated by

the 8-bit timer/counter, TC0. If the TOL0 clock signal is used, you can modify its frequency to adjust the serial

data transmission rate.

SERIAL I/O OPERATION SEQUENCE

The general operation sequence of the serial I/O interface can be summarized as follows:

1. Set SIO mode to transmit-and-receive or to receive-only.

2. Select MSB-first or LSB-first transmission mode.

3. Set the SCK clock signal in the mode register, SMOD.

4. Set SIO interrupt enable flag (IES) to "1".

5. Initiate SIO transmission by setting bit 3 of the SMOD to "1".

6. When the SIO operation is complete, IRQS flag is set and an interrupt is generated.

13–1

SERIAL I/O INTERFACE

KS57C21516/P21516 MICROCONTROLLER

INTERNAL BUS

8

LSB / MSB

8

SO

SI

SBUF (8-BIT)

R

OVERFLOW

IRQS

Q

D

CK

SCK

P0.0/

TOL0

Q0

Q1 Q2

3-BIT COUNTER

CPU CLK

CLOCK

R

S

SELECTOR

10

fxx/2

Q

CLEAR

4

fxx/2

SMOD.7 SMOD.6 SMOD.5

SMOD.3 SMOD.2 SMOD.1 SMOD.0

-

8

(note)

BITS

INTERNAL BUS

Instruction Execution

NOTE:

Figure 13–1. Serial I/O Interface Circuit Diagram

13–2

KS57C21516/P21516 MICROCONTROLLER

SERIAL I/O MODE REGISTER (SMOD)

SERIAL I/O INTERFACE

The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface.

Its reset value is logical zero. SMOD is organized in two 4-bit registers, as follows:

FE0H

FE1H

SMOD.3

SMOD.7

SMOD.2

SMOD.6

SMOD.1

SMOD.5

SMOD.0

0

SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in

transmit-and-receive mode or receive-only mode. SMOD is a write-only register and can be addressed only by 8-

bit RAM control instructions. One exception to this is SMOD.3, which can be written by a 1-bit RAM control

instruction. When SMOD.3 is set to 1, the contents of the serial interface interrupt request flag, IRQS, and the 3-

bit serial clock counter are cleared, and SIO operations are initiated. When the SIO transmission starts, SMOD.3

is cleared to logical zero.

Table 13–1. SIO Mode Register (SMOD) Organization

SMOD.0

SMOD.1

SMOD.2

0

1

0

1

0

Most significant bit (MSB) is transmitted first

Least significant bit (LSB) is transmitted first

Receive-only mode

Transmit-and-receive mode

Disable the data shifter and clock counter; retain contents of IRQS flag when serial

transmission is halted

1

0

Enable the data shifter and clock counter; set IRQS flag to "1" when serial

transmission is halted

SMOD.3

SMOD.4

Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset

this bit to logic zero

Bit not used; value is always "0"

SMOD.7

SMOD.6

SMOD.5

Clock Selection

R/W Status of SBUF

0

External clock at SCK pin

SBUF is enabled when SIO

operation is halted or when SCK

goes high.

0

1

0

1

0

1

x

0

Use TOL0 clock from TC0

CPU clock: fxx/4, fxx/8, fxx/64

Enable SBUF read/write

10

SBUF is enabled when SIO

operation is halted or when SCK

goes high.

4.09 kHz clock: fxx/2

4

1

262 kHz clock: fxx/2

NOTES:

1. 'fxx' = system clock; 'x' means 'don't care.'

2. kHz frequency ratings assume a system clock (fxx) running at 4.19 MHz.

3. The SIO clock selector circuit cannot select a fxx/2⁴clock if the CPU clock is fxx/64.

4. It must be selected MSB-first or LSB-first transmission mode before loading the data to SBUF.

13–3

SERIAL I/O INTERFACE

KS57C21516/P21516 MICROCONTROLLER

SERIAL I/O TIMING DIAGRAMS

SCK

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SI

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

SO

IRQS

TRANSMIT

COMPLETE

SET SMOD.3

Figure 13–2. SIO Timing in Transmit/Receive Mode

SCK

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SI

HIGH IMPEDANCE

SO

IRQS

TRANSMIT

COMPLETE

SET SMOD.3

Figure 13–3. SIO Timing in Receive-Only Mode

13–4

KS57C21516/P21516 MICROCONTROLLER

SERIAL I/O BUFFER REGISTER (SBUF)

SERIAL I/O INTERFACE

The serial I/O buffer register ,SBUF, can be read or written using 8-bit RAM control instructions. Following a

RESET, the value of SBUF is undetermined.

When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer

register are output to the SO pin (P0.1) at the rate of one bit for each falling edge of the SIO clock. Receive data

are simultaneously input from the SI pin (P0.2) to SBUF at the rate of one bit for each rising edge of the SIO

clock. When receive-only mode is used, incoming data are input to the SIO buffer at the rate of one bit for each

rising edge of the SIO clock.

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O

1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fxx/2 and in

MSB-first mode:

BITS

SMB

LD

BITS

EMB

15

EA,#03H

PMG1,EA

EA,#0E6H

SMOD,EA

EA,#48H

SBUF,EA

SMOD.3

; P0.0 / SCK and P0.1 / SO ¬ Output

;

; SIO data transfer

SCK

/ P0.0

EXTERNAL

DEVICE

SO / P0.1

[KS57C21516]

2. Use CPU clock to transfer and receive serial data at high speed:

BITS

SMB

LD

BITS

BITR

BTSTZ

JR

LD

SMB

LD

EMB

15

EA,#03H

PMG1,EA

EA,#47H

SMOD,EA

EA,TDATA

SBUF,EA

SMOD.3

IES

; P0.0 / SCK and P0.1 / SO ¬ Output, P0.2 / SI

; ¬ Input

; SIO start

STEST

IRQS

STEST

EA,SBUF

0

RDATA,EA

13–5

SERIAL I/O INTERFACE

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)

3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode:

BITS

SMB

LD

BITS

EI

EMB

15

EA,#03H

PMG1,EA

EA,#87H

SMOD,EA

EA,TDATA

SBUF,EA

SMOD.3

; P0.0 / SCK and P0.1 / SO ¬ Output, P0.2/SI ¬ Input

; SIO start

BITS

.

IES

.

INTS

PUSH

LD

SMB

XCH

SMB

LD

BITS

POP

IRET

SB

EA

EA,TDATA

15

EA,SBUF

0

RDATA,EA

SMOD.3

EA

; Store SMB, SRB

; Store EA

; EA ¬ Transmit data

; EA ¬ Receive data

; RDATA ¬ Receive data

; SIO start

SB

SCK

/ P0.0

EXTERNAL

DEVICE

SO / P0.1

SI / P0.2

[KS57C21516]

13–6

KS57C21516/P21516 MICROCONTROLLER

SERIAL I/O INTERFACE

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)

4. Transmit and receive an external clock in LSB-first mode:

BITS

SMB

LD

EMB

15

EA,#02H

PMG1,EA

EA,#07H

SMOD,EA

LD

; P0.1 / SO ¬ Output, P0.0 / SCK and P0.2 / SI ¬

Input

INTS

LD

BITS

EI

BITS

.

EA,TDATA

SBUF,EA

SMOD.3

; SIO start

IES

.

PUSH

LD

SMB

XCH

SMB

LD

BITS

POP

IRET

SB

EA

EA,TDATA

15

EA,SBUF

0

RDATA,EA

SMOD.3

EA

; Store SMB, SRB

; Store EA

; EA ¬ Transmit data

; EA ¬ Receive data

; RDATA ¬ Receive data

; SIO start

SB

SCK

/ P0.0

EXTERNAL

DEVICE

SO / P0.1

SI / P0.2

[KS57C21516]

High Speed SIO Transmission

13–7

SERIAL I/O INTERFACE

KS57C21516/P21516 MICROCONTROLLER

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Concluded)

Use CPU clock to transfer and receive serial data at high speed:

BITS

SMB

LD

BITS

BITR

BTSTZ

JR

LD

SMB

LD

EMB

15

EA,#03H

PMG1,EA

EA,#47H

SMOD, EA

EA,TDATA

SBUF,EA

SCMOD.3

IES

; P0.0 / SCK and P0.1 / SO ¨ Output, P0.2 / SI ¨ Input

; SIO start

STEST

IRQS

STEST

EA,SBUF

0

RDATA,EA

13–8

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, information on KS57C21516 electrical characteristics is presented as tables and graphics. The

information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings

— D.C. electrical characteristics

— Main system clock oscillator characteristics

— Subsystem clock oscillator characteristics

— I/O capacitance

— A.C. electrical characteristics

— Operating voltage range

Miscellaneous Timing Waveforms

— A.C timing measurement point

— Clock timing measurement at X

in

— Clock timing measurement at XT

in

— TCL timing

— Input timing for RESET

— Input timing for external interrupts

— Serial data transfer timing

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode

— Stop mode release timing when initiated by RESET

— Stop mode release timing when initiated by an interrupt request

14–1

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

Table 14–1. Absolute Maximum Ratings

°

(T = 25 C)

A

Parameter

Symbol

Conditions

Rating

Units

V

DD

Supply Voltage

Input Voltage

–

– 0.3 to + 6.5

V

I

– 0.3 to V

+ 0.3

Ports 0–9

V

DD

V

O

– 0.3 to V

+ 0.3

Output Voltage

Output Current High

–

V

I

One I/O pin active

All I/O pins active

One I/O pin active

– 15

– 35

mA

OH

I

Output Current Low

+ 30 (Peak value)

mA

OL

+ 15 ^(note)

+ 100 (Peak value)

+ 60 ^(note)

Total for ports 0, 2–9

T

A

°

Operating Temperature

Storage Temperature

–

– 40 to + 85

– 65 to + 150

C

T

°

C

stg

NOTE: The values for Output Current Low ( I_OL) are calculated as Peak Value ´

Duty .

Table 14–2. D.C. Electrical Characteristics

°

(T = – 40 C to + 85 C, V

= 1.8 V to 5.5 V)

DD

A

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V

IH1

0.7V

V

DD

Input High

Voltage

All input pins except those

specified below for V –V

–

V

DD

IH2 IH3

V

IH2

0.8V

V

DD

Ports 0, 1, 6, P3.2, P3.3, and

RESET

DD

V

IH3

X , X , and XT

in out in

V

DD

– 0.1

V

DD

V

0.3V

Input Low

Voltage

All input pins except those

specified below for V –V

–

V

IL1

IL2

IL3

DD

IL2 IL3

V

0.2V

Ports 0, 1, 6, P3.2, P3.3, and

RESET

DD

V

X , X , and XT

0.1

–

in

out

in

V

I

= 4.5 V to 5.5 V

= – 1 mA

V

– 1.0

DD

Output High

Voltage

–

V

OH

DD

OH

Ports 0, 2–9

V = 4.5 V to 5.5 V

V

Output Low

Voltage

–

2.0

OL

DD

= 15 mA

I

OL

Ports 0, 2–9

14–2

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

Table 14–2. D.C. Electrical Characteristics (Continued)

°

(T = – 40 C to + 85 C, V

= 1.8 V to 5.5 V)

DD

A

Parameter

Symbol

Conditions

Min

Typ

Max

Units

I

V = V

I

Input High

Leakage

Current

–

3

µA

LIH1

DD

All input pins except those

specified below for I

LIH2

I

V = V

20

– 3

– 20

3

LIH2

I

DD

X

XT and RESET

in,

in, out,

I

V = 0 V

Input Low

Leakage

–

µA

LIL1

I

X

and XT

in

in, out,

Current

I

V = 0 V

LIL2

I

X , X

in out,

and XT

in

I

V = V

DD

Output High

Leakage

Current

–

µA

kW

LOH

O

All output pins

I

V = 0 V

O

Output Low

Leakage

Current

– 3

LOL

All output pins

R

LI

V = 0 V; V

= 5 V

Pull-Up

Resistor

25

47

100

I

DD

Port 0–9

V

DD

= 3 V

50

100

200

25

95

220

450

55

200

400

800

80

R

L2

V = 0 V; V

I

= 5 V, RESET

V

DD

= 3 V

R

LCD

LCD Voltage

Dividing

Ta = 25 °C

kW

Resistor

V

– 15 µA per common pin

– 15 µA per segment pin

–

120

mV

| DD-COMi|

DC

Voltage Drop

(i = 0–15)

V

| DD-SEGx|

DS

Voltage Drop

(x = 0–55)

V

LCD clock = 0 Hz, V

LC5

= 0 V

0.8V -0.2 0.8V

DD

0.8V +0.2

DD

V

LC1 Output

LC1

DD

Voltage

V

LC2

V

LC3

V

LC4

0.6V -0.2 0.6V

DD

0.6V +0.2

DD

LC2 Output

Voltage

V

0.4V -0.2 0.4V

DD

0.4V +0.2

DD

LC3 Output

Voltage

V

0.2V -0.2 0.2V

DD

0.2V +0.2

DD

LC4 Output

Voltage

14–3

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

Table 14–2. D.C. Electrical Characteristics (Concluded)

°

(T = – 40 C to + 85 C, V

= 1.8 V to 5.5 V)

DD

A

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V

= 5 V ± 10%

(2)

Supply

Current

6.0 MHz

4.19 MHz

–

3.9

2.9

8.0

5.5

mA

DD

I

DD1

Crystal oscillator

C1 = C2 = 22 pF

V

DD

= 3 V ± 10%

6.0 MHz

4.19 MHz

1.8

1.3

4.0

3.0

(2)

Idle mode;

= 5 V ± 10%

6.0 MHz

4.19 MHz

1.3

1.2

2.5

1.8

I

DD2

V

DD

Crystal oscillator

C1 = C2 = 22 pF

V

DD

= 3 V ± 10%

6.0 MHz

4.19 MHz

0.5

0.44

1.5

1.0

V

= 3 V ± 10%

(3)

–

15.3

6.4

2.5

0.5

0.2

0.1

30

15

5

µA

DD

I

DD3

32 kHz crystal oscillator

Idle mode; V = 3 V ± 10%

DD

DD4

I

32 kHz crystal oscillator

Stop mode;

SCMOD =

0000B

DD5

V

= 5 V ± 10%

DD

Stop mode;

= 3 V ± 10%

XT = 0V

3

V

DD

Stop mode;

= 5 V ± 10%

SCMOD =

0100B

3

V

DD

Stop mode;

= 3 V ± 10%

2

V

DD

NOTES:

1. Data includes power consumption for subsystem clock oscillation.

2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the

subsystem clock is used.

3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,

output port drive currents.

14–4

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

Table 14–3. Main System Clock Oscillator Characteristics

°

(T = – 40 C + 85 C, V

= 1.8 V to 5.5 V)

DD

A

Oscillator

Clock

Configuration

Parameter

Test Condition

Min

Typ

Max Units

(1)

Ceramic

Oscillator

–

0.4

–

6.0

MHz

Oscillation frequency

Xin Xout

C1

C2

(2)

Stabilization occurs

–

4

ms

Stabilization time

when V

is equal

DD

to the minimum

oscillator voltage

range; V

= 3.0 V.

DD

(1)

Crystal

Oscillator

–

0.4

6.0

MHz

Oscillation frequency

Xin

Xout

C1

C2

(2)

V

= 3.0 V

–

10

30

ms

DD

Stabilization time

= 2.0 V to 5.5 V

–

DD

(1)

External

Clock

0.4

6.0

MHz

Xin

Xout

X input frequency

in

X input high and low

in

–

83.3

–

2

1250

–

ns

level width (t , t

)

XH XL

RC

Frequency

MHz

Xin

Xout

R = 20 kW,

= 5 V

V

Oscillator

DD

R

–

1

–

R = 39 kW,

= 3 V

V

DD

NOTES:

1. Oscillation frequency and X_ininput frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is

terminated.

14–5

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

Table 14–4. Recommended Oscillator Constants

°

(T = – 40 C + 85 C, V

= 1.8 V to 5.5 V)

DD

A

Manufacturer

Series

Number ⁽¹⁾

Frequency Range

Load Cap (pF)

Oscillator Voltage

Range (V)

Remarks

C1

33

(2)

C2

33

(2)

MIN

2.0

MAX

5.5

TDK

3.58 MHz–6.0 MHz

Leaded Type

FCR” ðÿM5

2.0

5.5

On-chip C

FCR” ðÿMC5

Leaded Type

(3)

3.58 MHz–6.0 MHz

2.0

5.5

On-chip C

SMD Type

CCR” ðÿMC3

NOTES:

1. Please specify normal oscillator frequency.

2. On-chip C: 30pF built in.

3. On-chip C: 38pF built in.

14–6

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

Table 14–5. Subsystem Clock Oscillator Characteristics

°

(T = – 40 C + 85 C, V

= 1.8 V to 5.5 V)

DD

A

Oscillator

Clock

Parameter

Test Condition

Min

Typ

Max

Units

Configuration

Crystal

Oscillator

Oscillation

frequency ⁽¹⁾

–

32

32.768

35

kHz

XTin XTout

C1

C2

Stabilization time ⁽²⁾

V_DD= 2.7 V to 5.5 V

V_DD= 2.0 V to 5.5 V

–

1.0

–

2

s

10

XT input

in

frequency ⁽¹⁾

External

Clock

32

–

100

kHz

XTin XTout

XT input high and

in

–

5

–

15

µs

low level width (t

,

XTL

t

)

XTH

NOTES:

1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.

in

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.

Table 14–6. Input/Output Capacitance

°

(T = 25 C, V = 0 V )

A

DD

Parameter

Symbol

Condition

Min

Typ

Max

Units

C

Input

Capacitance

f = 1 MHz; Unmeasured pins

–

15

pF

IN

are returned to V

SS

C

OUT

Output

Capacitance

–

C

IO

I/O Capacitance

14–7

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

Table 14–7. A.C. Electrical Characteristics

= 1.8 V to 5.5 V)

°

(T = – 40 C to + 85 C, V

A

DD

Parameter

Symbol

Conditions

Min

Typ

Max

Units

t

V

= 2.7 V to 5.5 V

Instruction Cycle

Time

0.67

–

64

µs

CY

, f

DD

(note)

V

= 2.0 V to 5.5 V

= 2.7 V to 5.5 V

0.95

0

64

DD

f

TCL0, TCL1 Input

Frequency

–

1.5

MHz

µs

TI0 TI1

DD

V

= 2.0 V to 5.5 V

= 2.7 V to 5.5 V

1

–

DD

t

, t

TIH0 TIL0

TCL0, TCL1 Input

High, Low Width

0.48

DD

, t

TIH1 TIL1

V

= 2.0 V to 5.5 V

1.8

800

DD

t

= 2.7 V to 5.5 V; Input

SCK Cycle Time

–

ns

KCY

DD

Internal SCK source; Output

= 2.0 V to 5.5 V; Input

650

V

3200

3800

325

DD

Internal SCK source; Output

= 2.7 V to 5.5 V; Input

t

, t

V

DD

SCK High, Low

Width

KH KL

t

/2 –

KCY

Internal SCK source; Output

50

V

DD

= 2.0 V to 5.5 V; Input

1600

Internal SCK source; Output

t

_KCY/2 –

150

t

V

= 2.7 V to 5.5 V; Input

SI Setup Time to

SCK High

100

–

ns

SIK

DD

V

DD

V

DD

V

DD

V

DD

= 2.7 V to 5.5 V; Output

= 2.0 V to 5.5 V; Input

= 2.0 V to 5.5 V; Output

= 2.7 V to 5.5 V; Input

150

500

400

t

SI Hold Time to

SCK High

KSI

V

DD

V

DD

V

DD

= 2.7 V to 5.5 V; Output

= 2.0 V to 5.5 V; Input

= 2.0 V to 5.5 V; Output

400

600

500

NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.

14–8

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

Table 14–7. A.C. Electrical Characteristics (Continued)

_

(T = – 40 C to + 85 C, V

= 1.8 V to 5.5 V)

A

DD

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t

V

DD

= 2.7 V to 5.5 V; Input

Output Delay for

SCK to SO

–

300

ns

KSO

V

= 2.7 V to 5.5 V; Output

= 2.0 V to 5.5 V; Input

= 2.0 V to 5.5 V; Output

250

1000

–

DD

t

,

Interrupt Input

High, Low Width

INT0, INT1, INT2, INT4,

K0–K7

10

–

µs

INTH

INTL

t

RESET Input Low

Width

Input

–

RSL

NOTE: Minimum value for INT0 is based on a clock of 2t_CYor 128 / fx as assigned by the IMOD0 register setting.

Main Oscillator Frequency

CPU CLOCK

1.5 MHz

(Divided by 4)

6 MHz

4.2 MHz

3 MHz

1.05 MHz

750 kHz

15.6 kHz

1

2

3

4

5

6

7

1.8 V

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 14–1. Standard Operating Voltage Range

14–9

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

Table 14–8. RAM Data Retention Supply Voltage in Stop Mode

°

(T = – 40 C to + 85 C)

A

Parameter

Symbol

Conditions

–

Min

1.8

–

Typ

–

Max

5.5

10

Unit

V

DDDR

Data retention supply voltage

Data retention supply current

I

V

= 1.8 V

0.1

µA

DDDR

t

Release signal set time

–

0

–

µs

SREL

2¹⁷/ fx

t

Oscillator stabilization wait

Released by RESET

ms

WAIT

(1)

time

(2)

Released by interrupt

–

NOTES:

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator

start-up.

2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

14–10

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

TIMING WAVEFORMS

RESET

INTERNAL

OPERATION

IDLE MODE

NORMAL MODE

STOP MODE

DATA RETENTION MODE

V

DD

V

DDDR

EXECUTION OF

STOP INSTRUCTION

RESET

t

WAIT

t

SREL

Figure 14–2. Stop Mode Release Timing When Initiated by RESET

IDLE MODE

NORMAL MODE

STOP MODE

DATA RETENTION MODE

V_DD

V_DDDR

t_SREL

EXECUTION OF

STOP INSTRUCTION

t_WAIT

POWER-DOWN MODE TERMINATING SIGNAL

(INTERRUPT REQUEST)

Figure 14–3. Stop Mode Release Timing When Initiated by Interrupt Request

14–11

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

0.8 V_DD

0.2 V_DD

0.8 V_DD

0.2 V_DD

MEASUREMENT

POINTS

Figure 14–4. A.C. Timing Measurement Points (Except for X and XT )

in

1 / fx

t

XH

XL

X

in

V

-0.1 V

DD

0.1 V

Figure 14–5. Clock Timing Measurement at X

in

1 / fxt

t

XTH

XTL

XT

in

V

- 0.1 V

DD

0.1 V

Figure 14–6. Clock Timing Measurement at XT

in

14–12

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

1 / f

TI

t

TIH

TIL

0.8 V

DD

TCL0

0.2 V

DD

Figure 14–7. TCL Timing

t

RSL

RESET

0.2 V

DD

Figure 14–8. Input Timing for RESET Signal

t

INTL

INTH

0.8V

0.2V

DD

INT0, 1, 2, 4 K0 to K7

DD

Figure 14–9. Input Timing for External Interrupts and Quasi-Interrupts

14–13

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

t

KCY

t

KH

KL

0.8 V

DD

SCK

0.2 V

DD

t

KSI

SIK

0.8 V

DD

INPUT DATA

SI

0.2 V

DD

t

KSO

SO

OUTPUT DATA

Figure 14–10. Serial Data Transfer Timing

14–14

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

NOTES

14–15

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

CHARACTERISTIC CURVES

NOTE

The characteristic values shown in the following graphs are based on actual test measurements.

They do not, however, represent guaranteed operating values.

(T = 25 °C, fx = 4.2 MHz)

A

5.0

4.5

I

, CPU Clock = fx/4

DD1

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

I

, CPU Clock = fx/64

DD1

I

DD2

0

2.7

4.0

4.5

6.0

V

(V)

DD

, I

Figure 14–11. I

VS. V

DD

DD1 DD2

14–16

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

(T = 25 °C, fx = 32.768 kHz)

A

50

45

40

35

30

25

20

15

10

5

I

DD3

I

DD4

DD5

I

0

2.0

2.5

3.0

3.5

4.0

V

4.5

5.0

5.5

6.0

6.5

(V)

DD

Figure 14–12. I

, I

VS. V

DD3 DD4 DD5

DD

14–17

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

(T = 25 °C, CPU CLOCK = fx/4)

A

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 6.0 V

= 4.5 V

DD

V

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

Main System Clock Frequency (MHz)

Figure 14–13. I

VS. Main System Clock Frequency

DD1

(T = 25 °C)

A

1.6

V

= 6.0 V

= 4.5 V

DD

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

DD

0.5

1.0

Main System Clock Frequency (MHz)

Figure 14–14. I VS. Main System Clock Frequency

1.5

2.0

2.5

3.0

3.5

4.0

4.5

DD2

14–18

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

(T = 25 °C, Ports 0, 2, 3, 4, 5, 6, 7)

A

–25.0

–22.5

–20.0

–17.5

–15.0

–12.5

–10.0

–7.5

–5.0

–2.5

V

= 4.5 V

4.0

V

= 6.0 V

DD

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.5

5.0

5.5

6.0

V

(V)

OH

Figure 14–15. I

OH

VS. V

(P0, 2, 3, 4, 5, 6, 7)

OH

14–19

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

(T = 25 °C, Ports 8, 9)

A

–25.0

–22.5

–20.0

–17.5

–15.0

–12.5

–10.0

–7.5

–5.0

–2.5

V

= 4.5 V

4.0

V

= 6.0 V

5.5

DD

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.5

5.0

6.0

V

(V)

OH

Figure 14–16. I

OH

VS. V (P8, 9)

OH

14–20

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

(T = 25 °C, Ports 0, 2, 3, 4, 5, 6, 7)

A

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

V

= 6.0 V

DD

V

= 4.5 V

DD

0

0.5

1.0

1.5

2.0

2.5

3.0

OL

3.5

4.0

4.5

5.0

5.5

6.0

V

(V)

Figure 14–17. I

OL

VS. V

(P0, 2, 3, 4, 5, 6, 7)

OL

14–21

ELECTRICAL DATA

KS57C21516/P21516 MICROCONTROLLER

(T = 25 °C, Ports 8, 9)

A

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

V

= 6.0 V

DD

V

= 4.5 V

DD

0

0.5

1.0

1.5

2.0

2.5

3.0

OL

3.5

4.0

4.5

5.0

5.5

6.0

V

(V)

Figure 14–18. I

OL

VS. V

OL

(P8, 9)

14–22

KS57C21516/P21516 MICROCONTROLLER

ELECTRICAL DATA

NOTES

14–23

KS57C21516/P21516 MICROCONTROLLER

MECHANICAL DATA

15 MECHANICAL DATA

OVERVIEW

This section contains the following information about the device package:

—

Package dimensions in millimetersD

Pad diagram

Pad/pin coordinate data table

15–1

MECHANICAL DATA

KS57C21516/P21516 MICROCONTROLLER

20.00 TYP

C

D

100 QFP

(Top View)

B

+ 0.1

0.15

0.65 TYP

0.30 ± 0.1

– 0.05

A

E

Item

A

B

C

D

E

Package

+ 0.1

– 0.05

100-QFP-1420A 25.00 ± 0.3 19.00 ± 0.3 2.45 MAX

100-QFP-1420C 23.20 ± 0.3 17.20 ± 0.3 3.00 MAX

0.15

1.20 ± 0.2

0.80 ± 0.2

0.15 ± 0.1

NOTE

: Typical dimensions are in millimeters.

Figure 15–1. 100-QFP Package Dimensions

15-2

KS57C21516/P21516 MICROCONTROLLER

KS57P21516 OTP

16 KS57P21516 OTP

OVERVIEW

The KS57P21516 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

KS57C21516 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by

serial data format.

The KS57P21516 is fully compatible with the KS57C21516, both in function and in pin configuration. Because of

its simple programming requirements, the KS57P21516 is ideal for use as an evaluation chip for the

KS57C21516.

16–1

KS57P21516 OTP

KS57C21516/P21516 MICROCONTROLLER

1

2

3

4

5

6

7

8

SEG4

SEG3

SEG2

SEG1

SEG0

VLC5

VLC4

VLC3

VLC2

VLC1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

P9.3/SEG40

P9.2/SEG41

P9.1/SEG42

P9.0/SEG43

P8.3/SEG44

P8.2/SEG45

P8.1/SEG46

P8.0/SEG47

P7.3/SEG48

P7.2/SEG49

P7.1/SEG50

P7.0/SEG51

P6.3/SEG52/K7

P6.2/SEG53/K6

P6.1/SEG54/K5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P0.0/SCK /K0

P0.1/SO/K1

/P0.2/SI/K2

SDAT

SCLK

/P0.3/BUZ/K3

KS57P21516

(100-QFP-1420C)

VDD

/VDD

VSS

/VSS

Xout

Xin

/TEST

XTin

XTout

/RESET

VPP

RESET

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

P2.0/CLO

P2.1/LCDCK

P2.2/LCDSY

P3.0/TCLO0

NOTE:

The bolds indicate an OTP pin name.

Figure 16–1. KS57P21516 Pin Assignments (100-QFP Package)

16–2

KS57C21516/P21516 MICROCONTROLLER

KS57P21516 OTP

Table 16–1. Descriptions of Pins Used to Read/Write the EPROM

Main Chip

Pin Name

P0.2

During Programming

I/O

Pin Name

Pin No.

Function

SDAT

13

I/O

Serial data pin. Output port when reading and

input port when writing. Can be assigned as a

Input / push-pull output port.

P0.3

SCLK

14

19

I/O

I

Serial clock pin. Input only pin.

V

(TEST)

TEST

Power supply pin for EPROM cell writing

(indicates that OTP enters into the writing

mode). When 12.5 V is applied, OTP is in

writing mode and when 5 V is applied, OTP is in

reading mode. (Option)

PP

22

I

Chip initialization

RESET

V / V

DD

V

/ V

15/16

Logic power supply pin. VDD should be tied to

+5 V during programming.

DD

SS

Table 16–2. Comparison of KS57P21516 and KS57C21516 Features

Characteristic

KS57P21516

16 Kbyte EPROM

1.8 V to 5.5 V

= 5 V, V (TEST)=12.5V

KS57C21516

16 Kbyte mask ROM

1.8 V to 5.5 V

Program Memory

Operating Voltage (V

)

DD

V

OTP Programming Mode

DD

100 QFP

User Program 1 time

PP

Pin Configuration

100 QFP

EPROM Programmability

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V (TEST) pin of the KS57P21516, the EPROM programming mode is entered.

PP

The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 16–3 below.

Table 16–3. Operating Mode Selection Criteria

V

Vpp

(TEST)

5 V

REG/

Address

(A15-A0)

0000H

R/W

Mode

DD

MEM

5 V

0

1

0

1

0

EPROM read

12.5 V

0000H

EPROM program

EPROM verify

0000H

0E3FH

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

16–3

KS57P21516 OTP

KS57C21516/P21516 MICROCONTROLLER

Table 16–4. D.C. Electrical Characteristics

°

(T = – 40 C to + 85 C, V

= 1.8 V to 5.5 V)

A

DD

Parameter

Symbol

Conditions

Min

Typ

Max

Units

(2)

V

= 5 V ± 10%

Supply

Current

6.0 MHz

4.19 MHz

–

3.9

2.9

8.0

5.5

mA

DD

I

DD1

Crystal oscillator

C1 = C2 = 22 pF

V

DD

= 3 V ± 10%

6.0 MHz

4.19 MHz

1.8

1.3

4.0

3.0

(2)

Idle mode;

= 5 V ± 10%

6.0 MHz

4.19 MHz

1.3

1.2

2.5

1.8

I

DD2

V

DD

Crystal oscillator

C1 = C2 = 22 pF

V

DD

= 3 V ± 10%

6.0 MHz

4.19 MHz

0.5

0.44

1.5

1.0

(3)

V

= 3 V ± 10%

–

15.3

6.4

2.5

0.5

0.2

0.1

30

15

5

µA

DD

I

DD3

32 kHz crystal oscillator

Idle mode; V = 3 V ± 10%

DD

DD4

I

32 kHz crystal oscillator

Stop mode;

= 5 V ± 10%

SCMOD =

0000B

DD5

V

DD

Stop mode;

= 3 V ± 10%

XT = 0V

3

V

DD

Stop mode;

= 5 V ± 10%

SCMOD =

0100B

3

V

DD

Stop mode;

= 3 V ± 10%

2

V

DD

NOTES:

1. Data includes power consumption for subsystem clock oscillation.

2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the

subsystem clock is used.

3. Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,

output port drive currents.

16–4

KS57C21516/P21516 MICROCONTROLLER

KS57P21516 OTP

Main Oscillator Frequency

CPU CLOCK

1.5 MHz

(Divided by 4)

6 MHz

1.05 MHz

750 kHz

4.2 MHz

3 MHz

15.6 kHz

1

2

3

4

5

6

7

1.8 V

SUPPLY VOLTAGE (V)

CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 16–2. Standard Operating Voltage Range

16–5

KS57P21516 OTP

KS57C21516/P21516 MICROCONTROLLER

NOTES

16–6

KS57C21516/P21516 MICROCONTROLLER

DEVELOPMENT TOOLS

17 DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system in turnkey form. The development

support system is configured with a host system, debugging tools, and support software. For the host system, any

standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool

including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for

KS57, KS86, KS88 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.

Samsung also offers support software that includes debugger, assembler, and a program for setting options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE

provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked

help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be

sized, moved, scrolled, highlighted, added, or removed completely.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates

object code in standard hexadecimal format. Assembled program code includes the object code that is used for

ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and

an auxiliary definition (DEF) file with device specific information.

SASM57

The SASM57 is an relocatable assembler for Samsung's KS57-series microcontrollers. The SASM57 takes a

source file containing assembly language statements and translates into a corresponding source code, object

code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating

system. It produces the relocatable object code only, so the user should link object file. Object files can be linked

with other object files and loaded into memory.

HEX2ROM

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be

needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by

HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device

automatically.

TARGET BOARDS

Target boards are available for all KS57-series microcontrollers. All required target system cables and adapters

are included with the device-specific target board.

OTPS

One time programmable microcontroller (OTP) for the KS57C21516 microcontroller and OTP programmer

(Gang) are now available.

17-1

DEVELOPMENT TOOLS

KS57C21516/P21516 MICROCONTROLLER

IBM-PC AT or Compatible

RS-232C

SMDS2+

TARGET

APPLICATION

SYSTEM

PROM/MTP WRITER UNIT

RAM BREAK/ DISPLAY UNIT

TRACE/TIMER UNIT

PROBE

ADAPTER

TB5721516A

TARGET

BOARD

POD

SAM4 BASE UNIT

EVA

CHIP

POWER SUPPLY UNIT

Figure 17-1. SMDS Product Configuration (SMDS2+)

17-2

KS57C21516/P21516 MICROCONTROLLER

DEVELOPMENT TOOLS

TB5721516A TARGET BOARD

The TB5721516A target board is used for the KS57C21516 microcontroller. It is supported by the SMDS2+

development system.

TB5721516A

To User_Vcc

OFF

ON

RESET

STOP

IDLE

74HC11

+

XTI

25

J101

J102

1

2

1

2

160 QFP

KS57E21500

EVA CHIP

1

XI

EXTERNAL

TRIGGERS

49

50 49

50

CH1

CH2

SM1255A

Figure 17-2. TB5721516A Target Board Configuration

17-3

DEVELOPMENT TOOLS

KS57C21516/P21516 MICROCONTROLLER

Table 17-1. Power Selection Settings for TB5721516A

Operating Mode

'To User_Vcc' Settings

Comments

The SMDS2/SMDS2+

To User_Vcc

supplies V

to the target

CC

TARGET

SYSTEM

OFF

ON

TB5721516A

board (evaluation chip) and

the target system.

V

CC

V

SS

V

CC

SMDS2/SMDS2+

The SMDS2/SMDS2+

To User_Vcc

OFF ON

supplies V

only to the

CC

External

TARGET

SYSTEM

TB5721516A

target board (evaluation chip).

The target system must have

its own power supply.

V

CC

V

SS

V

CC

SMDS2+

Table 17-2. Main-Clock Selection Settings for TB5721516A

Operating Mode

Main Clock Setting

Comments

Set the XIN switch to “MDS”

when the target board is

connected to the

XI

EVA CHIP

KS57E21500

MDS

XTAL

SMDS2/SMDS2+.

X_OUT

X

IN

No connection

100 pin connector

SMDS2/SMDS2+

Set the XIN switch to “XTAL”

when the target board is used

as a standalone unit, and is

not connected to the

XI

EVA CHIP

MDS

XTAL

KS57E21500

X_OUT

SMDS2/SMDS2+.

X

IN

XTAL

TARGET BOARD

17-4

KS57C21516/P21516 MICROCONTROLLER

DEVELOPMENT TOOLS

Comments

Table 17-3. Sub-Clock Selection Settings for TB5721516A

Sub Clock Setting

Operating Mode

Set the XTI switch to “MDS”

when the target board is

connected to the

XTI

EVA CHIP

KS57E21500

MDS

XTAL

SMDS2/SMDS2+.

XT_OUT

XT

IN

No connection

100 pin connector

SMDS2/SMDS2+

Set the XTI switch to “XTAL”

when the target board is used

as a standalone unit, and is

not connected to the

XTI

EVA CHIP

MDS

XTAL

KS57E21500

XT_OUT

SMDS2/SMDS2+.

XT

IN

XTAL

TARGET BOARD

Table 17-4. Using Single Header Pins as the Input Path for External Trigger Sources

Target Board Part

Comments

Connector from

external trigger

sources of the

application system

EXTERNAL

TRIGGERS

CH1

CH2

You can connect an external trigger source to one of the two external

trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace

functions.

IDLE LED

This LED is ON when the evaluation chip (KS57E21500) is in idle mode.

STOP LED

This LED is ON when the evaluation chip (KS57E21500) is in stop mode.

17-5

DEVELOPMENT TOOLS

KS57C21516/P21516 MICROCONTROLLER

J101

J102

1

3

5

7

2

4

6

P6.1/SEG54/K5

P6.3/SEG52/K7

P7.1/SEG50

P7.3/SEG48

P8.1/SEG46

P8.3/SEG44

P9.1/SEG42

P9.3/SEG40

SEG38

1

3

5

7

2

4

6

SEG4

SEG2

SEG0

VLC4

VLC2

SEG3

SEG1

VLC5

VLC3

P6.2/SEG53/K6

P7.0/SEG51

P7.2/SEG49

P8.0/SEG47

P8.2/SEG45

P9.0/SEG43

P9.2/SEG41

SEG39

SEG37

SEG35

SEG33

SEG31

SEG29

SEG27

SEG25

SEG23

SEG21

SEG19

SEG17

SEG15

8

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

VLC1

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

P0.0/SCK /K0

P0.2/SI/K2

VDD

P0.1/SO/K1

P0.3/BUZ/K3

VSS

Xin

XTin

Xout

TEST

XTout

SEG36

SEG34

SEG32

SEG30

SEG28

SEG26

SEG24

SEG22

SEG20

SEG18

SEG16

SEG14

SEG12

SEG10

SEG8

SEG6

RESET

P1.0/INT0

P1.2/INT2

P2.0/CLO

P2.2/LCDSY

P3.1/TCLO1

P3.3/TCL1

COM1

P1.1/INT1

P1.3/INT4

P2.1/LCDCK

P3.0/TCLO0

P3.2/TCL0

COM0

COM2

COM4

COM6

P4.0/COM8

P4.2/COM10

P5.0/COM12

P5.2/COM14

P6.0/SEG55/K4

COM3

COM5

COM7

SEG13

SEG11

SEG9

SEG7

P4.1/COM9

P4.3/COM11

P5.1/COM13

P5.3/COM15

SEG5

Figure 17-3. 50-Pin Connectors for TB5721516A

TARGET BOARD

J101 J102

TARGET SYSTEM

J102

J101

1

2

1

2

1

2

1

2

Target Cable for 50-Pin Connector

Part Name: AS50D-A

Order Code: SM6305

49 50 49 50

Figure 17-4. TB5721516A Adapter Cable for 100 QFP Package (KS57C21516)

17-6

KS57C21516/P21516 MICROCONTROLLER

DEVELOPMENT TOOLS

17-7


型号：	KS57C21516Q-XX
厂家：	SAMSUNG
描述：	Microcontroller, 4-Bit, MROM, CMOS, PQFP100, 14 X 20 MM, QFP-100 微控制器
文件：	总338页 (文件大小：1373K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS57C21516Q-XX [SAMSUNG]

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