KS57C5532N-XX_技术文档

Product Overview

Address Spaces

Addressing Modes

Memory Map

SAM47 Instruction Set

KS57C5532/P5532

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

OVERVIEW

The KS57C5532/P5532 single-chip CMOS microcontroller has been designed for high-performance using

Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The KS57P5532 is a

microcontroller which has 32-kbyte one-time-programmable EPROM but its functions are same to KS57C5532.

With its DTMF generator, 8-bit serial I/O interface, and versatile 8-bit timer/counters, the KS57C5532/P5532

offers an excellent design solution for a wide variety of telecommunication applications.

Up to 55 pins of the 64-pin SDIP or QFP package can be dedicated to I/O. Seven vectored interrupts provide fast

response to internal and external events. In addition, the KS57C5532/P5532's advanced CMOS technology

provides for low power consumption and a wide operating voltage range.

DEVELOPMENT SUPPORT

The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based develop-

ment environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its

window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction

timing, and performance measurement applications.

The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and

accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard

hex files that also contain program control data for SMDS compatibility.

1-1

PRODUCT OVERVIEW

KS57C5532/P5532

FEATURES SUMMARY

Memory

Bit Sequential Carrier

·

1 K ´ 4-bit RAM

32 K ´ 8-bit ROM

·

Supports 8-bit serial data transfer in arbitrary

format

Interrupts

55 I/O Pins

·

3 external interrupt vectors

·

Input only: 4 pins

4 internal interrupt vectors

2 quasi-interrupts

I/O: 43 pins

N-channel open-drain I/O (S/W): 8 pins

Power-Down Modes

Memory-Mapped I/O Structure

Data memory bank 15

·

Idle: Only CPU clock stops

Stop: Main system clock stops

Subsystem clock stop mode

·

DTMF Generator

16 dual-tone frequencies for tone dialing

·

Oscillation Sources

8-bit Basic Timer

·

Crystal, ceramic for main system clock

Crystal oscillator for subsystem clock

·

Programmable internal timer

Watchdog timer

Main system clock frequency:

3.579545 MHz (typical)

Two 8-bit Timer/Counters

·

Subsystem clock frequency: 32.768 kHz (typical)

CPU clock divider circuit (by 4, 8, or 64)

·

Programmable interval timer

External event counter function

Instruction Execution Times

Timer/counters clock outputs to TCLO0 and

TCLO1 pins

·

0.67, 1.33, 10.7 µs at 6.0 MHz

1.12, 2.23, 17.88 µs at 3.579545 MHz

122 µs at 32.768 kHz

·

External clock signal divider

Serial I/O interface clock generator

Watch Timer

Operating Temperature

·

Time interval generation:

0.5 s, 3.9 ms at 32.768 kHz

°

·

– 40 C to 85 C

·

4 frequency outputs to the BUZ pin

Operating Voltage Range

·

1.8 V to 5.5 V (at 3 MHz)

2.7 V to 5.5 V (at 6 MHz)

8-bit Serial I/O Interface

·

8-bit transmit/receive mode

8-bit receive mode

Package Types

64 SDIP, 64 QFP

LSB-first or MSB-first transmission selectable

·

1-2

KS57C5532/P5532

PRODUCT OVERVIEW

BLOCK DIAGRAM

Watch

Timer

Basic

Timer

Watch-Dog

Timer

X

IN

XT

OUT

XT

INT0, INT1, INT2 INT4

RESET

IN

OUT

P0.0/

SCK

P0.1/SO

P0.2/SI

P0.3/BTCO

I/O Port 0

8-BIT

Timer/

Counter 0

Interrupt

Control

Block

Stack

Pointer

Clock

Serial I/O

Port

8-BIT

Timer/

Counter 1

Program

Counter

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

Internal

Interrupts

Input

Port1

P6.0-P6.3/

KS0-KS3

I/O Port 6

I/O Port 7

P7.0-P7.3/

KS4-KS7

P2.0/TCLO0

P2.1/TCLO1

P2.2/CLO

Program

Status

Word

Instruction Decoder

I/O Port 2

I/O Port 3

P2.3/BUZ

P8.0-P8.3

P9.0-P9.3

I/O Port 8

I/O Port 9

P3.0/TCLO0

P3.1/TCLO1

P3.2

Arithmetic

and

Logic Unit

Flags

P3.3

I/O Port 4

I/O Port 5

P4.0-P4.3

P5.0-P5.3

P10.0-P10.3

P11.0-P11.3

I/O Port 10

I/O Port 11

1 K x 4-BIT

Data

Memory

32 K Byte

Program

Memory

P12.0-P12.3

P13.0-P13.2

I/O Port 12

I/O Port 13

DTMF

Generator

DTMF

Figure 1-1. KS57C5532/P5532 Simplified Block Diagram

1-3

PRODUCT OVERVIEW

KS57C5532/P5532

PIN ASSIGNMENTS

VSS

P9.0

P9.1

P9.2

P9.3

P8.0

P8.1

P8.2

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P13.2

P13.1

P13.0

P2.3/BUZ

P2.2/CLO

P2.1/TCLO1

P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/SCK

P10.3

1

2

3

4

5

6

7

8

P8.3

9

P7.0/KS4

P7.1/KS5

P7.2/KS6

P7.3/KS7

P6.0/KS0

P6.1/KS1

P6.2/KS2

P6.3/KS3

XTOUT

XT_IN

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P10.2

P10.1

P10.0

P11.3

P11.2

P11.1

P11.0

P12.3

P12.2

P12.1

P12.0

P3.3

P3.2

TEST

DTMF

VDD

X_IN

XOUT

RESET

P5.0

P5.1

P5.2

P5.3

P4.0

P4.1

P4.2

P4.3

P3.0/TCL0

P3.1/TCL1

Figure 1-2. KS57C5532/P5532 Pin Assignment Diagrams

1-4

KS57C5532/P5532

PRODUCT OVERVIEW

P8.0

P9.3

P9.2

P9.1

P9.0

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

P5.3

P4.0

P4.1

P4.2

P4.3

SS

V

P3.0/TCL0

P3.1/TCL1

VDD

DTMF

TEST

P3.2

KS57C5532

(64-QFP-1420F)

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P13.2

P13.1

P13.0

P3.3

P12.0

Figure 1-2. KS57C5532/P5532 Pin Assignment Diagrams (Continued)

1-5

PRODUCT OVERVIEW

KS57C5532/P5532

PIN DESCRIPTIONS

Table 1-1. KS57C5532/P5532 Pin Descriptions

Description

Pin Name

P0.0

P0.1

P0.2

P0.3

Pin Type

Number

Share Pin

I/O

4-bit I/O port.

15 (8)

14 (7)

13 (6)

12 (5)

1-bit or 4-bit read/write and test is possible.

Individual pins are software configurable as input or

output.

SO

SI

BTCO

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

I

P1.0

P1.1

P1.2

P1.3

4-bit input port.

1 (61)

2 (60)

3 (59)

4 (58)

INT0

INT1

INT2

INT4

1-bit and 4-bit read and test is possible.

4-bit pull-up resistors are assignable by software to

port 1.

I/O

Same as port 0.

P2.0

P2.1

P2.2

P2.3

11 (4)

10 (3)

9 (2)

TCLO0

TCLO1

CLO

8 (1)

BUZ

P3.0

P3.1

P3.2

P3.3

34 (27)

33 (26)

29 (22)

28 (21)

TCL0

TCL1

SCLK ⁽¹⁾

SDAT ⁽¹⁾

–

P4.0–P4.3

4-bit I/O ports.

38–35

(31–28)

42–39

1-bit and 4-bit read/write and test is possible.

4-bit pull-up resistors are software assignable to input

pins and are automatically disable for output pins.

N-channel open-drain or push-pull output can be

selected by software. Port 4 and 5 can be paired to

support 8-bit data transfer.

P5.0–P5.3

(35–32)

P6.0–P6.3

P7.0–P7.3

I/O

4-bit I/O ports.

51–48

(44–41)

55–52

KS0–KS3

KS4–KS7

1-bit or 4-bit read/write and test is possible.

Port 6 pins are individually software configurable as

input or output.

(48–45)

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

Ports 6 and 7 can be paired to enable 8-bit data

transfer.

P8.0–P8.3

P9.0–P9.3

I/O

Same as port 0.

59–56

(52–49)

–

4-bit I/O port.

63–60

1-bit or 4-bit read/write and test is possible.

4-bit pull-up resistors are software assignable; pull-up

resistors are automatically disabled for output pins.

(56–53)

NOTES

1. SCLK and SDAT are used for KS57P5532 only.

2. Parentheses indicate pin number for 64 QFP package.

1-6

KS57C5532/P5532

PRODUCT OVERVIEW

Table 1-1. KS57C5532/P5532 Pin Descriptions (Continued)

Pin Type Description

Pin Name

Number

Share Pin

I/O

–

P10.0–P10.3

Same as port 9.

Ports 10 and 11 can be paired to support 8-bit data

transfer.

19–16

(12–9)

23–20

P11.0–P11.3

P12.0–P12.3

(16–13)

I/O

–

4-bit I/O port.

27–24

(20–17)

1-bit or 4-bit read/write and test is possible.

Individual pins are software configurable as input or

output.

4-bit pull-down resistors are software assignable;

pull-down resistors are automatically disabled for

output pins.

P13.0–P13.2

DTMF

I/O

3-bit I/O port; characteristics are same as port 9.

7–5

(64–62)

O

I/O

I

DTMF output.

31 (24)

15 (8)

14 (7)

13 (6)

12 (5)

–

P0.0

Serial I/O interface clock signal

Serial data output

SO

P0.1

SI

Serial data input

P0.2

BTCO

INT0, INT1

Basic timer clock output

P0.3

P1.0, P1.1

External interrupts. The triggering edge for INT0 and

INT1 is selectable. INT0 is synchronized to system

clock.

4, 3

(61, 60)

INT2

INT4

I

Quasi-interrupt with detection of rising edges

2 (59)

1 (58)

P1.2

P1.3

External interrupt with detection of rising and falling

edges.

TCLO0

TCLO1

CLO

I/O

Timer/counter 0 clock output

Timer/counter 1 clock output

Clock output

11 (4)

10 (3)

9 (2)

P2.0

P2.1

P2.2

P2.3

BUZ

8 (1)

2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at

the watch timer clock frequency of 32.768 kHz for

buzzer sound

TCL0

I/O

External clock input for timer/counter 0

External clock input for timer/counter 1

Quasi-interrupt inputs with falling edge detection

34 (27)

33 (26)

P3.0

P3.1

TCL1

KS0–KS3

51–48

(44–41)

55–52

P6.0–P6.3

KS4–KS7

P7.0–P7.3

(48–45)

NOTE: Parentheses indicate pin number for 64 QFP package.

1-7

PRODUCT OVERVIEW

KS57C5532/P5532

Table 1-1. KS57C5532/P5532Pin Descriptions (Concluded)

Pin Name

V_DD

Pin Type

Description

Number

Share Pin

–

Power supply

32 (25)

64 (57)

43 (36)

–

V_SS

Ground

–

I

Reset signal

–

X_IN,X_OUT

–

Crystal, ceramic, or R/C oscillator signal for main

system clock. (For external clock input, use X_INand

45, 44

(38, 37)

input X_IN's reverse phase to X_OUT

)

XT_IN,XT_OUT

–

Crystal oscillator signal for subsystem clock.

(For external clock input, use XT_INand input XT_IN's

46, 47

(39, 40)

–

reverse phase to XT_OUT

)

TEST

Chip test input pin.

30 (23)

Hold GND when the device is operating.

NOTE: Parentheses indicate pin number for 64 QFP package.

1-8

KS57C5532/P5532

PRODUCT OVERVIEW

Table 1-2. Overview of KS57C5532/P5532 Pin Data

Pin Names

P0.0–P0.3

Share Pins

I/O Type

Reset Value

Input

Circuit Type

, SO, SI, BTCO

I/O

I

D-4

A-1

P1.0–P1.3

INT0, INT1, INT2,

INT4

Input

P2.0–P2.3

TCLO0, TCLO1, CLO,

BUZ

I/O

Input

D-2

P3.0–P3.1

P3.2–P3.3

TCL0, TCL1

I/O

Input

D-4

D-2

E-2

–

P4.0–P4.3

P5.0–P5.3

I/O

D-4

P6.0–P6.3

P7.0–P7.3

KS0–KS3

KS4–KS7

Input

P8.0–P8.3

P9.0–P9.3

–

I/O

D-2

Input

P10.0–P10.3

P11.0–P11.3

P12.0–P12.3

P13.0–P13.2

DTMF

–

I/O

O

D-6

D-2

G-6

–

Input

High impedence

–

X_IN, X_OUT

–

XT_IN, XT_OUT

–

I

–

B

–

NC

–

V_DD, V_SS

1-9

PRODUCT OVERVIEW

KS57C5532/P5532

PIN CIRCUIT DIAGRAMS

VDD

Pull-Up

Resistor

P-Channel

In

N-Channel

Schmitt Trigger

Figure 1-3. Pin Circuit Type A

Figure 1-5. Pin Circuit Type B

VDD

Pull-Up

Resistor

P-Channel

Pull-Up

Data

P-Channel

In

Resistor

Enable

Out

N-Channel

Output

DIsable

Schmitt Trigger

Figure 1-4. Pin Circuit Type A-1

Figure 1-6. Pin Circuit Type C

1-10

KS57C5532/P5532

PRODUCT OVERVIEW

Data

VDD

Circuit

Type C

I/O

Output

DIsable

Pull-up

Enable

P-Channel

Data

Circuit

I/O

Type C

Output

DIsable

Pull-down

Enable

Figure 1-7. Pin Circuit Type D-2

Figure 1-9. Pin Circuit Type D-6

VDD

PNE

VDD

Pull-up

Enable

P-Channel

I/O

Pull-up

Enable

Data

Circuit

Type C

I/O

Output

Disable

Output

Disable

Schmitt Trigger

Figure 1-10. Pin Circuit Type E-2

Figure 1-8. Pin Circuit Type D-4

1-11

PRODUCT OVERVIEW

KS57C5532/P5532

-

DTMF Out

+

Disable

1-12

KS57C5532/P5532

ADDRESS SPACES

2

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

ROM maps for the KS57C5532 are mask programmable at the factory. In its standard configuration, the device's

32,768 ´ 8-bit program memory has three areas that are directly addressable by the program counter (PC):

— 16-byte area for vector addresses

— 16-byte general-purpose area

— 96-byte instruction reference area

— 32,640-byte general-purpose area

General-Purpose Program Memory

Two program memory areas are allocated for general-purpose use: One area is 16 bytes in size and the other is

32,640 bytes.

Vector Addresses

A 16-byte vector address area is used to store the vector addresses required to execute

interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the enable

memory bank (EMB) and enable register bank (ERB) flags that are used to initialize the corresponding service

routines. The 16-byte area can be used alternately as general-purpose ROM.

REF Instructions

Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF

instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte

instructions, and 3-byte instructions which are stored in the look-up table. Unused look-up table addresses can be

used as general-purpose ROM.

Table 2-1. Program Memory Address Ranges

ROM Area Function

Vector address area

Address Ranges

0000H–000FH

0010H–001FH

0020H–007FH

0080H–7FFFH

Area Size (in Bytes)

16

General-purpose program memory

REF instruction look-up table area

General-purpose program memory

96

32,640

2-1

ADDRESS SPACES

KS57C5532/P5532

GENERAL-PURPOSE MEMORY AREAS

The 16-byte area at ROM locations 0010H–001FH and the 32,640-byte area at ROM locations 0080H–7FFFH are

used as general-purpose program memory. Unused locations in the vector address area and REF instruction

look-up table areas can be used as general-purpose program memory. However, care must be taken not to

overwrite live data when writing programs that use special-purpose areas of the ROM.

VECTOR ADDRESS AREA

The 16-byte vector address area of the ROM is used to store the vector addresses for executing

interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable

memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines.

16-byte vector addresses are organized as follows:

EMB

PC7

ERB

PC6

PC13

PC5

PC12

PC4

PC11

PC3

PC10

PC2

PC9

PC1

PC8

PC0

To set up the vector address area for specific programs, use the insturction VENTn. The programming tips on

the next page explain how to do this.

0000H

7

6

5

4

3

2

1

0

Vector Address Area

(16 Bytes)

0000H

0002H

0004H

0006H

0008H

000AH

000CH

000EH

RESET

INTB/INT4

INT0

000FH

0010H

General- Purpose Area

(16 Bytes)

001FH

0020H

INT1

Instruction Reference Area

(96 Bytes)

007FH

0080H

INTS

INTT0

INTT1

General-Purpose Area

(32,640 Bytes)

Not implemented

(Reseved for future use)

7FFFH

Figure 2-1. ROM Address Structure

Figure 2-2. Vector Address Map

2-2

KS57C5532/P5532

ADDRESS SPACES

+

PROGRAMMING TIP — Defining Vectored Interrupts

The following examples show you several ways you can define the vectored interrupt and instruction reference

areas in program memory:

1. When all vector interrupts are used:

ORG

0000H

;

VENT0

VENT1

VENT2

VENT3

VENT4

VENT5

VENT6

1,0,RESET

0,0,INTB

0,0,INT0

0,0,INT1

0,0,INTS

0,0,INTT0

0,0,INTT1

;

EMB ¬ 1, ERB ¬ 0; Jump to RESET address by RESET

EMB ¬ 0, ERB ¬ 0; Jump to INTB address INTB

EMB ¬ 0, ERB ¬ 0; Jump to INT0 address INT0

EMB ¬ 0, ERB ¬ 0; Jump to INT1 address INT1

EMB ¬ 0, ERB ¬ 0; Jump to INTS address INTS

EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address INTT0

EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address INTT1

2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt

locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations:

ORG

0000H

;

VENT0

VENT1

1,0,RESET

0,0,INTB

;

EMB ¬ 1, ERB ¬ 0; Jump to RESET address by RESET

EMB ¬ 0, ERB ¬ 0; Jump to INTB address by INTB

;

ORG

0006H

;

INT0 interrupt not used

VENT3

VENT4

0,0,INT1

0,0,INTS

;

EMB ¬ 0, ERB ¬ 0; Jump to INT1 address by INT1

EMB ¬ 0, ERB ¬ 0; Jump to INTS address by INTS

;

ORG

00C0H

;

INTT0 interrupt not used

VENT6

ORG

0,0,INTT1

0010H

EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address by INTT1

2-3

ADDRESS SPACES

KS57C5532/P5532

+

PROGRAMMING TIP — Defining Vectored Interrupts (Continued)

3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is

not written by a ORG instruction in Example 2, a CPU malfunction will occur:

ORG

0000H

;

VENT0

VENT1

VENT3

VENT4

VENT5

VENT6

1,0,RESET

0,0,INTB

0,0,INT1

0,0,INTS

0,0,INTT0

0,0,INTT1

;

EMB ¬ 1, ERB ¬ 0; Jump to RESET address by RESET

EMB ¬ 0, ERB ¬ 0; Jump to INTB address by INTB

EMB ¬ 0, ERB ¬ 0; Jump to INT1 address INT1

EMB ¬ 0, ERB ¬ 0; Jump to INTS address INTS

EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address INTT0

EMB ¬ 0, ERB ¬ 0; Jump to INTT1 address INTT1

;

ORG

0010H

General-purpose ROM area

In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS,

but VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a

CPU malfunction to occur.

2-4

KS57C5532/P5532

ADDRESS SPACES

INSTRUCTION REFERENCE AREA

Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in ad-

dresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or

look-up table. Locations in the REF look-up table may contain two 1-byte instructions, one 2-byte instruction, or

one 3-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are referencing

must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area

in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL. In summary, there are three ways to the

REF instruction:

By using REF instructions you can execute instructions larger than one byte. In summary, there are three ways

you can use the REF instruction:

— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions,

— Branching to any location by referencing a branch instruction stored in the look-up table,

— Calling subroutines at any location by referencing a call instruction stored in the look-up table.

+

PROGRAMMING TIP — Using the REF Look-up Table

Here is one example of how to use the REF instruction look-up table:

ORG

0020H

;

JMAIN

KEYCK

WATCH

INCHL

TJP

MAIN

KEYFG

CLOCK

@HL,A

HL

;

0, MAIN

1, KEYFG check

2, call CLOCK

BTSF

TCALL

LD

3, (HL) ¬

A

INCS

•

ABC

LD

ORG

EA,#00H

0080

;

47, EA ¬ #00H

;

MAIN

NOP

•

REF

KEYCK

JMAIN

WATCH

INCHL

;

BTSF KEYFG (1-byte instruction)

KEYFG = 1, jump to MAIN (1-byte instruction)

KEYFG = 0, call CLOCK (1-byte instruction)

LD @HL,A

INCS HL

LD EA,#00H (1-byte instruction)

REF

ABC

•

2-5

ADDRESS SPACES

KS57C5532/P5532

DATA MEMORY (RAM)

OVERVIEW

In its standard configuration, the 1024 ´ 4-bit data memory has four areas:

— 32 ´ 4-bit working register area

— 224 ´ 4-bit general-purpose area (also used as stack area)

— 3 ´ 256 ´ 4-bit general-purpose area

— 128 ´ 4-bit area for peripheral hardware

To make it easier to reference, the data memory area has three memory banks — bank 0, bank 1, bank 2, bank

3, and bank 15. The select memory bank instruction (SMB) is used to select the bank you want to select as

working data memory. Data stored in RAM locations are 1-, 4-, and 8-bit addressable.

Initialization values for the data memory area are not defined by hardware and must therefore be initialized by

program software following

. However, when

signal is generated in power-down mode, the most

of data memory contents are held.

000H

Working Registers

(32 x 4 Bits)

01FH

020H

Bank 0

General-purpose

Registers and

Stack Area

(224 x 4 Bits)

0FFH

100H

General-purpose

Registers

Bank 1

Bank 2

Bank 3

(256 x 4 Bits)

1FFH

200H

General-purpose

Registers

(256 x 4 Bits)

2FFH

300H

General-purpose

Registers

(256 x 4 Bits)

3FFH

F80H

Periphral

Hardware

Registers

Bank 15

FFFH

Figure 2-3. Data Memory (RAM) Map

2-6

KS57C5532/P5532

ADDRESS SPACES

Memory Banks 0, 1, 2, 3, and 15

Bank 0

(000H–0FFH)

The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers;

the next 224 nibbles (020H–0FFH) can be used both as stack area and as

general-purpose data memory. Use the stack area for implementing subroutine

calls and returns, and for interrupt processing.

(100H–1FFH)

(200H–2FFH)

(300H–3FFH)

(F80H–FFFH)

Bank 1

Bank 2

The 256 nibbles of bank 1 (100H–1FFH) are for general-purpose use.

The 256 nibbles of bank 1 (200H–2FFH) are for general-purpose use.

The 256 nibbles of bank 1 (300H–3FFH) are for general-purpose use.

Bank 3

Bank 15

The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed

RAM locations for each peripheral hardware register: the port latches, timers,

peripherals controls, etc. are mapped into this area.

Data Memory Addressing Modes

The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, 2, 3, or 15.

When the EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether

direct or indirect addressing is used. With direct addressing, you can access locations 000H–07FH of bank 0 and

bank 15. With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic

one, all five data memory banks can be accessed according to the current SMB value.

For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to

address RAM locations, remember to use the even-numbered register address as the instruction operand.

Working Registers

The RAM working register area in data memory bank 0 is further divided into four register banks

(bank 0, 1, 2, and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable.

Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag

bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for

indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable

to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.

2-7

ADDRESS SPACES

KS57C5532/P5532

Table 2-2. Data Memory Organization and Addressing

Addresses

000H–01FH

020H–0FFH

100H–1FFH

200H–2FFH

300H–3FFH

F80H–FFFH

Register Areas

Working registers

Bank

EMB Value

SMB Value

0

0, 1

0

Stack and general-purpose registers

General-purpose registers

1

2

1

2

General-purpose registers

3

1

3

Peripheral hardware registers

15

0, 1

15

+

PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1

Clear banks 0 and 1 of the data memory area:

RAMCLR

RMCL1

;

SMB

LD

INCS

JR

1

;

RAM (100H–1FFH) clear

RAM (010H–0FFH) clear

HL,#00H

A,#0H

@HL,A

HL

RMCL1

SMB

LD

INCS

JR

0

HL,#10H

@HL,A

HL

RMCL0

2-8

KS57C5532/P5532

ADDRESS SPACES

WORKING REGISTERS

Working registers, mapped to RAM address 000H–01FH in data memory bank 0, are used to temporarily store

intermediate results during program execution, as well as pointer values used for indirect addressing. Unused

registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-

bit units or, using paired registers, as 8-bit units.

000H

001H

002H

A

E

L

003H

H

X

Working

Register

Bank 0

004H

005H

006H

007H

008H

W

Z

Data

Memory

Bank 0

Y

Register

Bank 1

A ...Y

00FH

010H

Register

Bank 2

017H

018H

Register

Bank 3

01FH

Figure 2-4. Working Register Map

2-9

ADDRESS SPACES

KS57C5532/P5532

Working Register Banks

For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2,

and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection

instruction (SRB n) and by setting the status of the register bank enable flag (ERB).

Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou-

tines. Following this convention helps to prevent possible data corruption during program execution due to con-

tention in register bank addressing.

Table 2-3. Working Register Organization and Addressing

ERB Setting

SRB Settings

Selected Register Bank

3

2

1

x

0

1

0

x

0

1

0

1

0

1

0

Always set to bank 0

Bank 0

0

Bank 1

Bank 2

Bank 3

NOTE: 'x' means don't care.

Paired Working Registers

Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E

and A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data

manipulation.

The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z

always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit

registers or four 8-bit double registers in each of the four working register banks.

(MSB)

(LSB)

(MSB)

(LSB)

Y

W

H

E

Z

X

L

A

Figure 2-5. Register Pair Configuration

2-10

KS57C5532/P5532

ADDRESS SPACES

Special-Purpose Working Registers

Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also

be used as a 1-bit accumulator.

8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register

serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working

registers as program loop counters by letting you transfer a value to the L register and increment or decrement it

using a single instruction.

C

1-Bit Accumulator

4-Bit Accumulator

8-Bit Accumulator

A

EA

Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator

Recommendation for Multiple Interrupt Processing

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

2-11

ADDRESS SPACES

KS57C5532/P5532

+

PROGRAMMING TIP — Selecting the Working Register Area

The following examples show the correct programming method for selecting working register area:

1. When ERB = "0":

VENT2

;

1,0,INT0

;

EMB ¬ 1, ERB ¬ 0, Jump to INT0 address

INT0

PUSH

SRB

PUSH

SMB

LD

INCS

LD

POP

IRET

SB

2

HL

WX

YZ

EA

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

EA

YZ

WX

HL

SB

;

PUSH current SMB, SRB

Instruction does not execute because ERB = "0"

PUSH HL register contents to stack

PUSH WX register contents to stack

PUSH YZ register contents to stack

PUSH EA register contents to stack

;

POP EA register contents from stack

POP YZ register contents from stack

POP WX register contents from stack

POP HL register contents from stack

POP current SMB, SRB

The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an

interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB

and SRB values, as shown in Example 2 below.

2. When ERB = "1":

VENT2

;

1,1,INT0

;

EMB ¬ 1, ERB ¬ 1, Jump to INT0 address

INT0

PUSH

SRB

SMB

LD

INCS

LD

POP

IRET

SB

2

0

EA,#00H

80H,EA

HL,#40H

HL

WX,EA

YZ,EA

SB

;

Store current SMB, SRB

Select register bank 2 because of ERB = "1"

;

Restore SMB, SRB

2-12

KS57C5532/P5532

ADDRESS SPACES

STACK OPERATIONS

STACK POINTER (SP)

The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data

memory set aside for temporary storage of stack addresses. The SP can be read or written by 8-bit control

instructions. When addressing the SP, bit 0 must always remain cleared to logic zero.

F80H

F81H

SP3

SP7

SP2

SP6

SP1

SP5

"0"

SP4

There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack

(pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the

last data to be written to the stack.

The program counter contents and program status word are stored in the stack area prior to the execution of a

CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out)

type. The stack area is located in general-purpose data memory bank 0.

During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has

completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed.

The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the en-

able memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register areas

can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s).

Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack

pointer by program code to location 00H. This sets the first register of the stack area to 0FFH.

NOTE

A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or

interrupt routines are used continuously, the stack area should be set in accordance with the maximum

number of subroutine levels. To do this, estimate the number of nibbles that will be used for the

subroutines or interrupts and set the stack area correspondingly.

+

PROGRAMMING TIP — Initializing the Stack Pointer

To initialize the stack pointer (SP):

1. When EMB = "1":

SMB

LD

15

EA,#00H

SP,EA

;

Select memory bank 15

Bit 0 of accumulator A is always cleared to "0"

Stack area initial address (0FFH) ¬ (SP) – 1

2. When EMB = "0":

LD

EA,#00H

SP,EA

;

Memory addressing area (00H–7FH, F80H–FFFH)

2-13

ADDRESS SPACES

KS57C5532/P5532

PUSH OPERATIONS

Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the

stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number

determined by the type of push operation and then points to the next available stack location.

PUSH Instructions

A PUSH instruction references the SP to write two 4-bit data nibbles to the stack. Two 4-bit stack addresses are

referenced by the stack pointer: one for the upper register value and another for the lower register. After the

PUSH has executed, the SP is decremented by two and points to the next available stack location.

CALL Instructions

When a subroutine call is issued, the CALL instruction references the SP to write the PC's contents to six 4-bit

stack locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag

are also pushed to the stack. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up

to the number of levels permitted in the stack.

Interrupt Routines

An interrupt routine references the SP to push the contents of the PC and the program status word (PSW) to the

stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed, the SP is

decremented by six and points to the next available stack location. During an interrupt sequence, subroutines

may be nested up to the number of levels which are permitted in the stack area.

INTERRUPT

(When INT is acknowledged

SP SP - 6)

PUSH

(After PUSH, SP

CALL, LCALL

(After CALL or LCALL, SP

SP - 2)

SP - 6)

SP - 6

PC11 - PC8

PC14 - PC12

PC3 - PC0

PC7 - PC4

PC11 - PC8

PC13 - PC12

PC3 - PC0

PC7 - PC4

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP

0

SP - 5

SP - 4

SP - 3

SP - 2

SP - 1

SP

0

SP - 2

SP - 1

SP

Lower Register

Upper Register

0

EMB ERB

PSW

IS1

C

IS0 EMB ERB

PSW

SC2 SC1 SC0

0

Figure 2-7. Push-Type Stack Operations

2-14

KS57C5532/P5532

ADDRESS SPACES

POP OPERATIONS

For each push operation there is a corresponding pop operation to write data from the stack back to the source

register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET; for

interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined by

the type of operation and points to the next free stack location.

POP Instructions

A POP instruction references the SP to write data stored in two 4-bit stack locations back to the register pairs and

SB register. The value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register.

After the POP has executed, the SP is incremented by two and points to the next free stack location.

RET and SRET Instructions

The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP to

reference the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and the

ERB. After the RET or SRET has executed, the SP is incremented by six and points to the next free stack

location.

IRET Instructions

The end of an interrupt sequence is signaled by the instruction IRET. IRET references the SP to locate the six 4-

bit stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has

executed, the SP is incremented by six and points to the next free stack location.

POP

SP + 2)

RET or SRET

IRET

SP + 6)

(SP

SP + 6)

PC11 - PC8

PC14 - PC12

PC3 - PC0

(SP

SP

Lower Register

Upper Register

PC11 - PC8

PC13 - PC12

PC3 - PC0

PC7 - PC4

SP + 1

SP + 2

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

0

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

0

PC7 - PC4

0

EMB ERB

PSW

IS1

C

IS0 EMB ERB

PSW

SC2 SC1 SC0

0

Figure 2-8. Pop-Type Stack Operations

2-15

ADDRESS SPACES

KS57C5532/P5532

BIT SEQUENTIAL CARRIER (BSC)

The bit sequential carrier (BSC) is a 8-bit general register that can be manipulated using 1-, 4-, and 8-bit RAM

control instructions. clears all BSC bit values to logic zero.

Using the BSC, you can specify sequential addresses and bit locations using 1-bit indirect addressing

(memb.@L). (Bit addressing is independent of the current EMB value.) In this way, programs can process 16-bit

data by moving the bit location sequentially and then incrementing or decrementing the value of the L register.

BSC data can also be manipulated using direct addressing.

If the values of the L register are 0H at BSC2.@L, the address and bit location assignment is FC0H.0. If the L

register content is 8H at BSC2.@L, the address and bit location assignment is FC3H.3.

Table 2-4. BSC Register Organization

Name

BSC0

BSC1

BSC2

BSC3

Address

FC0H

Bit 3

Bit 2

Bit 1

Bit 0

BSC0.3

BSC1.3

BSC2.3

BSC3.3

BSC0.2

BSC1.2

BSC2.2

BSC3.2

BSC0.1

BSC1.1

BSC2.1

BSC3.1

BSC0.0

BSC1.0

BSC2.0

BSC3.0

FC1H

FC2H

FC3H

+

PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data

To use the bit sequential carrier (BSC) register to output 8-bit data (59H) to the P2.3 pin:

BITS

SMB

LD

SMB

LD

LDB

INCS

JR

EMB

15

EA,#37H

BSCO,EA

EA,#59H

BSC2,EA

0

L,#0H

C,BSC0.@L

P2.3,C

L

;

BSCO ¬ A, BSC1 ¬

BSC2 ¬ A, BSC3 ¬

E

;

AGN

P2.3 ¬

C

AGN

RET

2-16

KS57C5532/P5532

ADDRESS SPACES

PROGRAM COUNTER (PC)

A 15-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a

or an interrupt occurs, bits PC13 through PC0 are set to the vector address.

Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-

byte REF instruction which is used to reference instructions stored in the ROM.

PROGRAM STATUS WORD (PSW)

The program status word (PSW) is an 8-bit word that defines system status and program execution status and

which permits an interrupted process to resume operation after an interrupt request has been serviced. PSW

values are mapped as follows:

FB0H

FB1H

IS1

C

IS0

EMB

SC1

ERB

SC0

SC2

The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific

bit or bits being addressed. The PSW can be addressed during program execution regardless of the current value

of the enable memory bank (EMB) flag.

Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the in-

terrupt has been processed, the PSW values are popped from the stack back to the PSW address.

When a

is generated, the EMB and ERB values are set according to the

vector address, and the carry

flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all cleared to

logical zero.

Table 2-5. Program Status Word Bit Descriptions

PSW Bit Identifier

IS1, IS0

Description

Interrupt status flags

Enable memory bank flag

Enable register bank flag

Carry flag

Bit Addressing

Read/Write

R/W

1, 4

1

EMB

R/W

ERB

1

R/W

C

1

R/W

SC2, SC1, SC0

Program skip flags

8

R

2-17

ADDRESS SPACES

KS57C5532/P5532

INTERRUPT STATUS FLAGS (IS0, IS1)

PSW bits IS0 and IS1 contain the current interrupt execution status values. You can manipulate IS0 and IS1 flags

directly using 1-bit RAM control instructions

By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process

multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit

determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status

flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined

by the IPR.

When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically

incremented to the next status. Then, when the interrupt service routine ends with an IRET instruction, IS0 and

IS1 values are restored to the PSW. Table 2-6 shows the effects of IS0 and IS1 flag settings.

Table 2-6. Interrupt Status Flag Bit Settings

IS1

Value

IS0

Value

Status of Currently

Executing Process

Effect of IS0 and IS1 Settings

on Interrupt Request Control

0

1

0

1

All interrupt requests are serviced

Only high-priority interrupt as determined in the interrupt

priority register (IPR) is serviced

1

0

1

2

–

No more interrupt requests are serviced

Not applicable; these bit settings are undefined

Since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter-

rupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI in-

struction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI

instruction to re-enable interrupt processing.

+

PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing

The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:

INTB

DI

;

Disable interrupt

IS1 ¬ 0

Allow interrupts according to IPR priority level

Enable interrupt

BITR

BITS

EI

IS1

IS0

2-18

KS57C5532/P5532

EMB FLAG (EMB)

ADDRESS SPACES

The EMB flag is used to enable whether the memory bank selected by SMB register is to be valid or not. In this

way, it controls the addressing mode for data memory banks 0, 1, or 15.

When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H–07FH of

memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", the general-purpose

areas of bank 0, 1, and 15 can be accessed by using the appropriate SMB value.

+

PROGRAMMING TIP — Using the EMB Flag to Select Memory Banks

EMB flag settings for memory bank selection:

1. When EMB = "0":

SMB

LD

SMB

LD

SMB

LD

1

;

Non-essential instruction since EMB = "0"

A,#9H

90H,A

34H,A

0

90H,A

34H,A

15

;

(F90H) ¬ A, bank 15 is selected

(034H) ¬ A, bank 0 is selected

Non-essential instruction since EMB = "0"

(F90H) ¬ A, bank 15 is selected

(034H) ¬ A, bank 0 is selected

Non-essential instruction, since EMB = "0"

(020H) ¬ A, bank 0 is selected

(F90H) ¬ A, bank 15 is selected

20H,A

90H,A

LD

2. When EMB = "1":

SMB

LD

SMB

LD

SMB

LD

1

;

Select memory bank 1

A,#9H

90H,A

34H,A

0

90H,A

34H,A

15

;

(190H) ¬ A, bank 1 is selected

(134H) ¬ A, bank 1 is selected

Select memory bank 0

(090H) ¬ A, bank 0 is selected

(034H) ¬ A, bank 0 is selected

Select memory bank 15

20H,A

90H,A

Program error, but assembler does not detect it

(F90H) ¬ A, bank 15 is selected

LD

2-19

ADDRESS SPACES

ERB FLAG (ERB)

KS57C5532/P5532

The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the

ERB flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank

selection register (SRB). When the ERB flag is "0", register bank 0 is the selected working register area,

regardless of the current value of the register bank selection register (SRB).

When an internal

is generated, bit 6 of program memory address 0000H is written to the ERB flag. This

automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective address table in

program memory is written to the ERB flag, setting the correct flag status before the interrupt service routine is

executed.

During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW

bits. Afterwards, it is popped back to the FB0H.0 bit location in the PSW. The initial ERB flag settings for each

vectored interrupt are defined using VENTn instructions.

+

PROGRAMMING TIP — Using the ERB Flag to Select Register Banks

ERB flag settings for register bank selection:

1. When ERB = "0":

SRB

1

;

Register bank 0 is selected (since ERB = "0", the

SRB is configured to bank 0)

Bank 0 EA ¬ #34H

Bank 0 HL ¬ EA

Register bank 0 is selected

Bank 0 YZ ¬ EA

LD

SRB

LD

SRB

LD

EA,#34H

HL,EA

2

YZ,EA

3

Register bank 0 is selected

Bank 0 WX ¬ EA

WX,EA

2. When ERB = "1":

SRB

LD

SRB

LD

SRB

LD

1

;

Register bank 1 is selected

Bank 1 EA ¬ #34H

EA,#34H

HL,EA

2

YZ,EA

3

Bank 1 HL ¬ Bank 1 EA

Register bank 2 is selected

Bank 2 YZ ¬ BANK2 EA

Register bank 3 is selected

Bank 3 WX ¬ Bank 3 EA

WX,EA

2-20

KS57C5532/P5532

ADDRESS SPACES

SKIP CONDITION FLAGS (SC2, SC1, SC0)

The skip condition flags SC2, SC1, and SC0 indicate the current program skip conditions and are set and reset

automatically during program execution. Skip condition flags can only be addressed by 8-bit read instructions.

Direct manipulation of the SC2, SC1, and SC0 bits is not allowed.

CARRY FLAG (C)

The carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving

a carry (ADC, SBC). The carry flag can also be used as a 1-bit accumulator for performing Boolean operations

involving bit-addressed data memory.

If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry

flag is set to "1". Otherwise, its value is "0". When a

occurs, the current value of the carry flag is retained

during power-down mode, but when normal operating mode resumes, its value is undefined.

The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other

bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2–7, affect the carry

flag.

Table 2-7. Valid Carry Flag Manipulation Instructions

Operation Type

Instructions

Carry Flag Manipulation

Set carry flag to "1"

Direct manipulation

SCF

RCF

CCF

Clear carry flag to "0" (reset carry flag)

Invert carry flag value (complement carry flag)

Test carry and skip if C = "1"

BTST C

(1)

Bit transfer

Load carry flag value to the specified bit

LDB (operand) ,C

(1)

Load contents of the specified bit to carry flag

LDB C,(operand)

(1)

Boolean manipulation

AND the specified bit with contents of carry flag and save

the result to the carry flag

BAND C,(operand)

(1)

OR the specified bit with contents of carry flag and save

the result to the carry flag

BOR C,(operand)

(1)

XOR the specified bit with contents of carry flag and save

the result to the carry flag

BXOR C,(operand)

(2)

Interrupt routine

Save carry flag to stack with other PSW bits

INTn

Return from interrupt

IRET

Restore carry flag from stack with other PSW bits

NOTES:

1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b.

2. 'INTn' refers to the specific interrupt being executed and is not an instruction.

2-21

ADDRESS SPACES

KS57C5532/P5532

+

PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator

1. Set the carry flag to logic one:

SCF

LD

ADC

;

C ¬ 1

EA ¬ #0C3H

HL ¬ #0AAH

EA ¬ #0C3H + #0AAH + #1H, C ¬

EA,#0C3H

HL,#0AAH

EA,HL

1

2. Logical-AND bit 3 of address 3FH with P3.3 and output the result to P5.0:

LD

H,#3H

;

Set the upper four bits of the address to the H register

value

;

LDB

BAND

LDB

C,@H+0FH.3

C,P3.3

P5.0,C

;

C ¬ bit 3 of 3FH

C ¬ C AND P3.3

Output result from carry flag to P5.0

2-22

KS57C5532/P5532

ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

The enable memory bank flag, EMB, controls the two addressing modes for data memory. When the EMB flag is

set to logic one, you can address the entire RAM area; when the EMB flag is cleared to logic zero, the

addressable area in the RAM is restricted to specific locations.

The EMB flag works in connection with the select memory bank instruction, SMBn. You will recall that the SMBn

instruction is used to select RAM bank 0, 1, 2, 3, or 15. The SMB setting is always contained in the upper four bits

of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply specifically to

the memory bank indicated by the SMB instruction, and any restrictions to the addressable area within banks 0, 1,

2, 3, or 15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. Several RAM locations are

addressable at all times, regardless of the current EMB flag setting.

Here are a few guidelines to keep in mind regarding data memory addressing:

— When you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped

hardware component can be used as the operand in place of the actual address location.

— Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing.

— With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the

instruction specifies a register which contains the operand's address.

3-1

ADDRESSING MODES

KS57C5532/P5532

Addressing

Mode

DA

DA.b

@HL

@H+DA.b

@WX

@WL

mema.b memb.@L

RAM

Areas

EMB = 0 EMB = 1 EMB = 0 EMB = 1

X

000H

Working

Registers

01FH

020H

07FH

080H

SMB = 0

Bank 0

(General

Registers

and Stack)

0FFH

100H

Bank 1

(General

Registers)

SMB = 1

SMB = 2

SMB = 3

SMB = 1

SMB = 2

SMB = 3

1FFH

200H

Bank 2

( General

Registers)

2FFH

300H

Bank 3

(General

Registers)

3FFH

F80H

FB0H

FBFH

FC0H

Bank 15

(Peripheral

Hardware

Registers)

SMB = 15

FF0H

FFFH

NOTES:

1. 'X' means don't care.

2. Blank columns indicate RAM areas that are not addressable, given the addressing method and

enable memory bank (EMB) flag setting shown in the column headers.

Figure 3-1. RAM Address Structure

3-2

KS57C5532/P5532

ADDRESSING MODES

EMB AND ERB INITIALIZATION VALUES

The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt

vector address. When a RESET is generated internally, bit 7 of program memory address 0000H is written to the

EMB flag, initializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector

address table is written to the EMB. This automatically sets the EMB flag status for the interrupt service routine.

When the interrupt is serviced, the EMB value is automatically saved to stack and then restored when the

interrupt routine has completed.

At the beginning of a program, the initial EMB and ERB flag values for each vectored interrupt must be set by

using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR)

despite the current SMB setting.

+

PROGRAMMING TIP — Initializing the EMB and ERB Flags

The following assembly instructions show how to initialize the EMB and ERB flag settings:

ORG

0000H

; ROM address assignment

VENT0 1,0,RESET

VENT1 0,1,INTB

VENT2 0,1,INT0

VENT3 0,1,INT1

VENT4 0,1,INTS

VENT5 0,1,INTT0

VENT6 0,1,INTT1

; EMB ¬ 1, ERB ¬ 0, branch RESET

; EMB ¬ 0, ERB ¬ 1, branch INTB

; EMB ¬ 0, ERB ¬ 1, branch INT0

; EMB ¬ 0, ERB ¬ 1, branch INT1

; EMB ¬ 0, ERB ¬ 1, branch INTS

; EMB ¬ 0, ERB ¬ 1, branch INTT0

; EMB ¬ 0, ERB ¬ 1, branch INTT1

•

RESET BITR

EMB

3-3

ADDRESSING MODES

KS57C5532/P5532

ENABLE MEMORY BANK SETTINGS

EMB = "1"

When the enable memory bank flag EMB is set to logic one, you can address the data memory bank specified by

the select memory bank (SMB) value (0, 1, 2, 3, or 15) using 1-, 4-, or 8-bit instructions. You can use both direct

and indirect addressing modes. The addressable RAM areas when EMB = "1" are as follows:

— If SMB = 0,

— If SMB = 1,

— If SMB = 2,

000H–0FFH

100H–1FFH

200H–2FFH

— If SMB = 3, 300H–3FFH

— If SMB = 15,

F80H–FFFH

EMB = "0"

When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of the

SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is used.

If EMB = "0", the addressable area is restricted to locations 000H–07FH in bank 0 and to locations F80H–FFFH in

bank 15 for direct addressing. For indirect addressing, only locations 000H–0FFH in bank 0 are addressable,

regardless of SMB value.

To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to

"1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of ROM

address 0000H.

EMB-Independent Addressing

At any time, several areas of the data memory can be addressed independently of the current status of the EMB

flag. These exceptions are described in Table 3-1.

Table 3-1. RAM Addressing not Affected by the EMB Value

Address

Addressing Method

Affected Hardware

Program Examples

000H–0FFH

4-bit indirect addressing using WX Not applicable

and WL register pairs;

LD

A,@WX

8-bit indirect addressing using SP

PUSH

POP

FB0H–FBFH

FF0H–FFFH

1-bit direct addressing

PSW,

IEx, IRQx, I/O

BITS EMB

BITR

IE4

FC0H–FFFH

1-bit indirect addressing using the

L register

I/O

BAND C,P3.@L

3-4

KS57C5532/P5532

ADDRESSING MODES

SELECT BANK REGISTER (SB)

The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists

of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in

Figure 3-2.

During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB

instruction. You later restore the value to the SB using the POP SB instruction.

SMB (F83H)

SMB 2 SMB 1

SRB (F82H)

SRB 1

SB

Register

SMB 3

SMB 0

0

SRB 0

Figure 3-2. SMB and SRB Values in the SB Register

Select Register Bank (SRB) Instruction

The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The

SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, 3.

One of the four register banks is selected by the combination of ERB flag status and the SRB value that is set

using the 'SRB n' instruction. The current SRB value is retained until another register is requested by program

software. PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts

and subroutine calls. RESET clears the 4-bit SRB value to logic zero.

Select Memory Bank (SMB) Instruction

To select one of the four available data memory banks, you must execute an SMB n instruction specifying the

number of the memory bank you want (0, 1, 2, 3, or 15). For example, the instruction 'SMB 1' selects bank 1 and

'SMB 15' selects bank 15. (And remember to enable the selected memory bank by making the appropriate EMB

flag setting.

The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not

specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB

value to logic zero.

The PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack

area during interrupts and subroutine calls.

3-5

ADDRESSING MODES

KS57C5532/P5532

DIRECT AND INDIRECT ADDRESSING

1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or

bit address as the instruction operand.

Indirect addressing specifies a memory location that contains the required direct address. The KS57 instruction

set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an even-numbered RAM

address must always be used as the instruction operand.

1-BIT ADDRESSING

Table 3-2. 1-Bit Direct and Indirect RAM Addressing

Operand

Notation

Addressing Mode

Description

EMB Flag Addressable

Memory

Bank

Hardware I/O

Mapping

Setting

Area

DA.b

Direct: bit is indicated by the

0

000H–07FH

F80H–FFFH

Bank 0

–

Bank 15

RAM address (DA), memory

bank selection, and specified

bit number (b).

All 1-bit

addressable

peripherals

(SMB = 15)

1

x

000H–FFFH

SMB = 0, 1, 2, 3,

15

mema.b

Bank 15

Direct: bit is indicated by

addressable area (mema)

and bit number (b).

FB0H–FBFH

FF0H–FFFH

IS0, IS1, EMB,

ERB, IEx,

IRQx, Pn.n

memb.@L Indirect: lower two bits of

register L is indicated by the

upper 10 bits of RAM area

(memb) and the upper two

bits of register L.

x

FC0H–FFFH

Bank 15

BSCn.x

Pn.n

@H + DA.b Indirect: bit is indicated by the

lower four bits of the address

0

1

000H–0FFH

000H–FFFH

Bank 0

All 1-bit

addressable

peripherals

(SMB = 15)

(DA), memory bank selection,

and the H register identifier.

SMB = 0, 1, 2, 3,

15

NOTE: x = not applicable.

3-6

KS57C5532/P5532

ADDRESSING MODES

+

PROGRAMMING TIP — 1-Bit Addressing Modes

1-Bit Direct Addressing

1. If EMB = "0":

AFLAG

BFLAG

CFLAG

EQU

SMB

BITS

BTST

BITS

34H.3

85H.3

0BAH.0

0

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

;

34H.3 ¬

F85H.3 (BMOD.3) ¬

If FBAH.0 (IRQW) = 1, skip

Else if, FBAH.0 (IRQW) = 0, F85H.3 (BMOD.3) ¬

FF3H.0 (P3.0) ¬

1

2. If EMB = "1":

AFLAG

BFLAG

CFLAG

EQU

34H.3

85H.3

0BAH.0

0

AFLAG

BFLAG

CFLAG

BFLAG

P3.0

EQU

SMB

BITS

BTST

BITS

;

34H.3 ¬

85H.3 ¬

If 0BAH.0 = 1, skip

Else if 0BAH.0 = 0, 085H.3 ¬

FF3H.0 (P3.0) ¬

1

1-Bit Indirect Addressing

1. If EMB = "0":

AFLAG

BFLAG

CFLAG

EQU

SMB

LD

34H.3

85H.3

0BAH.0

0

H,#0BH

@H+CFLAG

CFLAG

;

H ¬ #0BH

If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

Else if 0BAH.0 = 0, FBAH.0 (IRQW) ¬

BTSTZ

BITS

1

2. If EMB = "1":

AFLAG

BFLAG

CFLAG

EQU

34H.3

85H.3

EQU

SMB

LD

BTSTZ

BITS

0BAH.0

0

H,#0BH

@H+CFLAG

CFLAG

;

H ¬ #0BH

If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip

Else if 0BAH.0 = 0, 0BAH.0 ¬

1

3-7

ADDRESSING MODES

4-BIT ADDRESSING

KS57C5532/P5532

Table 3-3. 4-Bit Direct and Indirect RAM Addressing

Addressing Mode EMB Flag Addressable Memory

Operand

Notation

Hardware I/O

Mapping

Description

Setting

Area

Bank

Bank 0

Bank 15

DA

Direct: 4-bit address indicated

0

000H–07FH

F80H–FFFH

–

by the RAM address (DA) and

the memory bank selection

All 4-bit

addressable

peripherals

1

0

000H–FFFH

000H–0FFH

(SMB = 15)

SMB = 0, 1, 2, 3,

15

@HL

Bank 0

–

Indirect: 4-bit address

indicated by the memory bank

selection and register HL

1

000H–FFFH

SMB = 0, 1, 2, 3,

15

All 4-bit

addressable

peripherals

(SMB = 15)

@WX

@WL

Indirect: 4-bit address

indicated by register WX

x

000H–0FFH

Bank 0

–

Indirect: 4-bit address

indicated by register WL

NOTE: x = not applicable.

PROGRAMMING TIP — 4-Bit Addressing Modes

+

4-Bit Direct Addressing

1. If EMB = "0":

ADATA

BDATA

EQU

SMB

LD

SMB

LD

46H

8EH

15

A,P3

0

;

Non-essential instruction, since EMB = "0"

A ¬ (P3)

Non-essential instruction, since EMB = "0"

ADATA,A

BDATA,A

(046H) ¬

(F8EH) ¬

A

LD

2. If EMB = "1":

ADATA

BDATA

EQU

46H

8EH

15

A,P3

0

EQU

SMB

LD

SMB

LD

;

A ¬ (P3)

ADATA,A

BDATA,A

;

(046H) ¬

(08EH) ¬

A

LD

3-8

KS57C5532/P5532

ADDRESSING MODES

+

PROGRAMMING TIP — 4-Bit Addressing Modes (Continued)

4-Bit Indirect Addressing (Example 1)

1. If EMB = "0", compare bank 0 locations 040H–046H with bank 0 locations 060H–066H:

ADATA

BDATA

EQU

SMB

LD

CPSE

SRET

DECS

JR

46H

66H

1

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

;

Non-essential instruction, since EMB = "0"

COMP

;

A ¬ bank 0 (040H–046H)

If bank 0 (060H–066H) = A, skip

L

COMP

RET

2. If EMB = "1", compare bank 0 locations 040H–046H to bank 1 locations 160H–166H:

ADATA

BDATA

EQU

SMB

LD

CPSE

SRET

DECS

JR

46H

66H

1

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

COMP

;

A ¬ bank 0 (040H–046H)

If bank 1 (160H–166H) = A, skip

L

COMP

RET

3-9

ADDRESSING MODES

KS57C5532/P5532

+

PROGRAMMING TIP — 4-Bit Addressing Modes (Concluded)

4-Bit Indirect Addressing (Example 2)

1. If EMB = "0", exchange bank 0 locations 040H–046H with bank 0 locations 060H–066H:

ADATA

BDATA

EQU

SMB

LD

46H

66H

1

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

TRANS

;

Non-essential instruction, since EMB = "0"

TRANS

;

A ¬ bank 0 (040H–046MH)

Bank 0 (060H–066H) ¬ A

XCHD

JR

2. If EMB = "1", exchange bank 0 locations 040H–046H to bank 1 locations 160H–166H:

ADATA

BDATA

EQU

SMB

LD

46H

66H

1

HL,#BDATA

WX,#ADATA

A,@WL

A,@HL

TRANS

;

A ¬ bank 0 (040H–046H)

Bank 1 (160H–166H) ¬

XCHD

JR

A

3-10

KS57C5532/P5532

ADDRESSING MODES

8-BIT ADDRESSING

Table 3-4. 8-Bit Direct and Indirect RAM Addressing

Addressing Mode EMB Flag Addressable Memory

Instruction

Notation

Hardware I/O

Mapping

Description

Setting

Area

Bank

Bank 0

Bank 15

DA

Direct: 8-bit address indicated

0

000H–07FH

F80H–FFFH

–

by the RAM address (DA =

even number) and memory

bank selection

All 8-bit

addressable

peripherals

1

0

000H–FFFH SMB = 0, 1, 2, 3, 15 (SMB = 15)

@HL

Indirect: the 8-bit address

indicated by the memory bank

selection and register HL; (the

4-bit L register value must be

an even number)

000H–0FFH

Bank 0

–

1

000H–FFFH SMB = 0, 1, 2, 3, 15

All 8-bit

addressable

peripherals

(SMB = 15)

3-11

ADDRESSING MODES

KS57C5532/P5532

+

PROGRAMMING TIP — 8-Bit Addressing Modes

8-Bit Direct Addressing

1. If EMB = "0":

ADATA

BDATA

EQU

SMB

LD

SMB

LD

46H

8EH

15

EA,P4

0

;

Non-essential instruction, since EMB = "0"

E ¬ (P5), A ¬ (P4)

ADATA,EA

BDATA,EA

;

(046H) ¬ A, (047H) ¬

(F8EH) ¬ A, (F8FH) ¬

E

LD

2. If EMB = "1":

ADATA

BDATA

EQU

46H

8EH

15

EA,P4

0

EQU

SMB

LD

;

E ¬ (P5), A ¬ (P4)

SMB

LD

ADATA,EA

BDATA,EA

;

(046H) ¬ A, (047H) ¬

(08EH) ¬ A, (08FH) ¬

E

8-Bit Indirect Addressing

1. If EMB = "0":

ADATA

EQU

SMB

LD

46H

1

HL,#ADATA

;

Non-essential instruction, since EMB = "0"

LD

EA,@HL

A ¬ (046H), E ¬ (047H)

2. If EMB = "1":

ADATA

EQU

46H

SMB

LD

1

HL,#ADATA

EA,@HL

;

A ¬ (146H), E ¬ (147H)

3-12

KS57C5532/P5532

MEMORY MAP

4

MEMORY MAP

OVERVIEW

To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank

15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the

specific memory location.

Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank

flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the

current SMB value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of

the current EMB value.

I/O MAP FOR HARDWARE REGISTERS

Table 4-1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations

F80H–FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map

gives you the following information:

— Register address

— Register name (mnemonic for program addressing)

— Bit values (both addressable and non-manipulable)

— Read-only, write-only, or read and write addressability

— 1-bit, 4-bit, or 8-bit data manipulation characteristics

4-1

MEMORY MAP

KS57C5532/P5532

Table 4-1. I/O Map for Memory Bank 15

Memory Bank 15

Addressing Mode

Address

F80H

Register

Bit 3

.3

Bit 2

.2

Bit 1

.1

Bit 0

"0"

R/W

1-Bit

4-Bit

8-Bit

SP

R/W

No

Yes

F81H

.7

.6

.5

.4

F82H–F84H are not mapped.

F85H

F86H

F87H

F88H

F89H

BMOD

BCNT

.3

.2

.1

.0

W

R

.3

Yes

No

Yes

.3⁽¹⁾

WMOD

TMOD0

.3

.7

.2

.1

.5

.0

.4

W

No

Yes

"0"

F8AH–F8FH are not mapped.

F90H

F91H

F92H

F93H

F94H

F95H

F96H

F97H

F98H

F99H

F9AH

FA0H

FA1H

.3

"0"

.2

"0"

.5

"0"

.4

.3

.6

TOE1

"0"

TOE0

TOL1

BOE

TOL0

"0"

R/W

R

Yes

No

Yes

No

TCNT0

TREF0

R

Yes

W

No

Yes

WDMOD

.3

.7

.2

.6

.1

.5

.0

.4

WDFLAG ⁽²⁾

TMOD1

WDTCF

.3

“0”

.2

“0”

"0"

.5

“0”

"0"

.4

W

Yes

.3

Yes

No

Yes

"0"

.6

FA2H–FA3H are not mapped.

FA6H–FA7H are not mapped.

FAAH–FABH are not mapped.

FA4H

FA5H

TCNT1

TREF1

DTMR

R

W

No

Yes

FA8H

FA9H

FACH

FADH

“0”

.7

.2

.6

.1

.5

.0

.4

4-2

KS57C5532/P5532

MEMORY MAP

Table 4-1. I/O Map for Memory Bank 15 (Continued)

Memory Bank 15

Addressing Mode

Address

Register

Bit 3

Bit 2

Bit 1

Bit 0

R/W

1-Bit

4-Bit

8-Bit

FAEH–FAFH are not mapped.

FB0H

FB1H

FB2H

FB3H

FB4H

FB5H

FB6H

FB7H

FB8H

PSW

IS1

C ⁽³⁾

IME

.3

IS0

SC2

.2

EMB

SC1

.1

ERB

SC0

.0

R/W

R

Yes

No

Yes

No

Yes

IPR

W

IME

No

Yes

No

PCON

IMOD0

IMOD1

IMOD2

SCMOD

.2

.1

.0

W

.3

"0"

.1

.0

W

No

"0"

.3

"0"

.1

.0

W

"0"

.0

W

.2

"0"

IEB

.0

W

Yes

No

IE4

IRQ4

IRQB

R/W

Yes

FB9H is not mapped.

FBAH

FBBH

FBCH

FBDH

FBEH

FBFH

FC0H

FC1H

FC2H

FC3H

"0"

IE1

"0"

IEW

IET1

IET0

IES

IRQW

IRQT1

IRQT0

IRQS

IRQ0

R/W

Yes

No

"0"

IRQ1

"0"

IE0

IE2

IRQ2

BSC0

BSC1

BSC2

BSC3

R/W

Yes

FC4H – FCFH are not mapped.

"0" .1 .0

FD1H – FD9H are not mapped.

FD0H

CLMOD

PNE1

.3

W

No

Yes

No

FDAH

FDBH

FDCH

FDDH

FDEH

FDFH

FE0H

FE1H

PNE4.3 PNE4.2 PNE4.1 PNE4.0

PNE5.3 PNE5.2 PNE5.1 PNE5.0

Yes

PUMOD1

PUMOD2

SMOD

PUR3

PUR9

PUR13

"0"

PUR2

PUR8

PDR12

"0"

PUR1

PUR7

PUR11

PUR5

.1

PUR0

PUR6

PUR10

PUR4

.0

No

.3

.2

W

.3

No

.7

.6

.5

"0"

4-3

MEMORY MAP

KS57C5532/P5532

Table 4-1. I/O Map for Memory Bank 15 (Concluded)

Memory Bank 15

Addressing Mode

Address

FE2H

FE3H

FE4H

FE5H

FE6H

FE7H

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

FEEH

FEFH

FF0H

FF1H

FF2H

FF3H

FF4H

FF5H

FF6H

FF7H

FF8H

FF9H

FFAH

FFBH

FFCH

FFDH

FFEH

FFFH

Register

Bit 3

Bit 2

Bit 1

Bit 0

R/W

1-Bit

4-Bit

8-Bit

SBUF

R/W

No

Yes

PMG1

PMG2

PMG3

PMG4

PM0.3

PM7

PM0.2

"0"

PM0.1

PM5

PM0.0

PM4

W

No

Yes

No

PM2.3

PM3.3

PM6.3

PM8.3

PM2.2

PM3.2

PM6.2

PM8.2

PM2.1

PM3.1

PM6.1

PM8.1

PM2.0

PM3.0

PM6.0

PM8.0

PM12.3 PM12.2 PM12.1 PM12.0

PM13

.3

PM11

.2

PM10

.1

PM9

.0

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port 10

Port 11

Port 12

Port 13

R/W

R

Yes

.3

.2

.1

.0

.3

.2

.1

.0

R/W

No

.3

.2

.1

.0

.3

.2

.1

.0

Yes

No

.3/.7

.3

.2/.6

.2

.1/.5

.1

.0/.4

.0

.3/.7

.3

.2/.6

.2

.1/.5

.1

.0/.4

.0

.3

.2

.1

.0

.3

.2

.1

.0

Yes

No

.3/.7

.3

.2/.6

.2

.1/.5

.1

.0/.4

.0

.3

.2

.1

.0

NOTES:

1. Bit 3 in the WMOD register is read only.

2. F9AH.0 F9AH.2 are fixed to “0”

3. The carry flag can be read or written by specific bit manipulation instructions only.

4-4

KS57C5532/P5532

MEMORY MAP

REGISTER DESCRIPTIONS

In this section, register descriptions are presented in a consistent format to familiarize you with the memory-

mapped I/O locations in bank 15 of the RAM. Figure 4–1 describes features of the register description format.

Register descriptions are arranged in alphabetical order. Programmers can use this section as a quick-reference

source when writing application programs.

Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are

not included in these descriptions. More detailed information about how these registers are used is included in

Part II of this manual, "Hardware Descriptions," in the context of the corresponding peripheral hardware module

descriptions.

4-5

MEMORY MAP

KS57C5532/P5532

Name of individual

bit or related bits

Bit identifiers used

for bit addressing

Register location

in RAM bank 15

Register ID

Register name

CLMOD — Clock Output Mode Control Register

FD0H

2

3

1

0

Bit

Identifier

RESET

.3

.2

.1

.0

0

Value

W

Read/Write

Bit Addressing

4

Enable/Disable Clock Output Control Bit

.3

0

1

Disable clock output

Enable clock output

Bit 2

.2

0

Always logic zero

Clock Source and Frequency Selection Control Bits

.1 – .0

0

1

0

1

Select CPU clock source

Select system clock fxx/8 (524 kHz at 4.19 MHz)

0

1

Select system clock fxx/16 (262 kHz at 4.19 MHz)

Select system clock fxx/64 (65.5 kHz at 4.19 MHz)

1

=

R

W

Read-only

Write-only

Bit value immediately

following a

Bit number in

MSB to LSB order

RESET

=

R/W Read/write

=

'–' Not used

Type of addressing

that must be used to

address the bit (1-bit,

4-bit, or 8-bit)

Description of the

effect of specific bit

settings

Bit identifier used

for bit addressing

Figure 4-1. Register Description Format

4-6

KS57C5532/P5532

MEMORY MAP

BMOD— Basic Timer Mode Register

BT

F85H

Bit

3

.3

2

.2

0

1

.1

0

.0

0

Identifier

Value

0

Read/Write

W

1/4

W

4

W

4

W

4

Bit Addressing

BMOD.3

Basic Timer Restart Bit

Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero

1

BMOD.2 – .0

Input Clock Frequency and Interrupt Interval Time Control Bits

12

0

1

0

1

0

1

0

1

Input clock frequency:

Interrupt interval time:

fxx/2 (0.87 kHz)

2²⁰/fxx (292.9 ms)

fxx/2⁹(6.99 kHz)

2¹⁷/fxx (36.6 ms)

Input clock frequency:

Interrupt interval time:

fxx/2⁷(27.9 kHz)

2¹⁵/fxx (9.15 ms)

Input clock frequency:

Interrupt interval time:

fxx/2⁵(111.8 kHz)

2¹³/fxx (2.29 ms)

Input clock frequency:

Interrupt interval time:

NOTES:

1. Interrupt interval time is the time required to set the IRQB to “1” periodically.

2. When a

occurs, the oscillation stabilization time is 36.6 ms (2¹⁷/fxx) at 3.579545 MHz.

3. 'fxx' is the system clock rate given a clock frequency of 3.579545 MHz.

4-7

MEMORY MAP

KS57C5532/P5532

CLMOD — Clock Output Mode Register

CPU

FD0H

Bit

3

.3

0

2

"0"

0

1

.1

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

CLMOD.3

Enable/Disable Clock Output Control Bit

0

1

Disable clock output

Enable clock output

CLMOD.2

Bit 2

0

Always logic zero

CLMOD.1 – .0

Clock Source and Frequency Selection Control Bits

0

Select CPU clock source fx/4, fx/8, fx/64 or fxt/4 (0.89 MHz, 447 kHz, or 55.9

kHz)

0

1

0

1

Select system clock fxx/8 (447.4 kHz)

Select system clock fxx/16 (223.7 kHz)

Select system clock fxx/64 (55.9 kHz)

NOTE: 'fxx' is the system clock, given a clock frequency of 3.579545 MHz.

4-8

KS57C5532/P5532

MEMORY MAP

DTMR — DTMF Mode Register

DTMF

FACH, FADH

Bit

3

.7

0

2

.6

0

1

.5

0

.4

0

3

–

2

.2

0

1

0

Identifier

.1

0

.0

0

Value

0

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

DTMR.7 – .4

DTMR Bit Values for Keyboard Inputs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Function key D

1

2

3

4

5

6

7

8

9

0

*

#

1

0

1

0

1

Function key A

Function key B

Function key C

DTMR.3

Bit 3

–

Don't care

DTMR.2 – .1

Tone Selection Bits

0

1

0

1

0

1

Dual-tone enable

Dual-tone enable (alternate setting)

Single-column tone enable

Single-low tone enable

DTMR.0

DTMF Operation Enable/Disable Bit

0

1

Disable DTMF operation

Enable DTMF operation

4-9

MEMORY MAP

KS57C5532/P5532

IE0, 1, IRQ0, 1— INT0, 1 Interrupt Enable/Request Flags

CPU

FBEH

Bit

3

IE1

0

2

IRQ1

0

1

IE0

0

IRQ0

0

Identifier

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IE1

INT1 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT1 pin

Enable interrupt requests at the INT1 pin

IRQ1

IE0

INT1 Interrupt Request Flag

–

Generate INT1 interrupt (This bit is set and cleared automatically by hardware

when rising or falling edge detected at INT1 pin.)

INT0 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT0 pin

Enable interrupt requests at the INT0 pin

IRQ0

INT0 Interrupt Request Flag

–

Generate INT0 interrupt (This bit is set and cleared automatically by hardware

when rising or falling edge detected at INT0 pin.)

4-10

KS57C5532/P5532

MEMORY MAP

IE2, IRQ2— INT2 Interrupt Enable/Request Flags

CPU

FBFH

Bit

3

"0"

0

2

"0"

0

1

IE2

0

IRQ2

0

Identifier

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IE2

Bits 3–2

0

Always logic zero

INT2 Interrupt Enable Flag

0

1

Disable INT2 interrupt requests at the INT2 pin or KS0–KS7 pins

Enable INT2 interrupt requests at the INT2 pin or KS0–KS7 pins

IRQ2

INT2 Interrupt Request Flag

–

Generate INT2 quasi-interrupt (This bit is set and is not cleared automatically by

hardware when a rising edge is detected at INT2 or when a falling edge is detected

at one of the KS0–KS7 pins. Since INT2 is a quasi-interrupt, IRQ2 flag must be

cleared by software.)

4-11

MEMORY MAP

KS57C5532/P5532

IE4, IRQ4— INT4 Interrupt Enable/Request Flags

IEB, IRQB— INTB Interrupt Enable/Request Flags

CPU

FB8H

Bit

3

IE4

0

2

IRQ4

0

1

IEB

0

IRQB

0

Identifier

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

IE4

INT4 Interrupt Enable Flag

0

1

Disable interrupt requests at the INT4 pin

Enable interrupt requests at the INT4 pin

IRQ4

IEB

INT4 Interrupt Request Flag

–

Generate INT4 interrupt (This bit is set and cleared automatically by hardware

when rising and falling signal edge detected at INT4 pin.)

INTB Interrupt Enable Flag

0

1

Disable INTB interrupt requests

Enable INTB interrupt requests

IRQB

INTB Interrupt Request Flag

–

Generate INTB interrupt (This bit is set and cleared automatically by hardware

when reference interval signal received from basic timer.)

4-12

KS57C5532/P5532

MEMORY MAP

IES, IRQS— INTS Interrupt Enable/Request Flags

CPU

FBDH

Bit

3

"0"

0

2

"0"

0

1

IES

0

IRQS

0

Identifier

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IES

Bits 3–2

0

Always logic zero

INTS Interrupt Enable Flag

0

1

Disable INTS interrupt requests

Enable INTS interrupt requests

IRQS

INTS Interrupt Request Flag

–

Generate INTS interrupt (This bit is set and cleared automatically by hardware

when serial data transfer completion signal received from serial I/O interface.)

4-13

MEMORY MAP

KS57C5532/P5532

IET0, IRQT0— INTT0 Interrupt Enable/Request Flags

CPU

FBCH

Bit

3

"0"

0

2

"0"

0

1

0

IRQT0

0

Identifier

IET0

0

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IET0

Bits 3–2

0

Always logic zero

INTT0 Interrupt Enable Flag

0

1

Disable INTT0 interrupt requests

Enable INTT0 interrupt requests

IRQT0

INTT0 Interrupt Request Flag

–

Generate INTT0 interrupt (This bit is set and cleared automatically by hardware

when contents of TCNT0 and TREF0 registers match.)

4-14

KS57C5532/P5532

MEMORY MAP

IET1, IRQT1— INTT1 Interrupt Enable/Request Flags

CPU

FBBH

Bit

3

"0"

0

2

"0"

0

1

0

IRQT1

0

Identifier

IET1

0

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IET1

Bits 3–2

0

Always logic 0

INTT1 Interrupt Enable Flag

0

1

Disable INTT1 interrupt requests

Enable INTT1 interrupt requests

IRQT1

INTT1 Interrupt Request Flag

–

Generate INTT1 interrupt (This bit is set and cleared automatically by hardware

when contents of TCNT1 and TREF1 registers match.)

4-15

MEMORY MAP

KS57C5532/P5532

IEW, IRQW— INTW Interrupt Enable/Request Flags

CPU

FBAH

Bit

3

"0"

0

2

"0"

0

1

0

IRQW

0

Identifier

IEW

0

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

R/W

1/4

Bit Addressing

.3 – .2

IEW

Bits 3–2

0

Always logic zero

INTW Interrupt Enable Flag

0

1

Disable INTW interrupt requests

Enable INTW interrupt requests

IRQW

INTW Interrupt Request Flag

–

Generate INTW interrupt (This bit is set when the timer interval is set to 0.5

seconds or 3.91 milliseconds at the watch timer frequency of 32.768 kHz.)

NOTE: Since INTW is a quasi-interrupt, the IRQW flag must be cleared by software.

4-16

KS57C5532/P5532

MEMORY MAP

IMOD0— External Interrupt 0 (INT0) Mode Register

CPU

FB4H

Bit

3

.3

0

2

"0"

0

1

.1

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD0.3

Interrupt Sampling Clock Selection Bit

0

1

Select CPU clock as a sampling clock

Select sampling clock frequency of the selected system clock (fxx/64)

IMOD0.2

Bit 2

0

Always logic zero

IMOD0.1 – .0

External Interrupt Mode Control Bits

0

1

0

1

0

1

Interrupt requests are triggered by a rising signal edge

Interrupt requests are triggered by a falling signal edge

Interrupt requests are triggered by both rising and falling signal edges

Interrupt request flag (IRQx) cannot be set to logic one

4-17

MEMORY MAP

KS57C5532/P5532

IMOD1— External Interrupt 1 (INT1) Mode Register

CPU

FB5H

Bit

3

"0"

0

2

"0"

0

1

"0"

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD1.3 – .1

IMOD1.0

Bits 3–1

0

Always logic zero

External Interrupt 1 Edge Detection Control Bit

0

1

Rising edge detection

Falling edge detection

4-18

KS57C5532/P5532

MEMORY MAP

IMOD2— External Interrupt 2 (INT2) Mode Register

CPU

FB6H

Bit

3

"0"

0

2

"0"

0

1

.1

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

IMOD2.3 – .2

IMOD2.1 – .0

Bits 3–2

0

Always logic zero

External Interrupt 2 Edge Detection Selection Bit

0

1

0

1

0

1

Interrupt request at INT2 pin triggered by rising edge

Interrupt request at KS4–KS7 triggered by falling edge

Interrupt request at KS2–KS7 triggered by falling edge

Interrupt request at KS0–KS7 triggered by falling edge

4-19

MEMORY MAP

KS57C5532/P5532

IPR— Interrupt Priority Register

CPU FB2H

Bit

3

IME

0

2

.2

0

1

.1

0

Identifier

.0

0

Value

Read/Write

W

4

W

4

W

4

Bit Addressing

1/4

IME

Interrupt Master Enable Bit (MSB)

0

1

Disable all interrupt processing

Enable processing of all interrupt service requests

IPR.2 – .0

Interrupt Priority Assignment Bits

0

1

0

1

0

1

0

1

0

1

0

1

0

Normal interrupt processing according to default priority settings

Process INTB and INT4 interrupts at highest priority

Process INT0 interrupts at highest priority

Process INT1 interrupts at highest priority

Process INTS interrupts at highest priority

Process INTT0 interrupts at highest priority

Process INTT1 interrupts at highest priority

NOTE: During normal interrupt processing, interrupts are processed in the order in which they occur. If two or more

interrupts occur simultaneously, the processing order is determined by the default interrupt priority settings shown

below. Using the IPR settings, you can select specific interrupts for high-priority processing in the event of

contention. When the high-priority (IPR) interrupt has been processed, waiting interrupts are handled according to

their default priorities. The default priorities are as follows ('1' is highest priority; '6' is lowest priority):

INTB, INT4

INT0

INT1

INTS

INTT0

INTT1

1

2

3

4

5

6

4-20

KS57C5532/P5532

MEMORY MAP

PCON— Power Control Register

CPU

FB3H

Bit

3

.3

0

2

.2

0

1

.1

0

.0

0

Identifier

Value

Read/Write

W

4

W

4

W

4

W

4

Bit Addressing

PCON.3 – .2

PCON.1 – .0

CPU Operating Mode Control Bits

0

1

0

1

0

Enable normal CPU operating mode

Initiate idle power-down mode

Initiate stop power-down mode

CPU Clock Frequency Selection Bits

0

1

0

1

Select fxx/64

Select fxx/8

Select fxx/4

NOTE: 'fxx' is the system clock.

4-21

MEMORY MAP

KS57C5532/P5532

PMG1 — Port I/O Mode Flags (Group 1: Ports 0, 4, 5, 7)

I/O

FE9H, FE8H

Bit

7

PM7

0

6

"0"

0

5

PM5

0

4

PM4

0

3

2

1

0

Identifier

PM0.3

PM0.2

PM0.1

PM0.0

Value

0

W

8

0

W

8

0

W

8

0

W

8

Read/Write

W

8

W

Bit Addressing

8

PM7

Port 7 I/O Mode Selection Flag

0

1

Set port 7 to input mode

Set port 7 to output mode

.6

Bit 6

0

Always logic zero

PM5

Port 5 I/O Mode Selection Flag

0

1

Set port 5 to input mode

Set port 5 to output mode

PM4

Port 4 I/O Mode Selection Flag

0

1

Set port 4 to input mode

Set port 4 to output mode

PM0.3

PM0.2

PM0.1

PM0.0

P0.3 I/O Mode Selection Flag

0

1

Set P0.3 to input mode

Set P0.3 to output mode

P0.2 I/O Mode Selection Flag

0

1

Set P0.2 to input mode

Set P0.2 to output mode

P0.1 I/O Mode Selection Flag

0

1

Set P0.1 to input mode

Set P0.1 to output mode

P0.0 I/O Mode Selection Flag

0

1

Set P0.0 to input mode

Set P0.0 to output mode

4-22

KS57C5532/P5532

MEMORY MAP

PMG2 — Port I/O Mode Flags (Group 2: Ports 2, 3)

I/O

FEBH, FEAH

Bit

7

6

5

4

3

2

1

0

Identifier

PM3.3

PM3.2

PM3.1

PM3.0

PM2.3

PM2.2

PM2.1

PM2.0

Value

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

Read/Write

Bit Addressing

PM3.3

PM3.2

PM3.1

PM3.0

PM2.3

PM2.2

PM2.1

PM2.0

P3.3 I/O Mode Selection Flag

0

1

Set P3.3 to input mode

Set P3.3 to output mode

P3.2 I/O Mode Selection Flag

0

1

Set P3.2 to input mode

Set P3.2 to output mode

P3.1 I/O Mode Selection Flag

0

1

Set P3.1 to input mode

Set P3.1 to output mode

P3.0 I/O Mode Selection Flag

0

1

Set P3.0 to input mode

Set P3.0 to output mode

P2.3 I/O Mode Selection Flag

0

1

Set P2.3 to input mode

Set P2.3 to output mode

P2.2 I/O Mode Selection Flag

0

1

Set P2.2 to input mode

Set P2.2 to output mode

P2.1 I/O Mode Selection Flag

0

1

Set P2.1 to input mode

Set P2.1 to output mode

P2.0 I/O Mode Selection Flag

0

1

Set P2.0 to input mode

Set P2.0 to output mode

4-23

MEMORY MAP

KS57C5532/P5532

PMG3 — Port I/O Mode Flags (Group 3: Ports 6, 8)

I/O

FEDH, FECH

Bit

7

6

5

4

3

2

1

0

Identifier

PM8.3

PM8.2

PM8.1

PM8.0

PM6.3

PM6.2

PM6.1

PM6.0

Value

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

Read/Write

Bit Addressing

PM8.3

PM8.2

PM8.1

PM8.0

PM6.3

PM6.2

PM6.1

PM6.0

P8.3 I/O Mode Selection Flag

0

1

Set P8.3 to input mode

Set P8.3 to output mode

P8.2 I/O Mode Selection Flag

0

1

Set P8.2 to input mode

Set P8.2 to output mode

P8.1 I/O Mode Selection Flag

0

1

Set P8.1 to input mode

Set P8.1 to output mode

P8.0 I/O Mode Selection Flag

0

1

Set P8.0 to input mode

Set P8.0 to output mode

P6.3 I/O Mode Selection Flag

0

1

Set P6.3 to input mode

Set P6.3 to output mode

P6.2 I/O Mode Selection Flag

0

1

Set P6.2 to input mode

Set P6.2 to output mode

P6.1 I/O Mode Selection Flag

0

1

Set P6.1 to input mode

Set P6.1 to output mode

P6.0 I/O Mode Selection Flag

0

1

Set P6.0 to input mode

Set P6.0 to output mode

4-24

KS57C5532/P5532

MEMORY MAP

PMG4 — Port I/O Mode Flags (Group 4: Ports 9, 10, 11, 12, 13)

I/O

FEFH, FEEH

Bit

7

PM13

0

6

PM11

0

5

PM10

0

4

PM9

0

3

2

1

0

Identifier

PM12.3 PM12.2 PM12.1 PM12.0

Value

0

W

8

0

W

8

0

W

8

0

W

8

Read/Write

W

Bit Addressing

8

PM13

Port 13 I/O Mode Selection Flag

0

1

Set port 13 to input mode

Set port 13 to output mode

PM11

Port 11 I/O Mode Selection Flag

0

1

Set port 11 to input mode

Set port 11 to output mode

PM10

Port 10 I/O Mode Selection Flag

0

1

Set port 10 to input mode

Set port 10 to output mode

PM9

Port 9 I/O Mode Selection Flag

0

1

Set port 9 to input mode

Set port 9 to output mode

PM12.3

PM12.2

PM12.1

PM12.0

P12.3 I/O Mode Selection Flag

0

1

Set P12.3 to input mode

Set P12.3 to output mode

P12.2 I/O Mode Selection Flag

0

1

Set P12.2 to input mode

Set P12.2 to output mode

P12.1 I/O Mode Selection Flag

0

1

Set P12.1 to input mode

Set P12.1 to output mode

P12.0 I/O Mode Selection Flag

0

1

Set P12.0 to input mode

Set P12.0 to output mode

4-25

MEMORY MAP

KS57C5532/P5532

PNE 1 — Port Open-Drain Enable Register 1

FDBH, FDAH

Bit

7

6

5

4

3

2

1

0

Identifier

RESET Value

Read/Write

Bit Addressing

PNE5.3 PNE5.2 PNE5.1 PNE5.0 PNE4.3 PNE4.2 PNE4.1 PNE4.0

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

0

W

8

PNE5.3

PNE5.2

PNE5.1

PNE5.0

PNE4.3

PNE4.2

PNE4.1

PNE4.0

P5.3 Output mode Control Bit

0

1

Push-pull output

N-channel open-drain output

P5.2 Output mode Control Bit

0

1

Push-pull output

N-channel open-drain output

P5.1 Output mode Control Bit

0

1

Push-pull output

N-channel open-drain output

P5.0 Output mode Control Bit

0

1

Push-pull output

N-channel open-drain output

P4.3 Output mode Control Bit

0

1

Push-pull output

N-channel open-drain output

P4.2 Output mode Control Bit

0

1

Push-pull output

N-channel open-drain output

P4.1 Output mode Control Bit

0

1

Push-pull output

N-channel open-drain output

P4.0 Output mode Control Bit

0

1

Push-pull output

N-channel open-drain output

4-26

KS57C5532/P5532

MEMORY MAP

PSW— Program Status Word

CPU

FB1H, FB0H

Bit

7

C

6

SC2

0

5

SC1

0

4

SC0

0

3

IS1

0

2

IS0

0

1

0

Identifier

EMB

0

ERB

0

(1)

Value

Read/Write

R/W

(2)

R

R/W

1/4/8

R/W

1/4/8

R/W

1/4/8

R/W

1/4/8

Bit Addressing

8

C

Carry Flag

0

1

No overflow or borrow condition exists

An overflow or borrow condition does exist

SC2–SC0

IS1, IS0

Skip Condition Flags

0

1

No skip condition exists; no direct manipulation of these bits is allowed

A skip condition exists; no direct manipulation of these bits is allowed

Interrupt Status Flags

0

1

Service all interrupt requests

Service only the high-priority interrupt(s) as determined in the interrupt

priority register (IPR)

1

0

1

Do not service any more interrupt requests

Undefined

EMB

Enable Data Memory Bank Flag

0

Restrict program access to data memory to bank 15 (F80H–FFFH) and to

the locations 000H–07FH in the bank 0 only

1

Enable full access to data memory banks 0, 1, 2, 3, and 15

ERB

Enable Register Bank Flag

0

1

Select register bank 0 as working register area

Select register banks 0, 1, 2, or 3 as working register area in accordance with the

select register bank (SRB) instruction operand

NOTES:

1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during

power-down mode (IDLE or STOP), the current value of the carry flag is retained.

2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for

detailed information.

4-27

MEMORY MAP

KS57C5532/P5532

PUMOD1 — Pull-up Resistor Mode Register 1

I/O

FDDH, FDCH

Bit

7

PUR9

0

6

PUR8

0

5

PUR7

0

4

PUR6

0

3

PUR3

0

2

1

PUR1

0

PUR0

0

Identifier

PUR2

Value

0

W

8

Read/Write

W

Bit Addressing

8

PUR9

PUR8

PUR7

PUR6

PUR3

PUR2

PUR1

PUR0

Connect/Disconnect Port 9 Pull-up Resistor Control Bit

0

1

Disconnect port 9 pull-up resistor

Connect port 9 pull-up resistor

Connect/Disconnect Port 8 Pull-up Resistor Control Bit

0

1

Disconnect port 8 pull-up resistor

Connect port 8 pull-up resistor

Connect/Disconnect Port 7 Pull-up Resistor Control Bit

0

1

Disconnect port 7 pull-up resistor

Connect port 7 pull-up resistor

Connect/Disconnect Port 6 Pull-up Resistor Control Bit

0

1

Disconnect port 6 pull-up resistor

Connect port 6 pull-up resistor

Connect/Disconnect Port 3 Pull-up Resistor Control Bit

0

1

Disconnect port 3 pull-up resistor

Connect port 3 pull-up resistor

Connect/Disconnect Port 2 Pull-up Resistor Control Bit

0

1

Disconnect port 2 pull-up resistor

Connect port 2 pull-up resistor

Connect/Disconnect Port 1 Pull-up Resistor Control Bit

0

1

Disconnect port 1 pull-up resistor

Connect port 1 pull-up resistor

Connect/Disconnect Port 0 Pull-up Resistor Control Bit

0

1

Disconnect port 0 pull-up resistor

Connect port 0 pull-up resistor

4-28

KS57C5532/P5532

MEMORY MAP

PUMOD2 — Pull-up Resistor Mode Register 2

I/O

FDFH, FDEH

Bit

7

"0"

0

6

"0"

0

5

PUR5

0

4

PUR4

0

3

2

1

0

Identifier

PUR13

PDR12

PUR11

PUR10

Value

0

W

8

0

W

8

0

W

8

0

W

8

Read/Write

W

8

W

8

W

Bit Addressing

8

.7 – .6

PUR5

Bits 7–6

0

Always cleared to logic zero

Connect/Disconnect Port 5 Pull-Up Resistor Control Bit

0

1

Disconnect port 5 pull-up resistor

Connect port 5 pull-up resistor

PUR4

Connect/Disconnect Port 4 Pull-Up Resistor Control Bit

0

1

Disconnect port 4 pull-up resistor

Connect port 4 pull-up resistor

PUR13

PDR12

PUR11

PUR10

Connect/Disconnect Port 13 Pull-Up Resistor Control Bit

0

1

Disconnect port 13 pull-up resistor

Connect port 13 pull-up resistor

Connect/Disconnect Port 12 Pull-Down Resistor Control Bit

0

1

Disconnect port 12 pull-down resistor

Connect port 12 pull-down resistor

Connect/Disconnect Port 11 Pull-Up Resistor Control Bit

0

1

Disconnect port 11 pull-up resistor

Connect port 11 pull-up resistor

Connect/Disconnect Port 10 Pull-Up Resistor Control Bit

0

1

Disconnect port 10 pull-up resistor

Connect port 10 pull-up resistor

4-29

MEMORY MAP

KS57C5532/P5532

SCMOD— System Clock Mode Control Register

CPU

FB7H

Bit

3

.3

0

2

.2

0

1

"0"

0

.0

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

1

W

1

W

1

W

1

SCMOD.3

Bit 3

0

1

Enable main system clock

Disable main system clock

SCMOD.2

Bit 2

0

1

Enable sub system clock

Disable sub system clock

SCMOD.1

SCMOD.0

Bit 1

0

Always logic zero

Bit 0

0

1

Select main system clock

Select sub system clock

NOTES:

1. SCMOD bits 3 and 0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by

separate 1-bit instructions.

2. Sub-oscillation goes into stop mode only by SCMOD.2. PCON which revokes stop mode cannot stop the sub-

oscillation. The stop of sub-oscillation is released only by reset regardless of the value of SCMOD.2.

3. You can use SCMOD.2 as follows (ex; after data bank was used, a few minutes have passed):

Main operation ® sub-operation ® sub-idle ® sub-operation ® main operation ® SCMOD.2 = 1 ® main stop mode.

4-30

KS57C5532/P5532

MEMORY MAP

SMOD — Serial I/O Mode Register

SIOFE1H, FE0H

Bit

7

.7

0

6

.6

0

5

.5

0

4

"0"

0

3

.3

2

.2

0

1

.1

0

.0

0

Identifier

Value

0

Read/Write

W

8

W

8

W

8

W

8

W

1/8

W

8

W

8

W

8

Bit Addressing

SMOD.7 – .5

Serial I/O Clock Selection and SBUF R/W Status Control Bits

0

1

0

1

x

Use an external clock at the

Enable SBUF when SIO operation is halted or when

pin;

goes high

Use the TOL0 clock from timer/counter 0;

Enable SBUF when SIO operation is halted or when

Use the selected CPU clock (fxx/4, 8, or 64; 'fxx' is the system clock)

then, enable SBUF read/write operation. 'x' means 'don't care.'

3.49 kHz clock (fxx/2¹⁰

)

1

0

1

0

1

223.7 kHz clock (fxx/2⁴); Note: You cannot select a fxx/2 clock fre-

4

quency if you have selected a CPU clock of fx/64

NOTE: All kHz frequency ratings assume a system clock of 3.579545 MHz.

SMOD.4

SMOD.3

Bit 4

0

Always logic zero

Initiate Serial I/O Operation Bit

1

Clear IRQS flag and 3-bit clock counter to logic zero; then initiate serial trans-

mission. When SIO transmission starts, this bit is cleared by hardware to logic 0.

SMOD.2

Enable/Disable SIO Data Shifter and Clock Counter Bit

0

Disable the data shifter and clock counter; the contents of IRQS flag is retained

when serial transmission is completed

1

Enable the data shifter and clock counter; The IRQS flag is set to logic one when

serial transmission is completed

SMOD.1

SMOD.0

Serial I/O Transmission Mode Selection Bit

0

1

Receive-only mode

Transmit-and-receive mode

LSB/MSB Transmission Mode Selection Bit

0

1

Transmit the most significant bit (MSB) first

Transmit the least significant bit (LSB) first

4-31

MEMORY MAP

KS57C5532/P5532

TMOD0— Timer/Counter 0 Mode Register

T/C0

F91H, F90H

Bit

3

"0"

0

2

.6

0

1

.5

0

.4

0

3

.3

2

.2

0

1

"0"

0

"0"

0

Identifier

Value

0

Read/Write

W

8

W

8

W

8

W

8

W

1/8

W

8

W

8

W

8

Bit Addressing

TMOD0.7

Bit 7

0

Always logic zero

TMOD0.6 – .4

Timer/Counter 0 Input Clock Selection Bits

0

1

0

1

0

External clock input at TCL0 pin on rising edge

External clock input at TCL0 pin on falling edge

10

Internal system clock (fxx) of 3.579545 MHz/2 (3.49 kHz)

6

1

0

1

0

1

Select clock: fxx/2 (55.93 kHz at 3.579545 MHz)

4

Select clock: fxx/2 (223.7 kHz at 3.579545 MHz)

Select clock: fxx (3.579545 MHz)

TMOD0.3

TMOD0.2

Clear Counter and Resume Counting Control Bit

1

Clear TCNT0, IRQT0, and TOL0 and resume counting immediately

(This bit is cleared automatically when counting starts.)

Enable/Disable Timer/Counter 0 Bit

0

1

Disable timer/counter 0; retain TCNT0 contents

Enable timer/counter 0

TMOD0.1

TMOD0.0

Bit 1

0

Always logic zero

Bit 0

0

4-32

KS57C5532/P5532

MEMORY MAP

TMOD1— Timer/Counter 1 Mode Register

T/C1

FA1H, FA0H

Bit

3

"0"

0

2

.6

0

1

.5

0

.4

0

3

.3

2

.2

0

1

"0"

0

"0"

0

Identifier

Value

0

Read/Write

W

8

W

8

W

8

W

8

W

1/8

W

8

W

8

W

8

Bit Addressing

TMOD1.7

Bit 7

0

Always logic zero

TMOD1.6 – .4

Timer/Counter 0 Input Clock Selection Bits

0

1

0

1

0

1

0

1

0

1

External clock input at TCL1 pin on rising edge

External clock input at TCL1 pin on falling edge

Internal system clock (fxx) of 3.579545 MHz/2¹²(0.87 kHz)

Select clock: fxx/2¹⁰(3.49 kHz at 3.579545 MHz)

Select clock: fxx/2⁸(13.98 kHz at 3.579545 MHz)

Select clock: fxx/2⁶(55.93 kHz at 3.579545 MHz)

TMOD1.3

TMOD1.2

Clear Counter and Resume Counting Control Bit

1

Clear TCNT1, IRQT1, and TOL1 and resume counting immediately

(This bit is cleared automatically when counting starts.)

Enable/Disable Timer/Counter 0 Bit

0

1

Disable timer/counter 1; retain TCNT1 contents

Enable timer/counter 1

TMOD1.1

TMOD1.0

Bit 1

0

Always logic zero

Bit 0

0

4-33

MEMORY MAP

KS57C5532/P5532

TOE— Timer Output Enable Flag Register

T/C

F92H

Bit

3

TOE1

0

2

TOE0

0

1

0

"0"

0

Identifier

BOE

0

Value

Read/Write

R/W

1/4

R/W

1/4

R/W

1/4

W

Bit Addressing

1/4

TOE1

TOE0

BOE

.0

Timer/Counter 1 Output Enable Flag

0

1

Disable timer/counter 1 output to the TCLO1 pin

Enable timer/counter 1 output to the TCLO1 pin

Timer/Counter 0 Output Enable Flag

0

1

Disable timer/counter 0 output at the TCLO0 pin

Enable timer/counter 0 output at the TCLO0 pin

Basic Timer Output Enable Flag

0

1

Disable basic timer output at the BTCO pin

Enable basic timer output at the BTCO pin

Bit 0

0

Always logic zero

4-34

KS57C5532/P5532

MEMORY MAP

WDFLAG — Watchdog Timer’s Counter Clear Flag

WT

F9AH

Bit

3

WDTCF

0

2

"0"

0

1

"0"

0

"0"

0

Identifier

RESET Value

Read/Write

Bit Addressing

W

4

W

4

W

4

1/4

WDTCF

Watchdog Timer's Counter Clear Bit

0

–

1

Clear the WDT's counter to zero and restart the WDT's counter

WDFLAG.2–.0

Bits 2–0

Always logic zero

0

4-35

MEMORY MAP

KS57C5532/P5532

WDMOD — Watchdog Timer Mode Control Register

WT

F99H,F98H

Bit

7

.7

1

6

.6

0

5

.5

1

4

.4

0

3

.3

0

2

.2

1

.1

0

.0

1

Identifier

RESET Value

Read/Write

Bit Addressing

W

8

W

8

W

8

W

8

W

8

W

8

W

8

W

8

WMOD.7–.0

Watchdog Timer Enable/Disable Control

0

1

0

1

0

1

0

Disable watchdog timer function

Enable watchdog timer function

Others

4-36

KS57C5532/P5532

MEMORY MAP

WMOD — Watch Timer Mode Register

WT

F89H, F88H

Bit

3

.7

0

2

.6

0

1

.5

0

.4

0

3

.3

2

.2

0

1

.1

0

.0

0

Identifier

(note)

R

Value

Read/Write

W

8

W

8

W

8

W

8

W

8

W

8

W

8

Bit Addressing

1

WMOD.7

Enable/Disable Buzzer Output Bit

0

1

Disable buzzer (BUZ) signal output

Enable buzzer (BUZ) signal output

WMOD.6

Bit 6

0

Always logic zero

WMOD.5 – .4

Output Buzzer Frequency Selection Bits

0

1

0

1

0

1

fw/16 buzzer (BUZ) signal output (2 kHz)

fw/8 buzzer (BUZ) signal output (4 kHz)

fw/4 buzzer (BUZ) signal output (8 kHz)

fw/2 buzzer (BUZ) signal output (16 kHz)

XT Input Level Control Bit

in

WMOD.3

Input level to XT pin is low; 1-bit read-only addressable for tests

in

0

1

Input level to XT pin is high; 1-bit read-only addressable for tests

in

WMOD.2

WMOD.1

Enable/Disable Watch Timer Bit

0

1

Disable watch timer and clear frequency dividing circuits

Enable watch timer

Watch Timer Speed Control Bit

0

1

Normal speed; set IRQW to 0.5 seconds

High-speed operation; set IRQW to 3.91 ms

WMOD.0

NOTES:

Watch Timer Clock Selection Bit

0

1

Select main system clock (fxx)/128 as the watch timer clock (fw)

Select a subsystem clock as the watch timer clock (fw)

1. System clock of 4.19 MHz and typical subsystem clock of 32.768 kHz are assumed.

2. RESET sets WMOD.3 to the current input level of the subsystem clock, XTin. If the input level is high, WMOD.3 is

logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register.

set to

4-37

MEMORY MAP

KS57C5532/P5532

NOTES

4-38

Oscillator Circuits

Interrupts

Power-Down

I/O Ports

Timers and Timer/Counters

DTMF Generator

Serial I/O Interface

Electrical Data

Mechanical Data

KS57P5532 OTP

Development Tools

KS57C5532/P5532

OSCILLATOR CIRCUITS

6

OSCILLATOR CIRCUITS

OVERVIEW

The KS57C5532 microcontrollers have two oscillator circuits: a main system clock circuit, and a subsystem clock

circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits.

Specifically, a clock pulse is required by the following peripheral modules:

— Basic timer

— Timer/counters 0 and 1

— Watch timer

— Serial I/O interface

— Clock output circuit

CPU Clock Notation

In this document, the following notation is used for descriptions of the CPU clock:

fx Main system clock

fxt Subsystem clock

fxx Selected system clock

Clock Control Registers

When the system clock mode register, SCMOD, and the power control register, PCON, registers are both cleared

to zero after RESET, the normal CPU operating mode is enabled, a main system clock of fx/64 is selected, and

main system clock oscillation is initiated.

The PCON is used to select normal CPU operating mode or one of two power-down modes — stop or idle. Bits 3

and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle power-

down mode.

The SCMOD, lets you select the main system clock (fx) or a subsystem clock (fxt) as the CPU clock and to start

(or stop) main/sub system clock oscillation. The resulting clock source, either main system clock or subsystem

clock, is referred to as the selected system clock (fxx).

The main system clock is selected and oscillation started when all SCMOD bits are cleared to”0”. By setting

SCMOD.3, SCMOD.2 and SCMOD.0 to different values, you can select a subsystem clock source and start or

stop main/sub system clock oscillation. To stop main system clock oscillation, You must use the stop instruction

(assuming the main system clock is selected) or manipulate SCMOD.3 to “1” (assuming the sub system clock is

selected).

The main system clock frequencies can be divided by 4, 8, or 64 and a subsystem clock frequencies can only be

divided by 4. By manipulating PCON bits 1 and 0, you select one of the following frequencies as the CPU clock.

6-1

OSCILLATOR CIRCUITS

KS57C5532/P5532

fx

4

fx

8

fx

64

fxt

4

,

Using a subsystem clock

If a subsystem clock is being used as the selected system clock, the idle power-down mode can be initiated by

executing an IDLE instruction.

The watch timer and buzzer operate normally with a subsystem clock source, since they operate at very low

speed (as low as 122 ms at 32.768 KHz) and with very low power consumption.

DTMF Generator

fx

fxt

Watch Timer

Main-system

Oscillator

Circuit

Sub-system

Oscillator

Circuit

Selector

Oscillator

Stop

X

IN

XOUT

XTIN

XTOUT

fxx

1/8-1/4096

Oscillator

Stop

Basic Timer

Frequency

Dividing

Circuit

Timer/Counters 0, and 1

Serial I/O Interface

Watch Timer

Clock Output Circuit

1/2

1/16

SCMOD.3

SCMOD.0

SCMOD.2

Selector

fx/1, 2, 16

fxt

Selector

1/4

CPU stop signal

(IDLE mode)

CPU Clock

PCON.0

PCON.1

PCON.2

PCON.3

Wait release signal

Internal signal

Oscillator

Control

Circuit

Idle

RESET

Stop

Power down release signal

fx: Main-system clock

fxt: Sub-system clock

fxx: System clock

PCON.3, .2 clear

Figure 6-1. Clock Circuit Diagram

6-2

KS57C5532/P5532

OSCILLATOR CIRCUITS

MAIN SYSTEM OSCILLATOR CIRCUITS

SUBSYSTEM OSCILLATOR CIRCUITS

XTIN

XIN

XTOUT

XOUT

32.768 kHz

Figure 6-5. Crystal/Ceramic Oscillator

Figure 6-2. Crystal/Ceramic Oscillator

XTIN

XIN

External

Clock

External

Clock

XTOUT

XOUT

Figure 6-6. External Oscillator

Figure 6-3. External Oscillator (fx)

XIN

R

XOUT

Figure 6-4. RC Oscillator

6-3

OSCILLATOR CIRCUITS

KS57C5532/P5532

POWER CONTROL REGISTER (PCON)

The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control

CPU operating and power-down modes. PCON can be addressed directly by 4-bit write instructions or indirectly

by the instructions IDLE and STOP.

FB3H

PCON.3

PCON.2

PCON.1

PCON.0

PCON bits 3 and 2 are addressed by the STOP and IDLE instructions, respectively, to engage the idle and stop

power-down modes. Idle and stop modes can be initiated by these instruction despite the current value of the

enable memory bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency. There

are two basic choices:

— Main system clock (fx) or subsystem clock (fxt);

— Divided fx clock frequency of 4, 8, or 64.

PCON.1 and PCON.0 settings are also connected with the system clock mode control register, SCMOD. If

SCMOD.0 = "0" the main system clock is always selected by the PCON.1 and PCON.0 setting; if SCMOD.0 =

"1" the subsystem clock is selected.

sets PCON register values (and SCMOD) to logic zero: SCMOD.3 and SCMOD.0 select the main system

clock (fx) and start clock oscillation; PCON.1 and PCON.0 divide the selected fx frequency by 64, and PCON.3

and PCON.2 enable normal CPU operating mode.

Table 6-1. Power Control Register (PCON) Organization

PCON Bit Settings

Resulting CPU Operating Mode

PCON.3

PCON.2

0

1

0

1

0

Normal CPU operating mode

Idle power-down mode

Stop power-down mode

PCON Bit Settings

Resulting CPU Clock Frequency

PCON.1

PCON.0

If SCMOD.0 = "0"

If SCMOD.0 = "1"

0

1

0

1

fx/64

fx/8

–

fx/4

fxt/4

+

PROGRAMMING TIP — Setting the CPU Clock

To set the CPU clock to 0.89 MHz at 3.579545 MHz:

BITS

SMB

LD

EMB

15

A,#3H

PCON,A

LD

6-4

KS57C5532/P5532

OSCILLATOR CIRCUITS

INSTRUCTION CYCLE TIMES

The unit of time that equals one machine cycle varies depending on whether the main system clock (fx) or a

subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). Table 6–2 shows

corresponding cycle times in microseconds.

Table 6-2. Instruction Cycle Times for CPU Clock Rates

Selected

CPU Clock

Resulting Frequency

Oscillation

Source

Cycle Time (µsec)

fx/64

fx/8

55.9 kHz

447.4 kHz

0.89 MHz

fx = 3.579545 MHz

17.88

2.23

1.12

fx/4

fxt/4

8.19 kHz

fxt = 32.768 kHz

122.0

SYSTEM CLOCK MODE REGISTER (SCMOD)

The system clock mode register, SCMOD, is a 4-bit register that is used to select the CPU clock and to control

main system clock oscillation. clears all SCMOD values to logic zero, selecting the main system clock (fx)

as the CPU clock and starting clock oscillation.

Only SCMOD.0, SCMOD.2 and SCMOD.3 bits of the SCMOD register can be manipulated by 1-bit write

instructions. (In other words, SCMOD.0 SCMOD.2 and SCMOD.3 cannot be modified simultaneously by a 4-bit

write.) Bit 1 is always logic zero.

FB7H

SCMOD.3 SCMOD.2

"0"

SCMOD.0

A subsystem clock (fxt) can be selected as the system clock by manipulating the SCMOD.3 and SCMOD.0 bit

settings. If SCMOD.3 = "0" and SCMOD.0 = "1", the subsystem clock is selected and main system clock

oscillation continues. If SCMOD.3 = "1" and SCMOD.0 = "1", fxt is selected, but main system clock oscillation

stops.

Even if you have selected fx as the CPU clock, setting SCMOD.3 to “1” will not stop main system clock

oscillation, but malfuction may be occured. To operate safely, main system clock should be stopped by a stop

instruction in main system clock mode.

Table 6-3. System Clock Mode Register (SCMOD) Organization

SCMOD Register Bit Settings

Resulting Clock Selection

CPU Clock fx Oscillation

SCMOD.3

SCMOD.0

0

1

0

1

fx

On

Off

fxt

Table 6-4. SCMOD.2 for Sub-Oscillation on/off

SCMOD.2

Sub-oscillation on/off

0

1

Enable sub system clock

Disable sub system clock

6-5

OSCILLATOR CIRCUITS

KS57C5532/P5532

SWITCHING THE CPU CLOCK

Together, bit settings in the power control register, PCON, and the system clock mode register, SCMOD,

determine whether a main system or a subsystem clock is selected as the CPU clock, and also how this

frequency is to be divided. This makes it possible to switch dynamically between main and subsystem clocks and

to modify operating frequencies.

SCMOD.3 and SCMOD.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main

system clock oscillation. PCON.1 and PCON.0 control the frequency divider circuit, and divide the selected fx

clock by 4, 8, or 64.

NOTE

A clock switch operation does not go into effect immediately when you make the SCMOD and PCON

register modifications — the previously selected clock continues to run for a certain number of machine

cycles.

For example, you are using the default CPU clock (normal operating mode and a main system clock of fx/64) and

you want to switch from the fx clock to a subsystem clock and to stop the main system clock. To do this, you first

need to set SCMOD.0 to "1". This switches the clock from fx to fxt but allows main system clock oscillation to

continue. Before the switch actually goes into effect, a certain number of machine cycles must elapse. After this

time interval, you can then disable main system clock oscillation by setting SCMOD.3 to "1".

This same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first,

clear SCMOD.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles

has elapsed, select the main system clock by clearing all SCMOD values to logic zero.

Following a

, CPU operation starts with the lowest main system clock frequency of 15.3 µsec at 4.19 MHz

after the standard oscillation stabilization interval of 31.3 ms has elapsed. Table 6-5 details the number of

machine cycles that must elapse before a CPU clock switch modification goes into effect.

Table 6-5. Elapsed Machine Cycles During CPU Clock Switch

AFTER

SCMOD.0 = 0

SCMOD.0 = 1

BEFORE

PCON.1 = 0 PCON.0 = 0 PCON.1 = 1 PCON.0 = 0 PCON.1 = 1 PCON.0 = 1

PCON.1 = 0

PCON.0 = 0

PCON.1 = 1

PCON.0 = 0

PCON.1 = 1

PCON.0 = 1

N/A

1 Machine Cycle

8 Machine Cycles

N/A

SCMOD.0 = 0

8 Machine Cycles

16 Machine Cycles

N/A

16 Machine Cycles

N/A

fx/4fxt

N/A

SCMOD.0 = 1

fx/4fxt (M/C)

NOTES:

1. Even if oscillation is stopped by setting SCMOD.3 during main system clock operation, the stop mode is not entered.

2. Since the Xin input is connected internally to V to avoid current leakage due to the crystal oscillator in stop mode, do

SS

not set SCMOD.3 to "1", or stop instruction when an external clock is used as the main system clock.

3. When the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during

the time intervals shown in Table 6-5.

4. 'N/A' means 'not available'.

6-6

KS57C5532/P5532

OSCILLATOR CIRCUITS

+

PROGRAMMING TIP — Switching Between Main System and Subsystem Clock

1. Switch from the main system clock to the subsystem clock:

MA2SUB

BITS

CALL

BITS

RET

LD

NOP

DECS

JR

SCMOD.0

DLY80

SCMOD.3

;

Switches to subsystem clock

Delay 80 machine cycles

Stop the main system clock

DLY80

DEL1

A,#0FH

A

DEL1

RET

2. Switch from the subsystem clock to the main system clock:

SUB2MA

BITR

CALL

BITR

RET

SCMOD.3

DLY80

SCMOD.0

;

Start main system clock oscillation

Delay 80 machine cycles

Switch to main system clock

6-7

OSCILLATOR CIRCUITS

KS57C5532/P5532

CLOCK OUTPUT MODE REGISTER (CLMOD)

The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the

CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4-bit write instructions

only.

FD0H

CLMOD.3

"0"

CLMOD.1

CLMOD.0

clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without

initiating clock oscillation), and disables clock output.

CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four

possible clock sources and frequencies: normal CPU clock, fxx/8, fxx/16, or fxx/64.

Table 6-5. Clock Output Mode Register (CLMOD) Organization

CLMOD Bit Settings

Resulting Clock Output

CLMOD.1

CLMOD.0

Clock Source

Frequency

0.89 MHz, 447.4 kHz, 55.9 kHz

447.4 kHz

0

1

0

1

0

1

CPU clock (fx/4, fx/8, fx/64 or fxt/4)

fxx/8

fxx/16

fxx/64

223.7 kHz

55.9 kHz

CLMOD.3

Result of CLMOD.3 Setting

0

1

Clock output is disabled

Clock output is enabled

NOTE: Frequencies assume that fxx = 3.579545 MHz.

6-8

KS57C5532/P5532

OSCILLATOR CIRCUITS

CLOCK OUTPUT CIRCUIT

The clock output circuit, used to output clock pulses to the CLO pin, has the following components:

— 4-bit clock output mode register (CLMOD)

— Clock selector

— Output latch

— Port mode flag

— CLO output pin (P2.2)

CLMOD.3

CLO

CLMOD.2

4

CLMOD.1

Clock

Selector

P2.2 Output Latch

PM 2.2

CLMOD.0

Clocks

(fx/8, fx/16, fx/64, CPU clock)

Figure 6-7. CLO Output Pin Circuit Diagram

CLOCK OUTPUT PROCEDURE

The procedure for outputting clock pulses to the CLO pin may be summarized as follows:

1. Disable clock output by clearing CLMOD.3 to logic zero.

2. Set the clock output frequency (CLMOD.1, CLMOD.0).

3. Load a "0" to the output latch of the CLO pin (P2.2).

4. Set the P2.2 mode flag (PM2.2) to output mode.

5. Enable clock output by setting CLMOD.3 to logic one.

6-9

OSCILLATOR CIRCUITS

KS57C5532/P5532

+

PROGRAMMING TIP — CPU Clock Output to the CLO Pin

To output the CPU clock to the CLO pin:

BITS

SMB

LD

BITR

LD

EMB

15

EA,#04H

PMG2,EA

P2.2

A,#8H

CLMOD,A

;

P2.2 ¬ Output mode

Clear P2.2 output latch

LD

6-10

KS57C5532/P5532

INTERRUPTS

7

INTERRUPTS

OVERVIEW

The KS57C5532's interrupt control circuit has five functional components:

— Interrupt enable flags (IEx)

— Interrupt request flags (IRQx)

— Interrupt master enable register (IME)

— Interrupt priority register (IPR)

— Power-down release signal circuit

Three kinds of interrupts are supported:

— Internal interrupts generated by on-chip processes

— External interrupts generated by external peripheral devices

— Quasi-interrupts used for edge detection and as clock sources

Table 7-1. Interrupt Types and Corresponding Port Pin(s)

Interrupt Type

External interrupts

Interrupt Name

INT0, INT1, INT4

Corresponding Port Pin

P1.0, P1.1, P1.3

Not applicable

Internal interrupts

Quasi-interrupts

INTB, INTT0, INTT1, INTS

INT2

P1.2, Ports 6 and 7 (KS0–KS7)

Not applicable

INTW

7-1

INTERRUPTS

KS57C5532/P5532

Vectored Interrupts

Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program

software. A vectored interrupt is generated when the following flags and register settings, corresponding to the

specific interrupt (INTn) are set to logic one:

— Interrupt enable flag (IEx)

— Interrupt master enable flag (IME)

— Interrupt request flag (IRQx)

— Interrupt status flags (IS0, IS1)

— Interrupt priority register (IPR)

If all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is

loaded into the program counter and the program starts executing the service routine from this address.

EMB and ERB flags for RAM memory banks and registers are stored in the vector address area of the ROM

during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction.

The initial flag values determine the vectors for resets and interrupts. Enable flag values are saved during the

main routine, as well as during service routines. Any changes that are made to enable flag values during a service

routine are not stored in the vector address.

When an interrupt occurs, the EMB and the ERB flag values before the interrupt is initiated are saved along with

the program status word (PSW), and the enable flag values for the interrupt are fetched from the respective vector

address. Then, if necessary, you can modify the enable flags during the interrupt service routine. When the

interrupt service routine is returned to the main routine by the IRET instruction, the original values saved in the

stack are restored and the main program continues program execution with these values.

Software-Generated Interrupts

To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the

interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met,

and the service routine can be initiated.

Multiple Interrupts

By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and

thereby process multiple interrupts simultaneously.

If more than four interrupts are being processed at one time, you can avoid possible loss of working register data

by using the PUSH RR instruction to save register contents to the stack before the service routines are executed

in the same register bank. When the routines have executed successfully, you can restore the register contents

from the stack to working memory using the POP instruction.

Power-Down Mode Release

An interrupt (with the exception of INT0) can be used to release power-down mode (stop or idle). Interrupts for

power-down mode release are initiated by setting the corresponding interrupt enable flag. Even if the IME flag is

cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag

has been set. In such cases, the interrupt routine will not be executed since IME = "0".

7-2

KS57C5532/P5532

INTERRUPTS

Interrupt is generated (INT xx)

Request flag (IRQx)

1

No

IEx = 1?

Yes

Retain value until IEx = 1

Generate corresponding vector interrupt

and release power-down mode

No

IME = 1?

Yes

Retain value until IME= 1

Yes

Retain value until interrupt

IS1, 0 = 0, 0?

service routine is completed

No

IS1, 0 = 0, 1?

Yes

High-priority interrupt

Yes

IS1, 0 = 0, 1

IS1, 0 = 1, 0

Store contents of PC and PSW in the stack area;

set PC contents to corresponding vector address

Yes

Are both interrupt sources

of shared vector address used?

IRQx flag value remains 1

No

Reset corresponding IRQx flag

Jump to interrupt start address

Verify interrupt source and clear

IRQx with a BTSTZ instruction

Figure 7-1. Interrupt Execution Flowchart

7-3

INTERRUPTS

KS57C5532/P5532

IMOD1

IMOD0

IE2 IEW IET1 IET0 IETS IE1 IE0 IE4 IEB

IRQB

IRQ4

INTB

INT4

INT0

INT1

#

@

IRQ0

@

IRQ1

INTS

INTT0

INTT1

INTW

IRQS

IRQT0

IRQT1

IRQW

IRQ2

INT2

SELECTOR

KS0-KS7

IMOD2

Power-Down

Mode

Release Signal

IME

IPR

IS1 IS0

Interrupt Control Unit

Vector Interrupt

Generator

# = Noise Filtering Circuit

@ = Edge Detection Circuit

Figure 7-2. Interrupt Control Circuit Diagram

7-4

KS57C5532/P5532

INTERRUPTS

MULTIPLE INTERRUPTS

The interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter-

rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service

routine for a lower-priority request is accepted during the execution of a higher priority routine.

Two-Level Interrupt Handling

Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits

of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all

interrupt requests are serviced (see Figure 7–3).

Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one, and the values are stored in the

stack along with the other PSW bits. After the interrupt routine has been serviced, the modified IS1 and IS0

values are automatically restored from the stack by an IRET instruction.

IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable

memory bank flag (EMB). Before you can modify an interrupt status flag, however, you must first disable interrupt

processing with a DI instruction.

When IS1 = "0" and IS0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt

currently defined by the interrupt priority register (IPR).

Normal Program

Processing

High or Low Level

Interrupt Processing

(Status 1)

(Status 0)

High Level Interrupt

Processing

INT Disable

(Status 2)

Set IPR

INT Enable

Low or

High Level

Interrupt

High Level

Interrupt

Generated

Figure 7-3. Two-Level Interrupt Handling

7-5

INTERRUPTS

KS57C5532/P5532

Multi-Level Interrupt Handling

With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority interrupt

is being serviced. This is done by manipulating the interrupt status flags, IS0 and IS1 (see Table 7–2).

When an interrupt is requested during normal program execution, interrupt status flags IS0 and IS1 are set to "1"

and "0", respectively. This setting allows only highest-priority interrupts to be serviced. When a high-priority

request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority

level can be serviced. In this way, the high- and low-priority requests can be serviced in parallel (see Figure 7–4).

Table 7-2. IS1 and IS0 Bit Manipulation for Multi-Level Interrupt Handling

Process Status

Before INT

IS1 IS0

Effect of ISx Bit Setting

After INT ACK

IS1

0

IS0

1

0

1

0

All interrupt requests are serviced.

0

1

Only high-priority interrupts as determined by the

current settings in the IPR register are serviced.

1

0

2

–

1

0

1

No additional interrupt requests will be serviced.

Value undefined

–

Normal Program

Processing

Single

Interrupt

(Status 0)

2-Level

Interrupt

INT Disable

Set IPR

Status 1

3-Level

INT Disable

Interrupt

INT Enable

Modify Status

INT Enable

Status 0

Low or

High Level

Interrupt

High Level

Low or

High Level

Interrupt

Generated

Status 1

Status 2

Generated

Status 0

Figure 7-4. Multi-Level Interrupt Handling

7-6

KS57C5532/P5532

INTERRUPTS

INTERRUPT PRIORITY REGISTER (IPR)

The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. Its reset value is logic

zero. Before the IPR can be modified by 4-bit write instructions, all interrupts must first be disabled by a DI

instruction.

FB2H

IME

IPR.2

IPR.1

IPR.0

By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or

you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by

a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by

any other interrupt source.

Table 7-3. Standard Interrupt Priorities

Interrupt

INTB, INT4

INT0

Default Priority

1

2

3

4

5

6

INT1

INTS

INTT0

INTT1

The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if

an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the

IME flag is set to logic one. The IME flag can be directly manipulated by EI and DI instructions, regardless of the

current enable memory bank (EMB) value.

Table 7-4. Interrupt Priority Register Settings

IPR.2

IPR.1

IPR.0

Result of IPR Bit Setting

Normal interrupt handling according to default priority settings

Process INTB and INT4 interrupts at highest priority

Process INT0 interrupts at highest priority

0

1

0

1

0

1

0

1

0

1

0

1

0

Process INT1 interrupts at highest priority

Process INTS interrupts at highest priority

Process INTT0 interrupts at highest priority

Process INTT1 interrupts at highest priority

NOTE: During normal interrupt processing, interrupts are processed in the order in which they occur. If two or more interrupts

occur simultaneously, the processing order is determined by the default interrupt priority settings shown in Table 7–3.

Using the IPR settings, you can select specific interrupts for high-priority processing in the event of contention. When

the high-priority (IPR) interrupt has been processed, waiting interrupts are handled according to their default priorities.

7-7

INTERRUPTS

KS57C5532/P5532

+

PROGRAMMING TIP — Setting the INT Interrupt Priority

The following instruction sequence sets the INT1 interrupt to high priority:

BITS

SMB

DI

LD

EMB

15

;

IPR.3 (IME) ¬

0

1

A,#3H

IPR,A

EI

EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (IMOD0, IMOD1)

The following components are used to process external interrupts at the INT0 and INT1 pin:

— Noise filtering circuit for INT0

— Edge detection circuit

— Two mode registers, IMOD0 and IMOD1

The mode registers are used to control the triggering edge of the input signal. IMOD0 and IMOD1 settings let you

choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The INT4 interrupt is

an exception since its input signal generates an interrupt request on both rising and falling edges.

FB4H

FB5H

IMOD0.3

"0"

IMOD0.1

"0"

IMOD0.0

IMOD1.0

IMOD0 and IMOD1 bits are addressable by 4-bit write instructions.

selecting rising edges as the trigger for incoming interrupt requests.

clears all IMOD values to logic zero,

Table 7-5. IMOD0 and IMOD1 Register Organization

IMOD0

IMOD0.3

0

IMOD0.1

IMOD0.0

Effect of IMOD0 Settings

Select CPU clock for sampling

Select fxx/64 sampling clock

Rising edge detection

0

1

0

1

0

1

0

1

Falling edge detection

Both rising and falling edge detection

IRQ0 flag cannot be set to "1"

IMOD1

0

IMOD1.0

Effect of IMOD1 Settings

Rising edge detection

0

1

Falling edge detection

7-8

KS57C5532/P5532

INTERRUPTS

EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (Continued)

When a sampling clock rate of fx/64 is used for INT0, an interrupt request flag must be cleared before 16 machine

cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take the

following precautions when you use it:

— To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of

the clock selected by IMOD0. This is true even when the INT0 pin is used for general-purpose input.

— Since the INT0 input sampling clock does not operate during stop or idle mode, you cannot use INT0 to re-

lease power-down mode.

Noise Filter

Edge Detection

IRQ0

IRQ1

INT0

Clock

Selector

XX

/64

CPU Clock

f

INT1

Edge Detection

IMOD1

IMOD0

P1.1

P1.0

Figure 7-5. Circuit Diagram for INT0 and INT1 Pins

When modifying the IMOD0 and IMOD1 registers, it is possible to accidentally set an interrupt request flag. To

avoid unwanted interrupts, take these precautions when writing your programs:

1. Disable all interrupts with a DI instruction.

2. Modify the IMOD0 or IMOD1 register.

3. Clear all relevant interrupt request flags.

4. Enable the interrupt by setting the appropriate IEx flag.

5. Enable all interrupts with an EI instructions.

7-9

INTERRUPTS

KS57C5532/P5532

EXTERNAL INTERRUPT 2 MODE REGISTER (IMOD2)

The mode register for external interrupts at the INT2 pin, IMOD2 is addressable only by 4-bit write instructions.

clears all IMOD2 bits to logic zero.

FB6H

"0"

IMOD2.1

IMOD2.0

When IMOD2 is cleared to logic zero, INT2 uses the rising edge of an incoming signal as the interrupt request

trigger. If a rising edge is detected at the INT2 pin, or when a falling edge is detected at any one of the pins KS0–

KS7, the IRQ2 flag is set to logic one and a release signal for power-down mode is generated.

If one or more of the pins which are configured as key interrupt (KS0–KS1) are in low input, the key interrupt can

not be occurred.

Table 7-6. IMOD2 Register Bit Settings

IMOD2

0

IMOD2.1

IMOD2.0

Effect of IMOD2 Settings

Select rising edge at INT2 pin

Select falling edge at KS4–KS7

Select falling edge at KS2–KS7

Select falling edge at KS0–KS7

0

1

0

1

0

1

7-10

KS57C5532/P5532

INTERRUPTS

Rising Edge

Detection

INT 2

P7.3/KS7

P7.2/KS6

P7.1/KS5

P7.0/KS4

P6.3/KS3

P6.2/KS2

P6.1/KS1

P6.0/KS0

Falling

Edge

Detection

Circuit

Clock

Selector

IRQ2

IMOD2

NOTE: To generate a key interrupt on a falling edge at KS0-KS7, all KS0-KS7 pins must be configured

to the input mode. Particularly, the KS4-KS7 must always be configured to the input mode.

Figure 7-6. Circuit Diagram for INT2 and KS0–KS7 Pins

7-11

INTERRUPTS

KS57C5532/P5532

+

PROGRAMMING TIP — Using INT2 as a Key Input Interrupt

When the INT2 interrupt is used as a key interrupt, the selected key interrupt source pin must be set to input:

1. When KS0–KS7 are selected (eight pins):

BITS

SMB

LD

EMB

15

A,#3H

LD

IMOD2,A

EA,#0FH

PMG1,EA

EA,#00H

PMG3,EA

EA,#30H

PUMOD1,EA

;

(IMOD2) ¬ #3H, KS0–KS7 falling edge select

P7 ¬ input mode

P6 ¬ input mode

Enable P6 and P7 pull-up resistors

2. When KS2–KS7 are selected (six pins):

BITS

SMB

LD

EMB

15

A,#2H

LD

IMOD2,A

EA,#0FH

PMG1,EA

EA,#0CH

PMG3,EA

EA,#30H

PUMOD1,EA

;

(IMOD2) ¬ #2H, KS2–KS7 falling edge select

P7 ¬ input mode

P6.2–P6.3 ¬ input mode

Enable P6 and P7 pull-up resistors

3. When KS4–KS7 are selected (four pins), P7 must be specified as a key strobe signal input:

BITS

SMB

LD

EMB

15

A,#1H

LD

IMOD2,A

EA,#0FH

PMG1,EA

EA,#20H

PUMOD1,EA

;

(IMOD2) ¬ #1H, KS4–KS7 falling edge select

P7 ¬ input mode

LD

Enable P7 pull-up resistor

7-12

KS57C5532/P5532

INTERRUPTS

INTERRUPT FLAGS

There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in-

terrupt, the interrupt master enable flag, which enables or disables all interrupt processing.

Interrupt Master Enable Flag (IME)

The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an IRQx

flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the IME flag

is set to logic one.

The IME flag is located in the IPR register (IPR.3). It can be directly be manipulated by EI and DI instructions,

regardless of the current value of the enable memory bank flag (EMB).

IME

0

IPR.2

IPR.1

IPR.0

Effect of Bit Settings

Inhibit all interrupts

Enable all interrupts

1

Interrupt Enable Flags (IEx)

IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request

flag is set to logic one, an interrupt will not be serviced until its corresponding IEx flag is also enabled.

Interrupt enable flags can be read, written, or tested directly by 1-bit instructions (BITS and BITR) or 4-bit

instructions. IEx flags can be addressed directly at their specific RAM addresses, despite the current value of the

enable memory bank (EMB) flag.

Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses

Address

FB8H

Bit 3

IE4

0

Bit 2

Bit 1

IEB

Bit 0

IRQB

IRQW

IRQT1

IRQT0

IRQS

IRQ0

IRQ4

FBAH

FBBH

FBCH

FBDH

FBEH

FBFH

0

IEW

IET1

IET0

IES

0

IE1

0

IRQ1

0

IE0

IE2

IRQ2

NOTES:

1. IEx refers to all interrupt enable flags.

2. IRQx refers to all interrupt request flags.

3. IEx = 0 is interrupt disable mode.

4. IEx = 1 is interrupt enable mode.

7-13

INTERRUPTS

KS57C5532/P5532

Interrupt Request Flags (IRQx)

Interrupt request flags, are read/write addressable by 1-bit or 4-bit instructions.IRQx flags can be addressed

directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag.

When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then

automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt

request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt

service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary,

follow these guidelines for using IRQx flags:

1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.

2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the

exception of IRQW and IRQ2).

3. If IRQx is set to "1" by software, an interrupt is also generated.

When two interrupts share the same service routine start address, interrupt processing may occur in one of

two ways:

— When only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been

serviced.

— When two interrupts are enabled, the request flag is not automatically cleared so that the user has an

opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared

manually using a BTSTZ instruction.

Table 7-8. Interrupt Request Flag Conditions and Priorities

Pre-condition for IRQx Flag Setting

Interrupt

Source

Internal /

External

Interrupt

Priority

IRQ Flag

Name

INTB

I

Reference time interval signal from basic timer

Both rising and falling edges detected at INT4

Rising or falling edge detected at INT0 pin

Rising or falling edge detected at INT1 pin

1

2

3

4

IRQB

IRQ4

IRQ0

IRQ1

IRQS

INT4

INT0

INT1

INTS

E

I

Completion signal for serial transmit-and-re-

ceive or receive-only operation

INTT0

I

5

6

IRQT0

IRQT1

IRQ2

Signals for TCNT0 and TREF0 registers

match

INTT1

Signals for TCNT1 and TREF1 registers

match

INT2^(note)

INTW

E

I

—

Rising edge detected at INT2 or else a falling

edge is detected at any of the KS0–KS7 pins

Time interval of 0.5 secs or 3.19 msecs

IRQW

NOTE: The quasi-interrupt INT2 is only used for testing incoming signals.

7-14

KS57C5532/P5532

INTERRUPTS

+

PROGRAMMING TIP — Enabling the INTB and INT4 Interrupts

To simultaneously enable INTB and INT4 interrupts:

INTB

DI

BTSTZ

JR

IRQB

INT4

;

IRQB = 1 ?

If no, INT4 interrupt; if yes, INTB interrupt is processed

•

EI

IRET

;

INT4

BITR

IRQ4

;

INT4 is processed

•

EI

IRET

To simultaneously enable INTT0 and INTT1B interrupts:

INTT0

DI

BTSTZ

JR

IRQT0

INTT1B

;

IRQB = 1 ?

If no, INTT1B interrupt; if yes, INTT0 interrupt is

processed

•

EI

IRET

;

INTT1B

BITR

IRQT2

;

INTT1B is processed

•

EI

IRET

7-15

INTERRUPTS

KS57C5532/P5532

NOTES

7-16

KS57C5532/P5532

POWER-DOWN

8

POWER-DOWN

OVERVIEW

The KS57C5532 microcontroller has two power-down modes to reduce power consumption: idle and stop. Idle

mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions must

always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while peripherals

and the oscillation source continue to operate normally.

When

occurs during normal operation or during a power-down mode, a reset operation is initiated and the

CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has

elapsed, normal CPU operation resumes.

In stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hard-

ware components are powered-down. The effect of stop mode on specific peripheral hardware components —

CPU, basic timer, serial I/O, timer/counters, and watch timer — and on external interrupt requests, is detailed in

Table 8-1.

Idle or stop modes are terminated either by a

enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by

, or by an interrupt with the exception of INT0, which are

input, a

normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag are

set to "1", power-down mode is released immediately upon entering power-down mode.

When an interrupt is used to release power-down mode, the operation differs depending on the value of the

interrupt master enable flag (IME):

— If the IME flag = "0", if the power down mode release signal is generated, after releasing the power-down

mode, program execution starts immediately under the instruction to enter power down mode without

execution of interrupt service routine. The interrupt request flag remains set to logic one.

— If the IME flag = "1", if the power down mode release signal is generated, after releasing the power down

mode, two instructions following the instruction to enter power down mode are executed first and the interrupt

service routine is executed, finally program is resumed.

However, when the release signal is caused by INT2 or INTW, the operations is identical to the IME = “0”

condition because INT2 and INTW are a quasi-interrupt.

NOTE

Do not use stop mode if you are using an external clock source because X input must be restricted

in

internally to V

to reduce current leakage

SS

8-1

POWER-DOWN

KS57C5532/P5532

Table 8-1. Hardware Operation During Power-Down Modes

Operation

Stop Mode (STOP)

Idle Mode (IDLE)

CPU clock oscillation stops (system

Clock oscillator

System clock oscillation stops

clock oscillation continues)

Basic timer

Basic timer stops

Basic timer operates (with IRQB set at

each reference interval)

Serial interface

Timer/counter 0

Timer/counter 1

Operates only if external

selected as the serial I/O clock

input is

Operates if a clock other than the CPU

clock is selected as the serial I/O clock

Operates only if TCL0 is selected as the Timer/counter 0 operates

counter clock

Operates only if TCL1 is selected as the Timer/counter 1 operates

counter clock

Watch timer

Watch timer operation is stopped

Watch timer operates

External interrupts

INT0, INT1, INT2, and INT4 are

acknowledged

INT1, INT2, and INT4 are acknowledged;

INT0 is not serviced

CPU

All CPU operations are disabled

Power-down mode

release signal

Interrupt request signals (except INT0)

are enabled by an interrupt enable flag or are enabled by an interrupt enable flag or

by input by input

Interrupt request signals (except INT0)

8-2

KS57C5532/P5532

POWER-DOWN

IDLE MODE TIMING DIAGRAMS

Oscillator

Stabilization

Wait Time

Idle

Istruction

(36.6 ms/3.58 MHz)

RESET

Normal Mode

Idle Mode

Normal Mode

Normal Oscillation

Clock

Signal

Figure 8-1. Timing When Idle Mode is Released by

Idle

Istruction

Mode

Release

Signal

Interrupt Acknowledge (IME = 1)

Normal Mode

Idle Mode

Normal Mode

Normal Oscillation

Clock

Signal

Figure 8-2. Timing When Idle Mode is Released by an Interrupt

8-3

POWER-DOWN

KS57C5532/P5532

STOP MODE TIMING DIAGRAMS

Oscillator

Stabilization

Wait Time

Stop

Istruction

(36.6 ms/3.58 MHz)

RESET

Normal Mode

Idle Mode

Normal Mode

Stop mode

Oscillation

Stops

Oscillation Resumes

Clock

Signal

Figure 8-3. Timing When Stop Mode is Released by

Oscillator

Stabilization

Wait Time

Stop

Istruction

(BMOD Setting)

Mode

Release

signal

INT Ack (Ime=1)

Normal Mode

Idle Mode

Stop mode

Oscillation

Stops

Oscillation Resumes

Clock

Signal

Figure 8-4. Timing When Stop Mode is Released by an Interrupt

8-4

KS57C5532/P5532

POWER-DOWN

+

PROGRAMMING TIP — Reducing Power Consumption for Key Input Interrupt Processing

The following code shows interrupt processing for key inputs to reduce power consumption. In this example, the

system clock source is switched from the main system clock to a subsystem clock:

KEYCLK

DI

CALL

MA2SUB

;

Main system clock ® subsystem clock switch

subroutine

;

SMB

LD

SMB

BITR

BITS

BTSTZ

JR

15

EA,#00H

P4,EA

A,#3H

IMOD2,A

0

IRQ2

IE2

IRQ2

CIDLE

SUB2MA

;

All key strobe outputs to low level

Select KS0–KS7 enable

CLKS1

CIDLE

CALL

;

Subsystem clock ® main system clock switch

;

subroutine

EI

RET

IDLE

NOP

JPS

Engage idle mode

CLKS1

8-5

POWER-DOWN

KS57C5532/P5532

PORT PIN CONFIGURATION FOR POWER-DOWN

The following method describes how to configure I/O port pins to reduce power consumption during power-down

modes (stop, idle):

Condition 1: If the microcontroller is not configured to an external device:

1. Connect unused port pins according to the information in Table 8–2.

2. Disable all pull-up resistors for output pins by making the appropriate modifications to the pull-up resistor

mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be un-

expected surges of current through the pull-up.

3. Disable pull-up resistors for input pins configured to V

DD

or V levels in order to check the current input

SS

option. Reason: If the input level of a port pin is set to V when a pull-up resistor is enabled, it will draw an

SS

unnecessarily large current.

Condition 2: If the microcontroller is configured to an external device and the external device's V

source is

DD

turned off in power-down mode.

1. Connect unused port pins according to the information in Table 8–2.

2. Disable the pull-up resistors of output pins by making the appropriate modifications to the pull-up resistor

mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be un-

expected surges of current through the pull-up.

3. Disable pull-up resistors for input pins configured to V

DD

or V levels in order to check the current input

SS

option. Reason: If the input level of a port pin is set to V when a pull-up resistor is enabled, it will draw an

SS

unnecessarily large current.

4. Disable the pull-up resistors of input pins connected to the external device by making the necessary modi-

fications to the PUMOD register.

5. Configure the output pins that are connected to the external device to low level. Reason: When the external

device's V

source is turned off, and if the microcontroller's output pins are set to high level, V – 0.7 V is

DD

supplied to the V

of the external device through its input pin. This causes the device to operate at the level

– 0.7 V. In this case, total current consumption would not be reduced.

DD

V

DD

6. Determine the correct output pin state necessary to block current pass in according with the external tran-

sistors (PNP, NPN).

8-6

KS57C5532/P5532

POWER-DOWN

RECOMMENDED CONNECTIONS FOR UNUSED PINS

To reduce overall power consumption, please configure unused pins according to the guidelines described in

Table 8-2.

Table 8-2. Unused Pin Connections for Reducing Power Consumption

Pin/Share Pin Names

P0.0 /

Recommended Connection

Input mode: Connect to V

DD

P0.1 / SO

P0.2 / SI

Output mode: No connection

P0.3 / BTCO

Connect to V

DD

P1.0 / INT0–P1.2 / INT2

P1.3 / INT4

Connect to V

SS

Input mode: Connect to V

DD

Output mode: No connection

P2.0 / TCLO0

P2.1 / TCLO1

P2.2 / CLO

P2.3 / BUZ

P3.0 / TCL0

P3.1 / TCL1

P3.2

P3.3

P4.0–P4.3

P5.0–P5.3

P6.0 / KS0–P6.3 / KS3

P7.0 / KS4–P7.3 / KS7

P8.0–P8.3

P9.0–P9.3

P10.0–P10.3

P11.0–P11.3

P13.0–P13.2

Input mode: Connect to V

SS

P12.0–P12.3

Output mode: No connection

DTMF

NC

No connection

Connect to V

SS

8-7

POWER-DOWN

KS57C5532/P5532

NOTES

8-8

KS57C5532/P5532

RESET

9

RESET

OVERVIEW

When a RESET signal is input during normal operation or power-down mode, a hardware RESET operation is

initiated and the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 36.6 ms at

3.579545 MHz has elapsed, normal system operation resumes.

Regardless of when the RESET occurs — during normal operating mode or during a power-down mode — most

hardware register values are set to the RESET values described in Table 9–1. The current status of several

register values is, however, always retained when a RESET occurs during idle or stop mode; If a RESET occurs

during normal operating mode, their values are undefined. Current values that are retained in this case are as

follows:

— Carry flag

— General-purpose registers E, A, L, H, X, W, Z, and Y

— Serial I/O buffer register (SBUF)

Oscillator

Stabilization

Wait Time

(36.6 ms/3.58 MHz)

RESET

Input

Normal Mode or

Operatng Mode

Idle Mode

Power-Down

Mode

Reset Operation

Figure 9-1. Timing for Oscillation Stabilization after RESET

HARDWARE REGISTER VALUES AFTER RESET

Table 9-1 gives you detailed information about hardware register values after a RESET occurs during power-down

mode or during normal operation.

9-1

RESET

KS57C5532/P5532

Table 9-1. Hardware Register Values after RESET

Hardware Component

or Subcomponent

If RESET Occurs During

Power-Down Mode

If RESET Occurs During

Normal Operation

Program counter (PC)

Lower six bits of address 0000H

are transferred to PC13–8, and

Lower six bits of address 0000H

are transferred to PC13–8, and

the contents of 0001H to PC7–0. the contents of 0001H to PC7–0.

Program Status Word (PSW):

Carry flag ©

Values retained

Undefined

Skip flag (SC0–SC2)

0

Interrupt status flags (IS0, IS1)

Bank enable flags (EMB, ERB)

0

Bit 6 of address 0000H in

program memory is transferred to program memory is transferred to

the ERB flag, and bit 7 of the

address to the EMB flag.

the ERB flag, and bit 7 of the

address to the EMB flag.

Stack pointer (SP)

Undefined

Data Memory (RAM):

General registers E, A, L, H, X, W, Z, Y

General-purpose registers

Values retained

Undefined

0, 0

Values retained (note)

Bank selection registers (SMB, SRB)

BSC register (BSC0-BSC3)

0, 0

0

Clocks:

Power control register (PCON)

0

Clock output mode register (CLMOD)

System clock mode register (SCMOD)

Interrupts:

Interrupt request flags (IRQx)

Interrupt enable flags (IEx)

Interrupt priority flag (IPR)

Interrupt master enable flag (IME)

INT0 mode register (IMOD0)

INT1 mode register (IMOD1)

INT2 mode register (IMOD2)

0

NOTE: The values of the 0F8H – 0FDH are not retained when a RESET signal is input.

9-2

KS57C5532/P5532

RESET

Table 9-1. Hardware Register Values after RESET (Continued)

Hardware Component

or Subcomponent

If RESET Occurs During

Power-Down Mode

If RESET Occurs During

Normal Operation

I/O Ports:

Output buffers

Off

0

Off

0

Output latches

Port mode flags (PM)

0

Pull-up resistor mode reg

(PUMOD1/2)

0

Basic Timer:

Count register (BCNT)

Mode register (BMOD)

Mode register (WDMOD)

Counter clear flag (WDTCF)

Undefined

0

A5H

0

A5H

0

Timer/Counters 0 and 1:

Count registers (TCNT0/1)

0

Reference registers (TREF0/TREF1)

Mode registers (TMOD0/TMOD1)

Output enable flags (TOE0/1)

FFH,FFFFH

0

Watch Timer:

Watch timer mode register (WMOD)

Serial I/O interface:

0

SIO mode resister (SMOD)

SIO interface buffer (SBUF)

0

Values retained

Undefined

N-Channel Open-Drain Mode Register:

PNE1

0

DTMF Generator:

DTMF mode register (DTMR)

9-3

RESET

KS57C5532/P5532

NOTES

9-4

KS57C5532/P5532

I/O PORTS

10 I/O PORTS

OVERVIEW

The KS57C5532 has 1 input port and 13 I/O ports. Pin addresses for all I/O ports are mapped in bank 15 of the

RAM. The contents of I/O port pin latches can be read, written, or tested at the corresponding address using bit

manipulation instructions.

There are total of 4 input pins and 51 configurable I/O pin for a maximum number of 55 I/O pins.

Port Mode Flags

Port mode flags (PM) are used to configure I/O ports 0, 4, 5, and 7 (port mode group 1), ports 2 and 3 (port mode

group 2), ports 6 and 8 (port mode group 3), and ports 9, 10, 11, 12, and 13 (port mode group 4) to input or

output mode by setting or clearing the corresponding I/O buffer. PM flags are grouped in four 8-bit registers, and

are addressable by 8-bit write instructions only.

PUMOD Control Register

The pull-up register mode registers (PUMOD1 and 2) are 8-bit registers used to assign internal pull-up resistors

by software to specific I/O ports and pull-down resistors to port 12.

When configurable I/O ports 0, 2, 3, 6, 8, 9 10,11,12, and 13 serves as an output pin, its assigned pull-up/down

resistor is automatically disabled, even though the pin's pull-up/down resistor is enabled by a corresponding bit

setting in the pull-up resistor mode register (PUMOD).

PUMOD1 and 2 are addressable by 8-bit write instructions only.

clears PUMOD register values to logic zero,

automatically disconnecting all software-assignable port pull-up/down resistors.

Table 10-1. I/O Port Overview

Port

I/O

Pins

Pin Names

Address

Function Description

4-bit I/O port.

0

I/O

4

P0.0–P0.3

FF0H

1-bit and 4-bit read/write and test is possible.

Individual pins are software configurable as

input or output.

4-bit pull-up resistors are assignable by

software.; pull-up resistors are automatically

disabled for output pins.

1

I

4

P1.0–P1.3

FF1H

4-bit input port.

1-bit and 4-bit read and test is possible.

4-bit pull-up resistors are software assignable

by software to port 1.

2

3

I/O

4

P2.0–P2.3

P3.0–P3.3

FF2H

FF3H

Same as port 0.

10-1

I/O PORTS

KS57C5532/P5532

Table 10-1. I/O Port Overview (Continued)

Port

I/O

Pins

Pin Names

Address

Function Description

4-bit I/O ports.

4, 5

I/O

8

P4.0–P4.3

P5.0–P5.3

FF4H

FF5H

1-bit and 4-bit read/write/test is possible.

4-bit pull-up resisters are software assignable

to input pins and are automatically disable for

output pins. N-channel open-drain or push-pull

output can be selected by software.

Ports 4 and 5 can be paired to support 8-bit

data transfer.

6, 7

I/O

8

P6.0–P6.3

P7.0–P7.3

FF6H

FF7H

4-bit I/O ports.

1-bit and 4-bit read/write/test is possible.

Port 6 pins are individually software

configurable as input or output.

4-bit pull-up resistors are software assignable;

pull-up resistors are automatically disabled for

output pins.

Ports 6 and 7 can be paired for 8-bit data

transfer.

8

9

I/O

4

P8.0–P8.3

P9.0–P9.3

FF8H

FF9H

Same as port 0.

4-bit I/O port.

1-bit and 4-bit read/write and test is possible.

4-bit pull-up resistors are assignable by

software.; pull-up resistors are automatically

disabled for output pins.

10, 11

12

I/O

4

P10.0–P10.3

P12.0–P12.3

FFAH

FFBH

Same as port 9.

Ports 10 and 11 can be paired to support 8-bit

data transfer.

FFCH

4-bit I/O port.

1-bit and 4-bit read/write and test is possible.

Individual pins are software configurable as in-

put or output.

4-bit pull-down resistors are assignable by

software.; pull-down resistors are automatically

disabled for output pins.

13

I/O

4

P13.0–P13.2

FFDH

3-bit I/O port.

1-bit and 4-bit read/write and test is possible.

3-bit pull-up resistors are assignable by

software.; pull-up resistors are automatically

disabled for output pins.

10-2

KS57C5532/P5532

Instruction Type

I/O PORTS

Table 10-2. Port Pin Status During Instruction Execution

Example

Input Mode Status

Output Mode Status

1-bit test

BTST P0.1

Input or test data at each pin

Input or test data at output latch

1-bit input

4-bit input

8-bit input

LDB

LD

C,P1.3

A,P7

EA,P4

1-bit output

BITR P2.3

Output latch contents undefined

Output pin status is modified

4-bit output

8-bit output

LD

P2,A

P6,EA

Transfer accumulator data to the

output latch

Transfer accumulator data to the

output pin

PORT MODE FLAGS (PM FLAGS)

Port mode flags (PM) are used to configure I/O ports 0 and 2–13 to input or output mode by setting or clearing

the corresponding I/O buffer.

For convenient program reference, PM flags are organized into four groups — PMG1, PMG2, PMG3, and PMG4

as shown in Table n. PM flags are addressable by 8-bit write instructions only.

When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output.

port mode flags to logic zero, automatically configuring the corresponding I/O ports to input mode.

clears all

Table 10-3. Port Mode Group Flags

PM Group ID

Address

FE8H

FE9H

FEAH

FEBH

FECH

FEDH

FEEH

FEFH

Bit 3

PM0.3

PM7

Bit 2

PM0.2

"0"

Bit 1

PM0.1

PM5

Bit 0

PMG1

PM0.0

PM4

PMG2

PMG3

PMG4

PM2.3

PM3.3

PM6.3

PM8.3

PM12.3

PM13

PM2.2

PM3.2

PM6.2

PM8.2

PM12.2

PM11

PM2.1

PM3.1

PM6.1

PM8.1

PM12.1

PM10

PM2.0

PM3.0

PM6.0

PM8.0

PM12.0

PM9

NOTE: If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode: PM0.0 for

P0.0 PM4 for port 4 and so on.. All flags are cleared to "0" following

.

10-3

I/O PORTS

KS57C5532/P5532

+

PROGRAMMING TIP — Configuring I/O Ports to Input or Output

Configure P0.3 and P2 as an output port and the other ports as input ports:

BITS

SMB

LD

EMB

15

EA,#08H

PMG1,EA

EA,#0FH

PMG2,EA

EA,#00H

PMG3,EA

PMG4,EA

;

P0.3 ¬ Output, P0.0–0.2, P4, P5, P7 ¬ Input

P2 ¬ Output, P3 ¬ Input

;

P6, P8 ¬ Input

P9, P10, P11, P12, P13 ¬ Input

10-4

KS57C5532/P5532

I/O PORTS

PULL-UP RESISTOR MODE REGISTER (PUMOD)

The pull-up resistor mode registers (PUMOD1 and 2) are 8-bit registers used to assign internal pull-up resistors

by software to specific I/O ports and pull-down resistor to port 12. When a configurable I/O port pin is used as an

output pin, its assigned pull-up resisters automatically disabled, even though the pin’s pull-up is enabled by a

corresponding PUMOD bit setting.

PUMOD1 and PUMOD2 are addressable by 8-bit write instructions only.

clears PUMOD register values to

logic zero, automatically disconnecting all software-assignable port pull-up and down resistors.

Table 10-4. Pull-up Resistor Mode Register (PUMOD) Organization

PUMOD ID

Address

FDCH

FDDH

FDEH

FDFH

Bit 3

PUR3

PUR9

PUR13

"0"

Bit 2

PUR2

PUR8

PDR12

"0"

Bit 1

PUR1

PUR7

PUR11

PUR5

Bit 0

PUR0

PUR6

PUR10

PUR4

PUMOD1

PUMOD2

NOTE: When bit = "1", pull-up resistors are assigned to the corresponding I/O port: PUR3 for port 3, PUR2 for port 2, and so

on. If bit PDR12 is set to 1, pull-down resistors are assigned to port 12.

+

PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-up Resistors

P6–P9 enable pull-up resistors, P0–P3 disable pull-up resistors.

BITS

SMB

LD

EMB

15

EA,#0F0H

PUMOD1,EA

LD

; P6–P9 enable

N-CHANNEL OPEN DRAIN MODE REGISTER (PNE)

The n-channel open-drain mode register (PNE1) is ports 4, 5 to n-channel, open-drain or as push-pull outputs,

when a bit in the PNE resister is set to “1”, the corresponding output pin is configured to n-channel open-drain;

when set to “0”, the output pin is configured to push-pull. The all PNE resisters consist of 8-bit resisters only.

Table 10-5. N-Channel Open Drain Move Register (PNE) Organization

PNE ID

Address

FDAH

Bit 3

Bit 2

Bit 1

Bit 0

PNE4.0

PNE.0

PNE1

PNE4.3

PNE5.3

PNE4.2

PNE5.2

PNE4.1

PNE5.1

FDBH

10-5

I/O PORTS

KS57C5532/P5532

PORT 0 CIRCUIT DIAGRAM

P0.0

SCK Latch

P0.1

Latch

P0.2 P0.3

Latch Latch

BTCO

SO

VDD

SCK

SI

PUR0

PM0.3

PM0.2

PM0.1

PM0.0

P0.0/SCK

P0.1/SO

P0.2/SI

P0.3/BTCO

NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled,

even though the port's pull-up resistor is enabled by bit settings to the pull-up

resistor mode register (PUMOD).

Figure 10-1. Port 0 Circuit Diagram

10-6

KS57C5532/P5532

I/O PORTS

PORT 1 CIRCUIT DIAGRAM

VDD

INT0 INT1 INT2 INT4

PUR1.0

PUR1.1

PUR1.2

PUR1.3

IMOD0

N/R

Circuit

P1.0/INT0

P1.1/INT1

P1.2/INT2

P1.3/INT4

Figure 10-2. Port 1 Circuit Diagram

10-7

I/O PORTS

KS57C5532/P5532

PORT 0, 2, 3, 6, 8 CIRCUIT DIAGRAM

VDD

x = port number (0, 2, 3, 6, 8)

PURx

PMx.3

PMx.2

PMx.1

PMx.0

Px.0

Px.1

Px.2

Px.3

Output

Latch

1, 4, 8

MUX

1, 4, 8

NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though

the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

Figure 10-3. Port 0, 2, 3, 6, and 8 Circuit Diagram

10-8

KS57C5532/P5532

I/O PORTS

PORT 4, 5 CIRCUIT DIAGRAM

VDD

b = 4, 5

P-CH

PUMOD2.b

8

PNE

P-CH

Output

Latch

1, 4, 8

8

N-CH

PMx.b

x = 4, 5

b = 0, 1, 2, 3

VSS

MUX

Figure 10-4. Port 4 and 5 Circuit Diagram

10-9

I/O PORTS

KS57C5532/P5532

PORT 7, 9, 10, 11, 13 CIRCUIT DIAGRAM

VDD VDD

PURx

x = (7, 9,10, 11,13 )

PMx

8

Px.0

Px.1

Px.2

Px.3

Output

Latch

1, 4, 8

MUX

1, 4, 8

Figure 10-5. Port 7, 9, 10, 11, and 13 Circuit Diagram

10-10

KS57C5532/P5532

I/O PORTS

PORT 12 CIRCUIT DIAGRAM

(b =0, 1, 2, 3 )

PM12.b

8

Output

Latch

P12.b

1, 4, 8

PDR12

MUX

1, 4, 8

NOTE: When a port pin acts as an output, its pull-down resistor is automatically disabled,

even though the ports pull-down resistor is enabled by bit settings to the PUMOD

register.

Figure 10-6. Port 12 Circuit Diagram

10-11

I/O PORTS

KS57C5532/P5532

NOTES

10-12

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

11 TIMERS and TIMER/COUNTERS

OVERVIEW

The KS57C5532 microcontroller has four timer and timer/counter modules:

— 8-bit basic timer (BT)

— 8-bit timer/counters (TC0, 1)

— Watch timer (WT)

The 8-bit basic timer (BT) is the microcontroller's main interval timer. It generates an interrupt request at a fixed

time interval when the appropriate modification is made to its mode register. When the contents of the basic

timer counter register BCNT overflows, a pulse is output to the basic timer output pin, BTCO. The basic timer

also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time when stop mode

is released by an interrupt and after a

.

The 8-bit timer/counters (TC0, 1) are programmable timer/counters that are used primarily for event counting and

for clock frequency modification and output. In addition, TC0 generates a clock signal that can be used by the

serial I/O interface.

The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency

divider circuit. Watch timer functions include real-time and watch-time measurement, system clock interval

timing, and buzzer output generation.

11-1

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

BASIC TIMER (BT)

OVERVIEW

The 8-bit basic timer (BT) has six functional components:

— Clock selector logic

— 4-bit mode register (BMOD)

— 8-bit counter register (BCNT)

— Output enable flag (BOE)

— 8-bit watchdog timer mode register (WDMOD)

— Watchdog timer counter clear flag (WDTCF)

The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.

Timer pulses are output from the basic timer's counter register BCNT to the output pin BTCO when an overflow

occurs in the counter register BCNT. You can use the basic timer as a "watchdog" timer for monitoring system

events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and after a

Bit settings in the basic timer mode register BMOD turns the BT module on and off, selects the input clock

frequency, and controls interrupt or stabilization intervals.

.

Interval Timer Function

The basic timer's primary function is to measure elapsed time intervals. The standard time interval is equal to

256 basic timer clock pulses.

To restart the basic timer, one bit setting is required: bit 3 of the mode register BMOD is set to logic one. The

input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values

to BMOD.2–BMOD.0.

The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the

frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs (

255). An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated

time interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting

continues from 00H.

Watchdog Timer Function

The basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation

error. For this purpose, instruction that clear the watchdog timer (BITS WDTCF) should be executed at proper

points in a program within given period. If an instruction that clears the watchdog timer is not executed within the

given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset

status. An operation of watchdog timer is as follows:

— Write some values (except #5AH) to watchdog timer mode register, WDMOD

— If WDCNT overflows, system reset is generated.

Oscillation Stabilization Interval Control

Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also

determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when stop

mode is released by an interrupt. When a

, the standard stabilization interval for system clock

oscillation after a the

is 36.6 ms at 3.58 MHz.

11-2

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

Table 11-1. Basic Timer Register Overview

Description Size RAM

Register Type

Name

Addressing

Mode

Reset

Value

Address

BMOD

Control

Controls the clock frequency (mode) 4-bit F85H

of the basic timer; also, the

oscillation stabilization interval after

stop mode release or RESET

4-bit write-only;

BMOD.3: 1-bit

writeable

“0”

U ^(note)

BCNT

BOE

Counter Counts clock pulses matching the

BMOD frequency setting

8-bit F86H–F87H 8-bit read-only

Flag

Controls output of basic timer

output latch to the BTCO pin

1-bit F92H.1 1-, 4-bit read/write “0”

WDMOD Control

WDTCF Control

Controls watchdog timer operation. 8-bit F98H–F99H 8-bit write-only

A5H

Clears the watchdog timer’s

counter.

1-bit F9AH.3

1-, 4-bit write-only “0”

NOTE: ’U' means the value is undetermined after a

.

11-3

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

"Clear" Signal

Clear

BCNT

Clear

IRQB

BITS

Instruction

BMOD.3

BMOD.2

BMOD.1

BMOD.0

Interrupt

Request

Overflow

Clock

Selector

BCNT

IRQB

4

1-Bit R/W

CPU Clock

Start Signal

8

(Power-Down Release)

Clock Input

1 Pulse Period = BT Input Clock 2 ⁸(1/2 Duty)

3-Bit Counter

Overflow

WDCNT

Reset Signal

Generation

RESET

Clear

WDMOD

8

WDTCF

BITS

DELAY

(note)

Stop

Clear

WAIT

RESET

Instruction

NOTES:

RESET

1. WAIT means stabilization time after

or stabilization time after stop mode release.

2. The RESET signal can be generated if the WDMOD is toggled for 8 times where "toggle"

means change from 5AH to other value and vice versa.

3. Refer to Table 11 - 3.

Figure 11-1. Basic Timer Circuit Diagram

11-4

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

BASIC TIMER MODE REGISTER (BMOD)

The basic timer mode register, BMOD, is a 4-bit write-only register. Bit 3, the basic timer start control bit, is also

1-bit addressable. All BMOD values are set to logic zero following interrupt request signal generation is

set to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following effects:

— Restart the basic timer;

— Control the frequency of clock signal input to the basic timer;

— Determine time interval required for clock oscillation to stabilize following the release of stop mode by an

interrupt.

By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency

12

5

during program execution. Four BT frequencies, ranging from fxx/2 to fxx/2 , are selectable. Since BMOD's

12

reset value is logic zero, the default clock frequency setting is fxx/2

.

The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set

to logic one by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT interrupt

request flag (IRQB) are both cleared to logic zero, and timer operation is restarted.

The combination of bit settings in the remaining three registers — BMOD.2, BMOD.1, and BMOD.0 — determine

the clock input frequency and oscillation stabilization interval.

Table 11-2. Basic Timer Mode Register (BMOD) Organization

BMOD.3

Basic Timer Start Control Bit

1

Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0"

BMOD.2

BMOD.1

BMOD.0

Basic Timer Input

Clock

Interrupt Interval Time

(wait time when stop mode is released)

fxx/2¹²(0.87 kHz)

fxx/2⁹(6.99 kHz)

fxx/2⁷(27.9 kHz)

fxx/2⁵(111.8 kHz)

2²⁰/fxx (292.9 ms)

2¹⁷/fxx (36.6 ms)

2¹⁵/fxx (9.15 ms)

2¹³/fxx (2.29 ms)

0

1

0

1

0

1

0

1

NOTES:

1. Clock frequencies and interrupt interval time assume a system oscillator clock frequency (fxx) of 3.579545 MHz.

2. fxx = system clock frequency.

3. Wait time is the time required to stabilize clock signal oscillation after stop mode is released.

4. The standard stabilization time for system clock oscillation following a

is 36.6 ms at 3.579545 MHz.

11-5

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

BASIC TIMER COUNTER (BCNT)

BCNT is an 8-bit counter for the basic timer. It can be addressed by 8-bit read instructions.

leaves the

BCNT counter value undetermined. BCNT is automatically cleared to logic zero whenever the BMOD register

control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock pulse of the

frequency determined by the current BMOD bit settings is detected.

When BCNT has incremented to hexadecimal 'FFH' ( 255 clock pulses), it is cleared to '00H' and an overflow is

generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt

request is generated, BCNT immediately resumes counting incoming clock signals.

NOTE

Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while

the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the

latter value as valid data. Until the results of the consecutive reads match, however, the read operation

must be repeated until the validation condition is met.

BASIC TIMER OUTPUT ENABLE FLAG (BOE)

The basic timer output enable flag (BOE) enables and disables basic timer output to the BTCO pin at I/O port 0

(P0.3). When BOE is logic zero, basic timer output to the BTCO pin is disabled; when it is logic one, BT output to

the BTCO pin is enabled. A

clears the BOE flag to "0", disabling basic timer output to the BTCO pin. When

the BOE flag is set to "1" and the BCNT register overflows, the overflow signal is sent to the BTCO pin. BOE can

be addressed by 1-bit read and write instructions.

Bit 3

Bit 2

Bit 1

BOE

Bit 0

0

F92H

TOE1

TOE0

BASIC TIMER OPERATION SEQUENCE

The basic timer's sequence of operations may be summarized as follows:

1. Set BMOD.3 to logic one to restart the basic timer

2. BCNT is then incremented by one after each clock pulse corresponding to BMOD selection

3. BCNT overflows if BCNT 255 (BCNT = FFH)

4. When an overflow occurs, the IRQB flag is set by hardware to logic one

5. The interrupt request is generated

6. BCNT is then cleared by hardware to logic zero

7. Basic timer resumes counting clock pulses

11-6

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Using the Basic Timer

1. To read the basic timer count register (BCNT):

BITS

SMB

LD

EMB

15

BCNTR

EA,BCNT

YZ,EA

EA,BCNT

EA,YZ

BCNTR

CPSE

JR

2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 36.6 ms:

BITS

SMB

LD

EMB

15

A,#0BH

BMOD,A

LD

;

Wait time is 36.6 ms

NOP

STOP

NOP

Set stop power-down mode

NORMAL

STOP MODE

IDLE MODE

(36.6 ms)

OPERATING MODE

CPU

OPERATION

STOP

INSTRUCTION

STOP MODE IS

RELEASED BY

INTERRUPT

3. To set the basic timer interrupt interval time to 2.29 ms (at 3.579545 MHz):

BITS

SMB

LD

EMB

15

A,#0FH

BMOD,A

LD

EI

BITS

IEB

;

Basic timer interrupt enable flag is set to "1"

4. Clear BCNT and the IRQB flag and restart the basic timer:

BITS

SMB

BITS

EMB

15

BMOD.3

11-7

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

WATCHDOG TIMER MODE REGISTER (WDMOD)

The watchdog timer mode register, WDMOD, is a 8-bit write-only register. WDMOD register controls to enable or

disable the watchdog function. WDMOD values are set to logic “A5H” following RESET and this value enables the

watchdog timer. Watchdog timer is set to the longest interval because BT overflow signal is generated with the

longest interval.

WDMOD

Watchdog Timer Enable/Disable Control

Disable watchdog timer function

Enable watchdog timer function

5AH

Any other value

WATCHDOG TIMER COUNTER (WDCNT)

The watchdog timer counter, WDCNT, is a 3-bit counter. WDCNT is automatically cleared to logic zero, and

restarts whenever the WDTCF register control bit is set to “1”. RESET, stop, and wait signal clears the WDCNT to

logic zero also.

WDCNT increments each time a clock pulse of the overflow frequency determined by the current BMOD bit

setting is generated. When WDCNT has incremented to hexadecimal ‘07H’, it is cleared to ‘00H’ and an overflow

is generated. The overflow causes the system RESET. When the interrupt request is generated, BCNT immediately

resumes counting incoming clock signals.

WATCHDOG TIMER COUNTER CLEAR FLAG (WDTCF)

The watchdog timer counter clear flag, WDTCF, is a 1-bit write instruction. When WDTCF is set to one, it clears

the WDCNT to zero and restarts the WDCNT. WDTCF register bits 2–0 are always logic zero.

Table 11-3. Watchdog Timer Interval Time

BMOD

x000b

BT Input Clock

fxx/2¹²

WDCNT Input Clock

fxx/(2¹²´ 2⁸)

fxx/(2⁹´ 2⁸)

WDT Interval Time

(7–8) ´ (2¹²´ 2⁸) / fxx = 1.75–2 sec

(7–8) ´ (2⁹´ 2⁸) / fxx = 218.7–250 ms

(7–8) ´ (2⁷´ 2⁸) / fxx = 54.6–62.5 ms

(7–8) ´ (2⁵´ 2⁸) / fxx = 13.6–15.6 ms

fxx/2⁹

x011b

x101b

x111b

fxx/2⁷

fxx/(2⁷´ 2⁸)

fxx/2⁵

fxx/(2⁵´ 2⁸)

NOTES:

1. Clock frequencies assume a system oscillator clock frequency (fx) of 4.19 MHz

2. fxx = system clock frequency.

3. When the watchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to “0”, the BCNT value is not

cleared but increased continuously. As a result, the 3-bit counter of the watchdog timer (WDCNT) can be increased

by 1. For example, when the BMOD value is x000b and the watchdog timer is enabled, the watchdog timer interval time

3

12

8

3

12

8

is from 2 ´ 2 ´ 2 /fxx to (2 –1) ´ 2 ´ 2 /fxx.

11-8

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Using the Watchdog Timer

RESET

DI

LD

EA,#00H

SP,EA

·

LD

A,#0DH

;

WDCNT input clock is 7.82 ms

LD

BMOD,A

·

MAIN

BITS

WDTCF

MAIN

;

Main routine operation period must be shorter than

watchdog-timer’s period

·

JP

11-9

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

8-BIT TIMER/COUNTERS 0 AND 1 (TC0, 1)

OVERVIEW

The KS57C5532's TC0 and TC1 are identical except that they have different counter clock sources, which are

controlled by the TMODn register. Timer/counters 0 and 1 (TC0, 1) are used to count system 'events' by

identifying the transition (high-to-low or low-to-high) of incoming square wave signals. To indicate that an event

has occurred, or that a specified time interval has elapsed, TC generates an interrupt request. By counting signal

transitions and comparing the current counter value with the reference register value, TC can be used to measure

specific time intervals.

TC has a reloadable counter that consists of two parts: an 8-bit reference register, TREFn (n = 0, 1) into which

you write the counter reference value, and an 8-bit counter register ,TCNTn (n = 0, 1) whose value is

automatically incremented by counter logic.

8-bit mode register, TMODn (n = 0, 1), is used to activate the timer/counter and to select the basic clock

frequency to be used for timer/counter operations. To dynamically modify the basic frequency, new values can be

loaded into the TMODn register during program execution.

TC FUNCTION SUMMARY

8-bit programmable timer

External event counter

Generates interrupts at specific time intervals based on the selected clock fre-

quency.

Counts various system "events" based on edge detection of external clock sig-

nals at the TC input pin, TCLn (n = 0, 1).

Arbitrary frequency output

External signal divider

Outputs clock frequencies to the TC output pin, TCLOn (n = 0, 1).

Divides the frequency of an incoming external clock signal according to a

modifiable reference value (TREFn), and outputs the modified frequency to the

TCLOn pin.

Serial I/O clock source

TC0 can output a modifiable clock signal for use as the

clock source.

11-10

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

TC COMPONENT SUMMARY

Mode register (TMODn)

Activates the timer/counter and selects the internal clock frequency or the

external clock source at the TCLn pin.

Reference register (TREFn)

Counter register (TCNTn)

Clock selector circuit

8-bit comparator

Stores the reference value for the desired number of clock pulses between in-

terrupt requests.

Counts internal or external clock pulses based on the bit settings in TMODn

and TREFn.

Together with the mode register (TMODn), lets you select one of four internal

clock frequencies or an external clock.

Determines when to generate an interrupt by comparing the current value of the

counter register (TCNTn) with the reference value previously programmed into

the reference register (TREFn).

Output latch (TOLn)

Where a TC clock pulse is stored pending output to the serial I/O circuit or to

the TC output pin, TCLOn.

When the contents of the TCNTn and TREFn registers coincide, the

timer/counter interrupt request flag (IRQTn) is set to "1", the status of TOLn is

inverted, and an interrupt is generated.

Output enable flag (TOEn)

Must be set to logic one before the contents of the TOLn latch can be output to

TCLOn.

Interrupt request flag (IRQTn) Cleared when TC operation starts and the TC interrupt service routine is

executed and set to one whenever the counter value and reference value

coincide.

Interrupt enable flag (IETn)

Must be set to logic one before the interrupt requests generated by

timer/counters can be processed.

Table 11-4. TC Register Overview

Register

Name

Type

Description

Size

RAM

Address

Addressing

Mode

Reset

Value

F90H–F91H

FA0H–FA1H

8-bit write-

only;

(TMODn.3 is

also 1-bit

writeable)

TMOD0

TMOD1

Control

Controls TC0 and 1 enable/disable 8-bit

(bit 2); clears and resumes

counting operation (bit 3); sets

input clock and clock frequency

(bits 6–4)

"0"

F94H–F95H

FA4H–FA5H

8-bit

read-only

TCNT0

TCNT1

Counter

Reference

Flag

Counts clock pulses matching the

TMODn frequency setting

8-bit

1-bit

"0"

FFH

"0"

F96H–F97H

FA8H–FA9H

8-bit

write-only

TREF0

TREF1

Stores reference value for the

timer/counters interval setting

F92H.2

F92H.3

1/4-bit

read/write

TOE0

TOE1

Controls timer/counters output to

the TCLOn pin

11-11

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

Clocks

4

TCLn

8

TMOD1.7

TMOD1.6

8-Bit

Comparator

TCNTn

TREFn

Clock

Selector

8

TMOD1.5

TMOD1.4

TMOD1.3

TMOD1.2

TMOD1.1

TMOD1.0

Clear

Inverted

TOLn

Clear

Set

Clear

IRQTn

Serial

I/O

TCLOn

PM2.n

P2.n Latch

TOEn

Figure 11-2. TC Circuit Diagram

TC ENABLE/DISABLE PROCEDURE

Enable Timer/Counter

— Set TMODn.2 to logic one

— Set the TC interrupt enable flag IETn to logic one

— Set TMODn.3 to logic one

TCNTn, IRQTn, and TOLn are cleared to logic zero, and timer/counter operation starts.

Disable Timer/Counter

— Set TMODn.2 to logic zero

Clock signal input to the counter register TCNTn is halted. The current TCNTn value is retained and can be read

if necessary.

11-12

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

TC PROGRAMMABLE TIMER/COUNTER FUNCTION

Timer/counters can be programmed to generate interrupt requests at various intervals based on the selected

system clock frequency. Its 8-bit TC mode register TMODn is used to activate the timer/counter and to select the

clock frequency. The reference register TREFn stores the value for the number of clock pulses to be generated

between interrupt requests. The counter register, TCNTn, counts the incoming clock pulses, which are compared

to the TREFn value as TCNTn is incremented. When there is a match (TREFn = TCNTn), an interrupt request is

generated.

To program timer/counter to generate interrupt requests at specific intervals, choose one of four internal clock

frequencies (divisions of the system clock, fxx) and load a counter reference value into the reference register. The

count register is incremented each time an internal counter pulse is detected with the reference clock frequency

specified by TMODn.4–TMODn.6 settings. To generate an interrupt request, the TC interrupt request flag (IRQTn)

is set to logic one, the status of TOLn is inverted, and the interrupt is generated. The content of the counter

register is then cleared to 00H and TC continues counting. The interrupt request mechanism for TC includes an

interrupt enable flag (IETn) and an interrupt request flag (IRQTn).

TC OPERATION SEQUENCE

The general sequence of operations for using TC can be summarized as follows:

1. Set TMODn.2 to "1" to enable TC0 and 1

2. Set TMODn.6 to "1" to enable the system clock (fxx) input

n

3. Set TMODn.5 and TMODn.4 bits to desired internal frequency (fxx/2 )

4. Load a value to TREFn to specify the interval between interrupt requests

5. Set the TC interrupt enable flag (IETn) to "1"

6. Set TMODn.3 bit to "1" to clear TCNTn, IRQTn, and TOLn, and start counting

7. TCNTn increments with each internal clock pulse

8. When the comparator shows TCNTn = TREFn, the IRQTn flag is set to "1"

9. Output latch (TOLn) logic toggles high or low

10. Interrupt request is generated

11. TCNTn is cleared to 00H and counting resumes

12. Programmable timer/counter operation continues until TMODn.2 is cleared to "0".

11-13

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

TC EVENT COUNTER FUNCTION

Timer/counters can monitor or detect system 'events' by using the external clock input at the TCLn pin as the

counter source. The TC mode register selects rising or falling edge detection for incoming clock signals. The

counter register is incremented each time the selected state transition of the external clock signal occurs.

With the exception of the different TMODn.4–TMODn.6 settings, the operation sequence for TC's event counter

function is identical to its programmable timer/counter function. To activate the TC event counter function,

— Set TMODn.2 to "1" to enable TC;

— Clear TMODn.6 to "0" to select the external clock source at the TCLn pin;

— Select TCLn edge detection for rising or falling signal edges by loading the appropriate values to TMODn.5

and TMODn.4.

— P3.0 and P3.1 must be set to input mode.

Table 11-5. TMODn Settings for TCLn Edge Detection

TMODn.5

TMODn.4

TCLn Edge Detection

Rising edges

0

1

Falling edges

11-14

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

TC CLOCK FREQUENCY OUTPUT

Using timer/counters, a modifiable clock frequency can be output to the TC clock output pin, TCLOn. To select

the clock frequency, load the appropriate values to the TC mode register, TMODn. The clock interval is selected

by loading the desired reference value into the reference register TREFn. In summary, the operational sequence

required to output a TC-generated clock signal to the TCLOn pin is as follows:

1. Load a reference value to TREFn.

2. Set the internal clock frequency in TMODn.

3. Initiate TCn clock output to TCLOn (TMODn.2 = "1").

4. Set port 2 mode flag (PM2.0 and PM 2.1) to "1".

5. Set P2.0 and P2.1 output latches to "0".

6. Set TOEn flag to "1".

Each time TCNTn overflows and an interrupt request is generated, the state of the output latch TOLn is inverted

and the TC-generated clock signal is output to the TCLOn pin.

+

PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin

Output a 30 ms pulse width signal to the TCLO0 pin:

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#68H

TREF0,EA

EA,#4CH

TMOD0,EA

EA,#01H

PMG2,EA

P2.0

;

P2.0 ¬ output mode

P2.0 clear

TOE0

11-15

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

TC0 SERIAL I/O CLOCK GENERATION

Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter

and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register,

SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface.

Use TMOD0 and TREF0 register settings to select the frequency and interval of the TC0 clock signals to be used

as

input to the serial interface. The generated clock signal is then sent directly to the serial I/O clock selector

circuit — not through the port 2.0 latch and TCLO0 pin (the TOE0 flag may be disabled).

TC EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC reference register, TREFn, you

can divide the incoming clock signal by the TREFn value and then output this modified clock frequency to the

TCLOn pin. The sequence of operations used to divide external clock input can be summarized as follows:

1. Load a signal divider value to the TREFn register

2. Clear TMODn.6 to "0" to enable external clock input at the TCLn pin

3. Set TMODn.5 and TMODn.4 to desired TCLn signal edge detection

4. Set port 2 mode flag (PM2.0, PM2.1) to output ("1")

5. Set P2.0 and P2.1 output latches to "0"

6. Set TOEn flag to "1" to enable output of the divided frequency to the TCLOn pin

+

PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin

Output external TCL0 clock pulse to the TCLO0 pin (divide by four):

External (TCL0)

Clock Pulse

TCLO0

Output Pulse

BITS

SMB

LD

BITR

BITS

EMB

15

EA,#01H

TREF0,EA

EA,#0CH

TMOD0,EA

EA,#01H

PMG2,EA

P2.0

;

P2.0 ¬ output mode

P2.0 clear

TOE0

TC MODE REGISTER (TMODn)

TMODn are the 8-bit mode control registers for timer/counter 0 and 1. They are addressable by 8-bit write

11-16

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

instructions. One bit, TMODn.3, is also 1-bit writeable.

operations.

clears all TMODn bits to logic zero and disables TC

F90H

F91H

TMOD0.3

"0"

TMOD0.2

TMOD0.6

"0"

TMOD0

TMOD1

TMOD0.5

TMOD0.4

FA0H

FA1H

TMOD1.3

"0"

TMOD1.2

TMOD1.6

"0"

TMOD1.5

TMOD1.4

TMODn.2 is the enable/disable bit for timer/counter 0 and 1. When TMODn.3 is set to "1", the contents of

TCNTn, IRQTn, and TOLn are cleared, counting starts from 00H, and TMODn.3 is automatically reset to "0" for

normal TC operation. When TC operation stops (TMODn.2 = "0"), the contents of the counter register TCNTn are

retained until TC is re-enabled.

The TMODn.6, TMODn.5, and TMODn.4 bit settings are used together to select the TC clock source. This

selection involves two variables:

— Synchronization of timer/counter operations with either the rising edge or the falling edge of the clock signal

input at the TCLn pin, and

— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in

internal TC operation.

Table 11-6. TC Mode Register (TMODn) Organization

Bit Name

TMODn.7

TMODn.6

TMODn.5

TMODn.4

TMODn.3

Setting

Resulting TC0 Function

Address

0

Always logic zero

F91H (TMOD0)

FA1H (TMOD1)

0,1

Specify input clock edge and internal frequency

1

Clear TCNTn, IRQTn, and TOLn and resume counting

immediately (This bit is automatically cleared to logic zero

immediately after counting resumes.)

F90H (TMOD0)

FA0H (TMOD1)

TMODn.2

0

1

0

Disable timer/counter; retain TCNTn contents

Enable timer/counter

TMODn.1

TMODn.0

Always logic zero

11-17

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

Table 11-7. TMODn.6, TMODn.5, and TMODn.4 Bit Settings

TMODn.6

TMODn.5

TMODn.4

TC0 Counter Source

TC1 Counter Source

0

External clock input (TCL0) on

rising edges

External clock input (TCL1) on

rising edges

0

1

External clock input (TCL0) on

falling edges

External clock input (TCL1) on

falling edges

10

12

1

0

1

0

1

0

1

fxx/2

(3.49 kHz)

fxx/2

(0.87 kHz)

(3.49 kHz)

6

10

fxx /2 (55.93 kHz)

fxx /2

4

8

fxx/2 (223.7 kHz)

fxx/2 (13.98 kHz)

6

fxx = 3.58 MHz

fxx/2 (55.93 kHz)

NOTE: 'fxx' = system clock of 3.579545 MHz.

+

PROGRAMMING TIP — Restarting TC0 Counting Operation

1. Set TC0 timer interval to 3.49 kHz:

BITS

SMB

LD

EMB

15

EA,#4CH

TMOD0,EA

LD

EI

BITS

IET0

2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation:

BITS

SMB

BITS

EMB

15

TMOD0.3

11-18

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

TC COUNTER REGISTER (TCNTn)

The 8-bit counter register for TC, TCNTn, is read-only and can be addressed by 8-bit RAM control instructions.

sets all counter register values to logic zero (00H).

Whenever TMODn.3 is enabled, TCNTn is cleared to logic zero and counting resumes. The TCNTn register value

is incremented each time an incoming clock signal is detected that matches the signal edge and frequency

setting of the TMODn register (specifically, TMODn.6–TMODn.4).

Each time TCNTn is incremented, the new value is compared to the reference value stored in the reference

register, TREFn. When TCNTn = TREFn, an overflow occurs in the counter register, the interrupt request flag,

IRQTn, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter

interval has elapsed.

Count

Clock

TREFn

TCNTn

Reference Value = n

n

0

1

2

n-1

0

1

2

n-1

0

1

2

3

Match

TOLn

Interval Time

Timer Start Instruction

(TMODn.3 is set)

IRQTn Set

Figure 11-3. TC Timing Diagram

11-19

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

TC REFERENCE REGISTER (TREFn)

The TC reference register TREFn is an 8-bit write-only register that is

initializes the TREFn value to 'FFH'.

TREFn is used to store a reference value to be compared to the incrementing TCNTn register in order to identify

an elapsed time interval. Reference values will differ depending upon the specific function that TC is being used

to perform — as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output

source.

During timer/counter operation, the value loaded into the reference register is compared to the counter value.

When TCNTn = TREFn, the TC output latch (TOLn) is inverted and an interrupt request is generated to signal the

interval or event. The TREFn value, together with the TMODn clock frequency selection, determines the specific

TC timer interval. Use the following formula to calculate the correct value to load to the TREFn reference register:

1

TC timer interval = (TREFn value + 1)

´

TMODn frequency setting

( assuming a TREFn value ¹ 0 )

TC OUTPUT ENABLE FLAG (TOEn)

The 1-bit timer/counter output enable flag TOEn controls output from timer/counter to the TCLOn pin. TOEn is

addressable by 1-bit read and write instructions.

Bit 3

Bit 2

Bit 1

BOE

Bit 0

0

F92H

TOE1

TOE0

When you set the TOEn flag to "1", the contents of TOLn can be output to the TCLOn pin. Whenever a

occurs, TOEn is automatically set to logic zero, disabling all TC output. Even when the TOE0 flag is disabled,

timer/counter 0 can continue to output an internally-generated clock frequency, via TOL0, to the serial I/O clock

selector circuit.

TC OUTPUT LATCH (TOLn)

TOLn is the output latch for timer/counter 0 and 1. When the 8-bit comparator detects a correspondence between

the value of the counter register TCNTn and the reference value stored in the TREFn register, the TOLn value is

inverted — the latch toggles high-to-low or low-to-high. Whenever the state of TOLn is switched, the TC signal is

output. TC output may be directed to the TCLOn pin. TC0 signal can also be output directly to the serial I/O clock

selector circuit as the

signal.

Assuming TC is enabled, when bit 3 of the TMODn register is set to "1", the TOLn latch is cleared to logic zero,

along with the counter register and the interrupt request flag, IRQTn, and counting resumes immediately. When

TCn is disabled (TMODn.2 = "0"), the contents of the TOLn latch are retained and can be read, if necessary.

11-20

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Setting a TC0 Timer Interval

To set a 30 ms timer interval for TC0, given fxx = 3.579545 MHz, follow these steps.

1. Select the timer/counter 0 mode register with a maximum setup time of 73.3 ms (assume the TC0 counter

10

clock = fxx/2 , and TREF0 is set to FFH):

2. Calculate the TREF0 value:

TREF0 value + 1

30 ms =

3.49 kHz

30 ms

286 µs

TREF0 + 1 =

= 104.8 = 69H

TREF0 value = 69H – 1 = 68H

3. Load the value 68H to the TREF0 register:

BITS

SMB

LD

EMB

15

EA,#68H

TREF0,EA

EA,#4CH

TMOD0,EA

LD

11-21

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

WATCH TIMER

OVERVIEW

The watch timer is a multi-purpose timer consisting of three basic components:

— 8-bit watch timer mode register (WMOD)

— Clock selector

— Frequency divider circuit

Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. It

is also used as a clock source for generating buzzer output.

Real-Time and Watch-Time Measurement

To start watch timer operation, set bit 2 of the watch timer mode register, WMOD.2, to logic one. The watch timer

starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence in 0.5-

second intervals.

Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be

cleared to logic zero by program software as soon as a requested interrupt service routine has been executed.

Using a System Clock Source

The watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock.

When the zero bit of the WMOD register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its

source; if WMOD.0 = "0", the main system clock (fx) is used as the signal source, according to the following for-

mula:

Main system clock (fx)

Watch timer clock (fw) =

= 32.768 kHz

128

(assuming fxx = 4.19 MHz)

This feature is useful for controlling timer-related operations during stop mode. When stop mode is engaged, the

main system clock (fx) is halted, but the subsystem clock continues to oscillate. By using the subsystem clock as

the oscillation source during stop mode, the watch timer can set the interrupt request flag IRQW to "1", thereby

releasing stop mode.

Buzzer Output Frequency Generator

The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal at 4.19 MHz to the BUZ pin. To

select the BUZ frequency you want, load the appropriate value to the WMOD register. This output can then be

used to actuate an external buzzer sound. To generate a BUZ signal, three conditions must be met:

— The WMOD.7 register bit is set to "1"

— The output latch for I/O port 2.3 is cleared to "0"

— The port 2.3 output mode flag (PM2.3) set to 'output' mode

11-22

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

Timing Tests in High-Speed Mode

By setting WMOD.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91

ms at 4.19 MHz. At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5

seconds. High-speed mode is useful for timing events for program debugging sequences.

Check Subsystem Clock Level Feature

The watch timer can also check the input level of the subsystem clock by testing WMOD.3. If WMOD.3 is "1", the

input level at the XT pin is high; if WMOD.3 is "0", the input level at the XT pin is low.

in

P2.3 Latch

PM2.3

WMOD.7

WMOD.6

WMOD.5

WMOD.4

WMOD.3

WMOD.2

WMOD.1

WMOD.0

BUZ

MUX

8

fw/16 (2kHz)

fw/8 (4kHz)

fw/4 (8kHz)

fw/2 (16 kHz)

Enable/Disable

Selector

Circuit

IRQW

fw/2⁷

fw/2¹⁴(2 Hz)

Frequency

Dividing

Circuit

fw

Clock

Selector

32.768 kHz

fx = Main system Clock

fxt = Subsystem Clock

fxt

fx/128

fw = Watch Timer Frequency

Figure 11-4. Watch Timer Circuit Diagram

11-23

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

WATCH TIMER MODE REGISTER (WMOD)

The watch timer mode register WMOD is used to select specific watch timer operations. It is 8-bit write-only

addressable. An exception is WMOD bit 3 (the XT input level control bit) which is 1-bit read-only addressable. A

in

automatically sets WMOD.3 to the current input level of the subsystem clock, XT (high, if logic one; low, if

in

logic zero), and all other WMOD bits to logic zero.

F88H

F89H

WMOD.3

WMOD.7

WMOD.2

"0"

WMOD.1

WMOD.5

WMOD.0

WMOD.4

In summary, WMOD settings control the following watch timer functions:

— Watch timer clock selection

— Watch timer speed control

— Enable/disable watch timer

(WMOD.0)

(WMOD.1)

(WMOD.2)

(WMOD.3)

— XT input level control

in

— Buzzer frequency selection

— Enable/disable buzzer output

(WMOD.4 and WMOD.5)

(WMOD.7)

Table 11-8. Watch Timer Mode Register (WMOD) Organization

Bit Name

Values

Function

Disable buzzer (BUZ) signal output

Enable buzzer (BUZ) signal output

Address

WMOD.7

0

1

WMOD.6

0

Always logic zero

F89H

WMOD.5 – .4

0

1

0

1

0

1

fw/16 buzzer (BUZ) signal output (2 kHz)

fw/8 buzzer (BUZ) signal output (4 kHz)

fw/4 buzzer (BUZ) signal output (8 kHz)

fw/2 buzzer (BUZ) signal output (16 kHz)

Input level to XT pin is low

in

WMOD.3

0

1

0

1

0

1

0

1

Input level to XT pin is high

in

WMOD.2

WMOD.1

WMOD.0

Disable watch timer; clear frequency dividing circuits

Enable watch timer

F88H

Normal mode; sets IRQW to 0.5 seconds

High-speed mode; sets IRQW to 3.91 ms

Select (fx/128 ) as the watch timer clock (fw)

Select subsystem clock as watch timer clock (fw)

NOTE: Main system clock frequency (fx) is assumed to be 4.19 MHz; subsystem clock frequency is assumed to be 32.768

kHz. 'fw' = watch timer clock frequency.

11-24

KS57C5532/P5532

TIMERS and TIMER/COUNTERS

+

PROGRAMMING TIP — Using the Watch Timer

1. Select a 0.5 second interrupt, and 2 kHz buzzer enable:

BITS

SMB

LD

BITR

LD

EMB

15

EA,#08H

PMG2,EA

P2.3

EA,#84H

WMOD,EA

IEW

;

P2.3 ¬ output mode

Clear P2.3 output latch

LD

BITS

2. Sample real-time clock processing method:

CLOCK

BTSTZ

RET

•

IRQW

;

0.5 second check

No, return

Yes, 0.5 second interrupt generation

;

Increment HOUR, MINUTE, SECOND

11-25

TIMERS and TIMER/COUNTERS

KS57C5532/P5532

NOTES

11-26

KS57C5532/P5532

DTMF GENERATOR

12 DTMF GENERATOR

OVERVIEW

The dual-tone multi-frequency (DTMF) output circuit is used to generate 16 dual-tone multiple frequency signals

for tone dialing. This function is controlled by the DTMF mode register. By writing the contents of the output latch

for DTMF circuit with output instructions, 16 dual or single tones can be output to the DTMF output pin. The tone

output frequency is selected by the DTMF mode register. Figure 12–1 shows the DTMF block diagram. A

frequency of 3.579545 MHz is used for DTMF generator. Clock output is inhibited when DTMR.0 (DTMF Enable

Bit) goes low.

The decoder receives data from the data latch and outputs the result to the row and column tone counter. The

row and column tone counter are incremented until new data is latched. When DTMR.0 is logic one, data is

latched, and the tone output is changed. Table 12–1 shows the 16 available keyboard frequencies.

Internal Bus

DTMF Mode

Register

Mode

Decorder

Row

Counter

Shift Counter

D/A Converter

Clock Sync

Circuit

Tone Mode

Control

Tone

Output

f

SYCLK

3.579545 MHz

Shift Counter

Column

Counter

Sine Wave Synthesizer

Figure 12-1. Block Diagram of DTMF Generator

12-1

DTMF GENERATOR

KS57C5532/P5532

Table 12-1. Keyboard Arrangement

1

4

7

*

2

5

8

0

3

6

9

#

A

B

C

D

ROW1

ROW2

ROW3

ROW4

COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4

Table 12-2. Tone Output Frequencies

Input

Row1

Specified Frequency (Hz)

Actual Frequency (Hz)

% Error

697

770

699.1

766.2

+ 0.31

– 0.49

– 0.54

+ 0.74

+ 0.57

– 0.32

– 0.35

+ 0.73

Row2

Row3

852

847.4

Row4

941

948.0

Column 1

Column 2

Column 3

Column 4

1209

1336

1477

1633

1215.7

1331.7

1471.7

1645.0

DTMF MODE REGISTER

DTMF output is controlled by the DTMF mode register. Bit position DTMR.0 enables or disables DTMF operation.

If DTMR.0 = 1, DTMF operation is enabled.

Programmers should write zeros or ones to bit positions DTMR.4–DTMR.7 according to the keyboard input

specification. Writing the data in a look-up table is useful for program efficiency. The DTMR register is a write-

only register, and is manipulated using 8-bit RAM control instructions.

VDD

VSS

DTMF ON

DTMF OFF

Figure 12-2. DTMF Output Waveform

12-2

KS57C5532/P5532

DTMF GENERATOR

Table 12-3. DTMF Mode Register (DTMR) Organization

Bit Name

Setting

Resulting DTMF Function

Address

DTMR.7–.4

0,1

Specify according to keyboard

FC1H

DTMR.3

–

Don't care

FC0H

DTMR.2–.1

0

1

0

1

0

1

Dual-tone enable

Single-column tone enable

Single-row tone enable

Disable DTMF operation

Enable DTMF operation

DTMR.0

0

1

Table 12-4. DTMR.7–DTMR.4 key Input Control Settings

DTMR.7

DTMR.6

DTMR.5

DTMR.4

Keyboard

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D

1

2

3

4

5

6

7

8

9

0

*

#

A

B

C

1

0

1

0

1

0

1

12-3

DTMF GENERATOR

KS57C5532/P5532

NOTES

12-4

KS57C5532/P5532

SERIAL I/O INTERFACE

13 SERIAL I/O INTERFACE

OVERVIEW

The serial I/O interface (SIO) has the following functional components:

— 8-bit mode register (SMOD)

— Clock selector circuit

— 8-bit buffer register (SBUF)

— 3-bit serial clock counter

Using the serial I/O interface, 8-bit data can be exchanged with an external device. You control the transmission

frequency by the appropriate bit settings to the SMOD register.

The serial interface can run off an internal or an external clock source, or the TOL0 signal that is generated by the

8-bit timer/counter 0, TC0. If you use the TOL0 clock signal, you can modify its frequency to adjust the serial data

transmission rate.

SERIAL I/O OPERATION SEQUENCE

The general sequence of operations for the serial I/O interface may be summarized as follows:

1. Set SIO mode to transmit-and-receive or to receive-only.

2. Select MSB-first or LSB-first transmission mode.

3. Set the

clock signal in the mode register, SMOD.

4. Set SIO interrupt enable flag (IES) to "1".

5. Initiate SIO transmission by setting bit 3 of the SMOD to "1".

6. When the SIO operation is completed, IRQS flag is set and an interrupt is generated.

13-1

SERIAL I/O INTERFACE

KS57C5532/P5532

Internal Bus

8

LSB or MSB first

SO

SBUF (8-Bit)

SI

R

OverFlow

Q

D

IRQS

CK

P0.0/SCK

TOL0

Q0

Q1

Q2

CPU CLK

3-Bit Counter

Clock

Selector

R

S

fxx/2¹⁰

fxx/2⁴

Q

Clear

-

SMOD.7 SMOD.6 SMOD.5

SMOD.3 SMOD.2 SMOD.1 SMOD.0

(note)

BITS

8

Internal Bus

NOTE: Instruction Execution

f XX: System Clock

Figure 13-1. Serial I/O Interface Circuit Diagram

13-2

KS57C5532/P5532

SERIAL I/O INTERFACE

SERIAL I/O MODE REGISTER (SMOD)

The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface.

Its reset value is logic zero. SMOD is organized in two 4-bit registers, as follows:

FE0H

FE1H

SMOD.3

SMOD.7

SMOD.2

SMOD.6

SMOD.1

SMOD.5

SMOD.0

0

SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in

transmit-and-receive mode or receive-only mode.

SMOD is a write-only register and can be addressed only by 8-bit RAM control instructions. One exception to this

is SMOD.3, which can be written by a 1-bit RAM control instruction. When SMOD.3 is set to 1, the contents of

the serial interface interrupt request flag, IRQS, and the 3-bit serial clock counter are cleared, and SIO operations

are initiated. When the SIO transmission starts, SMOD.3 is cleared to logic zero.

Table 13-1. SIO Mode Register (SMOD) Organization

SMOD.0

SMOD.1

SMOD.2

0

1

0

1

0

Most significant bit (MSB) is transmitted first

Least significant bit (LSB) is transmitted first

Receive-only mode; output buffer is off

Transmit-and-receive mode

Disable the data shifter and clock counter; retain contents of IRQS flag when serial

transmission is halted

1

0

Enable the data shifter and clock counter; set IRQS flag to "1" when serial

transmission is halted

SMOD.3

SMOD.4

Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset

this bit to logic zero

Bit not used; value is always "0"

SMOD.7

SMOD.6

SMOD.5

Clock Selection

R/W Status of SBUF

0

External clock at

SBUF is enabled when SIO operation

is halted or when

goes high.

0

1

x

Use TOL0 clock from TC0

CPU clock: fxx/4, fxx/8,

fxx/64

Enable SBUF read/write

10

1

0

1

0

1

SBUF is enabled when SIO operation

3.49 kHz clock: fxx/2

is halted or when

goes high.

4

223.7 kHz clock: fxx/2

NOTES:

1. 'fxx' = system clock; 'x' means 'don't care.'

2. kHz frequency ratings assume a system clock (fxx) running at 3.579545 MHz.

3. The SIO clock selector circuit cannot select a fxx/2⁴clock if the CPU clock is fxx/64.

4. When a internal clock is selected as a clock source for the serial I/O interface (by setting other values than "000" in

SMOD.7–SMOD.5), the clock can be output from pin.

13-3

SERIAL I/O INTERFACE

KS57C5532/P5532

SERIAL I/O TIMING DIAGRAMS

SCK

SI

SO

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

Transmit

Complete

IRQS

SET SMOD.3

Figure 13-2. SIO Timing in Transmit/Receive Mode

SCK

SI

D17

D16

D15

D14

D13

D12

D11

D10

High Impendence

SO

Transmit

Complete

IRQS

SET SMOD.3

Figure 13-3. SIO Timing in Receive-Only Mode

13-4

KS57C5532/P5532

SERIAL I/O INTERFACE

SERIAL I/O BUFFER REGISTER (SBUF)

When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer

register are output to the SO pin at the rate of one bit for each falling edge of the SIO clock. Receive data is

simultaneously input from the SI pin to SBUF at the rate of one bit for each rising edge of the SIO clock.

When receive-only mode is used, incoming data is input to the SIO buffer at the rate of one bit for each rising

edge of the SIO clock.

SBUF can be read or written using 8-bit RAM control instructions. Following a

undetermined.

, the value of SBUF is

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O

4

1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fxx/2 and in

MSB-first mode:

BITS

SMB

LD

BITS

EMB

15

EA,#03H

PMG1,EA

EA,#0E6H

SMOD,EA

EA,#48H

SBUF,EA

SMOD.3

;

P0.0 /

and P0.1 / SO ¬ Output

;

SIO data transfer

SCK/P0.0

External

SO/P0.1

Device

[KS575532]

2. Use CPU clock to transfer and receive serial data at high speed:

BITR

LD

BITS

BITR

BTSTZ

JR

EMB

EA,#03H

PMG1,EA

EA,#47H

SMOD,EA

EA,#TDATA

SBUF,EA

SMOD.3

IES

;

P0.0/SCK and P0.1/SO ¬ Output, P0.2/SI ¬ Input

TDATA address = Bank0 (20H–7FH)

;

SIO start

SIO Interrupt Enable

STEST

IRQS

STEST

LD

EA,SBUF

RDATA,EA

;

RDATA address = Bank0 (20H–7FH)

13-5

SERIAL I/O INTERFACE

KS57C5532/P5532

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)

3. Transmit and receive an internal clock frequency of 3.49 kHz (at 3.579545 MHz) in LSB-first mode:

BITS

LD

BITS

EI

EMB

EA,#03H

PMG1,EA

EA,#87H

SMOD,EA

EA,TDATA

SBUF,EA

SMOD.3

;

P0.0 / SCK and P0.1 / SO ¬ Output, P0.2/SI ¬ Input

TDATA address = Bank0 (20H-7FH)

;

SIO start

BITS

•

IES

SIO Interrupt Enable

•

INTS

PUSH

BITR

LD

SB

EA

EMB

EA,TDATA

;

Store SMB, SRB

Store EA

;

EA ¬ Receive data

TDATA address = Bank0 (20H-7FH)

Transmit data « Receive data

XCH

EA,SBUF

LD

RDATA,EA

SMOD.3

EA

;

RDATA address = Bank0 (20H-7FH)

SIO start

BITS

POP

IRET

SB

SCK/P0.0

SO/P0.1

SI/P0.2

External

Device

[KS575532]

13-6

KS57C5532/P5532

SERIAL I/O INTERFACE

+

PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)

4. Transmit and receive an external clock in LSB-first mode:

BITR

LD

EMB

EA,#02H

PMG1,EA

EA,TDATA

SBUF,EA

EA,#0FH

SMOD,EA

;

P0.1 / SO ¬ Output, P0.0/SCK and P0.2/SI ¬ Input

TDATA address = Bank0 (20H-7FH)

LD

;

SIO start

EI

BITS

•

IES

SIO Interrupt Enable

•

INTS

PUSH

BITR

LD

SB

EA

EMB

EA,TDATA

;

Store SMB, SRB

Store EA

;

EA ¬ Transmit data

TDATA address = Bank0 (20H-7FH)

Transmit data « Receive data

RDATA address = Bank0 (20H-7FH)

SIO start

XCH

LD

BITS

POP

IRET

EA,SBUF

RDATA,EA

SMOD.3

EA

SB

SCK

/P0.0

SO/P0.1

SI/P0.2

External

Device

[KS575532]

High Speed SIO Transmission

13-7

SERIAL I/O INTERFACE

KS57C5532/P5532

NOTES

13-8

KS57C5532/P5532

ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, information on KS57C5532 electrical characteristics is presented as tables and graphics. The

information is arranged in the following order:

Standard Electrical Characteristics

— Absolute maximum ratings

— D.C. electrical characteristics

— System clock oscillator characteristics

— I/O capacitance

— A.C. electrical characteristics

— Operating voltage range

Miscellaneous Timing Waveforms

— A.C timing measurement point

— Clock timing measurement at X_INand X_OUT

— TCL timing

— Input timing for RESET

— Input timing for external interrupts

— Serial data transfer timing

Stop Mode Characteristics and Timing Waveforms

— RAM data retention supply voltage in stop mode

— Stop mode release timing when initiated by RESET

— Stop mode release timing when initiated by an interrupt request

14-1

ELECTRICAL DATA

KS57C5532/P5532

Table 14-1. Absolute Maximum Ratings

°

(T_A= 25 C)

Parameter

Symbol

Conditions

Rating

Units

V_DD

V_I1

Supply Voltage

Input Voltage

–

– 0.3 to 6.5

V

– 0.3 to V_DD+ 0.3

All I/O ports

–

V

V_O

Output Voltage

Output Current High

I_OH

One I/O port active

All I/O ports active

One I/O port active

– 15

– 30

mA

I_OL

Output Current Low

+ 30 (Peak value)

mA

+ 15 ^(note)

+ 100 (Peak value)

+ 60 ^(note)

All I/O ports, total

T_A

°

Operating Temperature

Storage Temperature

–

– 40 to + 85

C

T_stg

°

C

– 65 to + 150

NOTE: The values for Output Current Low ( I_OL) are calculated as Peak Value ´

Duty .

Table 14-2. D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

°

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_IH1

0.7 V_DD

V_DD

Input High

Voltage

All input pins except those

specified below for V_IH2–V_IH4

–

V

V_IH2

V_IH3

0.8 V_DD

0.7 V_DD

V_DD

Ports 0, 1, 3, 6, 7, and RESET

Ports 4 and 5 with pull-up

resistors assigned

V_IH4

V_IL1

X_IN,X_OUTand XT_IN

V_DD0.1

–

V_DD

0.3 V_DD

Input Low

Voltage

All input pins except those

specified below for V_IL2–V_IL3

–

V

V_IL2

V_IL3

0.2 V_DD

0.1

Ports 0, 1, 3, 6, 7, and RESET

X_IN,X_OUTand XT_IN

14-2

KS57C5532/P5532

ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter Symbol

Conditions

I_OH= – 1 mA Ports except 1

Min

Typ

Max

Units

V_OH

V_DD– 1.0

Output High

Voltage

–

V

V_OL1

V_DD= 4.5 V to 5.5 V

I_OL= 15 mA Ports 4,5 only

Output Low

Voltage

–

2

V

V_DD= 1.8 to 5.5 V, I_OL= 1.6mA

0.4

2

V

V_OL2

V_DD= 4.5 V to 5.5 V

I_OL= 4mA all out Ports except ports 4,5

V_DD= 1.8 to 5.5 V, I_OL= 1.6mA

V_I= V_DD

0.4

3

V

I_LIH1

Input High

Leakage

Current

–

mA

All input pins except those specified

below for I_LIH2

I_LIH2

V_I= V_DD

20

- 3

X_IN,X_OUTand XT_IN

I_LIL1

V = 0 V

I

Input Low

Leakage

Current

mA

All input pins except below and RESET

I_LIL2

V = 0 V

I

- 20

3

X_IN,X_OUTand XT_IN

I_LOH

V_O= V_DD

Output High

Leakage

Current

–

All output pins

I_LOL

V_O= 0 V

Output Low

Leakage

Current

- 3

All output pins

R_L1

V_DD= 5 V; V_I= 0 V

except RESET

Pull-Up

Resistor

25

45

100

kW

V_DD= 3 V

50

100

200

25

89

212

441

46

200

400

800

100

R_L3

R_L4

V_DD= 5 V; V_I= 0 V; RESET

V_DD= 3 V

Pull-Down

Resistor

V_DD= 5 V; V_I= V_DD; Port 12

V_DD= 3 V

50

95

200

14-3

ELECTRICAL DATA

KS57C5532/P5532

Table 14-2. D.C. Electrical Characteristics (Concluded)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max Units

I_DD1

Supply

Current ⁽¹⁾

–

3.0

5.0

mA

Run mode; V_DD= 5.0 V ± 10%

(DTMF ON)

3.58 MHz Crystal oscillator; C1 = C2 = 22 pF

V

_DD= 3 V ± 10%

1.6

2.7

3.0

8.0

I_DD2

6.0 MHz

Run mode; V_DD= 5.0 V ± 10%

(DTMF OFF) Crystal oscillator; C1 = C2 = 22 pF 3.58 MHz

2.0

1.3

0.9

0.8

4.0

2.3

2.5

6.0 MHz

3.58 MHz

6.0 MHz

V

_DD= 3 V ± 10%

I_DD3

Idle mode; V_DD= 5 V ± 10%

V_DD= 3 V ± 10%

3.58 MHz

6.0 MHz

3.58 MHz

0.7

0.3

1.8

1.5

1.0

30

0.2

I_DD4

I_DD5

I_DD6

–

12.5

Run mode; V_DD= 3.0 V ± 10%

mA

32 kHz Crystal oscillator

4.5

1.9

15

5

Idle mode; V_DD= 3.0 V ± 10%

32 kHz Crystal oscillator

Stop mode; V_DD= 5 V ± 10%

SCMOD =

0000B

XT = 0V

Stop mode; V_DD= 3 V ± 10%

Stop mode; V_DD= 5 V ± 10%

0.6

0.2

3

SCMOD =

0100B

Stop mode; V_DD= 3 V ± 10%

0.1

2

V_ROW

dB_CR

V_DD= 2.0 V to 5.5 V

Row Tone

Level ⁽²⁾

– 16

1

– 14

– 11

dBV

dB

R_L=12 KW; Temp = – 30 to 60 °C

V_DD= 2.0 V to 5.5 V

Ratio of

Column to

Row Tone ⁽²⁾

2

–

3

5

R_L= 12 KW; Temp = – 30 to 60 °C

Distortion ⁽²⁾

(Dual tone)

V_DD= 2.0 V to 5.5 V

1 MHz band, R_L= 12 KW

Temp = – 30 to 60 °C

THD

–

%

NOTES:

1. D.C. electrical values for Supply Current (I

to I ) do not include current drawn through internal pull-up resistors.

DD3

DD1

2. DTMF electrical characteristics.

3. For D.C. electrical values, the power control register (PCON) must be set to 0011B.

14-4

KS57C5532/P5532

ELECTRICAL DATA

Table 14-3. Main System Clock Oscillator Characteristics

°

(T = – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

A

Oscillator

Clock

Parameter

Test Condition

Min

Typ Max Units

Configuration

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Ceramic

Oscillator

0.4

–

6.0

MHz

XIN

XOUT

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3 V

0.4

–

3

4

Stabilization time ⁽²⁾

ms

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Crystal

Oscillator

0.4

6.0

MHz

XIN

XOUT

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3 V

0.4

–

3

Stabilization time ⁽²⁾

10

6.0

ms

X_INinput frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

External

Clock

0.4

MHz

XIN

XOUT

V_DD= 1.8 V to 5.5 V

–

0.4

–

3

X_INinput high and low

83.3

1250

ns

level width (t_XH,t_XL

)

NOTES:

1. Oscillation frequency and X_INinput frequency data are for oscillator characteristics only.

2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is

terminated.

14-5

ELECTRICAL DATA

KS57C5532/P5532

Table 14-4. Recommended Oscillator Constants

°

(T = – 40 C to + 85 C)

A

Manufacturer

Series

Number ⁽¹⁾

Frequency Range

Load Cap (pF)

Oscillator Voltage

Range (V)

Remarks

C1

33

(2)

C2

33

(2)

MIN

2.0

MAX

5.5

TDK

3.58 MHz–6.0 MHz

Leaded Type

FCR” ðÿM5

2.0

5.5

On-chip C

FCR” ðÿMC5

Leaded Type

(3)

3.58 MHz–6.0 MHz

2.0

5.5

On-chip C

SMD Type

CCR” ðÿMC3

NOTES:

1. Please specify normal oscillator frequency.

2. On-chip C: 30pF built in.

3. On-chip C: 38pF built in.

14-6

KS57C5532/P5532

ELECTRICAL DATA

Table 14-5. Subsystem Clock Oscillator Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Oscillator

Clock

Parameter

Test Condition

Min

Typ

Max

Units

Configuration

Oscillation frequency ⁽¹⁾

Crystal

Oscillator

–

32

32.76

8

35

kHz

XTI XTOUT

N

C1

C2

Stabilization time ⁽²⁾

V_DD= 2.7 V to 5.5 V

V_DD= 1.8 V to 5.5 V

–

1.0

–

2

s

10

XT_INinput frequency ⁽¹⁾

External

Clock

XTI XTOUT

N

–

32

–

100

kHz

XT_INinput high and low

–

5

–

15

µs

level width (t_XH,t_XL

)

NOTES:

1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.

IN

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is

terminated.

Table 14-6. Input/Output Capacitance

°

(T_A= 25 C, V_DD= 0 V )

Parameter

Input

Capacitance

Symbol

Condition

Min

Typ

Max

Units

C_IN

f = 1 MHz; Unmeasured pins

are returned to V_SS

–

15

pF

C_OUT

C_IO

Output

Capacitance

–

15

pF

I/O Capacitance

14-7

ELECTRICAL DATA

KS57C5532/P5532

Table 14-7. A.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

t_CY

V_DD= 2.7 V to 5.5 V

Instruction Cycle

Time ⁽¹⁾

0.67

–

64

µs

V_DD= 1.8 V to 5.5 V

V_DD= 2.7 V to 5.5 V

1.33

0

f

_TI0,f_TI1

TCL0, TCL1 Input

Frequency

–

1.5

MHz

V_DD= 1.8 V to 5.5 V

1

–

MHz

µs

t

_TIH0,t_TIL0V_DD= 2.7 V to 5.5 V

_TIH1,t_TIL1

TCL0, TCL1 Input

High, Low Width

0.48

V_DD= 1.8 V to 5.5 V

1.8

t_KCY

V_DD= 2.7 V to 5.5 V

External SCK source

Cycle Time

800

–

ns

Internal SCK source

V_DD= 1.8 V to 5.5 V

External SCK source

670

3200

Internal SCK source

V_DD= 2.7 V to 5.5 V

External SCK source

3800

335

t_KH,t_KL

SCK High, Low

Width

–

ns

t

–250

KCY

Internal SCK source

V_DD= 1.8 V to 5.5 V

External SCK source

1600

t

–2150

KCY

Internal SCK source

t_SIK

V_DD= 2.7 V to 5.5 V

External SCK source

SI Setup Time to

SCK High

100

–

ns

Internal SCK source

150

V_DD= 1.8 V to 5.5 V

External SCK source

Internal SCK source

500

400

t_KSI

V_DD= 2.7 V to 5.5 V

External SCK source

SI Hold Time to

SCK High

Internal SCK source

V_DD= 1.8 V to 5.5 V

External SCK source

400

600

Internal SCK source

500

14-8

KS57C5532/P5532

ELECTRICAL DATA

Table 14-7. A.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

V_DD= 2.7 V to 5.5 V

External SCK source

Min

Typ

Max

Units

(note)

Output Delay for

SCK to SO

–

300

ns

t_KSO

Internal SCK source

V_DD= 1.8 V to 5.5 V

External SCK source

250

1000

Internal SCK source

1000

–

t_INTH,t_INTL

t_RSL

10

Interrupt Input

High, Low Width

INT0, INT1, INT2, INT4, KS0–KS7

–

µs

RESET Input

Low Width

Input

–

NOTE: R (1 kW) and C (100 pF) are the load resistance and load capacitance of the SO output line.

Main Oscillator Frequency

(Divided by 4)

CPU Clock

1.5 MHz

6 MHz

1.05

MHz

4.2 MHz

3 MHz

0.75 MHz

15.625 kHz

1

2

3

4

5

6

7

1.8

2.7

Supply Voltage (V)

CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 14-1. Standard Operating Voltage Range

14-9

ELECTRICAL DATA

KS57C5532/P5532

Table 14-8. RAM Data Retention Supply Voltage in Stop Mode

°

(T = – 40 C to + 85 C)

A

Parameter

Symbol

Conditions

–

Min

Typ

Max

Unit

V_DDDR

Data retention supply voltage

1.8

–

5.5

V

I_DDDR

V

DDDR

= 1.5 V

Data retention supply current

–

0.1

10

µA

t_SREL

t_WAIT

Release signal set time

–

0

–

µs

2¹⁷/fx

Oscillator stabilization

wait time ⁽¹⁾

Released by

ms

(2)

Released by interrupt

–

ms

NOTES:

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator

start-up.

2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

14-10

KS57C5532/P5532

ELECTRICAL DATA

TIMING WAVEFORMS

Internal RESET

Operation

Idle Mode

Stop Mode

Operating Mode

Data Retention Mode

VDD

VDDDR

Execution of

STOP Instrction

RESET

t_WAIT

tSREL

Figure 14-2. Stop Mode Release Timing When Initiated by

Idle Mode

Normal

Operating

Mode

Stop Mode

Data Retention

VDD

VDDDR

tSREL

Execution of

STOP Instrction

tWAIT

Power-down Mode Terminating

(Interrupt Request)

Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request

14-11

ELECTRICAL DATA

KS57C5532/P5532

0.8 VDD

0.2 VDD

0.8 VDD

0.2 VDD

Measurement

Points

Figure 14-4. A.C. Timing Measurement Points (Except for X_INand XT_IN)

1/fx

tXL

tXH

XIN

VDD - 0.1 V

0.1 V

Figure 14-5. Clock Timing Measurement at X_IN(XT

)

IN

1/fTI

tTIL

tTIH

TCL

0.8 VDD

0.2 VDD

Figure 14-6. TCL0/1 Timing

14-12

KS57C5532/P5532

ELECTRICAL DATA

tRSL

RESET

0.2 VDD

Figure 14-7. Input Timing for

Signal

tINTL

tINTH

INT0, 1, 2, 4,

KS0 to KS7

0.8 VDD

0.2 VDD

Figure 14-8. Input Timing for External Interrupts and Quasi-Interrupts

14-13

ELECTRICAL DATA

KS57C5532/P5532

tKCY

tKL

tKH

SCK

0.8 VDD

0.2 VDD

t_SIK

t_KSI

0.8 VDD

0.2 VDD

SI

Input Data

t_KS

O

SO

Output Data

Figure 14-9. Serial Data Transfer Timing

14-14

KS57C5532/P5532

MECHANICAL DATA

15 MECHANICAL DATA

This section contains the following information about the device package:

— Package dimensions in millimeters

— Pad diagram

23.90 ± 0.3

20.00 ± 0.2

0-8

0.15 ^+0.10

-0.05

64-QFP-1420F

0.10 MAX

#64

#1

0.40+0.10

-0.05

1.00

(1.00)

0.05-0.25

2.65 ± 0.10

3.00 MAX

0.15 MAX

0.80 ± 0.20

NOTE: Dimensions are in millimeters.

Figure 15-1. 64-QFP-1420F Package Dimensions

15-1

MECHANICAL DATA

KS57C5532/P5532

#64

#33

0-15

64-SDIP-750

#1

#32

58.20 MAX

57.80 ± 0.2

± 0.1

0.45

1.778

(1.34)

1.00 ± 0.1

NOTE: Dimensions are in millimeters.

Figure 15-2. 64-SDIP-750C Package Dimensions

15-2

KS57C5532/P5532

KS57P5532 OTP

16 KS57P5532OTP

OVERVIEW

The KS57P5532 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the

KS57C5532 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by

serial data format.

The KS57P5532 is fully compatible with the KS57C5532, both in function and in pin configuration. Because of its

simple programming requirements, the KS57P5532 is ideal for use as an evaluation chip for the KS57C5532.

16-1

KS57P5532 OTP

KS57C5532/P5532

VSS/VSS

P9.0

P9.1

P9.2

P9.3

P8.0

P8.1

P8.2

P8.3

P7.0/KS4

P7.1/KS5

P7.2/KS6

P7.3/KS7

P6.0/KS0

P6.1/KS1

P6.2/KS2

P6.3/KS3

XTOUT

XTIN

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P13.2

1

2

3

4

5

6

7

8

P13.1

P13.0

P2.3/BUZ

P2.2/CLO

P2.1/TCLO1

P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/SCK

P10.3

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P10.2

P10.1

P10.0

P11.3

P11.2

P11.1

P11.0

P12.3

XIN

XOUT

RESET/RESET

P5.0

P5.1

P5.2

P5.3

P4.0

P4.1

P4.2

P12.2

P12.1

P12.0

SDAT/P3.3

SCLK/P3.2

P4.3

P3.0/TCL0

P3.1/TCL1

V

PP/TEST

DTMF

V

DD/VDD

NOTE: The bold indicate a OTP pin name.

Figure 16-1. KS57P5532 Pin Assignments (64-SDIP)

16-2

KS57C5532/P5532

KS57P5532 OTP

P8.0

P9.3

P9.2

P9.1

P9.0

52

53

54

55

56

57

58

59

60

61

62

63

64

32

31

30

29

28

27

26

25

24

23

22

21

20

P5.3

P4.0

P4.1

P4.2

P4.3

V

SS/VSS

P3.0/TCL0

P3.1/TCL1

DD/ DD

KS57P5532

(64-QFP-1420F)

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P13.2

V

DTMF

TEST/VPP

P3.2/SCLK

P3.3/SDAT

P12.0

P13.1

P13.0

NOTE: The bold indicate a OTP pin name.

Figure 16-2. KS57P5532 Pin Assignments (64-QFP)

16-3

KS57P5532 OTP

KS57C5532/P5532

Table 16-1. Descriptions of Pins Used to Read/Write the EPROM

During Programming

Pin Name

Pin No.

I/O

Function

SDAT

28 (21)

I/O

Serial data pin. Output port when reading and input port when

writing. Can be assigned as a Input/push-pull output port.

SCLK

29 (22)

30 (23)

I

Serial clock pin. Input only pin.

V_PP(TEST)

Power supply pin for EPROM cell writing (indicates that OTP

enters into the writing mode). When 12.5 V is applied, OTP is

in writing mode and when 5 V is applied, OTP is in reading

mode. (Option)

Hold GND when OTP is operating.

43 (36)

I

Chip initialization

RESET

V_DD/V_SS

Logic power supply pin. V_DDshould be tied to + 5 V during

programming.

32 (25) /

64 (57)

NOTE: Parentheses indicate pin number for 64 QFP package.

Table 16-2. Comparison of KS57P5532 and KS57C5532 Features

Characteristic

Program Memory

Operating Voltage (V_DD

KS57P5532

32 K byte EPROM

KS57C5532

32 K byte mask ROM

1.8 V to 5.5 V

)

1.8 V to 5.5 V

V_DD= 5 V, V_PP(TEST) = 12.5V

OTP Programming Mode

Pin Configuration

64 SDIP/QFP

EPROM Programmability

User Program 1 time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V_PP(TEST) pin of the KS57P5532, the EPROM programming mode is entered.

The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in

Table 16-3 below.

Table 16-3. Operating Mode Selection Criteria

V_DD

V_PP

REG/MEM

Address

(A15–A0)

R/W

Mode

(TEST)

5 V

0

1

0000H

0E3FH

1

0

1

0

EPROM read

12.5V

EPROM program

EPROM verify

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

16-4

KS57C5532/P5532

KS57P5532 OTP

Table 16-4. Absolute Maximum Ratings

°

(T = 25 C)

A

Parameter

Symbol

Conditions

Rating

Units

V_DD

V_I1

Supply Voltage

Input Voltage

–

– 0.3 to 6.5

V

– 0.3 to V_DD+ 0.3

All I/O ports

–

V

V_O

– 0.3 to V_DD+ 0.3

Output Voltage

Output Current High

I_OH

One I/O port active

All I/O ports active

One I/O port active

– 15

– 30

mA

I_OL

Output Current Low

+ 30 (Peak value)

mA

+ 15 ^(note)

+ 100 (Peak value)

+ 60 ^(note)

All I/O ports, total

°

T_A

Operating Temperature

Storage Temperature

–

– 40 to + 85

C

°

C

T_stg

– 65 to + 150

NOTE: The values for Output Current Low ( I_OL) are calculated as Peak Value ´

Duty .

Table 16-5. D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

°

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_IH1

0.7 V_DD

V_DD

Input High

Voltage

All input pins except those

–

V

specified below for V_IH2

V

–

IH4

V_IH2

V_IH3

0.8 V_DD

0.7 V_DD

V_DD

Ports 0, 1, 3, 6, 7, and RESET

Ports 4 and 5 with pull-up

resistors assigned

V_IH4

V_IL1

X_IN,X_OUTand XT_IN

V_DD0.1

–

V_DD

0.3 V_DD

Input Low

Voltage

All input pins except those

specified below for V_IL2

–

V

–

IL3

V_IL2

V_IL3

0.2 V_DD

0.1

Ports 0, 1, 3, 6, 7, and RESET

X_IN,X_OUTand XT_IN

16-5

KS57P5532 OTP

KS57C5532/P5532

Table 16-5. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

V_OH

I_OH= – 1 mA Ports except 1

V_DD1.0

–

Output High

Voltage

–

V

V_OL1

V_OL2

I_LIH1

V_DD= 4.5 V to 5.5 V

I_OL= 15 mA Ports 4,5 only

Output Low

Voltage

–

2

V

V_DD= 2.0 to 5.5 V, I_OL= 1.6mA

0.4

2

V

V_DD= 4.5 V to 5.5 V

I_OL= 4mA all out Ports except ports 4,5

V_DD= 2.0 to 5.5 V, I_OL= 1.6mA

V_I= V_DD

0.4

3

V

Input High

Leakage

Current

–

mA

All input pins except those specified

below for I_LIH2

I_LIH2

V_I= V_DD

20

- 3

X_IN, X_OUTand XT_IN

I_LIL1

V_I= 0 V

Input Low

Leakage

Current

mA

All input pins except below and RESET

I_LIL2

V_I= 0 V

– 20

3

X_IN, X_OUTand XT_IN

I_LOH

V_O= V_DD

Output High

Leakage

Current

–

All output pins

I_LOL

V_O= 0 V

Output Low

Leakage

Current

– 3

All output pins

R_L1

V_DD= 5 V; V_I= 0 V

except RESET

Pull-up

Resistor

25

45

100

kW

V_DD= 3 V

50

89

200

400

800

R_L3

R_L4

V_DD= 5 V; V_I= 0 V; RESET

V_DD= 3 V

100

200

212

441

V_DD= 5 V ; V_I= V_DD; Port 12

V_DD= 3 V

25

50

46

95

100

200

Pull-Down

Resistor

16-6

KS57C5532/P5532

KS57P5532 OTP

Table 16-5. D.C. Electrical Characteristics (Concluded)

°

(T = – 40 C to + 85 C, V_DD= 1.8 V to 5.5 V)

A

Parameter

Symbol

Conditions

Min

Typ

Max Units

I_DD1

Supply

–

3.0

5.0

mA

Run mode; V_DD= 5.0 V ± 10%

(1)

Current

(DTMF ON)

3.58 MHz Crystal oscillator; C1 = C2 = 22 pF

V

_DD= 3 V ± 10%

1.6

2.7

3.0

8.0

I_DD2

6.0 MHz

Run mode; V_DD= 5.0 V ± 10%

(DTMF OFF) Crystal oscillator; C1 = C2 = 22 pF 3.58 MHz

2.0

1.3

4.0

6.0 MHz

V_DD= 3 V ± 10%

3.58 MHz

6.0 MHz

0.9

0.8

2.3

2.5

I_DD3

Idle mode; V_DD= 5 V ± 10%

V_DD= 3 V ± 10%

3.58 MHz

6.0 MHz

0.7

0.3

1.8

1.5

3.58 MHz

0.2

1.0

30

I_DD4

I_DD5

I_DD6

–

12.5

Run mode; V_DD= 3.0 V ± 10%

mA

32 kHz Crystal oscillator

4.5

1.9

15

5

Idle mode; V_DD= 3.0 V ± 10%

32 kHz Crystal oscillator

Stop mode; V_DD= 5 V ± 10%

SCMOD =

0000B

XT = 0 V

Stop mode; V_DD= 3 V ± 10%

Stop mode; V_DD= 5 V ± 10%

Stop mode; V_DD= 3 V ± 10%

0.6

0.2

3

SCMOD =

0100B

0.1

2

V_ROW

V_DD= 2.0 V to 5.5 V

Row Tone

Level ⁽²⁾

– 16

1

– 14

– 11

dBV

dB

R_L=12 KW; Temp = – 30 to 60 °C

dB_CR

V_DD= 2.0 V to 5.5 V

Ratio of

Column to

Row Tone ⁽²⁾

2

–

3

5

R_L=12 KW; Temp = – 30 to 60 °C

Distortion ⁽²⁾

(Dual tone)

V_DD= 2.0 V to 5.5 V

1 MHz band, R_L= 12 KW

Temp = – 30 to 60 °C

THD

–

%

NOTES:

1. D.C. electrical values for Supply Current (I

to I ) do not include current drawn through internal pull-up resistors.

DD3

DD1

2. DTMF electrical characteristics.

3. For D.C. electrical values, the power control register (PCON) must be set to 0011B.

16-7

KS57P5532 OTP

KS57C5532/P5532

Table 16-6. Main System Clock Oscillator Characteristics

°

(T = – 40 C + 85 C, V_DD= 1.8 V to 5.5 V)

A

Oscillator

Clock

Parameter

Test Condition

Min

Typ

Max Units

Configuration

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Ceramic

Oscillator

0.4

–

6.0

MHz

X_INX_OUT

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3 V

0.4

–

3.0

4

Stabilization time ⁽²⁾

ms

Oscillation frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

Crystal

Oscillator

0.4

6.0

MHz

XIN

XOUT

C1

C2

V_DD= 1.8 V to 5.5 V

V_DD= 3 V

0.4

–

3.0

10

Stabilization time ⁽²⁾

ms

X_INinput frequency ⁽¹⁾

V_DD= 2.7 V to 5.5 V

External

Clock

0.4

6.0

MHz

XIN

XOUT

V_DD= 1.8 V to 5.5 V

–

0.4

–

3.0

X

input high and low

83.3

1250

ns

in

level width (t_XH,t_XL

)

NOTES:

1. Oscillation frequency and X input frequency data are for oscillator characteristics only.

IN

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is

terminated.

16-8

KS57C5532/P5532

KS57P5532 OTP

Table 16-7. Recommended Oscillator Constants

°

(T = – 40 C + 85 C, V_DD= 1.8 V to 5.5 V)

A

Manufacturer

Series

Number ⁽¹⁾

Frequency Range

Load Cap (pF)

Oscillator Voltage

Range (V)

Remarks

C1

33

(2)

C2

33

(2)

MIN

2.0

MAX

5.5

TDK

3.58 MHz–6.0 MHz

Leaded Type

FCR” ðÿM5

2.0

5.5

On-chip C

FCR” ðÿMC5

Leaded Type

(3)

3.58 MHz–6.0 MHz

2.0

5.5

On-chip C

SMD Type

CCR” ðÿMC3

NOTES:

1. Please specify normal oscillator frequency.

2. On-chip C: 30pF built in.

3. On-chip C: 38pF built in.

Table 16-8. Subsystem Clock Oscillator Characteristics

(T = – 40 C + 85 C, V_DD= 1.8 V to 5.5 V)

°

A

Oscillator

Clock

Parameter

Test Condition

Min

Typ

Max

Units

Configuration

Oscillation frequency ⁽¹⁾

Crystal

Oscillator

–

32

32.76

8

35

kHz

XTI XTOUT

N

C1

C2

Stabilization time ⁽²⁾

V_DD= 2.7 V to 5.5 V

V_DD= 1.8 V to 5.5 V

–

1.0

–

2

s

10

XT_INinput frequency ⁽¹⁾

External

Clock

XTI XTOUT

N

32

–

100

kHz

XT_INinput high and low

–

5

–

15

µs

level width (t_XH,t_XL

)

NOTES:

1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.

IN

2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is

terminated.

16-9

KS57P5532 OTP

KS57C5532/P5532

Table 16-9. Input/Output Capacitance

°

(T_A= 25 C, V_DD= 0 V )

Parameter

Input

Capacitance

Symbol

Condition

Min

Typ

Max

Units

C_IN

f = 1 MHz; Unmeasured pins

are returned to V_SS

–

15

pF

C_OUT

C_IO

Output

Capacitance

–

15

pF

I/O Capacitance

Main Oscillator Frequency

(Divided by 4)

CPU Clock

1.5 MHz

6 MHz

1.05

MHz

4.2 MHz

3 MHz

0.75 MHz

15.625 kHz

1

2

3

4

5

6

7

1.8

2.7

Supply Voltage (V)

CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)

Figure 16-3. Standard Operating Voltage Range

16-10

KS57C5532/P5532

DEVELOPMENT TOOLS

17 DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system in turnkey form. The development

support system is configured with a host system, debugging tools, and support software. For the host system,

any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging

tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for

KS57, KS86, KS88 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.

Samsung also offers support software that includes debugger, assembler, and a program for setting options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE

provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked

help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be

sized, moved, scrolled, highlighted, added, or removed completely.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates

object code in standard hexadecimal format. Assembled program code includes the object code that is used for

ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an

auxiliary definition (DEF) file with device specific information.

SASM57

The SASM57 is an relocatable assembler for Samsung's KS57-series microcontrollers. The SASM57 takes a

source file containing assembly language statements and translates into a corresponding source code, object

code and comments. The SASM57 supports macros and conditional assembly. It runs on the MS-DOS operating

system. It produces the relocatable object code only, so the user should link object file. Object files can be linked

with other object files and loaded into memory.

HEX2ROM

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be

needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by

HEX2ROM, the value 'FF' is filled into the unused ROM area upto the maximum ROM size of the target device

automatically.

TARGET BOARDS

Target boards are available for all KS57-series microcontrollers. All required target system cables and adapters

are included with the device-specific target board.

17-1

DEVELOPMENT TOOLS

OTPs

KS57C5532/P5532

One time programmable microcontroller (OTP) for the KS57C5532 microcontroller and OTP programmer (Gang)

are now available.

IBM-PC AT or Compatible

RS-232C

SMDS2+

Target

Application

System

PROM/OTP Writer Unit

RAM Break/Display Unit

Trace/Timer Unit

Probe

Adapter

TB575532A

Target

Board

POD

SAM4 Base Unit

Eva

Power Supply Unit

Chip

Figure 17-1. SMDS Product Configuration (SMDS2+)

17-2

KS57C5532/P5532

DEVELOPMENT TOOLS

TB575532A/TB575532A TARGET BOARD

The TB575532A/TB575532A target board is used for the KS57C5532/P5532 microcontroller. It is supported by

the SMDS2+ development system.

TB575532A

To User_VCC

74HC11

Off

On

RESET

Idle

+

Stop

+

MDS

XT1

25

J101

XTAL

64

1

144 QFP

KS57E5500

EVA Chip

1

36

33

32

SM1264A

Figure 17-2. TB575532A Target Board Configuration

17-3

DEVELOPMENT TOOLS

KS57C5532/P5532

Table 17-1. Power Selection Settings for TB575532A

Operating Mode

'To User_Vcc' Settings

Comments

The SMDS2/SMDS2+

supplies V_CCto the target

To User_VCC

Target

System

Off

On

VCC

VSS

TB575532A

board (evaluation chip) and

the target system.

VCC

SMDS2/SMDS2+

The SMDS2/SMDS2+

supplies V_CConly to the

To User_VCC

External

VCC

Target

System

Off

On

TB575532A

target board (evaluation chip).

The target system must have

its own power supply.

V_SS

V_CC

SMDS2+

17-4

KS57C5532/P5532

DEVELOPMENT TOOLS

Table 17-2. Clock Selection Settings for TB575532A

Operating Mode

Sub Clock Setting

Comments

Set the XTI switch to “MDS”

when the target board is

connected to the

XTI

EVA Chip

KS57E5500

MDS

XTAL

SMDS2/SMDS2+.

XTOUT

XTIN

No Connection

100 Pin Connector

SMDS2/SMDS2+

Set the XTI switch to “XTAL”

when the target board is used

as a standalone unit, and is

not connected to the

XTI

EVA Chip

KS57E5500

MDS

XTAL

SMDS2/SMDS2+.

XTOUT

XT_IN

XTAL

Target Board

IDLE LED

This LED is ON when the evaluation chip (KS57E5500) is in idle mode.

STOP LED

This LED is ON when the evaluation chip (KS57E5500) is in stop mode.

17-5

DEVELOPMENT TOOLS

KS57C5532/P5532

J101

SS

V

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

1

2

3

4

5

6

7

8

9

P1.3/INT4

P1.2/INT2

P1.1/INT1

P1.0/INT0

P13.2

P9.0

P9.1

P9.2

P9.3

P8.0

P8.1

P8.2

P8.3

P13.1

P13.0

P2.3/BUZ

P2.2/CLO

P2.1/TCLO1

P2.0/TCLO0

P0.3/BTC0

P0.2/SI

P0.1/SO

P0.0/SCK

P10.3

P10.2

P10.1

P10.0

P11.3

P11.2

P11.1

P11.0

P12.3

P12.2

P12.1

P12.0

P7.0/KS4

P7.1/KS5

P7.2/KS6

P7.3/KS7

P6.0/KS0

P6.1/KS1

P6.2/KS2

P6.3/KS3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

OUT

XT

IN

XT

XIN

XOUT

RESET

P5.0

P5.1

P5.2

P5.3

P4.0

P4.1

P4.2

P4.3

P3.3/SDAT

P3.2/SCLK

TEST

DTMF

VDD

P3.0/TCL0

P3.1/TCL1

Figure 17-3. 64-Pin Connector for TB575532A

17-6

KS57C5532/P5532

DEVELOPMENT TOOLS

Target Board

J101

Target System

1

64

Target Cable for 64 SDIP Package

Part Name: AS64SD

Order Cods: SM6101

32 33

Figure 17-4. TB575532A Adapter Cable (KS57C5532/P5532)

17-7

DEVELOPMENT TOOLS

KS57C5532/P5532

NOTES

17-8


型号：	KS57C5532N-XX
厂家：	SAMSUNG
描述：	Microcontroller, 4-Bit, MROM, CMOS, PDIP64, 0.750 INCH, SDIP-64 时钟微控制器光电二极管外围集成电路
文件：	总208页 (文件大小：1561K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS57C5532N-XX [SAMSUNG]

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