KS86C6408Q-XX [SAMSUNG]
Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44;
| 型号： | KS86C6408Q-XX |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, MROM, 6MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44 时钟 微控制器 外围集成电路 |
| 文件： | 总137页 (文件大小：1102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Overview
Address Spaces
Addressing Modes
Control Registers
Interrupt Structure
SAM87RI Instruction Set
KS86C6404/C6408/P6408
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87RI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM87RI microcontrollers have
an external interface that provides access to external memory and other peripheral devices.
KS86C6404/C6408/P6408 MICROCONTROLLER
The KS86C6404/C6408/P6408 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process.
It is built around the powerful SAM87RI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The KS86C6404 has 4 K bytes of program
memory on-chip and KS86C6408 has 8 K bytes.
Using the SAM87RI design approach, the following peripherals were integrated with the SAM87RI core:
— Five configurable I/O ports (32 pins)
— 20 bit-programmable pins for external interrupts
— 8-bit timer/counter with three operating modes
— Low speed USB function
The KS86C6404/C6408/P6408 is a versatile microcontroller that can be used in a wide range of low speed USB
support general purpose applications. It is especially suitable for use as a keyboard controller and is available in
a 42-pin SDIP and a 44-pin QFP package.
OTP
The KS86C6404/C6408 microcontroller is also available in OTP (One Time Programmable) version,
KS86P6408. KS86P6408 microcontroller has an on-chip 8-Kbyte one-time-programmable EPROM instead of
masked ROM. The KS86P6408 is comparable to KS86C6404/C6408, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS86C6404/C6408/P6408
FEATURES
CPU
•
SAM87RI CPU core
Timer/Counter
•
One 8-bit basic timer for watchdog function and
programmable oscillation stabilization interval
generation function
Memory
•
•
4/8-Kbyte internal program memory (ROM)
208-byte RAM
•
One 8-bit timer/counter with Compare/Overflow
Instruction Set
USB Serial Bus
•
•
41 instructions
•
Compatible to USB low speed (1.5 Mbps) device
1.0 specification.
IDLE and STOP instructions added for power-
down modes
•
•
1 Control endpoint and 2 Data endpoint
Serial bus interface engine (SIE)
Instruction Execution Time
1.0 ms at 6 MHz fOSC
— Packet decoding/generation
•
— CRC generation and checking
— NRZI encoding/decoding and bit-stuffing
8 bytes each receive/transmit USB buffer
Interrupts
•
25 interrupt sources with one vector, each
•
source has its pending bit
Operating Temperature Range
•
One level, one vector interrupt structure
° °
– 40 C to + 85 C
•
Oscillation Circuit
Operating Voltage Range
4.0 V to 5.25 V
•
•
6 MHz crystal/ceramic oscillator
External clock source (6 MHz)
•
Package Types
General I/O
•
•
42-pin SDIP
44-pin QFP
•
Bit programmable five I/O ports (34 pins total)
— (D+/PS2, D-/PS2 Included)
1-2
KS86C6404/C6408/P6408
PRODUCT OVERVIEW
BLOCK DIAGRAM
P1.0-P1.7
P0.0-P0.7/INT2
Port 0
P2.0-P2.7 / INT0
Port 2
Port 1
SAM87RI BUS
P3.0
X
IN
P3.1
P3.2
P3.3/CLO
OSC
I/O Port And
Interrupt Control
Port 3
X
OUT
P4.0 / INT1
P4.1 / INT1
P4.2 / INT1
P4.3 / INT1
Basic
Timer
Port 4
USB
SAM87RI CPU
D+/PS2
D-/PS2
3.3 V
OUT
TIMER 0
16 bytes
USB
Buffer
208-Byte
Register
4/8-KB ROM
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
KS86C6404/C6408/P6408
PIN ASSIGNMENTS
P3.1
P3.0
P3.2
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.3/CLO
D+/PS2
D-/PS2
3.3 VOUT
NC
2
INT0 / P2.0
3
INT0 / P2.1
INT0 / P2.2
INT0 / P2.3
INT0 / P2.4
INT0 / P2.5
INT0 / P2.6
INT0 / P2.7
4
5
6
P0.0 / INT
P0.1 / INT
P0.2 / INT
P0.3 / INT
P0.4 / INT
P0.5 / INT
P0.6 / INT
P0.7 / INT
P1.0
7
8
9
KS86C6404
KS86C6408
10
11
12
13
14
15
16
17
18
19
20
21
VDD
VSS
42-SDIP
(Top View)
XOUT
X
IN
TEST
INT1 / P4.0
P1.1
INT1 / P4.1
P1.2
RESET
P1.3
INT1 / P4.2
INT1 / P4.3
P1/7
P1.4
P1.5
P1.6
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
1-4
KS86C6404/C6408/P6408
PRODUCT OVERVIEW
P1.0
3.3 V
22
21
20
19
18
17
16
15
14
13
12
34
35
36
37
38
39
40
41
42
43
44
OUT
P1.1
D-/PS2
D+/PS2
P3.3/CLO
P3.2
P1.2
P1.3
P1.4
KS86C6404
P1.5
P3.1
KS86C6408
P1.6
P3.0
(Top View)
P1.7
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P4.3/INT1
P4.2/INT1
RESET
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
1-5
PRODUCT OVERVIEW
KS86C6404/C6408/P6408
PIN DESCRIPTIONS
Table 1-1. KS86C6404/C6408/P6408 Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Number
Pin
Numbers
Share
Pins
P0.0-P0.7
I/O
Bit-programmable I/O port for Schmitt trigger
input or open-drain output. Port0 can be
individually configured as external interrupt
inputs. Pull-up resistors are assignable by
software.
B
36-29
(30-23)
INT2
P1.0-P1.7
P2.0-P2.7
I/O
I/O
Bit-programmable I/O port for Schmitt trigger
input or open-drain output. Pull-up resistors are
assignable by software.
B
B
28-21
(22-15)
–
Bit-programmable I/O port for Schmitt trigger
input or open-drain output. Port2 can be
individually configured as external interrupt
inputs. Pull-up resistors are assignable by
software.
3-10
(41-44, 1-4)
INT0
P3.0-P3.3
P4.0-P4.3
I/O
I/O
Bit-programmable I/O port for Schmitt trigger
input, open-drain or push-pull output. P3.3 can
be used to system clock output(CLO) pin.
C
D
2, 1, 42, 41
(40-37)
P3.3/CLO
INT1
Bit-programmable I/O port for Schmitt trigger
input or open-drain output or push-pull output.
Port4 can be individually configured as external
interrupt inputs. In output mode, pull-up resistors
are assignable by software. But in input mode,
pull-up resistors are fixed.
16, 17, 19, 20
(10, 11, 13,
14)
D+/PS2
D-/PS2
I/O
Programmable port for
USB interface or PS2 interface.
–
40-39 (36-35)
38 (34)
–
3.3 VOUT
–
–
3.3 V output from internal voltage regulator
–
–
–
–
X , X
IN OUT
System clock input and output pin
(crystal/ceramic oscillator, or external clock
source)
14, 13
(8, 7)
INT0
INT1
INT2
I
External interrupt for bit-programmable port0,
port2 and port4 pins when set to input mode.
–
3-10, 16,17,
19, 20, 29-36
(30-23, 41-44,
1-4, 10, 11,
13, 14)
PORT2/
PORT4/
PORT0
RESET
TEST
I
I
RESET signal input pin. Input with internal pull-
up resistor.
A
–
18 (12)
–
–
Test signal input pin (for factory use only;
15 (9)
connected to V
)
SS
VDD
VSS
NC
–
–
–
Power input pin
Ground input pin
No connection
–
–
–
11 (5)
–
–
–
12, (6)
37
(31,32, 33)
NOTE: Pin numbers shown in parenthesis '( )' are for the 44-QFP package; others are for the 42-SDIP package.
1-6
KS86C6404/C6408/P6408
PRODUCT OVERVIEW
PIN CIRCUITS
Table 1-2. Pin Circuit Assignments for the KS86C6404/C6408/P6408
Circuit Number
Circuit Type
KS86C6404/C6408/P6408 Assignments
A
B
C
D
I
RESET signal input
Ports 0, 1, and 2
Port 3
I/O
I/O
I/O
Port 4
VDD
Pull-Up
Resistor
VDD
Pull-Up Enable
PULL-UP
RESISTOR
Output
Disable
I/O
Output
Data
Noise
Filter
IN
VSS
Input
Data
D0
D1
MUX
Mode
Input Data
Output
Input
D0
D1
Figure 1-4. Pin Circuit Type A (RESET)
Figure 1-5. Pin Circuit Type B (Ports 0, 1 and 2)
1-7
PRODUCT OVERVIEW
KS86C6404/C6408/P6408
VDD
Output
Data
Open
Drain
I/O
Output
Disable
VSS
D0
D1
Input
Data
MUX
Mode
Output
Input
Input Data
D0
D1
Figure 1-6. Pin Circuit Type C (Port 3)
1-8
KS86C6404/C6408/P6408
PRODUCT OVERVIEW
DD
V
Pull-Up
Resistor
Pull-Up
Enable
DD
V
Output
Data
Open
Drain
I/O
Output
Disable
VSS
D0
D1
Input
Data
MUX
Mode
Output
Input
Input Data
D0
D1
Figure 1-7. Pin Circuit Type D (Port 4)
1-9
PRODUCT OVERVIEW
APPLICATION CIRCUIT
5V
KS86C6404/C6408/P6408
5V
VDD
0
1
2
3
15
KS86C6404
KS86C6408
KS86P6408
X
IN
XOUT
0
1
2
3
RESET
D+/PS2
D-/PS2
DP
DM
H
7
O
S
T
KEYBOARD
MATRIX
VSS1
:
Port4 can use expend keyboard MATRIX.
NOTE
D+/PS2, D-/PS2 can use PS2 keyboard interface (see PS2CONINT, page 4-25).
Port 4.2, 4.3 can use PS2 mouse interface.
Port 3 can use LED direct drive.
Figure 1-8. Keyboard Application Circuit Diagram
1-10
KS86C6404/C6408/P6408
ADDRESS SPACES
2
ADDRESS SPACES
OVERVIEW
The KS86C6404/C6408/P6408 microcontroller has two kinds of address space:
— Program memory (ROM), internal
— Internal register file
A 13-bit address bus supports both program memory. A separate 8-bit register bus carries addresses and data
between the CPU and the internal register file.
The KS86C6404 has 4 K bytes of mask-programmable program memory on-chip and KS86C6408 has 8 K bytes.
There is one program memory configuration option:
— Internal ROM mode, in which only the 8-Kbyte internal program memory is used.
The KS86C6404/C6408/P6408 microcontroller has 208 general-purpose registers in its internal register file.
Twenty-seven bytes in the register file are mapped for system and peripheral control functions.
2-1
ADDRESS SAPCES
KS86C6404/C6408/P6408
PROGRAM MEMORY (ROM)
Normal Operating Mode (Internal ROM)
The KS86C6404 has 4 K bytes (locations 0H–0FFFH) of internal mask-programmable program memory. The
KS86C6408/P6408 has 8 K bytes (locations 0H–1FFFH) of internal mask-programmable program memory.
The first 2 bytes of the ROM (0000H–0001H) are an interrupt vector address.
The program reset address in the ROM is 0100H.
(DECIMAL)
8,191
(HEX)
1FFFH (KS86C6408/P6408)
8-Kbyte
Internal
Program
Memory
Area
4,095
0FFFH (KS86C6408)
4-Kbyte
Internal
Program
Memory
Area
Program start
0100H
256
2
1
0
0002H
0001H
0000H
Interrupt vector
Figure 2-1. Program Memory Address Space
2-2
KS86C6404/C6408/P6408
ADDRESS SPACES
REGISTER ARCHITECTURE
The upper 64 bytes of the KS86C6404/C6408/P6408's internal register file are addressed as working registers,
system control registers and peripheral control registers. The lower 192 bytes of internal register file (00H–BFH)
is called the general purpose register space. The total addressable register space is thereby 256 bytes. 233
registers in this space can be accessed.; 208 are available for general-purpose use.
For many SAM87RI microcontrollers, the addressable area of the internal register file is further expanded by the
additional of one or more register pages at general purpose register space (00H–BFH). This register file
expansion is not implemented in the KS86C6404/C6408/P6408, however. Page addressing is controlled by the
System Mode Register (SYM.1–SYM.0).
The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in
Table 2-1.
Table 2-1. Register Type Summary
Register Type
Number of Bytes
CPU and system control registers
11
34
Peripheral, I/O, and clock control and data registers
General-purpose registers (including the 16-bit
common working register area)
208
Total Addressable Bytes
253
2-3
ADDRESS SAPCES
KS86C6404/C6408/P6408
FFH
Peripheral Control
Registers
64 Bytes Of
Common Area
E0H
DFH
System Control
Registers
D0H
CFH
Working Registers
C0H
BFH
General Purpose
Register File
And Stack Area
192
Bytes
00H
Figure 2-2. Internal Register File Organization
2-4
KS86C6404/C6408/P6408
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H–CFH)
The SAM87RI register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations between different pages. However, because the
KS86C6404/C6408/P6408 uses only page 0, you can use the common area for any internal data operation.
The Register (R) addressing mode can be used to access this area
Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the
address of the first 8-bit register is always an even number and the address of the next register is an odd
number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least
significant byte is always stored in the next (+ 1) odd-numbered register.
MSB
Rn
LSB
n = EVEN ADDRES
Rn + 1
Figure 2-3. 16-Bit Register Pairs
+
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Examples:
1. LD
0C2H,40H
; Invalid addressing mode!
Use working register addressing instead:
LD
R2,40H
; R2 (C2H) ¨ the value in location 40H
; Invalid addressing mode!
2. ADD
0C3H,#45H
Use working register addressing instead:
ADD R3,#45H ; R3 (C3H) ¨ R3 + 45H
2-5
ADDRESS SAPCES
KS86C6404/C6408/P6408
SYSTEM STACK
KS86-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH
and POP instructions are used to control system stack operations. The KS86C6404/C6408/P6408 architecture
supports stack operations in the internal register file.
Stack Operations
Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address is always decremented before a push operation and incremented after
a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown
in Figure 2-4.
HIGH ADDRESS
PCL
PCL
PCH
TOP OF
STACK
PCH
TOP OF
STACK
FLAGS
STACK CONTENTS
AFTER A CALL
INSTRUCTION
STACK CONTENTS
AFTER AN
LOW ADDRESS
INTERRUPT
Figure 2-4. Stack Operations
Stack Pointer (SP)
Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset,
the SP value is undetermined.
Because only internal memory space is implemented in the KS86C6404/C6408/P6408, the SP must be initialized
to an 8-bit value in the range 00H–BFH.
NOTE: In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that
a Stack Pointer access invalid stack area.
2-6
KS86C6404/C6408/P6408
ADDRESS SPACES
+
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD
SP,#0C0H
; SP ¨ C0H (Normally, the SP is set to 0C0H by the
; initialization routine)
•
•
•
PUSH
PUSH
PUSH
PUSH
•
SYM
CLKCON
20H
; Stack address 0BFH ¨ SYM
; Stack address 0BEH ¨ CLKCON
; Stack address 0BDH ¨ 20H
; Stack address 0BCH ¨ R3
R3
•
•
POP
POP
POP
POP
R3
20H
CLKCON
SYM
; R3 ¨ Stack address 0BCH
; 20H ¨ Stack address 0BDH
; CLKCON ¨ Stack address 0BEH
; SYM ¨ Stack address 0BFH
2-7
ADDRESS SAPCES
KS86C6404/C6408/P6408
NOTES
2-8
KS86C6404/C6408/P6408
ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW
Instructions that are stored in program memory are fetched for execution using the program counter. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in SAM87RI instructions may be condition
codes, immediate data, or a location in the register file, program memory, or data memory.
The SAM87RI instruction set supports six explicit addressing modes. Not all of these addressing modes are
available for each instruction. The addressing modes and their symbols are as follows:
— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Relative Address (RA)
— Immediate (IM)
3-1
KS86C6404/C6408/P6408
ADDRESSING MODES
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register
addressing differs from Register addressing because it uses an 16-byte working register space in the register file
and an 4-bit register within that space (see Figure 3-2).
PROGRAM MEMORY
REGISTER FILE
OPERAND
8-BIT REGISTER
FILE ADDRESS
dst
POINTS TO ONE
REGISTER IN REGISTER
FILE
OPCODE
ONE-OPERAND
INSTRUCTION
(EXAMPLE)
VALUE USED IN
INSTRUCTION EXECUTION
SAMPLE INSTRUCTION:
DEC CNTR Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
;
REGISTER FILE
CFH
.
.
.
.
PROGRAM MEMORY
4-BIT
WORKING
REGISTER
4 LSBs
dst
src
OPERAND
POINTS TO THE
WORKING REGISTER
(1 OF 16)
TWO-
OPERAND
INSTRUCTION
(EXAMPLE)
OPCODE
C0H
SAMPLE INSTRUCTION:
ADD R1,R2 Where R1=C1H and R2=C2H
Figure 3-2. Working Register Addressing
;
3-2
KS86C6404/C6408/P6408
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of
the operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location.
REGISTER FILE
ADDRESS
PROGRAM MEMORY
8-BIT REGISTER
FILE ADDRESS
dst
POINTS TO ONE
REGISTER IN REGISTER
FILE
OPCODE
ONE-OPERAND
INSTRUCTION
(EXAMPLE)
ADDRESS OF OPERAND
USED BY INSTRUCTION
VALUE USED IN
INSTRUCTION
EXECUTION
OPERAND
SAMPLE INSTRUCTION:
RL @SHIFT ; Where SHIFT is the label of an 8-bit register address
Figure 3-3. Indirect Register Addressing to Register File
3-3
KS86C6404/C6408/P6408
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
REGISTER FILE
PROGRAM MEMORY
REGISTER
PAIR
EXAMPLE
dst
INSTRUCTION
POINTS TO
OPCODE
REFERENCES
PROGRAM
MEMORY
REGISTER PAIR
16-BIT
ADDRESS
POINTS TO
PROGRAM
MEMORY
PROGRAM MEMORY
OPERAND
SAMPLE INSTRUCTIONS:
CALL @RR2
VALUE USED IN
INSTRUCTION
JP
@RR2
Figure 3-4. Indirect Register Addressing to Program Memory
3-4
KS86C6404/C6408/P6408
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
REGISTER FILE
CFH
.
.
.
.
PROGRAM MEMORY
4-BIT
4 LSBs
WORKING
REGISTER
ADDRESS
dst
OPCODE
src
OPERAND
POINTS TO THE
WORKING REGISTER
(1 OF 16)
C0H
SAMPLE INSTRUCTION:
OR R6,@R2
VALUE USED IN
INSTRUCTION
OPERAND
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
KS86C6404/C6408/P6408
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Concluded)
REGISTER FILE
CFH
PROGRAM MEMORY
.
.
.
.
4-BIT
WORKING
REGISTER
dst
src
ADDRESS
NEXT 3 BITS
POINT TO
WORKING
REGISTER PAIR
(1 OF 8)
REGISTER
PAIR
OPCODE
EXAMPLE
INSTRUCTION
REFERENCES
EITHER
16-BIT
C0H
ADDRESS
POINTS TO
PROGRAM
MEMORY OR
DATA
PROGRAM
MEMORY OR
DATA MEMORY
PROGRAM MEMORY
OR
LSB SELECTS
MEMORY
DATA MEMORY
VALUE USED IN
INSTRUCTION
OPERAND
SAMPLE INSTRUCTIONS:
LDC R5,@RR2
LDE R3,@RR14
LDE @RR4,R8
; Program memory access
;
External data memory access
External data memory access
;
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
KS86C6404/C6408/P6408
ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range
–128 to +127. This applies to external memory accesses only (see Figure 3-8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address
(see Figure 3-9).
The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external
program memory, and for external data memory, when implemented.
REGISTER FILE
~
~
~
~
VALUE USED IN
INSTRUCTION
OPERAND
+
PROGRAM MEMORY
X(OFFSET)
4 LSBs
dst
OPCODE
src
TWO-
OPERAND
INDEX
POINTS TO ONE
OF THE WORKING
REGISTERS
INSTRUCTION
EXAMPLE
(1 OF 16)
SAMPLE INSTRUCTION:
LD R0,#BASE[R1]
; Where BASE is an 8-bit immediate value
Figure 3-7. Indexed Addressing to Register File
3-7
KS86C6404/C6408/P6408
ADDRESSING MODES
INDEXED ADDRESSING MODE (Continued)
REGISTER FILE
PROGRAM MEMORY
4-BIT
WORKING
REGISTER
ADDRESS
XS(OFFSET)
dst src
OPCODE
REGISTER
PAIR
NEXT 3 BITS
16-BIT
POINT TO
WORKING
REGISTER PAIR
(1 OF 8)
ADDRESS
ADDED TO
OFFSET
LSB SELECTS
+
8 BITS
16 BITS
PROGRAM MEMORY
OR
DATA MEMORY
VALUE USED IN
INSTRUCTION
OPERAND
16 BITS
SAMPLE INSTRUCTIONS:
LDC R4,#04H[RR2]
; The values in the program address (RR2 + #04H)
are loaded into register R4.
LDE R4,#04H[RR2]
; Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
KS86C6404/C6408/P6408
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
REGISTER FILE
PROGRAM MEMORY
H
XL (OFFSET)
L
4-BIT
WORKING
REGISTER
ADDRESS
XL (OFFSET)
dst src
OPCODE
REGISTER
PAIR
NEXT 3 BITS
16-BIT
POINT TO
WORKING
ADDRESS
ADDED TO
OFFSET
REGISTER PAIR
(1 OF 8)
LSB SELECTS
+
16 BITS
16 BITS
PROGRAM MEMORY
OR
DATA MEMORY
VALUE USED IN
INSTRUCTION
OPERAND
16 BITS
SAMPLE INSTRUCTIONS:
LDC R4,#1000H[RR2]
;
;
The values in the program address (RR2 + #1000H)
are loaded into register R4.
LDE R4,#1000H[RR2]
Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset
3-9
KS86C6404/C6408/P6408
ADDRESSING MODES
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
PROGRAM OR
DATA MEMORY
MEMORY
ADDRESS
USED
PROGRAM MEMORY
UPPER ADDR BYTE
LOWER ADDR BYTE
dst / src "0" OR "1"
OPCODE
LSB SELECTS PROGRAM
MEMORY OR DATA MEMORY:
"0" = PROGRAM MEMORY
"1" = DATA MEMORY
SAMPLE INSTRUCTIONS:
LDC R5,1234H
LDE R5,1234H
;
;
The values in the program address (1234H)
are loaded into register R5.
Identical operation to LDC example, except that
external program memory is accessed.
Figure 3-10. Direct Addressing for Load Instructions
3-10
KS86C6404/C6408/P6408
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
PROGRAM MEMORY
NEXT OPCODE
PROGRAM
MEMORY
ADDRESS
USED
LOWER ADDR BYTE
UPPER ADDR BYTE
OPCODE
SAMPLE INSTRUCTIONS:
JP
C,JOB1
;
;
Where JOB1 is a 16-bit immediate address
Where DISPLAY is a 16-bit immediate address
CALL DISPLAY
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
KS86C6404/C6408/P6408
ADDRESSING MODES
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.
The instructions that support RA addressing is JR.
PROGRAM MEMORY
NEXT OPCODE
PROGRAM MEMORY
ADDRESS USED
CURRENT
PC VALUE
+
DISPLACEMENT
OPCODE
CURRENT
INSTRUCTION
SIGNED
DISPLACEMENT
VALUE
SAMPLE INSTRUCTION:
JR ULT,$+OFFSET
; Where OFFSET is a value in the range
+127 to –128
Figure 3-12. Relative Addressing
IMMEDIATE MODE (IM)
In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the
operand field itself. Immediate addressing mode is useful for loading constant values into registers.
PROGRAM MEMORY
OPERAND
OPCODE
(THE OPERAND VALUE IS IN THE INSTRUCTION)
SAMPLE INSTRUCTION:
LD R0,#0AAH
Figure 3-13. Immediate Addressing
3-12
KS86C6404/C6408/P6408
CONTROL REGISTERS
4
CONTROL REGISTERS
OVERVIEW
In this section, detailed descriptions of the KS86C6404/C6408/P6408 control registers are presented in an easy-
to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can
also use them as a quick-reference source when writing application programs.
System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the
standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More information
about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this
manual.
4-1
CONTROL REGISTERS
KS86C6404/C6408/P6408
Table 4-1. System and Peripheral control Registers
Register Name
Mnemonic
T0CNT
Decimal
208
Hex
D0H
D1H
D2H
R/W
R
Timer 0 counter register
Timer 0 data register
Timer 0 control register
T0DATA
T0CON
209
R/W
R/W
210
Location D3H is not mapped.
Clock control register
System flags register
CLKCON
FLAGS
212
213
D4H
D5H
R/W
R/W
Locations D6H-D7H are not mapped.
Port 0 interrupt control register
Stack pointer
P0INT
SP
216
217
218
D8H
D9H
DAH
R/W
R/W
R/W
Port 0 interrupt pending register
P0PND
Location DBH is not mapped.
Basic timer control register
Basic timer counter register
BTCON
BTCNT
220
221
DCH
DDH
R/W
R
Location DEH is not mapped.
System mode register
SYM
P0
223
DFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 0 data register
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
Port 1 data register
P1
Port 2 data register
P2
Port 3 data register
P3
Port 4 data register
P4
Port 3 control register
P3CON
P0CONH
P0CONL
P1CONH
P1CONL
P2CONH
P2CONL
P2INT
P2PND
P4CON
P4INTPND
Port 0 control register (high byte)
Port 0 control register (low byte)
Port 1 control register (high byte)
Port 1 control register (low byte)
Port 2 control register (high byte)
Port 2 control register (low byte)
Port 2 interrupt control register
Port 2 interrupt pending register
Port 4 control register
Port 4 interrupt enable/pending register
4-2
KS86C6404/C6408/P6408
CONTROL REGISTERS
Table 4-1. System and Peripheral control Registers (Continued)
Register Name
Mnemonic
FADDR
Decimal
240
241
242
243
244
245
246
247
248
249
250
251
252
Hex
R/W
R/W
R/W
R/W
R
USB function address register
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
Control endpoint status register
Interrupt endpoint 1 control status register
Control endpoint byte count register
Control endpoint FIFO register
Interrupt endpoint 1 FIFO register
USB interrupt pending register
EP0CSR
EP1CSR
EP0BCNT
EP0FIFO
EP1FIFO
USBPND
USBINT
R/W
W
R/W
R
USB interrupt enable register
USB power management register
Interrupt endpoint 2 control status register
Interrupt endpoint 2 FIFO register
USB/PS2 Mode select register
PWRMGR
EP2CSR
EP2FIFO
USBSEL
PS2DATA
R/W
R/W
W
R/W
R/W
D+/PS2, D-/PS2 data register
(Only PS2 Mode)
PS2 control and interrupt pending register
PS2CONINT
XCON
253
254
FDH
FEH
R/W
R/W
USB Tranceiver crossover point control
register
USB reset register
USBRST
255
FFH
R/W
4-3
CONTROL REGISTERS
KS86C6404/C6408/P6408
Bit number(s) that is/are appended to
the register name for bit addressing
Name of individual
bit or bit function
Register
mnemonic
Register address
(hexadecimal)
Full register name
D5H
- System Flags Register
FLAGS
.7
.6
.5
.4
.3
.2
.1
.0
Bit Identifier
RESET
Value
x
x
x
x
x
x
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Carry Flag (C)
0
1
Operation does not generate a carry or borrow condition
Operation generates carry-out or borrow into high-order bit 7
.6
.5
Zero Flag (Z)
Operation result is a non-zero value
Operation result is zero
0
1
Sign Flag (S)
0
1
Operation generates positive number (MSB = "0")
Operation generates negative number (MSB = "1")
Description of the
effect of specific
bit settings
Bit number:
MSB = Bit 7
LSB = Bit 0
R
W
= Read-only
= Write-only
R/W = Read/write
'–' = Not used
RESET
value notation:
Not used
Undetermined value
Logic zero
Logic one
Addressing mode or modes
you can use to modify
register values
'–'
=
=
=
=
'x'
'0'
'1'
Figure 4-1. Register Description Format
4-4
KS86C6404/C6408/P6408
CONTROL REGISTERS
BTCON— Basic Timer Control Register
DCH
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.4
Watchdog Timer Enable Bits
Disable watchdog function
Any other value Enable watchdog function
1
0
1
0
.3 and .2
Basic Timer Input Clock Selection Bits
fOSC/4096
fOSC/1024
fOSC/128
0
0
1
1
0
1
0
1
Invalid setting
Basic Timer Counter Clear Bit (note)
.1
.0
0
1
No effect
Clear BTCNT
Basic Timer Divider Clear Bit (note)
0
1
No effect
Clear both dividers
NOTE: When you write a "1" to BTCON.0 (or BTCON.1), the basic timer counter (or basic timer divider) is cleared. The bit
is then cleared automatically to "0".
4-5
CONTROL REGISTERS
KS86C6404/C6408/P6408
CLKCON— System Clock Control Register
D4H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Oscillator IRQ Wake-up Function Bit
0
1
Enable IRQ for main system oscillator wake-up in power down mode
Disable IRQ for main system oscillator wake-up in power down mode
.6 and .5
.4 and .3
Not used for KS86C6404/C6408/P6408
CPU Clock (System Clock) Selection Bits (1)
Divide by 16 (fOSC/16)
Divide by 8 (fOSC/8)
Divide by 2 (fOSC/2)
Non-divided clock (fOSC
0
0
1
1
0
1
0
1
(2)
)
.2-.0
Not used for KS86C6404/C6408/P6408
NOTES:
1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.
2.
f
OSC
means oscillator frequency.
4-6
KS86C6404/C6408/P6408
CONTROL REGISTERS
EP0CSR— CONTROL ENDPOINT 0 STATUS REGISTER
F1H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
Setup Data End Clear Bit
0
1
No effect (when write)
To clear SETUP_END bit
Out Packet Ready Clear Bit
0
1
No effect (when write)
To clear OUT_PKT_RDY bit
STALL Signal Sending Bit
0
1
No effect (when write)
To send STALL signal
Setup Transfer End Bit
0
1
No effect (when write)
SIE sets this bit when a control transfer ends before DATA_END (bit3) is set
Setup Data End Bit
0
1
No effect (when write)
MCU set this bit after loading or unloading the last packet data into the FIFO
.2
.1
.0
STALL Signal Receive Bit
0
1
MCU clear this bit to end the STALL condition
SIE sets this bit if a control transaction is ended due to a protocol violation
In Packet Ready Bit
0
1
SIE clear this bit once the packet has been successfully sent to the host
MCU sets this bit after writing a packet of data into ENDPOINT0 FIFO
Out Packet Ready Bit
0
1
No effect (when write)
SIE sets this bit once a valid token is written to the FIFO
4-7
CONTROL REGISTERS
KS86C6404/C6408/P6408
EP1CSR — CONTROL ENDPOINT 1 STATUS REGISTER
F2H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Data Toggle Sequence Clear Bit
0
1
No effect (when write)
MCU sets this bit to clear the data toggle sequence bit. The data toggle is
initialized to DATA0.
.6-.3
Maximum Packet Size Bits
0
1
No effect (when write)
These bits indicate the maximum packet size for IN endpoint, and needs to be
updated by the MCU before it sets IN_PKT_RDY. Once set, the contents are
valid till MCU re-writes them.
.2
FIFO Flush Bit
0
1
No effect (when write)
When MCU writes a one to this register, the FIFO is flushed, and
IN_PKT_RDY cleared. The MCU should wait for IN_PKT_RDY to be cleared
for the flush to take place.
.1
.0
Force STALL Bit
0
1
No effect (when write)
MCU writes a 1 to this register to issue a STALL handshake to USB. MCU
clears this bit, to end the STALL condition.
In Packet Ready Bit
0
1
SIE clear this bit once the packet has been successfully sent to the host
MCU sets this bit, after writing a packet of data into ENDPOINT1 FIFO. USB
clears this bit, once the packet has been successfully sent to the host. An
interrupt is generated when USB clears this bit, so MCU can load the next
packet.
4-8
KS86C6404/C6408/P6408
CONTROL REGISTERS
EP2CSR — CONTROL ENDPOINT 2 STATUS REGISTER
F9H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Data Toggle Sequence Clear Bit
0
1
No effect (when write)
MCU sets this bit to clear the data toggle sequence bit. The data toggle is
initialized to DATA0.
.6-.3
Maximum Packet Size Bits
0
1
No effect (when write)
These bits indicate the maximum packet size for IN endpoint, and needs to be
updated by the MCU before it sets IN_PKT_RDY. Once set, the contents are
valid till MCU re-writes them.
.2
FIFO Flush Bit
0
1
No effect (when write)
When MCU writes a one to this register, the FIFO is flushed, and
IN_PKT_RDY cleared. The MCU should wait for IN_PKT_RDY to be cleared
for the flush to take place.
.1
.0
Force STALL Bit
0
1
No effect (when write)
MCU writes a 1 to this register to issue a STALL handshake to USB. MCU
clears this bit, to end the STALL condition.
In Packet Ready Bit
0
1
SIE clear this bit once the packet has been successfully sent to the host
MCU sets this bit, after writing a packet of data into ENDPOINT1 FIFO. USB
clears this bit, once the packet has been successfully sent to the host. An
interrupt is generated when USB clears this bit, so MCU can load the next
packet.
4-9
CONTROL REGISTERS
KS86C6404/C6408/P6408
FADDR— USB Function Address Register
F0H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
Not used for KS86C6404/C6408/P6408
.6-.0
FADDR
This register holds the USB address assigned by the host computer. FADDR is
located at address F0H and is read/write addressable.
4-10
KS86C6404/C6408/P6408
CONTROL REGISTERS
FLAGS — System Flags Register
D5H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
–
.2
–
.1
–
.0
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
Carry Flag (C)
Operation does not generate a carry or borrow condition
0
Zero Flag (Z)
0
1
Operation result is a non-zero value
Operation result is zero
.5
Sign Flag (S)
0
1
Operation generates a positive number (MSB = "0")
Operation generates a negative number (MSB = "1")
.4
Overflow Flag (V)
0
1
Operation result is £ +127 or _ –128
Operation result is _ +127 or £ –128
.3-0.
Not used for KS86C6404/C6408/P6408
4-11
CONTROL REGISTERS
KS86C6404/C6408/P6408
P0CONH — Port 0 Control Register (High Byte)
E6H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 0, P0.7 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 0, P0.6 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 0, P0.5 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 0, P0.4 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
4-12
KS86C6404/C6408/P6408
CONTROL REGISTERS
P0CONL — Port 0 Control Register (Low Byte)
E7H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 0, P0.3 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 0, P0.2 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 0, P0.1 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 0, P0.0 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
4-13
CONTROL REGISTERS
KS86C6404/C6408/P6408
P0INT — Port 0 Interrupt Control Register
D8H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P0.7 Configuration Bits
0
1
External interrupt disable
External interrupt enable
P0.6 Configuration Bits
0
1
External interrupt disable
External interrupt enable
P0.5 Configuration Bits
0
1
External interrupt disable
External interrupt enable
P0.4 Configuration Bits
0
1
External interrupt disable
External interrupt enable
P0.3 Configuration Bits
0
1
External interrupt disable
External interrupt enable
P0.2 Configuration Bits
0
1
External interrupt disable
External interrupt enable
P0.1 Configuration Bits
0
1
External interrupt disable
External interrupt enable
P0.0 Configuration Bits
0
1
External interrupt disable
External interrupt enable
4-14
KS86C6404/C6408/P6408
CONTROL REGISTERS
P0PND — Port 0 Interrupt Pending Register
DAH
Bit Identifier
RESET Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
(NOTE)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
.7
P0.7 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
.6
.5
.4
.3
.2
.1
.0
P0.6 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P0.5 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P0.4 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P0.3 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P0.2 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P0.1 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P0.0 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
4-15
CONTROL REGISTERS
KS86C6404/C6408/P6408
P1CONH— Port 1 Control Register (High Byte)
E8H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 1, P1.7 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 1, P1.6 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 1, P1.5 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 1, P1.4 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
4-16
KS86C6404/C6408/P6408
CONTROL REGISTERS
P1CONL— Port 1 Control Register (Low Byte)
E9H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 1, P1.3 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 1, P1.2 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 1, P1.1 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 1, P1.0 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
Schmitt trigger input with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
4-17
CONTROL REGISTERS
KS86C6404/C6408/P6408
P2CONH— Port 2 Control Register (High Byte)
EAH
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 2, P2.7 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edges external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 2, P2.6 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edges external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 2, P2.5 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edges external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 2, P2.4 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edges external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
4-18
KS86C6404/C6408/P6408
CONTROL REGISTERS
P2CONL — Port 2 Control Register (Low Byte)
EBH
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 2, P2.3 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edges external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 2, P2.2 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edges external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 2, P2.1 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edges external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
Port 2, P2.0 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edges external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
4-19
CONTROL REGISTERS
KS86C6404/C6408/P6408
P2INT — Port 2 Interrupt Enable Register
ECH
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P2.7 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P2.6 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P2.5 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P2.4 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P2.3 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P2.2 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P2.1 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P2.0 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
4-20
KS86C6404/C6408/P6408
CONTROL REGISTERS
P2PND— Port 2 Interrupt Pending Register
EDH
Bit Identifier
RESET Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
(NOTE)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
.7
P2.7 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
.6
.5
.4
.3
.2
.1
.0
P2.6 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P2.5 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P2.4 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P2.3 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P2.2 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P2.1 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
P2.0 Interrupt Pending Bit
0
1
No pending (when read)/clear pending bit (when write)
Pending (when read)/no effect (when write)
NOTE: To clear a port 2 interrupt pending condition, write a "0" to the corresponding P2PND register bit location.
4-21
CONTROL REGISTERS
KS86C6404/C6408/P6408
P3CON— Port 3 Control Register
E5H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
Port 3, P3.3 Configuration Bits
0
0
1
1
0
1
0
1
Schmitt trigger input
System clock output(CLO) mode. CLO comes from system clock circuit.
Push-pull output
N-channel open-drain output mode
.5 and .4
.3 and .2
Port 3, P3.2 Configuration Bits
0
1
1
x
0
1
Schmitt trigger input
Push-pull output
N-channel open-drain output mode
Port 3, P3.1 Configuration Bits
0
1
1
x
0
1
Schmitt trigger input
Push-pull output
N-channel open-drain output mode
.1 and .0
Port 3, P3.0 Configuration Bits
0
1
1
x
0
1
Schmitt trigger input
Push-pull output
N-channel open-drain output mode
NOTE: "x" means don't care
4-22
KS86C6404/C6408/P6408
CONTROL REGISTERS
P4CON— Port 4 Control Register
EEH
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
.5 and .4
.3 and .2
.1 and .0
Port 4, P4.3 Configuration Control Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode with pull-up
N-CH open drain output mode
Output pull-pull mode
Port 4, P4.2 Configuration Control Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode with pull-up
N-CH open drain output mode
Output pull-pull mode
Port 4, P4.1 Configuration Control Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode with pull-up
N-CH open drain output mode
Output pull-pull mode
Port 4, P4.0 Configuration Control Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode with pull-up
N-CH open drain output mode
Output pull-pull mode
4-23
CONTROL REGISTERS
KS86C6404/C6408/P6408
P4INTPND— Port 4 Interrupt Enable and Pending Register
EFH
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7
.6
.5
.4
.3
.2
.1
.0
P4.3 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P4.2 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P4.1 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P4.0 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
P4.3 Interrupt Pending Bit
0
1
No pending (when bit is read)/clear pending bit (when bit is write)
Pending (when bit is read)/no effect (when bit is write)
P4.2 Interrupt Pending Bit
0
1
No pending (when bit is read)/clear pending bit (when bit is write)
Pending (when bit is read)/no effect (when bit is write)
P4.1 Interrupt Pending Bit
0
1
No pending (when bit is read)/clear pending bit (when bit is write)
Pending (when bit is read)/no effect (when bit is write)
P4.0 Interrupt Pending Bit
0
1
No pending (when bit is read)/clear pending bit (when bit is write)
Pending (when bit is read)/no effect (when bit is write)
4-24
KS86C6404/C6408/P6408
CONTROL REGISTERS
PS2CONINT— PS2 Control and interrupt pending Register (PS2 Mode only) EEH
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
D+/PS2 Configuration Control Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, falling edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
.5 and .4
D-/PS2 Configuration Control Bits
0
0
1
1
0
1
0
1
Schmitt trigger input, falling edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output mode
N-CH open drain output mode with pull-up
.4
.3
D+/PS2 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
D-/PS2 Interrupt Enable Bit
0
1
External interrupt disable
External interrupt enable
.1
.0
D+/PS2 Interrupt Pending Bit
0
1
No pending (when bit is read)/clear pending bit (when bit is write)
Pending (when bit is read)/no effect (when bit is write)
D-/PS2 Interrupt Pending Bit
0
1
No pending (when bit is read)/clear pending bit (when bit is write)
Pending (when bit is read)/no effect (when bit is write)
4-25
CONTROL REGISTERS
KS86C6404/C6408/P6408
PWRMGR — USB POWER MANAGEMENT REGISTER
F8H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.2
.1
Not used for KS86C6404/C6408/P6408
RESUME Signal Sending Bit
0
1
RESUME signal is ended
While in suspend state, if the MCU wants to initiate a resume, it writes a 1 to
this register for 10ms (maximum of 15ms), and clears this register. In suspend
mode if this bit is a 1, USB generates resume signaling.
.0
SUSPEND Status Bit
0
Cleared when MCU writes a zero to RESUME signal sending bit or function
receives resume signal from the host while in suspend mode
1
This bit is set when SUSPEND interrupt occur
4-26
KS86C6404/C6408/P6408
CONTROL REGISTERS
SYM— System Mode Register
DFH
Bit Identifier
RESET Value
Read/Write
.6
–
.5
–
.4
–
.3
–
.2
0
.1
0
.0
0
.7
–
–
–
–
–
–
R/W
R/W
R/W
.7-.3
.2
Not used for KS86C6404/C6408/P6408
Global Interrupt Enable Bit (note)
0
1
Disable global interrupt processing
Enable global interrupt processing
.1 and .0
Page Selection Bits
Addressing page 0 locations for KS86C6404/C6408/P6408
Other values Enable global interrupt processing
NOTE: SYM must be selected bit 1 and 0 into 00 for KS86C6404/C6408/P6408.
0
0
4-27
CONTROL REGISTERS
KS86C6404/C6408/P6408
T0CON— Timer 0 Control Register
D2H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7 and .6
T0 Counter Input Clock Selection Bits
0
0
1
1
0
1
0
1
CPU clock/4096
CPU clock/256
CPU clock/8
Invalid selection
.5 and .4
T0 Operating Mode Selection Bits
0
0
Interval timer mode (The counter is automatically cleared whenever
T0DATA value equals to T0CNT value)
0
1
1
1
0
1
Invalid selection
Overflow mode (OVF interrupt can occur)
.3
.2
.1
.0
T0 Counter Clear Bit (T0CLR)
0
1
No effect when written
Clear T0 counter
T0 Overflow Interrupt Enable Bit (T0OVF)
0
1
Disable T0 overflow interrupt
Enable T0 overflow interrupt
T0 Match Interrupt Enable Bit (T0INT)
0
1
Disable T0 match interrupt
Enable T0 match interrupt
T0 Interrupt Pending Bit (T0PND)
No interrupt pending/Clear this pending bit (when write)
0
1
Interrupt is pending(when read)/No effect(when write)
NOTE: When you write a "1" to T0CON.3, the timer 0 counter is cleared. The bit is then cleared automatically to "0".
4-28
KS86C6404/C6408/P6408
CONTROL REGISTERS
USBPND— USB Interrupt Pending Register
F6H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.4
.3
Not used for KS86C6404/C6408/P6408
ENDPOINT 2 Interrupt Pending Bit
0
1
No effect (once read, this bit is cleared automatically)
This bit is set, when endpoint2 needs to be serviced
.3
.2
.1
.0
RESUME Interrupt Pending Bit
0
1
No effect (once read, this bit is cleared automatically)
While in suspend mode, if resume signaling is received this bit gets set
SUSPEND Interrupt Pending Bit
0
1
No effect (once read, this bit is cleared automatically)
This bit is set, when suspend signaling is received
ENDPOINT1 Interrupt Pending Bit
0
1
No effect (once read, this bit is cleared automatically)
This bit is set, when endpoint1 needs to be serviced
ENDPOINT0 Interrupt Pending Bit
0
1
No effect (once read, this bit is cleared automatically)
This bit is set, while endpoint 0 needs to serviced. It is set under the following
conditions;
—
—
—
—
—
OUT_PKT_RDY is set
IN_PKT_RDY get cleared
SENT_STALL gets set
DATA_END gets cleared
SETUP_END gets set
4-29
CONTROL REGISTERS
KS86C6404/C6408/P6408
USBINT— USB Interrupt Enable Register
F7H
Bit Identifier
RESET Value
Read/Write
.7
0
.6
0
.5
0
.4
0
.3
1
.2
0
.1
1
.0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.3
.3
Not used for KS86C6404/C6408/P6408
ENDPOINT2 Interrupt Pending Bit
0
1
Disable ENDPOINT 2 interrupt
Enable ENDPOINT 2 interrupt
.2
.1
.0
SUSPEND/RESUME Interrupt Enable Bit
0
1
Disable SUSPEND and RESEME interrupt
Enable SUSPEND and RESEME interrupt
ENDPOINT1 Interrupt Pending Bit
0
1
Disable ENDPOINT 1 interrupt
Enable ENDPOINT 1 interrupt
ENDPOINT0 Interrupt Pending Bit
0
1
Disable ENDPOINT 0 interrupt
Enable ENDPOINT 0 interrupt
4-30
KS86C6404/C6408/P6408
CONTROL REGISTERS
USBSEL — USB/PS2 Mode select Register
FBH
Bit Identifier
RESET Value
Read/Write
.7
–
.6
–
.5
–
.4
–
.3
–
.2
–
.1
–
.0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.1
.0
Not used for KS86C6404/C6408/P6408
USB/PS2 Mode select Bit
0
1
PS2 Mode
USB Mode
4-31
CONTROL REGISTERS
KS86C6404/C6408/P6408
XCON — USB Signal Crossover Point Control Register
FEH
Bit Identifier
RESET Value
Read/Write
.7
–
.6
–
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
–
–
R/W
R/W
R/W
R/W
R/W
R/W
.7-.6
.5-.0
Not used for KS86C6404/C6408/P6408
USB Signal Crossover Point Control Bit
Edge delay
Control
Bit 5, (2)
Bit 4, (1)
Bit 3, (0)
Delay
Value
Delay
Unit
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
4
0
1
2
4
RISE
edge
0
(about)
2.5nsec
FALL
edge
1
4-32
KS86C6404/C6408/P6408
CONTROL REGISTERS
USBRST— USB RESET REGISTER
FFH
Bit Identifier
RESET Value
Read/Write
.7
–
.6
–
.5
–
.4
–
.3
–
.2
–
.1
–
.0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
.7-.1
.0
Not used for KS86C6404/C6408/P6408
USB Reset Signal Receive Bit
0
1
Clear reset signal bit
This bit is set when host send USB reset signal
4-33
CONTROL REGISTERS
KS86C6404/C6408/P6408
NOTES
4-34
KS86C6404/C6408/P6408
INTERRUPT STRUCTURE
5
INTERRUPT STRUCTURE
OVERVIEW
The SAM87RI interrupt structure has two basic components: a vector, and sources. The number of interrupt
sources can be serviced through a interrupt vector which is assigned in ROM address 0000H-0001H.
Vector
Sources
S1
S2
S3
Sn
0000H
0001H
NOTES:
1. The SAM87RI interrupt has only one vector address (0000H-0001H)
2. The number of Sn value is expandable.
Figure 5-1. KS86-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. The
system-level control points in the interrupt structure are therefore:
— Global interrupt enable and disable (by EI and DI instructions)
— Interrupt source enable and disable settings in the corresponding peripheral control register(s)
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
The system mode register, SYM (DFH), is used to enable and disable interrupt processing.
SYM.2 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.2. An Enable
Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to
enable interrupt processing. Although you can manipulate SYM.2 directly to enable and disable interrupts during
normal operation, we recommend that you use the EI and DI instructions for this purpose.
5-1
INTERRUPT STRUCTURE
KS86C6404/C6408/P6408
INTERRUPT PENDING FUNCTION TYPES
When the interrupt service routine has executed, the application program's service routine must clear the
appropriate pending bit before the return from interrupt subroutine (IRET) occurs.
INTERRUPT PRIORITY
Because there is not a interrupt priority register in SAM87RI, the order of service is determined by a sequence of
source which is executed in interrupt service routine.
"EI" Instruction
S
R
Q
Interrupt Pending Register
Execution
RESET
Vector
Interrupt
Cycle
Interrupt Priority
Is Determined By
Software Polling Method
Source
Interrupts
Source
Interrupt
Enable
Global Interrupt Control (EI, DI
Instructions)
Figure 5-2. Interrupt Function Diagram
5-2
KS86C6404/C6408/P6408
INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request pending bit to "1".
2. The CPU generates an interrupt acknowledge signal.
3. The service routine starts and the source's pending flag is cleared to "0" by software.
4. Interrupt priority must be determined by software polling method.
INTERRUPT SERVICE ROUTINES
Before an interrupt request can be serviced, the following conditions must be met:
— Interrupt processing must be enabled (EI, SYM.2 = "1")
— Interrupt must be enabled at the interrupt's source (peripheral control register)
If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.
The CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.2 = "0")
to disable all subsequent interrupts.
2. Save the program counter and status flags to stack.
3. Branch to the interrupt vector to fetch the service routine's address.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores
the PC and status flags and sets SYM.2 to "1"(EI), allowing the CPU to process the next interrupt request.
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt
processing follows this sequence:
1. Push the program counter's low-byte value to stack.
2. Push the program counter's high-byte value to stack.
3. Push the FLAGS register values to stack.
4. Fetch the service routine's high-byte address from the vector address 0000H.
5. Fetch the service routine's low-byte address from the vector address 0001H.
6. Branch to the service routine specified by the 16-bit vector address.
5-3
INTERRUPT STRUCTURE
KS86C6404/C6408/P6408
KS86C6404/C6408/P6408 INTERRUPT STRUCTURE
The KS86C6404/C6408/P6408 microcontroller has fourteen peripheral interrupt sources:
— Timer 0 match interrupt
— Timer 0 overflow interrupt
— Eight external interrupts for port 2, P2.0-P2.7
— Four external interrupts for port 4, P4.0-P4.3
Vector
Pending Bits
T0CON.0
Enable/Disable
Sources
Timer 0 Match Interrupt
Timer 0 Overflow Interrupt
P0.X External Interrupt
P2.X External Interrupt
T0CON.1
T0CON.2
P0INT.X
P2INT.X
P0PND.X
P2PND.X
P4.0-3External Interrupt
Endpoint 0 Interrupt
Endpoint 1 Interrupt
Endpoint 2 Interrupt
P4INTPND.0-3
P4INTPND.0
P4INTPND.1
P4INTPND.4
P4INTPND.4-7
USBINT.0
USBINT.1
0000H
USBINT.3
EI/DI
(SYM.2)
D-/PS2 Interrupt
D+/PS2 Interrupt
Suspend Interrupt
PS2INPND.0
PS2INTPND.1
USBPND.2
PS2INTPND.2
PS2INTPND.3
USBINT.2
Resume Interrupt
USBPND.3
USBINT.2
“X” means 0 -7 bit.
NOTE:
Figure 5-3. KS86C6404/C6408/P6408 Interrupt Structure
5-4
KS86C6404/C6408/P6408
CLOCK CIRCUIT
7
CLOCK CIRCUIT
C1
C2
XIN
6 MHz
XOUT
KS86C6404
KS86C6408
Figure 7-1. Main Oscillator Circuit
(Crystal/Ceramic Oscillator)
MAIN OSCILLATOR LOGIC
To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator
circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the
CPU to efficiently process logic operations.
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows:
— In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file
and current system register values are retained. Stop mode is released, and the oscillator started, by a reset
operation or by an external interrupt with RC-delay noise filter (for KS86C6404/C6408/P6408, INT0-INT2).
— In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The
current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file
is retained. Idle mode is released by a reset or by an interrupt (external or internally-generated).
7-1
CLOCK CIRCUIT
KS86C6404/C6408/P6408
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the
following functions:
— Oscillator IRQ wake-up function enable/disable (CLKCON.7)
— Oscillator frequency divide-by value: non-divided, 2, 8 or 16 (CLKCON.4 and CLKCON.3)
The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release
(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7.
After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the
fOSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU
clock speed to fOSC, fOSC/2 or fOSC/8.
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
D4H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used for KS86C6404/C6408/P6408
Oscillator IRQ wake-up enable bit:
0 = Enable IRQ for main system
oscillator wake-up function
1 = Disable IRQ for main system
oscillator wake-up function
Divide-by selection bits for
CPU clock frequency:
00 = fOSC/16
01 = fOSC/8
10 = fOSC/2
11 = fOSC (non-divided)
Not used for KS86C6404/C6408/P6408
Figure 7-2. System Clock Control Register (CLKCON)
7-2
KS86C6404/C6408/P6408
CLOCK CIRCUIT
STOP
Instruction
CLKCON.3, .4
Oscillator
STOP
1/2
1/8
M
U
X
MAIN
OSC
CPU CLOCK
Oscillator
Wake-up
P3.3/CLO
1/16
NOISE
FILTER
P3CON
CLKCON.7
INT Pin
Figure 7-3. System Clock Circuit Diagram
7-3
CLOCK CIRCUIT
KS86C6404/C6408/P6408
NOTES
7-4
KS86C6404/C6408/P6408
RESET AND POWER-DOWN
8
RESET AND POWER-DOWN
SYSTEM RESET
OVERVIEW
During a power-on reset, the voltage at VDD is High level and the RESET pin is forced to Low level. The RESET
signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the
KS86C6404/C6408/P6408 into a known operating status.
The RESET pin must be held to Low level for a minimum time interval after the power supply comes within
tolerance in order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation
stabilization time for a reset is approximately 10ms (@ 216/fOSC, fOSC = 6 MHz).
When a reset occurs during normal operation (with both VDD and RESET at High level), the signal at the RESET
pin is forced Low and the reset operation starts. All system and peripheral control registers are then set to their
default hardware reset values (see Table 8-1).
The following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watchdog function (basic timer) is enabled.
— Ports 0-4 are set to Schmitt trigger input mode and all pull-up resistors are disabled.
— Peripheral control and data registers are disabled and reset to their initial values.
— The program counter is loaded with the ROM reset address, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location
0100H (and 0101H) is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, you must make the appropriate settings to
the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the
basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs),
you can disable it by writing '1010B' to the upper nibble of BTCON.
8-1
RESET AND POWER-DOWN
KS86C6404/C6408/P6408
POWER-DOWN MODES
STOP MODE
Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all
peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than
300 µA. All system functions are halted when the clock "freezes", but data stored in the internal register file is
retained. Stop mode can be released in one of two ways: by a RESET signal or by an external interrupt.
Using RESET to Release Stop Mode
Stop mode is released when the RESET signal is released and returns to High level. All system and peripheral
control registers are then reset to their default values and the contents of all data registers are retained. A reset
operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to '00B'.
After the oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by
fetching the 16-bit address stored in ROM locations 0100H and 0101H.
Using an External Interrupt to Release Stop Mode
Only external interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related
external interrupts cannot be used). External interrupts INT0-INT2 in the KS86C6404/C6408/P6408 interrupt
structure meet this criteria.
Note that when Stop mode is released by an external interrupt, the current values in system and peripheral
control registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and
CLKCON.4 register values remain unchanged, and the currently selected clock value is used. If you use an
external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization
interval. To do this, you must make the appropriate control and clock settings before entering Stop mode.
The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service
routine, the instruction immediately following the one that initiated Stop mode is executed.
IDLE MODE
Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select
peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt
logic and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered.
There are two ways to release Idle mode:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects a slow clock (1/16) because CLKCON.3 and
CLKCON.4 are cleared to '00B'. If interrupts are masked, a reset is the only way to release Idle mode.
2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle
mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock
value is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction
immediately following the one that initiated Idle mode is executed.
NOTE
Only external interrupts that are not clock-related can be used to release Stop mode. To release Idle
mode, however, any type of interrupt (that is, internal or external) can be used.
8-2
KS86C6404/C6408/P6408
RESET AND POWER-DOWN
HARDWARE RESET VALUES
Tables 8-1 through 8-3 list the values for CPU and system registers, peripheral control registers and peripheral
data registers following a reset operation in normal operating mode. The following notation is used in these tables
to represent specific reset values:
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An 'x' means that the bit value is undefined following a reset.
— A dash ('-') means that the bit is either not used or not mapped.
Table 8-1. Register Values after a Reset
Register Name
Mnemonic
Address
Dec Hex
Bit Values after RESET
7
x
x
0
1
0
6
x
x
0
1
0
5
x
x
0
1
0
4
x
x
0
1
0
3
x
x
0
1
0
2
x
x
0
1
0
1
x
x
0
1
0
0
x
x
0
1
0
General purpose registers
Working registers
–
000-191 00H-BFH
192-207 C0H-CFH
R0 - R15
T0CNT
T0DATA
T0CON
Timer 0 counter
208
209
210
D0H
D1H
D2H
Timer 0 data register
Timer 0 control register
Location D3H is not mapped.
Clock control register
System flags register
CLKCON
FLAGS
212
213
D4H
D5H
0
0
0
0
0
0
0
0
0
–
0
–
0
–
0
–
Locations D6H - D8H are not mapped.
Port 0 interrupt control register
Stack pointer
P0INT
SP
216
217
218
D8H
D9H
DAH
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
Port 0 interrupt pending register
P0PND
Location DBH is not mapped.
Basic timer control register
Basic timer counter
BTCON
BTCNT
220
221
DCH
DDH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Location DEH is not mapped.
System mode register
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
SYM
P0
223
224
225
226
227
228
DFH
E0H
E1H
E2H
E3H
E4H
0
0
0
0
0
0
–
0
0
0
0
0
–
0
0
0
0
0
–
0
0
0
0
0
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1
P2
P3
P4
8-3
RESET AND POWER-DOWN
KS86C6404/C6408/P6408
Table 8-1. Register Values after a Reset (continued)
Bank 0 Register Name
Mnemonic
Address
Dec Hex
229 E5H
230 E6H
231 E7H
232 E8H
233 E9H
234 EAH
235 EBH
236 ECH
237 EDH
238 EEH
Bit Values after a Reset
7
0
0
0
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Port 3 control register
P3CON
P0CONH
P0CONL
P1CONH
P1CONL
P2CONH
P2CONL
P2INT
Port 0 control register (high byte)
Port 0 control register (low byte)
Port 1 control register (high byte)
Port 1 control register (low byte)
Port 2 control register (high byte)
Port 2 control register (low byte)
Port 2 interrupt enable register
Port 2 interrupt pending register
Port 4 control register
P2PND
P4CON
Port 4 interrupt enable/pending
register
P4INTPND 239 EFH
USB function address register
Control endpoint status register
Interrupt endpoint status register
Control endpoint byte count register
Control endpoint FIFO register
Interrupt endpoint FIFO register
USB interrupt pending register
USB interrupt enable register
USB power management register
FADDR
EP0CSR
EP1CSR
EP0BCNT
EP0FIFO
EP1FIFO
USBPND
USBINT
240
241
242
243
244
245
246
247
248
249
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
x
x
0
1
0
0
0
0
0
0
x
x
0
1
0
0
PWRMGR
EP2CSR
Interrupt endpoint 2 control status
register
Interrupt endpoint 2 FIFO register
USB/PS2 Mode select register
EP2FIFO
USBSEL
PS2DATA
250 FAH
251 FBH
252 FCH
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
D+/PS2, D-/PS2 data register
(Only PS2 Mode)
PS2 control and interrupt pending
register
PS2CONINT 253 FDH
0
–
x
0
–
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
1
USB Tranceiver crossover point
control register
XCON
254 FEH
255 FFH
USB reset register
USBRST
8-4
KS86C6404/C6408/P6408
I/O PORTS
9
I/O PORTS
OVERVIEW
The KS86C6404/C6408/P6408 USB Mode has five I/O ports (0-4) with a total of 32 pins.
PS2 Mode has six I/O ports (0-4 and D+/PS2, D-/PS2) with a total of 34 pins.
You can access these ports directly by writing or reading port data register addresses.
For keyboard applications, ports 0, 1 and 2 are usually configured as keyboard matrix input/output. Port 3 can be
configured as LED drive. Port 4 is used for host communication or for controlling a mouse or other external
device.
Table 9-1. KS86C6404/C6408/P6408 Port Configuration Overview
Port
Function Description
Programmability
Bit-programmable I/O port for Schmitt trigger input or open-drain output.
Port0 can be individually configured as external interrupt inputs. Pull-up
resistors are assignable by software.
0
Bit
Bit-programmable I/O port for Schmitt trigger input or open-drain output.
Pull-up resistors are assignable by software.
1
2
Bit
Bit
Bit-programmable I/O port for Schmitt trigger input or open-drain output.
Port2 can be individually configured as external interrupt inputs. Pull-up
resistors are assignable by software.
Bit-programmable I/O port for Schmitt trigger input, open-drain or push-
pull output. P3.3 can be used to system clock output (CLO) pin.
3
4
Bit
Bit
Bit-programmable I/O port for Schmitt trigger input or open-drain output
or push-pull output. Port4 can be individually configured as external
interrupt inputs. In output mode, pull-up resistors are assignable by
software. But in input mode, pull-up resistors are fixed.
Bit-programmable I/O port for Schmitt trigger input or open-drain output
or push-pull output. This port individually configured as external interrupt
inputs. In output mode, pull-up resistors are assignable by software. But
in input mode, pull-up resistors are fixed.
D+/PS2
D-/PS2
(PS2 mode
Only)
Bit
9-1
I/O PORTS
S86C6404/C6408/P6408
PORT DATA REGISTERS
Table 9-2 gives you an overview of the port data register names, locations and addressing characteristics. Data
registers for ports 0-4 have the structure shown in Figure 9-1.
Table 9-2. Port Data Register Summary
Register Name
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Mnemonic
Decimal
224
Hex
E0H
E1H
E2H
E3H
E4H
R/W
R/W
R/W
R/W
R/W
R/W
P0
P1
P2
P3
P4
225
226
227
228
I/O PORT n DATA REGISTER (n = 0–4)
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Pn.0
Pn.1
Pn.2
Pn.3
Pn.4
Pn.5
Pn.6
Pn.7
:
Because only the four lower-nibble pins of port 3 and port 4
are mapped, data register bits P3.4-P3.7 and P4.4-P4.7
are not used.
NOTE
Figure 9-1. Port Data Register Format
9-2
KS86C6404/C6408/P6408
PORT 0 AND PORT 1
I/O PORTS
Ports 0 bit-programmable, general-purpose, I/O ports. You can select Schmitt trigger input mode, N-CH open
drain output mode.
You can access ports 0 and 1 directly by writing or reading the corresponding port data registers — P0 (E0H) and
P1 (E1H). A reset clears the port control registers P0CONH, P0CONL, P1CONH and P1CONL to '00H',
configuring all port 0 and port 1 pins as Schmitt trigger inputs.
In typical keyboard controller applications, the sixteen port 0 and port 1 pins can be used to check pressed key
from keyboard matrix by generating keystrobe output signals.
Port 0 Control Registers
P0CONH, E6H, R/W, P0CONL, E7H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P0CONH
P0CONL
P0.7/INT2
P0.3/INT2
P0.6/INT2
P0.2/INT2
P0.5/INT2
P0.1/INT2
P0.4/INT2
P0.0/INT2
7,5,3,1
Port Mode Selection
6,4,2,0
0
0
1
1
Schmitt trigger input, rising edge external interrupt mode
Schmitt trigger input, falling edge external interrupt mode with pull-up
N-CH open drain output mode
0
1
0
1
N-CH open drain output mode with pull-up
Figure 9-2. Port 0 Control Registers (P0CONH, P0CONL)
9-3
I/O PORTS
S86C6404/C6408/P6408
Port 1 Control Registers
P1CONH, E8H, R/W, P1CONL, E9H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P1CONH
P1CONL
P1.7
P1.3
P1.6
P1.2
P1.5
P1.1
P1.4
P1.0
Port Mode Selection
Schmitt trigger input mode
Schmitt trigger input mode with pull-up
N-CH open drain output mode
7,5,3,1 6,4,2,0
0
0
1
1
0
1
0
1
N-CH open drain output mode with pull-up
Figure 9-3. Port 1 Control Registers (P1CONH, P1CONL)
9-4
KS86C6404/C6408/P6408
PORT 2
I/O PORTS
Port 2 is an 8-bit I/O port with individually configurable pins. It can be used for general I/O (Schmitt trigger input
mode or push-pull output mode). Or, you can use port 2 pins as external interrupt (INT0) inputs. In addition, you
can configure a pull-up resistor to individual pins using control register settings. All port 2 pin circuits have noise
filters.
In typical keyboard controller applications, the port 2 pins are programmed to receive key input data from the
keyboard matrix.
You can address port 2 bits directly by writing or reading the port 2 data register, P2 (E2H). The port 2 high-byte
and low-byte control registers, P2CONH and P2CONL, are located at addresses EAH and EBH, respectively.
Two additional registers, are used for interrupt control: P2INT (ECH) and P2PND (EDH). By setting bits in the
port 2 interrupt enable register P2INT, you can configure specific port 2 pins to generate interrupt requests when
rising or falling signal edges are detected. The application program polls the port 2 interrupt pending register,
P2PND, to detect interrupt requests. When an interrupt request is acknowledged, the corresponding pending bit
must be cleared by the interrupt service routine.
In case of keyboard applications, the port 2 pins can be used to read key value from key matrix.
Port 2 Control Registers
P2CONH, EAH, R/W, P2CONL, EBH, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
P2CONH
P2CONL
P2.7/INT0
P2.3/INT0
P2.6/INT0
P2.2/INT0
P2.5/INT0
P2.1/INT0
P2.4/INT0
P2.0/INT0
7,5,3,1 6,4,2,0
Port Mode Selection
Schmitt trigger input, rising edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain
0
0
1
1
0
1
0
1
N-CH open drain with pull-up
Figure 9-4. Port 2 Control Registers (P2CONH, P2CONL)
9-5
I/O PORTS
S86C6404/C6408/P6408
Port 2 Interrupt Enable Register (P2INT)
ECH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.0/ INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
P2.6/INT0
P2.7/INT0
Port 2 interrupt control settings:
0 = Disable interrupt at P2.n pin
1 = Enable interrupt at P2.n pin
Figure 9-5. Port 2 Interrupt Enable Register (P2INT)
Port 2 Interrupt Pending Register (P2PND)
EDH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P2.4/INT0
P2.5/INT0
P2.6/INT0
P2.7/INT0
Port 2 interrupt request pending bits:
0 = No interrupt is pending
1 = Interrupt request is pending
Figure 9-6. Port 2 Interrupt Pending Register (P2PND)
9-6
KS86C6404/C6408/P6408
PORT 3
I/O PORTS
Port 3 is a 4-bit, bit-configurable, general I/O port. It is designed for high-current functions such as LED drive.
A reset configures P3.0-P3.3 to Schmitt trigger input mode. Using the P3CON register (E5H), you can
alternatively configure the port 3 pins as n-channel, open-drain outputs. P3.3 can be used to system clock output
(CLO) port.
Port3 Control Register (P3CON)
E5H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P3.3/CLO
7
P3.2
P3.1
P3.0
6
Port Mode Selection (Pin 3.3)
Schmitt trigger input
System Clock output (CLO) mode.
CLO comes from System clock circuit.
Push-pull output
0
0
0
1
1
1
0
1
N-CH Open drain output
5,3,1
4,2,0
Port Mode Selection (Pin 3.2-Pin 3.0)
Schmitt trigger input
Push-pull output
N-CH open drain output
0
1
1
x
0
1
Figure 9-7. Port 3 Control Register (P3CON)
9-7
I/O PORTS
PORT 4
S86C6404/C6408/P6408
Port 4 is a 4-bit I/O port with individually configurable pins. It can be used for general I/O (Schmitt trigger, N-CH
open drain output mode, push-pull output mode). Or, you can use port 4 pins as external interrupt (INT1) inputs.
In addition, you can configure a pull-up resistor to individual pins using control register settings. All port 4 pins
have noise filters.
A reset configures P4.0-P4.3 to input mode. You address port 4 directly by writing or reading the port 4 data
register, P4 (E4H). The port 4 control register, P4CON, is located at EEH.
A additional registers used for interrupt control: P4INTPND (EFH). By setting bits in the port 4 interrupt enable
and pending register P4INTPND.7-P4INTPND.4, you can configure specific port 4 pins to generate interrupt
requests when falling signal edges are detected. The application program polls the interrupt pending register,
P4INTPND.3-P4INTPND.0, to detect interrupt requests. When an interrupt request is acknowledged, the
corresponding pending bit must be cleared by the interrupt service routine.
Port 4 Control Register (P4CON)
EEH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P4.0/INT1
P4.1/INT1
P4.2/INT1
P4.3/INT1
P4CON Pin Configuration Settings:
00
01
10
11
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output with pull-up register
N-CH open drain output
Push-pull output
Figure 9-8. Port 4 Control Register (P4CON)
9-8
KS86C6404/C6408/P6408
I/O PORTS
Port 4 Interrupt Enable And Pending Register (P4INTPND)
EFH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P4.0/INT1
P4.1/INT1
P4.2/INT1
P4.3/INT1
P4.0/INT1
P4.1/INT1
P4.2/INT1
P4.3/INT1
P4INTPND.7 - 4 : Port 4 interrupt control settings:
0 = Disable interrupt at P4.n pin
1 = Enable interrupt at P4.n pin
P4INTPND.3 - 0 : Port 4 interrupt pending bits:
0 = No interrupt request pending
1 = Interrupt request is pending
Figure 9-9. Port 4 Interrupt Enable and Pending Register (P4INTPND)
9-9
I/O PORTS
S86C6404/C6408/P6408
D+/PS2, D-/PS2
PS2 Control And Interrupt And Pending Register
FDH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
D-/PS2PND
D+/PS2PND
D-/PS2INT
D+/PS2INT
D-/PS2
D+/PS2
PS2CONINT.7-4 Pin Configuration Settings: D+/PS2, D-/PS2
00
01
10
11
Schmitt trigger input, falling edge external interrupt
Schmitt trigger input, falling edge external interrupt with pull-up
N-CH open drain output
N-CH open drain output with pull-up register
PS2CONINT.3-2: Interrupt control setting
0 = Disable interrupt
1 = Enable interrupt
PS2CONINT.3 - 2: Interrupt control setting
0 = No interrupt request pending
1 = Interrupt request is pending
NOTE: Use only PS2MODE
Figure 9-10. PS2CONINT Register (PS2CONINT)
9-10
KS86C6404/C6408/P6408
BASIC TIMER AND TIMER 0
10 BASIC TIMER and TIMER 0
MODULE OVERVIEW
The KS86C6404/C6408/P6408 has two default timers: an 8-bit basic timer and one 8-bit general-purpose
timer/counter. The 8-bit timer/counter is called timer 0.
Basic Timer (BT)
You can use the basic timer (BT) in two different ways:
— As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.
— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
The functional components of the basic timer block are:
— Clock frequency divider (fOSC divided by 4096, 1024, or 128) with multiplexer
— 8-bit basic timer counter, BTCNT (DDH, read-only)
— Basic timer control register, BTCON (DCH, read/write)
Timer 0
Timer 0 has two operating modes, one of which you select by the appropriate T0CON setting:
— Interval timer mode
— Overflow mode
Timer 0 has the following functional components:
— Clock frequency divider (fOSC divided by 4096, 256, or 8) with multiplexer
— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)
— Timer 0 overflow interrupt (T0OVF) and match interrupt (T0INT) generation
— Timer 0 control register, T0CON
10-1
BASIC TIMER AND TIMER 0
KS86C6404/C6408/P6408
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watchdog timer function.
A reset clears BTCON to '00H'. This enables the watchdog function and selects a basic timer clock frequency of
fOSC/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic timer
register control bits BTCON.7-BTCON.4.
The 8-bit basic timer counter, BTCNT, can be cleared at any time during normal operation by writing a "1" to
BTCON.1. To clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a
"1" to BTCON.0.
BASIC TIMER CONTROL REGISTER (BTCON)
DCH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Divider clear bit for basic
timer and timer 0:
Watchdog timer enable bits:
1010B
= Disable watchdog
function
0 = No effect
1 = Clear both dividers
Other value = Enable watchdog
function
Basic timer counter clear bit:
0 = No effect
1 = Clear BTCNT
Basic timer input clock selection bits:
00 = fOSC /4096
01 = fOSC /1024
10 = fOSC /128
11 = Invalid selection
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
KS86C6404/C6408/P6408
BASIC TIMER AND TIMER 0
BASIC TIMER FUNCTION DESCRIPTION
Watchdog Timer Function
You can program the basic timer overflow signal to generate a reset by setting BTCON.7-BTCON.4 to any value
other than '1010B' (The '1010B' value disables the watchdog function). A reset clears BTCON to '00H',
automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the
current CLKCON register setting) divided by 4096 as the BT clock.
A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must
be cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always
broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when
Stop mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).
When BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the
clock signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when Stop mode is released:
1. During Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and
oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of fOSC /4096. If an external
interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.
3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.
4. When a BTCNT.4 is set, normal CPU operation resumes.
Figures 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release
10-3
BASIC TIMER AND TIMER 0
KS86C6404/C6408/P6408
Oscillation stabilization time
Normal operating mode
V
0.5 V
DD
DD
Reset Release Voltage
RESET
trst »RC
Internal
Reset
Release
0.5 V
DD
Oscillator
(Xout)
Oscillator stabilization time
BTCNT
clock
10000B
BTCNT
value
00000B
WAIT=(4096x16)/fosc
t
Basic timer increment and
CPU operations are IDLE mode
NOTE:
Duration of the oscillator stabilization wait time, tWAIT, when it is released by a
Power-on-reset is 4096x16/fosc.
trst » RC (R is external resister and C is on chip capacitor)
Figure 10-2. Oscillation Stabilization Time on RESET
10-4
KS86C6404/C6408/P6408
BASIC TIMER AND TIMER 0
Normal
operating
mode
Normal
operating
mode
STOP mode
Oscillation stabilization time
VDD
STOP
instruction
execution
STOP mode
release signal
External
interrupt
RESET
STOP
release
signal
Oscillator
(Xout)
BTCNT
clock
10000B
BTCNT
value
00000B
t
WAIT
Basic timer increment
Duration of the oscillator stabilization wait time, tWAIT, it is released by an interrupt is
determined by the setting in basic timer control register, BTCON.
NOTE:
BTCON.3
BTCON.2
tWAIT
tWAIT (When fosc is 6 MHz)
0
0
1
1
0
1
0
1
(4096 x 16) / fosc
(1024 x 16) / fosc
(128 x 16) / fosc
Invalid setting
10.92 ms
2.7 ms
0.34 ms
—
Figure 10-3. Oscillation Stabilization Time on STOP Mode Release
10-5
BASIC TIMER AND TIMER 0
KS86C6404/C6408/P6408
TIMER 0 CONTROL REGISTER (T0CON)
T0CON is located at address D2H, and is read/write addressable.
A reset clears T0CON to '00H'. This sets timer 0 to normal interval match mode, selects an input clock frequency
of fOSC/4096, and disables the timer 0 overflow interrupt and match interrupt. You can clear the timer 0 counter
at any time during normal operation by writing a "1" to T0CON.3.
The timer 0 overflow interrupt can be enabled by writing a "1" to T0CON.2. When a timer 0 overflow interrupt
occurs and is serviced by the CPU, the pending condition must be cleared by software by writing a "0" to the
timer 0 interrupt pending bit, T0CON.0.
To enable the timer 0 match interrupt, you must write T0CON.1 to "1". To detect an interrupt pending condition,
the application program polls T0CON.0. When a "1" is detected, a timer 0 match/ capture interrupt is pending.
When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0"
to the timer 0 interrupt pending bit, T0CON.0.
TIMER 0 CONTROL REGISTER (T0CON)
D2H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 0 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending (when read)
No effect (when write)
Timer 0 input clock selection bits:
00 = fOSC/4096
01 = fOSC/256
10 = fOSC/8
11 = Invalid selection
Timer 0 match interrupt enable bit:
0 = Disable match interrupt
1 = Enable match interrupt
Timer 0 operating mode selection bits:
00 = Interval match mode
01 = Invalid selection
10 = Invalid selection
11 = Overflow mode
Timer 0 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 counter clear bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Figure 10-4. Timer 0 Control Register (T0CON)
10-6
KS86C6404/C6408/P6408
BASIC TIMER AND TIMER 0
TIMER 0 FUNCTION DESCRIPTION
Interval Match Mode
In interval match mode, a match signal is generated when the counter value is identical to the value written to the
T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt and then clears the
counter. If for example, you write the value '10H' to T0DATA, the counter will increment until it reaches '10H'. At
this point, the T0 match interrupt is generated, the counter value is reset and counting resumes.
Overflow Mode
In overflow mode, a overflow signal is generated regardless of the value written to the T0 reference data register
when the counter value is overflowed. The overflow signal generates a timer 0 overflow interrupt and then T0
counter is cleared.
T0OVF
Data Bus
T0PND
8
T0INT
CLK
Counter
R
Match
Comparator
T0DATA Buffer Register
When 8-Bit counter is cleared,
this buffer is open
T0DATA
8
Data Bus
Figure 10-5. Simplified Timer 0 Function Diagram: Interval Timer Mode
10-7
BASIC TIMER AND TIMER 0
KS86C6404/C6408/P6408
Bit 1
Write '1010xxxxB' to disable.
Bits 7, 6, 5, 4
RESET or STOP
Data Bus
8
1/4096
1/1024
8-Bit Basic Counter
RESET
OVF
MUX
(
Read-Only)
BTCNT,
XIN
DIV
R
1/128
When BTCNT.4 is set after releasing from
RESET or STOP mode, CPU clock starts.
Bit 2
OVINT
Bits 3, 2
Bits 7, 6
Bit 0
Overflow
Data Bus
Bit 3
T0CLR
R
8
1/128
1/8
Bit 1
T0INT
8-Bit Counter
2-BIT
SCA
LER
R
(
Read-Only)
T0CNT,
DIV
Match
Signal
8
Bit 0
IRQ
Match/
8-Bit Comparator
8
Overflow
Bits 5, 4
T0DATA Buffer Register
When 8-Bit counter is cleared
this open.l
T0DATA
8
Data Bus
Basic Timer Control Register
Timer 0 Control Register
Figure 10-6. Basic Timer and Timer 0 Block Diagram
10-8
KS86C6404/C6408/P6408
UNIVERSAL SERIAL BUS
11 UNIVERSAL SERIAL BUS
OVERVIEW
Universal Serial Bus (USB) is a communication architecture that supports data transfer between a host computer
and a wide range of PC peripherals. USB is actually a cable bus in which the peripherals share its bandwidth
through a host scheduled token based protocol.
The USB module in KS86C6404/C6408/P6408 is designed to serve at a low speed transfer rate (1.5 Mbs) USB
device as described in the Universal Serial Bus Specification Revision 1.0. KS86C6404/C6408/P6408 can be
briefly describe as a microcontroller with SAM 87RI core with an on-chip USB peripheral as can be seen in figure
11-1.
The KS86C6404/C6408/P6408 comes equipped with Serial Interface Engine (SIE), which handles the
communication protocol of the USB. The KS86C6404/C6408/P6408 supports the following control logic: packet
decoding/generation, CRC generation/checking, NRZI encoding/decoding, Sync detection, EOP (end of packet)
detection and bit stuffing.
KS86C6404/C6408/P6408 supports two types of data transfers; control and interrupt. Three endpoints are used in
this device; Endpoint 0, Endpoint 1, and Endpoint 2 . Please refer to the USB specification revision 1.0 for detail
description of USB.
11-1
UNIVERSAL SERIAL BUS
KS86C6404/C6408/P6408
D+/PS2
D-/PS2
Transceiver
Voltage Regulator
SIE (Serial
Interface
Engine)
SAM87RI
CORE
Endpoint0 FIFO
Endpoint1,2 FIFO
Data Bus
Figure 11-1. USB Peripheral Interface
11-2
KS86C6404/C6408/P6408
UNIVERSAL SERIAL BUS
Serial Bus Interface Engine (SIE)
The Serial Interface Engine interfaces to the USB serial data and handles, deserialization/serialization of data,
NRZI encoding/decoding, clock extraction, CRC generation and checking, bit stuffing and other specifications
pertaining to the USB protocol such as handling inter packet time out and PID decoding.
Control Logic
The USB control logic manages data movements between the CPU and the transceiver by manipulating the
transceiver and the endpoint register. This includes both transmit and receive operations on the USB. The logic
contains byte count buffers for transmit operations that load the active transmit endpoint's byte count and use
this to determine the number of bytes to transfer. The same buffer is used for receive transactions to count the
number of bytes received and transfer that number to the receive endpoint's byte count register at the end of the
transaction.
The control logic in KS86C6404/C6408/P6408, when transmitting, manages parallel to serial conversion, packet
generation, CRC generation, NRZI encoding and bit stuffing.
When receiving, the control logic in KS86C6404/C6408/P6408 handles Sync detection, packet decoding, EOP
(end of packet) detection, bit stuffing, NRZI decoding, CRC checking and serial to parallel conversion
Bus Protocol
All bus transactions involve the transmission of packets. KS86C6404/C6408/P6408 supports three packet types;
Token, Data and Handshake. Each transaction starts when the host controller sends a Token Packet to the USB
device. The Token packets are generated by the USB host and decoded by the USB device. A Token Packet
includes the type description, direction of the transaction, USB device address and the endpoint number.
Data and Handshake packets are both decoded and generated by the USB device. In any transaction, the data is
transferred from the host to a device or from a device to the host. The transaction source then sends a Data
Packet or indicates that it has no data to transfer. The destination then responds with a Handshake Packet
indicating whether the transfer was successful.
Data Transfer Types
USB data transfer occurs between the host software and a specific endpoint on the USB device. An endpoint
supports a specific type of data transfer. The KS86C6404/C6408/P6408 supports two data transfer endpoints:
control and interrupt.
Control transfer configures and assigns an address to the device when detected. Control transfer also supports
status transaction, returning status information from device to host.
Interrupt transfer refers to a small, spontaneous data transfer from USB device to host.
Endpoints
Communication flows between the host software and the endpoints on the USB device. Each endpoint on a
device has an identifier number. In addition to the endpoint number, each endpoint supports a specific transfer
type. KS86C6404/C6408/P6408 supports three endpoints: Endpoint 0 supports control transfer, and Endpoint 1
and Endpoint 2 supports interrupt transfer.
11-3
UNIVERSAL SERIAL BUS
KS86C6404/C6408/P6408
USB FUNCTION ADDRESS REGISTER (FADDR)
This register holds the USB address assigned by the host computer. FADDR is located at address F0H and is
read/write addressable.
Bit7
Not used
Bit6-0 FADDR: MCU updates this register once it decodes a SET_ADDRESS command. MCU must write this
register before it clears OUT_PKT_RDY (bit0) and sets DATA_END (bit3) in the EP0CSR register. The
function controller use this register's value to decode USB Token packet address. At reset, if the device
is not yet configured the value is reset to 0.
USB Function Address Register (FADDR)
F0H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used for KS86C6404/C6408/P6408
7-bit programming device address. This register
maintains the USB address assigned by the host. The
function controller uses this register’s value to
decode USB token packet address. At reset when the
device is not yet configured the value is reset to 0.
Figure 11-2. USB Function Address Register (FADDR)
11-4
KS86C6404/C6408/P6408
UNIVERSAL SERIAL BUS
CONTROL ENDPOINT CONTROL STATUS REGISTER (EP0CSR)
EP0CSR register controls Endpoint 0 (Control Endpoint), and also holds status bits for Endpoint 0. EP0CSR is
located at F1H and is read/write addressable.
Bit7
Bit6
Bit5
CLEAR_SETUP_END: MCU writes “1” to this bit to clear SETUP_END bit (bit4). This bit is
automatically cleared after writing "1" by USB block.
CLEAR_OUT_PKT_RDY: MCU writes “1” to this bit to clear OUT_PKT_RDY bit (bit0). This bit is
automatically cleared after writing "1" by USB block.
SEND_STALL: MCU writes “1” to this bit to send STALL signal to the Host, at the same time it clears
OUT_PKT_RDY (bit0), if it decodes an invalid token. USB issues a STALL Handshake to the current
control transfer. This bit gets cleared once a STALL Handshake is issued to the current control transfer.
Bit4
Bit3
SETUP_END: USB sets this bit, when a control transfer ends before DATA_END bit (bit3) is set. MCU
clears this bit, by writing a “1” to CLEAR_SETUP_END bit (bit7). When USB sets this bit, an interrupt is
generated to MCU. When such condition occurs, USB flushes the FIFO, and invalidates MCU’s access to
FIFO.
DATA_END: MCU sets this bit:
— After loading the last packet of data into the FIFO, and at the same time IN_PKT_RDY bit is set.
— While it clears OUT_PKT_RDY bit after unloading the last packet of data.
— For a zero length data phase, when it clears OUT_PKT_RDY bit, and sets IN_PKT_RDY bit.
Bit2
Bit1
SENT_STALL: USB sets this bit, if a control transaction has ended due to a protocol violation. An
interrupt is generated when this bit gets set. MCU clears this bit to end the STALL condition.
IN_PKT_RDY: MCU sets this bit, after writing a packet of data into Endpoint 0 FIFO. USB clears this bit,
once the packet has been successfully sent to the host. An interrupt is generated when USB clears this
bit so that MCU can load the next packet. For a zero length data phase, MCU sets IN_PKT_RDY bit and
DATA_END bit at the same time.
Bit0
OUT_PKT_RDY: USB sets this bit, once a valid token is written to FIFO. An interrupt is generated,
when USB sets this bit. MCU clears this bit by writing "1” to CLEAR_OUT_PKT_RDY bit.
In control transfer case, where there is no data phase, MCU after unloading the setup token, sets IN_PKT_RDY,
and DATA_END at the same time it clears OUT_PKT_RDY for the setup token.
When SETUP_END bit is set, OUT_PKT_RDY bit may also be set. This happens when the current transfer has
ended, and a new control transfer is received before MCU can service the interrupt. In such case, MCU should
first clear SETUP_END bit, and then start servicing the new control transfer.
11-5
UNIVERSAL SERIAL BUS
KS86C6404/C6408/P6408
Control Endpoint Status Register (EP0CSR)
F1H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
CLEAR_
SETUP_END
OUT_PKT_RDY
IN_PKT_RDY
SENT_STALL
DATA_END
CLEAR_
OUT_PKT_RDY
SEND_STALL
SETUP_END
Figure 11-3. Control Endpoint Status Register (EP0CSR)
11-6
KS86C6404/C6408/P6408
UNIVERSAL SERIAL BUS
INTERRUPT ENDPOINT 1 CONTROL STATUS REGISTER (EP1CSR)
EP1CSR is the control register for Endpoint 1, Interrupt Endpoint. This register is located at address F2H and is
read/write addressable.
Bit7
CLEAR_DATA_TOGGLE: MCU writes “1” to this bit to clear the data toggle sequence bit. When the
MCU writes a 1 to this register, the data toggle bit is initialized to DATA0.
Bit6-3 MAXP: These bits indicate the maximum packet size for IN endpoint, and needs to be updated by MCU
before it sets IN_PKT_RDY. Once set, the contents are valid till MCU re-writes them.
Bit2
Bit1
Bit0
FLUSH_FIFO: When MCU writes “1” to this register, the FIFO is flushed, and IN_PKT_RDY cleared.
The MCU should wait for IN_PKT_RDY to be cleared for the flush to take place.
FORCE_STALL: MCU writes “1” to this register to issue a STALL Handshake to USB. MCU clears this
bit, to end the STALL condition.
IN_PKT_RDY: MCU sets this bit, after writing a packet of data into Endpoint 1 FIFO. USB clears this bit,
once the packet has been successfully sent to the Host. An interrupt is generated when USB clears this
bit, so MCU can load the next packet.
Control Endpoint Status Register (EP1CSR)
F2H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
CLEAR_DATA_TOGGLE
IN_PKT_RDY
FORCE_STALL
FLUSH_FIFO
MAXP
Figure 11-4. 1 Interrupt Endpoint 1 Status Register (EP1CSR)
11-7
UNIVERSAL SERIAL BUS
KS86C6404/C6408/P6408
INTERRUPT ENDPOINT 2 CONTROL STATUS REGISTER (EP2CSR)
EP2CSR is the control register for Endpoint 2, Interrupt Endpoint. This register is located at address F9H and is
read/write addressable.
Bit7
CLEAR_DATA_TOGGLE: MCU writes “1” to this bit to clear the data toggle sequence bit. When the
MCU writes a 1 to this register, the data toggle bit is initialized to DATA0.
Bit6-3 MAXP: These bits indicate the maximum packet size for IN endpoint, and needs to be updated by MCU
before it sets IN_PKT_RDY. Once set, the contents are valid till MCU re-writes them.
Bit2
Bit1
Bit0
FLUSH_FIFO: When MCU writes “1” to this register, the FIFO is flushed, and IN_PKT_RDY cleared.
The MCU should wait for IN_PKT_RDY to be cleared for the flush to take place.
FORCE_STALL: MCU writes “1” to this register to issue a STALL Handshake to USB. MCU clears this
bit, to end the STALL condition.
IN_PKT_RDY: MCU sets this bit, after writing a packet of data into Endpoint 1 FIFO. USB clears this bit,
once the packet has been successfully sent to the Host. An interrupt is generated when USB clears this
bit, so MCU can load the next packet.
Control Endpoint Status Register (EP2CSR)
F9H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
CLEAR_DATA_TOGGLE
IN_PKT_RDY
FORCE_STALL
FLUSH_FIFO
MAXP
Figure 11-5. 2 Interrupt Endpoint Status Register (EP2CSR)
CONTROL ENDPOINT BYTE COUNT REGISTER (EP0BCNT)
EP0BCNT register has the number of valid bytes in Endpoint 0 FIFO. It is located at address F3H read-only
addressable. Once the MCU receives a OUT_PKT_RDY (Bit0 of EP0CSR) for Endpoint 0, then it can read this
register to find out the number of bytes to be read from Endpoint 0 FIFO.
11-8
KS86C6404/C6408/P6408
UNIVERSAL SERIAL BUS
CONTROL ENDPOINT FIFO REGISTER (EP0FIFO)
This register is bi-directional, 8-byte depth FIFO used to transfer Control Endpoint data. EP0FIFO is located at
address F4H and is read/write addressable.
Initially, the direction of the FIFO, is from the Host to the MCU. After a setup token is received for a control
transfer, that is, after MCU unload the setup data packet, and clears OUT_PKT_RDY, the direction of FIFO is
changed automatically by the direction bit of data packet.
INTERRUPT ENDPOINT 1 FIFO REGISTER (EP1FIFO)
EP1FIFO is an uni-direction 8-byte depth FIFO used to transfer data from the MCU to the Host. MCU writes data
to this register, and when finished set IN_PKT_RDY. This register is located at address F5H.
INTERRUPT ENDPOINT 2 FIFO REGISTER (EP2FIFO)
EP1FIFO is an uni-direction 8-byte depth FIFO used to transfer data from the MCU to the Host. MCU writes data
to this register, and when finished set IN_PKT_RDY. This register is located at address FAH.
11-9
UNIVERSAL SERIAL BUS
KS86C6404/C6408/P6408
USB INTERRUPT PENDING REGISTER (USBPND)
USBPND register has the interrupt bits for endpoints and power management. This register is cleared once read
by MCU. While any one of the bits is set, an interrupt is generated. USBPND is located at address F6H.
Bit7-4 Not used
Bit4
Bit3
Bit2
Bit1
Bit0
ENDPT2_PND: This bit is set, when Endpoint 2 needs to be serviced.
RESUME_PND: While in suspend mode, if resume signaling is received this bit gets set.
SUSPEND_PND: This bit is set, when suspend signaling is received.
ENDPT1_PND: This bit is set, when Endpoint 1 needs to be serviced.
ENDPT0_PND: This bit is set, when Endpoint 0 needs to be serviced. It is set under any one of the
following conditions:
— OUT_PKT_RDY is set.
— IN_PKT_RDY gets cleared.
— SENT_STALL gets set.
— DATA_END gets cleared.
— SETUP_END gets set.
USB Interrupt Pending Register (USBPND)
F6H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
ENDPT2_PND
RESUME_PND
SUSPEND_PND
Not used
ENDPT0_PND
ENDPT1_PND
Figure 11-6. USB Interrupt Pending Register (USBPND)
11-10
KS86C6404/C6408/P6408
UNIVERSAL SERIAL BUS
USB INTERRUPT ENABLE REGISTER (USBINT)
USBINT is located at address F7H and is read/write addressable. This register serves as an interrupt mask
register. If the corresponding bit = 1 then the respective interrupt is enabled.
By default, all interrupts except suspend interrupt is enabled. Interrupt enables bits for suspend and resume is
combined into a single bit (bit 2).
Bit7-3 Not used
Bit3
Bit2
Bit1
Bit0
ENABLE_ENDPT2_INT:
1 Enable ENDPOINT 1 INTERRUPT (default)
0 Disable ENDPOINT 1 INTERRUPT
ENABLE_SUSPEND_RESUME_INT:
1 Enable SUSPEND and RESUME INTERRUPT
0 Disable SUSPEND and RESUME INTERRUPT (default)
ENABLE_ENDPT1_INT:
1 Enable ENDPOINT 1 INTERRUPT (default)
0 Disable ENDPOINT 1 INTERRUPT
ENABLE_ENDPT0_INT:
1 Enable ENDPOINT 0 INTERRUPT (default)
0 Disable ENDPOINT 0 INTERRUPT
USB Interrupt Enable Register (USBINT)
F7H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
ENABLE_ENDPT0_INT
ENABLE_ENDPT1_INT
ENABLE_SUSPEND_RESUME_INT
Not used
ENABLE_ENDPT2_INT
Figure 11-7. USB Interrupt Enable Register (USBINT)
11-11
UNIVERSAL SERIAL BUS
KS86C6404/C6408/P6408
USB POWER MANAGEMENT REGISTER (PWRMGR)
PWRMGR register interacts with the Host’s power management system to execute system power events such as
SUSPEND or RESUME. This register is located at address F8H and is read/write addressable.
Bit7-2 RESERVED: The value read from this bit is zero.
Bit1
Bit0
SEND_RESUME: While in SUSPEND state, if the MCU wants to initiate RESUME, it writes “1” to this
register for 10ms (maximum of 15 ms), and clears this register. In SUSPEND mode if this bit reads “1”,
USB generates RESUME signaling.
SUSPEND_STATE: Suspend state is set when the MCU sets suspend interrupt. This bit is cleared
automatically when:
— MCU writes “0” to SEND_RESUME bit to end the RESUME signaling (after SEND_RESUME is set
for
10 ms).
— MCU receives RESUMES signaling from the Host while in SUSPEND mode.
USB Power Management Register (PWRMGR)
F8H, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
SUSPEND_STATE
SEND_RESUME
The value read form
this bit is zero
Figure 11-8. USB Power Management Register (PWRMGR)
11-12
KS86C6404/C6408/P6408
UNIVERSAL SERIAL BUS
USB MODE SELECT REGISTER (USBSEL)
USBSEL is located at address FBH and is read/write addressable. This register serves as an USB Mode and
PS2 Mode.
Bit7-1 Not used
Bit0
USBSEL: 0 = PS2 Mode. (Default)
1 = USB Mode. (This bit is set when the D+/PS2, D-/PS2 port set the D+, D-)
USB Mode Select Register (USBSEL)
FBH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
USBSEL
Figure 11-9. USB Mode Select Register (USBSEL)
11-13
UNIVERSAL SERIAL BUS
KS86C6404/C6408/P6408
USB RESET REGISTER (USBRST)
USBRST register receives a reset signal from the Host. This register is located at address FFH and is read/write
addressable.
Bit7-1 Not used
Bit0
USBRST: This bit is set when the Host issues an USB reset signal.
USB RESET Register (USBRST)
FFH, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
USBRST
Not used
Figure 11-10. USB RESET Register (USBRST)
11-14
KS86C6404/C6408/P6408
ELECTRICAL DATA
12 ELECTRICAL DATA
OVERVIEW
In this section, the following KS86C6404/C6408/P6408 electrical characteristics are presented in tables and
graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— Input/Output capacitance
— A.C. electrical characteristics
— Input timing for external interrupt (Ports 0, 2 and 4) D+/PS2, D-/PS2 : PS2 Mode Only
— Input timing for RESET
— Oscillator characteristics
— Oscillation stabilization time
— Clock timing measurement points at XIN
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a reset
— Stop mode release timing when initiated by an external interrupt
— Characteristic curves
12-1
ELECTRICAL DATA
KS86C6404/C6408/P6408
Table 12-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
VDD
VIN
Conditions
–
Rating
Unit
V
Supply Voltage
Input Voltage
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 18
All input ports
V
Output Voltage
Output Current High
VO
All output ports
V
IOH
One I/O pin active
All I/O pins active
One I/O pin active
Total pin current for ports 3
Total pin current for ports 0, 1, 2, 4
–
mA
– 60
Output Current Low
IOL
+ 30
mA
+ 100
+ 100
Operating
Temperature
TA
– 40 to + 85
°
°
C
C
Storage
TSTG
–
– 65 to + 150
Temperature
12-2
KS86C6404/C6408/P6408
ELECTRICAL DATA
Table 12-2. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.25 V)
°
°
Parameter
Symbol
Conditions
fOSC = 6 MHz
Min
Typ
Max
Unit
VDD
Operating Voltage
4.0
5.0
5.25
V
(instruction clock = 1 MHz)
All input pins except VIH2
VIH1
VIH2
VIH3
VIL1
VIL2
VIL2
VOH
0.8 VDD
VDD
VDD
Input High Voltage
Input Low Voltage
–
V
V
V
XIN
VDD – 0.5
0.5VDD
–
RESET
All input pins except VIL2
0.2 VDD
0.4
–
XIN
0.5VDD
–
RESET
IOH = – 200 µA; All output
VDD – 1.0
Output High
Voltage
–
ports except ports 0, 1 and 2,
D+, D–
VOL
IOL
IOL = 1 mA
Output Low Voltage
Output Low Current
–
8
–
0.4
23
V
All output port except D+, D–
VOL = 3V
15
mA
Port 3 only
(3)
VIN = VDD
All inputs except ILIH2
except D+, D–
Input High
Leakage Current
–
–
3
µA
ILIH1
(3)
VIN = VDD
XIN, XOUT, RESET
–
–
–
–
20
µA
µA
ILIH2
(3)
VIN = 0 V
Input Low
– 3
ILIL1
Leakage Current
All inputs except ILIL2
except D+, D–
(3)
VIN = 0 V
–
–
– 20
µA
ILIL2
XIN, XOUT, RESET
12-3
ELECTRICAL DATA
KS86C6404/C6408/P6408
Table 12-2. D.C. Electrical Characteristics (continued)
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.25 V)
°
°
Parameter
Output High
Symbol
Conditions
VOUT = VDD
Min
Typ
Max
Unit
(1)
–
–
3
µA
ILOH
Leakage Current
All I/O pins and output pins
except D+, D–
ILOL (1)
VOUT = 0 V
Output Low
–
–
– 3
µA
Leakage Current
All I/O pins and output pins
except D+, D–
RL1
VIN = 0 V
Pull-up Resistors
Supply Current (2)
25
50
100
kW
Ports 0, 1, 2, 4.2-3, Reset
RL2
V
IN
= 0 V; P4.0-1
2.4
5.5
IDD1
Normal operation mode
6 MHz CPU clock
–
12
mA
IDD2
IDD3
Idle mode; 6 MHz oscillator
Stop mode
2.2
5
mA
µA
180
300
NOTES:
1. Except X and X
.
IN
OUT
2. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
3. When USB Mode Only in 4.2 V to 5.25 V, D+ and D– satisfy the USB spec 1.0.
12-4
KS86C6404/C6408/P6408
ELECTRICAL DATA
Table 12-3. Input/Output Capacitance
(TA = – 40 C to + 85 C, VDD = 0 V)
°
°
Parameter
Input
Capacitance
Symbol
Conditions
Min
Typ
Max
Unit
CIN
f = 1 MHz; Unmeasured pins
are connected to VSS
–
–
10
pF
COUT
CIO
Output
Capacitance
I/O Capacitance
Table 12-4. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, V
= 4.0 V to 5.25 V)
DD
Parameter
Symbol
Conditions
P0, P2 and P4
Min
Typ
Max
Unit
tINTH, tINTL
Interrupt Input
–
200
–
ns
High, Low Width
tRSL
RESET Input
Low Width
RESET
10
–
–
ms
t
t
INTH
INTL
0.8 V
DD
0.2 V
DD
Figure 12-1. Input timing for external interrupt (Ports 0, 2, and 4)
t
RSL
RESET
0.5VDD
Figure 12-2. Input Timing for RESET
12-5
ELECTRICAL DATA
KS86C6404/C6408/P6408
Table 12-5. Oscillator Characteristics
(TA = – 40 C + 85 C, VDD = 4.0 V to 5.25 V)
°
°
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Main crystal Main
Oscillation frequency
–
6.0
–
MHz
X
ceramic (fOSC
)
IN
C1
X
OUT
C2
External clock
Oscillation frequency
–
6.0
–
X
X
IN
OUT
Table 12-6. Oscillation Stabilization Time
(TA = – 40 C + 85 C, VDD = 4.0 V to 5.25 V)
°
°
Oscillator
Test Condition
Min
Typ
Max
Unit
fOSC = 6.0 MHz
Main Crystal
–
–
10
ms
(Oscillation stabilization occurs when VDD is equal to
the minimum oscillator voltage range.)
Main Ceramic
216/
fOSC
t
stop mode release time by a reset
Oscillator
Stabilization Wait
Time
–
–
–
–
WAIT
(note)
t
stop mode release time by an interrupt
WAIT
NOTE: The oscillator stabilization wait time, t
, is determined by the setting in the basic timer control register, BTCON.
WAIT
12-6
KS86C6404/C6408/P6408
ELECTRICAL DATA
Table 12-7. Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
VDDDR
Conditions
Stop mode
Min
Typ
Max
Unit
Data Retention
Supply Voltage
2.0
–
6
V
IDDDR
Stop mode; VDDDR = 2.0 V
Data Retention
Supply Current
–
–
300
µA
1/f
OSC
t
t
XH
XL
X
IN
VDD 0.5V
0.4V
Figure 12-3. Clock Timing Measurement Points at X
IN
12-7
ELECTRICAL DATA
KS86C6404/C6408/P6408
Internal Reset
Operation
Idle Mode
(Basic Timer
Active)
Stop Mode
Data Retention
Mode
VDD
Normal
Operating
Mode
VDDDR
Execution Of
Stop Instruction
RESET
0.5 VDD
0.5 VDD
t
WAIT
Figure 12-4. Stop Mode Release Timing When Initiated by a Reset
Idle Mode
(Basic Timer
Active)
Stop Mode
Data Retention Mode
VDD
Normal
Operating
Mode
VDDDR
Execution Of
Stop Instruction
External
Interrupt
0.8 VDD
0.2 VDD
t
WAIT
Figure 12-5. Stop Mode Release Timing When Initiated by an External Interrupt
12-8
KS86C6404/C6408/P6408
ELECTRICAL DATA
Table 12-8. Low Speed USB Electrical Characteristics
(TA = – 40°C to + 85°C, Voltage Regulator Output V33out = 2.8 V to 3.5 V, typ 3,3 V)
Parameter
Transition Time:
Rise Time
Symbol
Conditions
Min
Max
Unit
Tr
Tf
CL = 50 pF
CL = 350 pF
CL = 50 pF
75
–
–
ns
300
–
Fall Time
75
–
CL = 350 pF
(Tr/Tf) CL = 50 pF
CL = 50 pF
300
120
2.0
3.5
Rise/Fall Time Matching
Trfm
Vcrs
80
1.3
2.8
%
V
Output Signal Crossover Voltage
Voltage Regulator Output Voltage V33OUT
V
with V33OUT to GND 0.1 mF
capacitor
Test
Point
2.8V
90%
90%
Measurement
Points
S/W
CL
R2
10%
10%
D.U.T
R1
Tr
Tf
R1 = 15 K
R2 = 1.5 K
DM: S/W ON
DP: S/W OFF
W
W
CL = 50pF-350pF
Figure 12-6. USB Data Signal Rise and Fall Time
3.3 V
DP
MAX: 2.0 V
MIN: 1.3 V
0 V
Vcrs
DM
Figure 12-7. USB Output Signal Crossover Point Voltage
12-9
ELECTRICAL DATA
KS86C6404/C6408/P6408
NOTES
12-10
KS86C6404/C6408/P6408
MECHANICAL DATA
13 MECHANICAL DATA
OVERVIEW
The KS86C6404/C6408/P6408 is available in a 42-pin SDIP package (Samsung: 42-SDIP-600) and a 44-pin QFP
package (44-QFP-1010B). Package dimensions are shown in Figures 13-1 and 13-2.
#42
#22
0-15
°
40-SDIP-600
#1
#21
39.50 MAX
39.10 ± 0.2
0.50 ± 0.1
1.00 ± 0.1
1.778
(1.77)
Figure 13-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600 )
13-1
MECHANICAL DATA
KS86C6404/C6408/P6408
13.20 ± 0.3
10.00 ± 0.2
0 8°
-
+0.10
- 0.05
0.15
44-QFP-1010B
0.10 MAX
#44
0.05 MIN
2.05 ± 0.10
+0.10
- 0.05
#1
0.35
2.30 MAX
(1.00)
0.80
NOTE: Dimensions are in millimeters.
Figure 13-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
13-2
KS86C6404/C6408/P6408
KS86P6408 OTP
14 KS86P6408 OTP
OVERVIEW
The KS86P6408 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS86C6404/C6408 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is
accessed by serial data format.
The KS86P6408 is fully compatible with the KS86C6404/C6408, both in function and in pin configuration.
Because of its simple programming requirements, the KS86P6408 is ideal for use as an evaluation chip for the
KS86C6404/C6408.
P3.1
P3.0
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.2
P3.3/CLO
D+
2
INT0 / P2.0
INT0 / P2.1
INT0 / P2.2
INT0 / P2.3
INT0 / P2.4
INT0 / P2.5
3
4
D-
5
3.3 V
NC
OUT
6
7
P0.0 / INT2
P0.1 / INT2
P0.2 / INT2
P0.3 / INT2
P0.4 / INT2
P0.5 / INT2
P0.6 / INT2
P0.7 / INT2
P1.0
8
/INT0 / P2.6
SDAT
9
/INT0 / P2.7
SCLK
10
11
12
13
14
15
16
17
18
19
20
21
KS86P6408
/VDD
VDD
VSS
/VSS
/XOUT
XOUT
42-SDIP
(Top View)
/XIN
XIN
/TEST
TEST
INT1 / P4.0
INT1 / P4.1
P1.1
P1.2
RESET
/ RESET
P1.3
INT1 / P4.2
INT1 / P4.3
P1/7
P1.4
P1.5
P1.6
Figure 14-1. KS86P6408 Pin Assignments (42-SDIP Package)
14-1
KS86P6408 OTP
KS86C6404/C6408/P6408
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
3.3 V
22
21
20
19
18
17
16
15
14
13
12
34
35
36
37
38
39
40
41
42
43
44
OUT
D-/PS2
D+/PS2
P3.3/CLO
P3.2
KS86P6408
P3.1
(Top View)
P3.0
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
P4.3/INT1
P4.2/INT1
RESET/ RESET
Figure 14-2. KS86P6408 Pin Assignments (44-QFP Package)
14-2
KS86C6404/C6408/P6408
KS86P6408 OTP
Table 14-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
Pin Name
P2.6
During Programming
I/O
Pin Name
Pin No.
Function
9 (3)
SDAT
I/O
Serial DATa Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned
10 (4)
15 (9)
P2.7
SCLK
TEST
I/O
I
Serial CLocK Pin (Input Only Pin)
TEST
Chip Initialization and EPROM Cell Writing
Power Supply Pin (Indicates OTP Mode
Entering) When writing 12.5 V is applied and
when reading.
18 (12)
RESET
RESET
I
0 V: OTP write and test mode
5 V: Operating mode
11(5)/12(6)
VDD / VSS
VDD / VSS
–
Logic Power Supply Pin.
NOTE: ( ) means 44 QFP package.
Table 14-2. Comparison of KS86P6408 and KS86C6404/C6408 Features
Characteristic KS86P6408 KS86C6404/C6408
8-Kbyte EPROM
4.0 V to 5.25 V
= 5 V, VPP (RESET) = 12.5 V
Program Memory
8-Kbyte mask ROM
4.0 V to 5.25 V
Operating Voltage (VDD
)
V
DD
OTP Programming Mode
Pin Configuration
42 SDIP/44 QFP
42 SDIP/44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (RESET) pin of the KS86P6408, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 14-3 below.
Table 14-3. Operating Mode Selection Criteria
V
DD
REG/
MEM
R/W
MODE
VPP
(RESET)
ADDRESS
(A15-A0)
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
14-3
KS86P6408 OTP
KS86C6404/C6408/P6408
START
Address= First Location
V
DD
=5V, V =12.5V
PP
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 14-3. OTP Programming Algorithm
14-4
KS86C6404/C6408/P6408
KS86P6408 OTP
Table 14-4. D.C. Electrical Characteristics
_
_
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.25 V)
Parameter
Symbol
Conditions
Normal mode;
Min
Typ
Max
Unit
IDD1
IDD2
IDD3
Supply Current
(note)
–
5.5
12
mA
6 MHz CPU clock
Idle mode;
6 MHz CPU clock
2.2
5
Stop mode
180
300
µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
14-5
KS86P6408 OTP
KS86C6404/C6408/P6408
NOTES
14-6
KS86C6404/C6408/P6408
DEVELOPMENT TOOLS
15 DEVELOPMENT TOOLS
OVERVIEW
Samsung provides a powerful and easy-to-use development support system in turnkey form. The development
support system is configured with a host system, debugging tools, and support software. For the host system, any
standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool
including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for
KS57, KS86, KS88 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2.
Samsung also offers support software that includes debugger, assembler, and a program for setting options.
SHINE
Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE
provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked
help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be
sized, moved, scrolled, highlighted, added, or removed completely.
SAMA ASSEMBLER
The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates
object code in standard hexadecimal format. Assembled program code includes the object code that is used for
ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an
auxiliary definition (DEF) file with device specific information.
SASM86
The SASM86 is an relocatable assembler for Samsung's KS86-series microcontrollers. The SASM86 takes a
source file containing assembly language statements and translates into a corresponding source code, object
code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating
system. It produces the relocatable object code only, so the user should link object file. Object files can be linked
with other object files and loaded into memory.
HEX2ROM
HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be
needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by
HEX2ROM, the value "FF" is filled into the unused ROM area upto the maximum ROM size of the target device
automatically.
15-1
DEVELOPMENT TOOLS
TARGET BOARDS
KS86C6404/C6408/P6408
Target boards are available for all KS86-series microcontrollers. All required target system cables and adapters
are included with the device-specific target board.
OTPs
One times programmable microcontrollers (OTPs) are under development for KS86C6404/C6408
microcontroller.
IBM-PC AT or Compatible
RS-232C
SMDS2+
TARGET
APPLICATION
SYSTEM
PROM/OTP WRITER UNIT
RAM BREAK/ DISPLAY UNIT
TRACE/TIMER UNIT
SAM4 BASE UNIT
PROBE
ADAPTER
TB866408A
TARGET
BOARD
POD
EVA
CHIP
POWER SUPPLY UNIT
Figure 15-1. SMDS Product Configuration (SMDS2+)
15-2
KS86C6404/C6408/P6408
DEVELOPMENT TOOLS
TB866408A TARGET BOARD
The TB866408A target board is used for the KS86C6404/C6408 microcontrollers. It is supported by the SMDS2+
development systems. The TB866408A target board can also be used for KS86C6404/C6408.
TB866408A
To User_V CC
OFF
ON
RESET
IDLE
+
STOP
+
25
J101
1
40
CN1
144 QFP
KS86E6000
EVA CHIP
1
1
30
EXTERNAL
TRIGGERS
20
21
CH1
CH2
SMDS2
SMDS2+
SM1306A
Figure 15-2. TB866408A Target Board Configuration
15-3
DEVELOPMENT TOOLS
KS86C6404/C6408/P6408
Table 15-1. Power Selection Settings for TB866408A
Operating Mode
'To User_Vcc' Settings
Comments
The SMDS2/SMDS2+
To User_Vcc
supplies VCC to the target
TARGET
SYSTEM
OFF
ON
TB866408A
board (evaluation chip) and
the target system.
V
CC
V
SS
V
CC
SMDS2+
The SMDS2/SMDS2+
supplies VCC only to the
To User_Vcc
OFF
TB866408A
External
TARGET
SYSTEM
ON
target board (evaluation
chip). The target system must
have its own power supply.
V
CC
V
SS
V
CC
SMDS2+
NOTE: The following symbol in the "To User_V " Setting column indicates the electrical short (off) configuration:
CC
SMDS2+ Selection (SAM8)
In order to write data into program memory that is available in SMDS2+, the target board should be selected to
be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.
Table 15-2. The SMDS2+ Tool Selection Setting
"SW1" Setting
Operating Mode
SMDS2
SMDS2+
R/W*
R/W*
SMDS2+
TARGET
BOARD
15-4
KS86C6404/C6408/P6408
DEVELOPMENT TOOLS
Table 15-3. Using Single Header Pins as the Input Path for External Trigger Sources
Target Board Part Comments
Connector from
external trigger
sources of the
EXTERNAL
TRIGGERS
application system
CH1
CH2
a
You can connect an external trigger source to one of the two
external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint
and trace functions.
15-5
DEVELOPMENT TOOLS
KS86C6404/C6408/P6408
J101
P3.1
P3.0
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P3.2
P3.3/CLO
D+
INT0/P2.0
INT0/P2.1
INT0/P2.2
INT0/P2.3
INT0/P2.4
INT0/P2.5
INT0/P2.6
INT0/P2.7
D-
3.3 V
OUT
V
SS2
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4/INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
P1.0
P1.1
P1.2
P1.3
P1.4
9
10
11
12
13
14
15
16
17
18
19
20
V
DD
V
SS1
V
SS
INT1/P4.0
INT1/P4.1
RESET
INT1/P4.2
INT1/P4.3
P1.7
P1.6
P1.5
Figure 15-3. 40-Pin Connector for TB866408A
TARGET BOARD
J101
40
TARGET SYSTEM
J101
1
40
1
1
42
42 SDIP
Conversion
PCB
Part Name: AP42SD-J
Order Code: SM6524
20 21
21 22
20
21
Figure 15-4. KS86C6408 Probe Adapter Cable for 42-SDIP Package
15-6
KS86 SERIES MASK ROM ORDER FORM
Product description:
Device Number: KS86C__________- ___________ (write down the ROM code number)
Product Order Form:
Package
Pellet
Wafer
Package Type: __________
Package Marking (Check One):
Standard
Custom A
(Max 10 chars)
Custom B
(Max 10 chars each line)
@ YWW
Device Name
@ YWW
@ YWW
Device Name
SEC
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities:
Deliverable
ROM code
Required Delivery Date
Quantity
Comments
–
Not applicable
See ROM Selection Form
Customer sample
Risk order
See Risk Order Sheet
Please answer the following questions:
For what kind of product will you be using this order?
+
New product
Upgrade of an existing product
Other
Replacement of an existing product
If you are replacing an existing product, please indicate the former product name
(
)
+
What are the main reasons you decided to use a Samsung microcontroller in your product?
Please check all that apply.
Price
Product quality
Features and functions
Delivery on time
Development system
Used same micom before
Technical support
Quality of documentation
Samsung reputation
Mask Charge (US$ / Won):
Customer Information:
____________________________
Company Name:
___________________
Telephone number
_________________________
Signatures:
________________________
(Person placing the order)
__________________________________
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
KS86 SERIES
REQUEST FOR PRODUCTION AT CUSTOMER RISK
Customer Information:
Company Name:
Department:
Telephone Number:
Date:
________________________________________________________________
________________________________________________________________
__________________________
__________________________
Fax: _____________________________
Risk Order Information:
Device Number:
KS86C________- ________ (write down the ROM code number)
Package:
Number of Pins: ____________
Package Type: _____________________
Intended Application:
Product Model Number:
________________________________________________________________
________________________________________________________________
Customer Risk Order Agreement:
We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk
order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume
responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule:
Risk Order Quantity:
Delivery Schedule:
_____________________ PCS
Delivery Date (s)
Quantity
Comments
Signatures:
_______________________________
(Person Placing the Risk Order)
_______________________________________
(SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
KS86 SERIES OTP FACTORY WRITING ORDER FORM (1/2)
Product Description:
Device Number: KS86P________-________ (write down the ROM code number)
Product Order Form:
Package
Pellet
Wafer
If the product order form is package:
Package Type: _____________________
Package Marking (Check One):
Standard
Custom A
Custom B
(Max 10 chars)
(Max 10 chars each line)
@ YWW
@ YWW
@ YWW
Device Name
SEC
Device Name
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantity:
ROM Code Release Date
Required Delivery Date of Device
Quantity
Please answer the following questions:
+
What is the purpose of this order?
New product development
Upgrade of an existing product
Other
Replacement of an existing microcontroller
If you are replacing an existing microcontroller, please indicate the former microcontroller name
(
)
+
What are the main reasons you decided to use a Samsung microcontroller in your product?
Please check all that apply.
Price
Product quality
Features and functions
Delivery on time
Development system
Used same micom before
Technical support
Quality of documentation
Samsung reputation
Customer Information:
Company Name:
___________________
Telephone number
_________________________
Signatures:
________________________
(Person placing the order)
__________________________________
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
KS86P6408 OTP FACTORY WRITING ORDER FORM (2/2)
Device Number:
KS86P_________-________ (write down the ROM code number)
Customer Checksums:
Company Name:
_______________________________________________________________
________________________________________________________________
________________________________________________________________
Signature (Engineer):
Read Protection (1):
Yes
No
Please answer the following questions:
+
+
Are you going to continue ordering this device?
Yes No
If so, how much will you be ordering? _________________ PCS
Application (Product Model ID: _______________________)
Audio
Video
Telecom
LCD Databank
Industrials
Remocon
Caller ID
LCD Game
Office Automation
Other
Home Appliance
Battery Charger
Please describe in detail its application
___________________________________________________________________________
NOTES:
1. Once you choose a read protection, you cannot read again the programming code from the EPROM.
2. OTP Writing will be executed in our manufacturing site.
3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors
occurred from the writing program.
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
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