KS88C0424N-XX_技术文档

KS88C0416/P0416/C0424/P0424

PRODUCT OVERVIEW

1

PRODUCT OVERVIEW

KS88-SERIES MICROCONTROLLERS

Samsung's KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide

range of integrated peripheral, in various mask-programmable ROM sizes. Among its major CPU features are:

— Efficient register-oriented architecture

— Selectable CPU clock sources

— Idle and Stop power-down mode release by interrupt

— Built-in basic timer with watchdog function

The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more

interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to

specific interrupt levels.

KS88C0416/C0424 MICROCONTROLLER

The KS88C0416/C0424 single-chip CMOS microcontrollers are fabricated using a highly advanced CMOS

process, based on Samsung’s newest CPU architecture.

The KS88C0416/C0424 are microcontrollers containing a 16/24-Kbyte mask-programmable ROM. The

KS88P0416/P0424 are microcontroller containing a 16/24-Kbyte one-time-programmable EPROM.

Using a proven modular design approach, Samsung engineers have successfully developed the

KS88C0416/C0424 by integrating the following peripheral modules with the powerful SAM87 core:

— Four programmable I/O ports, including three 8-bit ports and one 2-bit port, for a total of 26 pins.

— Twelve bit-programmable pins for external interrupts.

— One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset).

— One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.

— One 8-bit counter with auto-reload function and one-shot or repeat control.

The KS88C0416/C0424 are versatile general-purpose microcontrollers especially suitable for use as a unified

remote transmitter controller.

OTP

The KS88P0416/P0424 is an OTP (One Time Programmable) version of the KS88C0416/C0424 microcontroller.

The KS88P0416/P0424 microcontroller has an on-chip 16/24-Kbyte one-time-programmable EPROM instead of

a masked ROM. The KS88P0416/P0424 is comparable to the KS88C0416/C0424, both in function and in pin

configuration.

1-1

PRODUCT OVERVIEW

KS88C0416/P0416/C0424/P0424

FEATURES

CPU

Carrier Frequency Generator

•

SAM87 CPU core

•

One 8-bit counter with auto-reload function and

one-shot or repeat control (Counter A)

Memory

Stop Error Detection and Recovery (SED and R)

•

16-Kbyte internal program memory (ROM):

KS88C0416

•

Special logic in relation to P0 and P1 to prevent

abnormal-stop status

24-Kbyte internal program memory (ROM):

KS88C0424

•

Releasing stop mode by level switching

detection in P0 and P1

Data memory: 317-byte internal register file

Back-up mode by reset input

Instruction Set

•

When reset pin is low, the chip enters back-up

mode to reduce current

•

78 instructions

IDLE and STOP instructions added for power-

down modes

Operating Temperature Range

°

•

– 40 C to + 85 C

Instruction Execution Time

750 ns at 8 MHz f_OSC(minimum)

•

Operating Voltage Range

•

2.0 V to 5.5 V at 4 MHz f_OSC

2.2 V to 5.5 V at 8 MHz f_OSC

Interrupts

•

Six interrupt levels and 18 interrupt sources

15 vectors (14 sources have a dedicated vector

address and four sources share a single vector)

Package Type

•

32-pin SOP

•

Fast interrupt processing feature (for one

selected interrupt level)

32-pin SDIP

40-pin DIP (KS88C0424 only)

I/O Ports

•

Three 8-bit I/O ports (P0–P2) and one 2-bit port

(P3) for a total of 26 bit-programmable pins

•

Twelve input pins for external interrupts

Timers and Timer/Counters

•

One programmable 8-bit basic timer (BT) for

oscillation stabilization control or watchdog timer

(software reset) function

•

One 8-bit timer/counter (Timer 0) with three

operating modes; Interval, Capture, and PWM

One 16-bit timer/counter (Timer 1) with two

operating modes; Interval and Capture

1-2

KS88C0416/P0416/C0424/P0424

PRODUCT OVERVIEW

BLOCK DIAGRAM

P0.0–P0.7

(INT0–INT4)

P1.0–P1.7

PORT 1

RESET

PORT 0

TEST

X

IN

MAIN

OSC

P2.0–P2.3

(INT5–INT8)

P2.4–P2.7

X

INTERNAL BUS

OUT

PORT2

I/O PORT and INTERRUPT

CONTROL

8-BIT

BASIC

TIMER

P3.0/T0PWM/

T0CAP/T1CAP

PORT 3

SAM87

CPU

P3.1/REM/T0CK

8-BIT

TIMER/

COUNTER

317-BYTE

REGISTER

FILE

16/24-KBYTE

PROGRAM

MEMORY

CARRIER

GENERATOR

(COUNTER A)

16-BIT

TIMER/

COUNTER

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW

KS88C0416/P0416/C0424/P0424

PIN ASSIGNMENTS

V

SS

V

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

DD

X

RESET/BACK-UP MODE

IN

X

P3.1/REM/T0CK

P3.0/T0PWM/T0CAP/T1CAP

OUT

TEST

P2.0/INT5

P2.1/INT6

P2.2/INT7

P2.3/INT8

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3/INT3

P0.4/INT4

P0.5/INT4

P0.6/INT4

P0.7/INT4

P2.7

P2.6

P2.5

P2.4

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

KS88C0416

KS88C0424

32-SOP/SDIP

9

10

11

12

13

14

15

16

(Top View)

Figure 1-2. Pin Assignment (32-Pin SOP/SDIP Package)

V

DD

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

SS

RESET/BACK-UP MODE

X

IN

P3.1/REM/T0CK

XOUT

TEST

P3.0/T0PWM/T0CAP/T1CAP

NC

P2.0/INT5

P2.1/INT6

P2.2/INT7

P2.3/INT8

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3/INT3

NC

P2.7

P2.6

P2.5

P2.4

P1.7

P1.6

P1.5

P1.4

NC

9

KS88C0424

40-DIP

10

11

12

13

14

15

16

17

18

19

20

(Top View)

NC

P0.4/INT4

P0.5/INT4

P0.6/INT4

P0.7/INT4

P1.3

P1.2

P1.1

P1.0

Figure 1-3. Pin Assignment (40-Pin DIP Package)

1-4

KS88C0416/P0416/C0424/P0424

PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. Pin Descriptions

Circuit Pin No. Pin No.

Shared

Names

Type

Description

Type

(32-pin) (40-pin) Functions

P0.0–P0.7

I/O

I/O port with bit-programmable pins.

Configurable to input or push-pull output

mode. Pull-up resistors are assignable by

software. Pins can be assigned individually

as external interrupt inputs with noise filters,

interrupt enable/disable, and interrupt

pending control.

1

9–16

11–14, INT0–INT4

17–20

P1.0–P1.7

I/O

I/O port with bit-programmable pins.

Configurable to C-MOS input mode or

output mode. Pin circuits are either push-

pull or n-channel open-drain type. Pull-up

resistors are assignable by software.

2

17–24

21–24,

27–30

–

P2.0–P2.3

P2.4–P2.7

General-purpose I/O port with bit-

3

4

5–8,

25–28

7–10,

31–34

INT5–INT8

–

programmable pins. Configurable to C-

MOS input mode, push-pull output mode, or

n-channel open-drain output mode. Pull-up

resistors are assignable by software. Lower

nibble pins, P2.3–P2.0, can be assigned as

external interrupt inputs with noise filters,

interrupt enable/disable, and interrupt

pending control.

P3.0

P3.1

I/O

2-bit I/O port with bit-programmable pins.

Configurable to C-MOS input mode, push-

pull output mode, or n-channel open-drain

output mode. Pull-up resistors are

5

29

30

37

38

T0PWM/

T0CAP/

T1CAP/

REM/T0CK

assignable by software. The two port 3 pins

have high current drive capability.

X_IN, X_OUT

–

I

System clock input and output pins

–

6

2, 3

31

2, 3

39

–

System reset signal input pin and back-up

mode input pin. The pin circuit is a C-MOS

input.

RESET/

BACK-UP

MODE

TEST

I

Test signal input pin (for factory use only;

must be connected to V_SS).

–

4

–

V_DD

V_SS

–

Power supply input pin

Ground pin

–

32

1

40

1

–

1-5

PRODUCT OVERVIEW

KS88C0416/P0416/C0424/P0424

PIN CIRCUITS

V

DD

PULL-UP RESISTOR

(Typical 21 K )

W

PULL-UP

ENABLE

V

DD

DATA

I/O

OUTPUT

DISABLE

V

SS

NOISE

FILTER

INTERRUPT INPUT

IRQ6,7 (INT0-4)

NORMAL

INPUT

Oscillator Release (SED and R circuit)

STOP

To prevent and recover from abnormal stop status caused by battery bouncing, the KS88C0416/C0424

has a special logic

NOTE:

SED and R circuit related to P0 and P1. This is a specific function for key

-

input/output of universal remote controller. When these ports (P0, P1) are used as a normal

input pin without pull-up resistor, unexpected stop mode recovery can occur by input level switching.

Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input

ports and stop mode be used.

Figure 1-4. Pin Circuit Type 1 (Port 0)

1-6

KS88C0416/P0416/C0424/P0424

PRODUCT OVERVIEW

V

DD

PULL-UP RESISTOR

(Typical 21 K )

W

PULL-UP

ENABLE

V

DD

DATA

I/O

OUTPUT

DISABLE

V

SS

NOISE

FILTER

NORMAL INPUT

Oscillator Release (SED and R circuit)

STOP

To prevent and recover from abnormal stop status caused by battery bouncing, the KS88C0416/C0424

has a special logic

NOTE:

SED and R circuit related to P0 and P1. This is a specific function for key

-

input/output of universal remote controller. When these ports (P0, P1) are used as a normal

input pin without pull-up resistor, unexpected stop mode recovery can occur by input level switching.

Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input

ports and stop mode be used.

Figure 1-5. Pin Circuit Type 2 (Port 1)

1-7

PRODUCT OVERVIEW

KS88C0416/P0416/C0424/P0424

V

DD

PULL-UP RESISTOR

(Typical 21 K )

W

PULL-UP

ENABLE

V

DD

DATA

I/O

OPEN-DRAIN

OUTPUT

DISABLE

V

SS

EXTERNAL

INTERRUPT

IRQ5 (INT5-8)

NOISE

FILTER

NORMAL INPUT

Figure 1-6. Pin Circuit Type 3 (Ports 2.0- 2.3)

1-8

KS88C0416/P0416/C0424/P0424

PRODUCT OVERVIEW

V

DD

PULL-UP RESISTOR

(Typical 21 K )

W

PULL-UP

ENABLE

V

DD

DATA

I/O

OPEN-DRAIN

OUTPUT

DISABLE

V

SS

NORMAL INPUT

Figure 1-7. Pin Circuit Type 4 (P2.4- P2.7)

1-9

PRODUCT OVERVIEW

KS88C0416/P0416/C0424/P0424

V

DD

PULL-UP RESISTOR

(Typical 21 K )

W

PULL-UP

ENABLE

SELECT

V

DD

M

U

X

DATA

PORT 3 DATA

ALTERNATIVE

OUTPUT

I/O

OPEN-DRAIN

OUTPUT

DISABLE

V

SS

NORMAL INPUT

NOISE

FILTER

ALTERNATIVE

INPUT

Figure 1-8. Pin Circuit Type 5 (PORT 3)

BACK-UP MODE

RESET/

BACK-UP

MODE

NOISE

FILTER

RESET

SYSTEM

Figure 1-9. Pin Circuit Type 6 (RESET/Back-up mode)

1-10

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

2

ADDRESS SPACES

OVERVIEW

The KS88C0416/C0424 microcontrollers have two types of address space:

— Internal program memory

— Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and

data between the CPU and the register file.

The KS88C0416/C0424 have a programmable internal 16/24-Kbyte ROM. An external memory interface has not

been implemented.

The 256-byte physical register space is expanded into an addressable area of 320 bytes through the use of

addressing modes.

There are 317 mapped registers in the internal register file. Of these, 272 registers are for general-purpose. (This

number includes a 16-byte working register common area used as a “scratch area” for data operations, a 192-

byte prime register area, and a 64-byte area (Set 2) for stack operations.) Eighteen 8-bit registers are used for the

CPU and system control and 27 registers are mapped for peripheral control and data registers. Three register

locations are not mapped.

2-1

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

PROGRAM MEMORY

Programmable memory stores program code or table data. The KS88C0416 has 16 K bytes of programmable

internal memory and the KS88C0424 has 24 K bytes. The programmable memory address range of the

KS88C0416 is therefore 0H–3FFFH and that of the KS88C0424 is 0H–5FFFH (see Figure 2-1).

The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this

address range can be used as normal program memory. When you use the vector address area to store program

code, be careful not to overwrite the vector addresses stored in these locations.

The ROM address at which program execution starts after a reset is 0100H.

(DECIMAL)

24,575

(HEX)

5FFFH

Internal Program

Memory (ROM)

3FFFH

16,383

KS88C0424

(24-Kbyte)

KS88C0416

(16-Kbyte)

255

0

0FFH

0H

Interrupt

Vector Area

Figure 2-1. Program Memory Address Space

2-2

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

REGISTER ARCHITECTURE

The KS88C0416/C0424 register files have 317 registers. To increase the size of the internal register file, the

upper 64-byte area of the register file is expanded to two 64-byte areas, set 1 and set 2. The remaining 192-byte

area of the physical register file contains freely-addressable, general-purpose registers called prime registers.

The extension of register space into separately addressable sets is internally supported by addressing mode

restrictions.

Specific register types and the area (in bytes) they occupy in the KS88C0416/C0424 internal register space are

summarized in Table 2-1.

Table 2-1. KS88C0416/C0424 Register Type Summary

Register Type

Number of Bytes

General-purpose registers (including the 16-byte

common working register area, the 192-byte prime

register area, and the 64-byte set 2 area)

272

CPU and system control registers

18

27

Mapped clock, peripheral, I/O control, and data registers

Total Addressable Bytes

317

2-3

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

SET 1

SET 2

FFH

SYSTEM AND

PERIPHERAL

CONTROL REGISTERS

(Register addressing

mode)

GENERAL-

PURPOSE DATA

REGISTERS

E0H

DFH

64

BYTES

SYSTEM REGISTERS

(Register addressing

mode)

(Indirect Register,

Indexed addressing

modes, or

D0H

CFH

stack operations)

WORKING REGISTERS

(Working register

addressing only)

C0H

BFH

256

BYTES

PRIME

DATA REGISTERS

192

BYTES

~

(All addressing

modes)

00H

Figure 2-2. Internal Register File Organization

2-4

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

REGISTER PAGE POINTER (PP)

The KS88-series architecture supports the logical expansion of the physical 256-byte internal register file (using

an 8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by the

register page pointer (PP, DFH). In the KS88C0416/C0424 microcontroller, a paged register file expansion is not

implemented and the register page pointer settings therefore always point to “page 0.”

After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always

"0000", automatically selecting page 0 as the source and the destination page for register addressing. These

page pointer (PP) register settings, as shown in Figure 2-3, should not be modified during the normal operation.

REGISTER PAGE POINTER (PP)

DFH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Destination register page selection bits:

0 0 0 0 Destination: page 0

Source register page selection bits:

0 0 0 0 Source: page 0

: In the KS88C0416/C0424 microcontroller, only page 0 is implemented. A hardware

reset operation writes the 4-bit destination and source values shown above to the

register page pointer. These values should not be modified.

NOTE

Figure 2-3. Register Page Pointer (PP)

2-5

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.

In some KS88-series microcontrollers, the upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two

32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to address

one bank or the other. In the KS88C0416/C0424 microcontroller, bank 1 is not implemented. A hardware reset

operation therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not necessary.

The upper 32-byte area of set 1 (FFH–E0H) contains 26 mapped system and peripheral control registers. The

lower 32-byte area contains 16 system registers (DFH–D0H) and a 16-byte common working register area (CFH–

C0H). You can use the common working register area as a “scratch” area for data operations being performed in

other areas of the register file.

Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte

working register area can only be accessed using working register addressing. (For more information about

working register addressing, please refer to Chapter 3, “Addressing Modes.”)

REGISTER SET 2

The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another

64 bytes of register space. This expanded area of the register file is called set 2. All set 2 locations (C0H–FFH)

are addressed as part of page 0 in the KS88C0416/C0424 register space.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only

Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register

Indirect addressing mode or Indexed addressing mode.

The set 2 register area is commonly used for stack operations.

2-6

KS88C0416/P0416/C0424/P0424

PRIME REGISTER SPACE

ADDRESS SPACES

The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) is called the prime register space or,

more simply, the prime area. You can access registers in this address using any addressing mode. (In other

words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.) All

registers in prime area locations are addressable immediately after a reset.

SET 1

FFH

FCH

FFH

C0H

SET 2

E0H

D0H

C0H

CPU and system registers

General-purpose registers

Peripheral control registers

PRIME

REGISTER

AREA

00H

Figure 2-4. Set 1, Set 2, and Prime Area Register Map

2-7

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.

When 4-bit working register addressing is used, the 256-byte register file can be seen as 32 groups or "slices" of

8-byte registers. Each slice consists of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to

form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block

anywhere in the addressable register file, except for the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected

working register spaces:

— One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15)

— One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15)

All the registers in an 8-byte working register slice have the same binary value for their five most significant

address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The

base addresses for the two selected 8-byte register slices are contained in the register pointers, RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).

FFH

SLICE 32

F8H

F7H

F0H

1 1 1 1 1

X X X

SET 1

ONLY

RP1 (Registers R8–R15)

CFH

C0H

Each register pointer points to

one 8-byte slice of the register

space, selecting a total 16-byte

working register block.

~

10H

FH

8H

7H

0H

0 0 0 0 0

X X X

SLICE 1

RP0 (Registers R0–R7)

Figure 2-5. 8-Byte Working Register Areas (Slices)

2-8

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

USING THE REGISTER POINTERS

The register pointers, RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable

8-byte working register slices in the register file. After a reset, they point to the working register common area:

RP0 points to the addresses, C0H–C7H, and RP1 points to the addresses C8H–CFH.

To change a register pointer value, you should load a new value to RP0 and/or RP1 using an SRP or LD

instruction (see Figures 2-6 and 2-7).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently

pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in

set 2, C0H–FFH, because these locations can be accessed only using Indirect Register or Indexed addressing

modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general

programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice

(see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-

contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to either of the two 8-byte slices in the working register block, you can

flexibly define the working register area to support program requirements.

+

PROGRAMMING TIP — Setting the Register Pointers

SRP

SRP1

SRP0

CLR

LD

#70H

#48H

#0A0H

RP0

RP1,#0F8H

; RP0 ¬ 70H, RP1 ¬ 78H

; RP0 ¬ no change, RP1 ¬ 48H,

; RP0 ¬ A0H, RP1 ¬ no change

; RP0 ¬ 00H, RP1 ¬ no change

; RP0 ¬ no change, RP1 ¬ 0F8H

REGISTER FILE

CONTAINS 32

8-BYTE SLICES

0 0 0 0 1

x x x

FH (R15)

16-BYTE

RP1

0 0 0 0 0

RP0

8-BYTE SLICE

UPPER SLICE

•

CONTIGUOUS

WORKING

REGISTER

BLOCK

8H

7H

x x x

8-BYTE SLICE

0H (R0)

Figure 2-6. Contiguous 16-Byte Working Register Block

2-9

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

F7H (R7)

|

8-BYTE SLICE

F0H (R0)

16-BYTE NON-

CONTIGUOUS

WORKING

REGISTER

BLOCK

REGISTER FILE

CONTAINS 32

8-BYTE SLICES

1 1 1 1 0

RP0

0 0 0 0 0

RP1

x x x

7H (R15)

|

0H (R8)

8-BYTE SLICE

Figure 2-7. Non-Contiguous 16-Byte Working Register Block

+

PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of the registers, 80H–85H, using the register pointer. The register addresses from 80H through

85H contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:

SRP0

ADD

ADC

#80H

; RP0 ¬ 80H

; R0 ¬ R0 + R1

; R0 ¬ R0 + R2 + C

; R0 ¬ R0 + R3 + C

; R0 ¬ R0 + R4 + C

; R0 ¬ R0 + R5 + C

R0,R1

R0,R2

R0,R3

R0,R4

R0,R5

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this

example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to

calculate the sum of these registers, the following instruction sequence would have to be used:

ADD

ADC

80H,81H

80H,82H

80H,83H

80H,84H

80H,85H

; 80H ¬ (80H) + (81H)

; 80H ¬ (80H) + (82H) + C

; 80H ¬ (80H) + (83H) + C

; 80H ¬ (80H) + (84H) + C

; 80H ¬ (80H) + (85H) + C

Now, the sum of the six registers is also located in the register 80H. In this case, this instruction string takes 15

bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

2-10

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

REGISTER ADDRESSING

The KS88-series register architecture provides an efficient method of working register addressing that takes full

advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or a register

pair, you can access any location in the register file except for set 2. With working register addressing, you can

use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within

that space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register

pair, the address of the first 8-bit register is always an even number and the address of the next register is always

an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and

the least significant byte is always stored in the next (+ 1) odd-numbered register.

Working register addressing differs from Register addressing as it uses a register pointer to identify a specific

8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

Rn

LSB

n = EVEN ADDRESS

Rn + 1

Figure 2-8. 16-Bit Register Pair

2-11

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

SPECIAL-PURPOSE

REGISTERS

GENERAL-PURPOSE

REGISTERS

SET 1

FFH

D0H

FFH

CONTROL

REGISTERS

SET 2

SYSTEM

REGISTERS

CFH

C0H

BFH

D7H

D6H

RP1

RP0

REGISTER

POINTERS

Each register pointer (RP) can independently point to

one of the 24 8-byte "slices" of the register file (other

than set 2). After a reset, RP0 points to locations

C0H–C7H and RP1 to locations C8H–CFH (that is, to

the common working register area).

PRIME

REGISTERS

Only page 0 is implemented. Page 0

contains all the addressable registers in

the internal register file.

:

NOTE

00H

PAGE 0

INDIRECT

REGISTER,

INDEXED

REGISTER ADDRESSING ONLY

ALL

ADDRESSING

MODES

ADDRESSING

MODES

CAN BE POINTED TO BY REGISTER POINTER

Figure 2-9. Register File Addressing

2-12

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

COMMON WORKING REGISTER AREA (C0H–CFH)

After a reset, the register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations

C0H–CFH, as the active 16-byte working register block:

RP0 ® C0H–C7H

RP1 ® C8H–CFH

This 16-byte address range is called common area. That is, locations in this area can be used as working

registers by operations that address any location on any page in the register file. Typically, these working

registers serve as temporary buffers for data operations between different pages.

PAGE 0

SET 1

FFH

FCH

FFH

SET 2

E0H

DFH

CFH

C0H

BFH

Following a hardware reset, the register

pointers, RP0 and RP1, point to the

common working register area,

locations C0H–CFH.

~

PRIME

AREA

~

RP0 = 1 1 0 0 0 0 0 0

RP1 = 1 1 0 0 1 0 0 0

00H

Figure 2-10. Common Working Register Area

2-13

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

+

PROGRAMMING TIP — Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H–CFH,

using working register addressing mode only.

Examples 1. LD

0C2H,40H

; Invalid addressing mode!

Use working register addressing instead:

SRP

LD

#0C0H

R2,40H

; R2 (C2H) ¬ the value in location 40H

2. ADD

0C3H,#45H

; Invalid addressing mode!

Use working register addressing instead:

SRP

ADD

#0C0H

R3,#45H

; R3 (C3H) ¬ R3 + 45H

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in

a register pointer serves as an addressing "window" that makes it possible for instructions to access working

registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected

working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1).

— The five high-order bits in the register pointer select an 8-byte slice of the register space.

— The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are

concatenated with the three low-order bits from the instruction address to form the complete address. As long as

the address stored in the register pointer remains unchanged, the three bits from the address will always point to

an address in the same 8-byte register slice.

Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction

"INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the

three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

2-14

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

RP0

RP1

SELECTS

RP0 OR RP1

ADDRESS

OPCODE

4-BIT ADDRESS

PROVIDES THREE

LOW-ORDER BITS

REGISTER POINTER

PROVIDES FIVE

HIGH-ORDER BITS

TOGETHER THEY CREATE AN

8-BIT REGISTER ADDRESS

Figure 2-11. 4-Bit Working Register Addressing

RP0

0 1 1 1 0

RP1

0 1 1 1 1

0 0 0

SELECTS RP0

R6

OPCODE

REGISTER

ADDRESS

(76H)

INSTRUCTION:

'INC R6'

0 1 1 0

1 1 1 0

0 1 1 1 0

1 1 0

q

Figure 2-12. 4-Bit Working Register Addressing Example

2-15

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To

initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value

1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working

register addressing.

As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit

addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the

three low-order bits of the complete address are provided by the original instruction.

Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction

address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in

RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register

address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from

RP1 and the three address bits from the instruction are concatenated to form the complete register address,

0ABH (10101011B).

RP0

RP1

SELECTS

RP0 OR RP1

ADDRESS

THESE ADDRESS

BITS INDICATE

8-BIT WORKING

REGISTER

8-BIT LOGICAL

ADDRESS

1

0

ADDRESSING

THREE

LOW-ORDER BITS

REGISTER POINTER

PROVIDES FIVE

HIGH-ORDER BITS

8-BIT PHYSICAL ADDRESS

Figure 2-13. 8-Bit Working Register Addressing

2-16

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

RP0

0 1 1 0 0

RP1

1 0 1 0 1

0 0 0

SELECTS RP1

R11

0 1 1

1 1 0 0

1

8-BIT ADDRESS

FROM INSTRUCTION

'LD R2,R11'

SPECIFIES WORKING

REGISTER ADDRESSING

REGISTER ADDRESS (0ABH)

1 0 1 0 1

0 1 1

Figure 2-14. 8-Bit Working Register Addressing Example

2-17

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

SYSTEM AND USER STACKS

The KS88-series microcontrollers use the system stack for data storage, and subroutine calls and returns. The

PUSH and POP instructions are used to control system stack operations. The KS88C0416/C0424 architecture

supports stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are

saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents

of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to

their original locations. The stack address value is always decreased by one before a push operation and

increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top

of the stack, as shown in Figure 2-15.

HIGH ADDRESS

PCL

PCH

TOP OF

STACK

TOP OF

STACK

PCH

FLAGS

STACK CONTENTS

AFTER A CALL

INSTRUCTION

STACK CONTENTS

AFTER AN

INTERRUPT

LOW ADDRESS

Figure 2-15. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,

PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL)

The register location D9H contains the 8-bit stack pointer (SPL) that is used for system stack operations. After a

reset, the SPL value is undetermined. Because only an internal memory 256-byte is implemented in the

KS88C0416/C0424, the SPL must be initialized to an 8-bit value in the range of 00H–FFH.

2-18

KS88C0416/P0416/C0424/P0424

ADDRESS SPACES

+

PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and

POP instructions:

LD

SPL,#0FFH

; SPL ¬ FFH

; (Normally, the SPL is set to 0FFH by the initialization

; routine)

•

PUSH

•

PP

; Stack address 0FEH ¬ PP

; Stack address 0FDH ¬ RP0

; Stack address 0FCH ¬ RP1

; Stack address 0FBH ¬ R3

RP0

RP1

R3

•

POP

R3

; R3 ¬ Stack address 0FBH

; RP1 ¬ Stack address 0FCH

; RP0 ¬ Stack address 0FDH

; PP ¬ Stack address 0FEH

RP1

RP0

PP

2-19

ADDRESS SPACES

KS88C0416/P0416/C0424/P0424

NOTES

2-20

KS88C0416/P0416/C0424/P0424

ADDRESSING MODES

3

ADDRESSING MODES

OVERVIEW

The program counter is used to fetch instructions that are stored in program memory for execution. Instructions

indicate the operation to be performed and the data to be operated on. Addressing mode is used to determine the

location of the data operand. The operands specified in instructions may be condition codes, immediate data, a

location in the register file, program memory, or data memory.

The KS88-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are

available for each instruction:

— Register (R)

— Indirect Register (IR)

— Indexed (X)

— Direct Address (DA)

— Indirect Address (IA)

— Relative Address (RA)

— Immediate (IM)

3-1

ADDRESSING MODES

KS88C0416/P0416/C0424/P0424

REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register or a register pair (see Figure 3-1).

Working register addressing differs from Register addressing as it uses a register pointer to specify an 8-byte

working register space in the register file and an 8-bit register within that space (see Figure 3-2).

PROGRAM MEMORY

REGISTER

FILE

8-BIT REGISTER

FILE ADDRESS

dst

OPERAND

POINTS TO ONE

REGISTER IN REGISTER

FILE

OPCODE

ONE-OPERAND

INSTRUCTION

(EXAMPLE)

VALUE USED IN

INSTRUCTION EXECUTION

SAMPLE INSTRUCTION:

DEC CNTR

;

Where CNTR is the label of an 8-bit register address

Figure 3-1. Register Addressing

REGISTER

FILE

MSB POINTS TO

RP0 or RP1

SELECTED

RP POINTS

TO START

OF WORKING

REGISTER

BLOCK

PROGRAM MEMORY

4-BIT

WORKING

REGISTER

3 LSBs

dst

src

OPERAND

POINTS TO THE

WORKING REGISTER

(1 of 8)

TWO-

OPERAND

INSTRUCTION

(EXAMPLE)

OPCODE

SAMPLE INSTRUCTION:

ADD R1,R2

;

Where R1 and R2 are registers in the currently selected

working register area

Figure 3-2. Working Register Addressing

3-2

KS88C0416/P0416/C0424/P0424

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of a specified register or a register pair is the address of the

operand. Depending on the instruction used, the actual address may point to a register in the register file, program

memory (ROM), or an external memory space, if implemented (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to

indirectly address another memory location. Remember, however, that the locations, C0H–FFH, in set 1 cannot be

accessed in Indirect Register addressing mode.

PROGRAM MEMORY

REGISTER FILE

ADDRESS

8-BIT REGISTER

FILE ADDRESS

dst

POINTS TO ONE

REGISTER IN

OPCODE

ONE-OPERAND

INSTRUCTION

(EXAMPLE)

REGISTER FILE

ADDRESS OF OPERAND

USED BY INSTRUCTION

VALUE USED IN

INSTRUCTION

EXECUTION

OPERAND

SAMPLE INSTRUCTION:

RL @SHIFT Where SHIFT is the label of an 8-bit register address.

;

Figure 3-3. Indirect Register Addressing to Register File

3-3

ADDRESSING MODES

KS88C0416/P0416/C0424/P0424

INDIRECT REGISTER ADDRESSING MODE (Continued)

REGISTER

FILE

PROGRAM MEMORY

REGISTER

PAIR

EXAMPLE

INSTRUCTION

REFERENCES

PROGRAM

dst

POINTS TO

REGISTER

PAIR

OPCODE

16-BIT

ADDRESS

POINTS TO

PROGRAM

MEMORY

PROGRAM MEMORY

OPERAND

SAMPLE INSTRUCTIONS:

CALL @RR2

VALUE USED IN

INSTRUCTION

JP

@RR2

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

KS88C0416/P0416/C0424/P0424

ADDRESSING MODES

INDIRECT REGISTER ADDRESSING MODE (Continued)

REGISTER FILE

RP0 or RP1

MSB POINTS TO

RP0 or RP1

SELECTED

RP POINTS

TO START OF

WORKING

REGISTER

BLOCK

~

PROGRAM MEMORY

4-BIT

3 LSBs

WORKING

REGISTER

ADDRESS

dst

src

OPCODE

ADDRESS

POINTS TO THE

WORKING

REGISTER (1 of 8)

SAMPLE INSTRUCTION:

OR R3,@R6

VALUE USED IN

INSTRUCTION

OPERAND

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

ADDRESSING MODES

KS88C0416/P0416/C0424/P0424

INDIRECT REGISTER ADDRESSING MODE (Continued)

REGISTER FILE

MSB POINTS TO

RP0 or RP1

SELECTED RP

POINTS TO

START OF

WORKING

REGISTER

BLOCK

PROGRAM MEMORY

4-BIT

WORKING

REGISTER

ADDRESS

dst

src

OPCODE

REGISTER

PAIR

NEXT 2 BITS POINT

TO WORKING

REGISTER PAIR

(1 of 4)

EXAMPLE

INSTRUCTION

REFERENCES

EITHER

PROGRAM

MEMORY OR

DATA MEMORY

16-BIT

ADDRESS

POINTS TO

PROGRAM

MEMORY OR

DATA

PROGRAM MEMORY

or

LSB SELECTS

DATA MEMORY

MEMORY

VALUE USED

IN

OPERAND

INSTRUCTION

SAMPLE INSTRUCTIONS:

LDC

LDE

R5,@RR6

R3,@RR14

@RR4,R8

;

Program memory access

Internal font and data memory, and External data memory access

LDE command is not available.

NOTE:

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

KS88C0416/P0416/C0424/P0424

ADDRESSING MODES

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during an instruction execution in order to

calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access

locations in the internal register file or in external memory (if implemented). You cannot, however, access the

locations, C0H–FFH, in set 1 in Indexed addressing mode.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to

+127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained

in a working register. For external memory accesses, the base address is stored in the working register pair

designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address

(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction

(LD). The LDC and the LDE instructions support Indexed addressing mode for internal program memory and for

external data memory (if implemented).

REGISTER FILE

MSB POINTS TO

RP0 or RP1

~

SELECTED RP

POINTS TO

START OF

WORKING

REGISTER

BLOCK

VALUE USED IN

INSTRUCTION

OPERAND

+

PROGRAM MEMORY

BASE ADDRESS

3 LSBs

dst / src

OPCODE

x

TWO-

OPERAND

INDEX

POINTS TO ONE

OF THE

INSTRUCTION

EXAMPLE

WORKING

REGISTERS

(1 of 8)

SAMPLE INSTRUCTION:

LD R0,#BASE[R1]

;

Where BASE is an 8-bit immediate value

Figure 3-7. Indexed Addressing to Register File

3-7

ADDRESSING MODES

KS88C0416/P0416/C0424/P0424

INDEXED ADDRESSING MODE (Continued)

REGISTER

FILE

MSB POINTS TO

RP0 or RP1

SELECTED

RP POINTS

TO START OF

WORKING

REGISTER

BLOCK

~

PROGRAM MEMORY

OFFSET

dst / src

OPCODE

4-BIT

WORKING

REGISTER

ADDRESS

REGISTER

PAIR

NEXT 2 BITS

POINT TO

WORKING

REGISTER

PAIR (1 of 4)

x

16-BIT

ADDRESS

ADDED TO

OFFSET

PROGRAM MEMORY

or

LSB SELECTS

DATA MEMORY

+

8 BITS

16 BITS

VALUE USED IN

INSTRUCTION

OPERAND

16 BITS

SAMPLE INSTRUCTIONS:

LDC

LDE

R4,#04H[RR2]

;

The values in the program address (RR2 + 04H) are

loaded into the register R4.

Operation identical to the LDC example, except that

external data memory is accessed.

:

LDE command is not available.

NOTE

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

KS88C0416/P0416/C0424/P0424

ADDRESSING MODES

INDEXED ADDRESSING MODE (Continued)

REGISTER FILE

RP0 OR RP1

MSB POINTS TO

RP0 OR RP1

SELECTED

RP POINTS

TO START OF

WORKING

REGISTER

BLOCK

~

PROGRAM MEMORY

OFFSET

4-BIT

WORKING

REGISTER

ADDRESS

OFFSET

dst / src

OPCODE

REGISTER

PAIR

NEXT 2 BITS

POINT TO

WORKING

REGISTER

PAIR

x

16-BIT

ADDRESS

ADDED TO

OFFSET

PROGRAM MEMORY

or

LSB SELECTS

DATA MEMORY

+

16 BITS

VALUE USED IN

INSTRUCTION

OPERAND

SAMPLE INSTRUCTIONS:

LDC R4,#1000H[RR2]

;

The values in the program address (RR2 + 1000H) are

loaded into the register R4.

LDE R4,#1000H[RR2]

Operation identical to the LDC example, except that external

data memory is accessed.

LDE command is not available.

NOTE:

Figure 3-9. Indexed Addressing to Program or Data Memory

3-9

ADDRESSING MODES

KS88C0416/P0416/C0424/P0424

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call

(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC

whenever a JP or CALL instruction is executed.

The LDC and the LDE instructions can use Direct Address mode to specify the source or the destination address

for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

PROGRAM or

DATA MEMORY

MEMORY

ADDRESS

USED

PROGRAM MEMORY

UPPER ADDR BYTE

LOWER ADDR BYTE

LSB SELECTS PROGRAM

dst / src

"0" or "1"

MEMORY OR DATA MEMORY:

"0" = PROGRAM MEMORY

"1" = DATA MEMORY

OPCODE

SAMPLE INSTRUCTIONS:

LDC

R5, 1234H

;

The values in the program address (1234H) are

are loaded into the register R5.

LDE

R5,1234H

;

Operation identical to the LDC example, except that

external program memory is accessed.

LDE command is not available.

NOTE:

Figure 3-10. Direct Addressing for Load Instructions

3-10

KS88C0416/P0416/C0424/P0424

ADDRESSING MODES

DIRECT ADDRESS MODE (Continued)

PROGRAM MEMORY

NEXT OPCODE

PROGRAM

MEMORY

ADDRESS

USED

LOWER ADDR BYTE

UPPER ADDR BYTE

OPCODE

SAMPLE INSTRUCTIONS:

JP

CALL

C,JOB1

DISPLAY

; Where JOB1 is a 16-bit immediate address

; Where DISPLAY is a 16-bit immediate address

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

ADDRESSING MODES

KS88C0416/P0416/C0424/P0424

INDIRECT ADDRESS MODE (IA)

In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program

memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.

Only the CALL instruction can use Indirect Address mode.

Because Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory,

only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be

all zeros.

PROGRAM

MEMORY

NEXT INSTRUCTION

LSB MUST BE ZERO

dst

CURRENT

INSTRUCTION

OPCODE

LOWER ADDR BYTE

PROGRAM MEMORY

LOCATIONS 0–255

UPPER ADDR BYTE

SAMPLE INSTRUCTION:

CALL #40H

;

The 16-bit value in the program memory addresses,

40H and 41H, is the subroutine start address.

Figure 3-12. Indirect Addressing

3-12

KS88C0416/P0416/C0424/P0424

ADDRESSING MODES

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified

in the instruction. The displacement value is then added to the current PC value. The result is the address of the

next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction

immediately following the current instruction.

Several program control instructions use Relative Address mode to perform conditional jumps. The instructions

that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

PROGRAM MEMORY

NEXT OPCODE

PROGRAM MEMORY

ADDRESS USED

CURRENT

PC VALUE

DISPLACEMENT

OPCODE

+

CURRENT

INSTRUCTION

SIGNED

DISPLACEMENT

VALUE

SAMPLE INSTRUCTION:

JR ULT,$+OFFSET

;

Where OFFSET is a value in the range

+127 to –128

Figure 3-13. Relative Addressing

3-13

ADDRESSING MODES

KS88C0416/P0416/C0424/P0424

IMMEDIATE MODE (IM)

In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself.

The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing

mode is useful for loading constant values into registers.

PROGRAM MEMORY

OPERAND

OPCODE

(The operand value is in the instruction.)

SAMPLE INSTRUCTION:

LD

R0,#0AAH

Figure 3-14. Immediate Addressing

3-14

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

4

CONTROL REGISTERS

OVERVIEW

In this chapter, detailed descriptions of the KS88C0416/C0424 control registers are presented in an easy-to-read

format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1

illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed

information about control registers is presented in the context of the specific peripheral hardware descriptions in

Part II of this manual.

Data and counter registers are not described in detail in this reference chapter. More information about all of the

registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this

manual.

The locations and read/write characteristics of all mapped registers in the KS88C0416/C0424 register file are

listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, “RESET and

Power-Down.”

4-1

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

Table 4-1. Mapped Registers (Set 1)

Register Name

Mnemonic

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

Decimal

208

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

R/W

R ^(note)

R/W

Timer 0 counter

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

Register pointer 0

209

210

211

212

213

214

Register pointer 1

RP1

215

Location D8H is not mapped.

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register

Interrupt mask register

System mode register

Register page pointer

Port 0 data register

SPL

217

218

219

220

221

222

223

224

225

226

227

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

E3H

R/W

R ^(note)

R/W

IPH

IPL

IRQ

IMR

SYM

PP

P0

P1

Port 1 data register

Port 2 data register

P2

Port 3 data register

P3

Location E4H is not mapped.

P2INT

Port 2 interrupt enable register

Port 2 interrupt pending register

Port 0 pull-up resistor enable register

Port 0 control register (high byte)

Port 0 control register (low byte)

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 1 pull-up enable register

Port 2 pull-up enable register

Port 2 control register (high byte)

Port 2 control register (low byte)

Port 3 control register

229

230

231

232

233

234

235

236

237

238

239

240

E5H

E6H

E7H

E8H

E9H

EAH

EBH

ECH

EDH

EEH

EFH

F0H

R/W

P2PND

P0PUR

P0CONH

P0CONL

P1CONH

P1CONL

P1PUR

P2PUR

P2CONH

P2CONL

P3CON

4-2

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

Table 4-1. Mapped Registers (Continued)

Register Name

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

Mnemonic

P0INT

Decimal

241

Hex

R/W

R ^(note)

R/W

W

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

P0PND

242

CACON

243

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

Timer 1 data register (low byte)

Timer 1 control register

CADATAH

CADATAL

T1CNTH

T1CNTL

T1DATAH

T1DATAL

T1CON

244

245

246

247

248

249

250

STOP Control register

STOPCON

251

Locations FCH is not mapped.

R ^(note)

R/W

Basic timer counter

BTCNT

EMT

253

FDH

FEH

FFH

External memory timing register

Interrupt priority register

254

255

IPR

R/W

NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.

4-3

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

Bit number(s) that is/are appended to

the register name for bit addressing

Name of an individual

bit or a bit function

Register location

Register

Register address in the internal

mnemonic

Full register name

(hexadecimal)

register file

FLAGS — System Flags Register

D5H

Set 1

Bit Identifier

.7

.6

.5

.4

.3

.2

.1

.0

RESET

x

0

Value

R/W

Read/Write

Register addressing mode only

Addressing Mode

Carry Flag (C)

.7

.6

.5

0

1

Operation does not generate a carry or borrow condition

Operation generates a carry-out or a borrow in the high-order bit 7

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

1

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

Description of the

effect of specific

bit settings

Bit number:

MSB = Bit 7

LSB = Bit 0

R = Read-only

W = Write-only

R/W = Read/write

'–' = Not used

RESET value notation:

'–' = Not used

Addressing mode/

modes you can use to

modify register values

'x' = Undetermined value

'0' = Logic zero

'1' = Logic one

Figure 4-1. Register Description Format

4-4

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

BTCON — Basic Timer Control Register

D3H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.4

Watchdog Timer Function Disable Code (for System Reset)

1

0

1

0

Disable watchdog timer function

Enable watchdog timer function

Others

.3 and .2

Basic Timer Input Clock Selection Bits

f_OSC/4096

0

1

0

1

0

1

f_OSC/1024

f_OSC/128

Invalid setting; not used for the KS88C0416/C0424

Basic Timer Counter Clear Bit ⁽¹⁾

.1

0

1

No effect

Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 ⁽²⁾

.0

0

1

No effect

Clear both clock frequency dividers

NOTES:

1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write

operation, the BTCON.1 value is automatically cleared to “0”.

2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the

write operation, the BTCON.0 value is automatically cleared to "0".

4-5

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

CACON— Counter A Control Register

F3H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

Counter A Input Clock Selection Bits

f_OSC

0

1

0

1

0

1

f_OSC/2

f_OSC/4

f_OSC/8

.5 and .4

Counter A Interrupt Timing Selection Bits

0

1

0

1

0

1

Elapsed time for Low data value

Elapsed time for High data value

Elapsed time for combined Low and High data values

Invalid setting; not used for the KS88C0416/C0424

.3

.2

.1

.0

Counter A Interrupt Enable Bit

0

1

Disable interrupt

Enable interrupt

Counter A Start Bit

0

1

Stop counter A

Start counter A

Counter A Mode Selection Bit

0

1

One-shot mode

Repeating mode

Counter A Output Flip-Flop Control Bit

0

1

Flip-Flop Low level (T-FF = Low)

Flip-flop High level (T-FF = High)

4-6

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

CLKCON— System Clock Control Register

D4H

Set 1

Bit Identifier

.7

–

.6

–

.5

–

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

–

R/W

Addressing Mode

Register addressing mode only

.7–.5

Not used for the KS88C0416/C0424

CPU Clock (System Clock) Selection Bits ⁽¹⁾

.4 and .3

f

/16

0

1

0

1

0

1

OSC

/8

/2

(non-divided)

Subsystem Clock Selection Bits ⁽²⁾

Invalid setting for the KS88C0416/C0424

Select main system clock (MCLK)

.2–.0

1

0

1

Others

NOTES:

1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the

appropriate values to CLKCON.3 and CLKCON.4.

2. These selection bits are required only for systems that have a main clock and a subsystem clock. The

KS88C0416/C0424 use only the main oscillator clock circuit. For this reason, the setting "101B" is invalid.

4-7

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

EMT— External Memory Timing Register ^(note)

FEH

Set 1

Bit Identifier

.7

0

.6

1

.5

1

.4

1

.3

1

.2

1

.1

0

.0

–

RESET Value

Read/Write

R/W

–

Addressing Mode

Register addressing mode only

.7

External WAIT Input Function Enable Bit

0

1

Disable WAIT input function for external device

Enable WAIT input function for external device

.6

Slow Memory Timing Enable Bit

0

1

Disable slow memory timing

Enable slow memory timing

.5 and .4

Program Memory Automatic Wait Control Bits

0

1

0

1

0

1

No wait

Wait one cycle

Wait two cycles

Wait three cycles

.3 and .2

Data Memory Automatic Wait Control Bits

0

1

0

1

0

1

No wait

Wait one cycle

Wait two cycles

Wait three cycles

.1

.0

Stack Area Selection Bit

0

1

Select internal register file area

Select external data memory area

Not used for the KS88C0416/C0424

NOTE: Not used for the KS88C0416/C0424. As an external peripheral interface is not implemented in the

KS88C0416/C0424, the EMT register is not used. The program initialization routine should clear the EMT register to

"00H" after a reset. Modification of the EMT values during a normal operation may cause a system malfunction.

4-8

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

FLAGS— System Flags Register

D5H

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

0

.0

0

RESET Value

Read/Write

R/W

R

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

Carry Flag (C)

0

1

Operation does not generate a carry or a borrow condition

Operation generates a carry-out or a borrow into high-order bit 7

Zero Flag (Z)

0

1

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

0

1

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

Overflow Flag (V)

0

1

Operation result is £ +127 or ³ –128

Operation result is > +127 or < –128

Decimal Adjust Flag (D)

0

1

Add operation completed

Subtraction operation completed

Half-Carry Flag (H)

0

1

No carry-out of bit 3 by addition or no borrow into bit 3 by subtraction

Addition generated a carry-out of bit 3 or subtraction generated a borrow into

bit 3

.1

.0

Fast Interrupt Status Flag (FIS)

0

1

Interrupt return (IRET) in progress (when read)

Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

0

1

Bank 0 is selected (normal setting for the KS88C0416/C0424)

Invalid selection (bank 1 is not implemented)

4-9

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

IMR— Interrupt Mask Register

DDH

Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

–

.2

–

.1

x

.0

x

RESET Value

Read/Write

R/W

–

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P2.3–P2.0

0

1

Disable (mask)

Enable (un-mask)

Interrupt Level 4 (IRQ4) Enable Bit; Counter A Interrupt

0

1

Disable (mask)

Enable (un-mask)

.3 and .2

.1

Not used for the KS88C0416/C0424

Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match/Capture or Overflow

0

1

Disable (mask)

Enable (un-mask)

.0

Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match/Capture or Overflow

0

1

Disable (mask)

Enable (un-mask)

NOTES:

1. When an interrupt level is masked, any interrupt request is not recognized by the CPU.

2. The interrupt levels, IRQ2 and IRQ3, are not used in the KS88C0416/C0424 interrupt structure.

4-10

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

IPH— Instruction Pointer (High Byte)

DAH

Set 1

Bit Identifier

RESET Value

Read/Write

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

R/W

Addressing Mode

Register addressing mode only

.7–.0

Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction

pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL

register (DBH).

IPL— Instruction Pointer (Low Byte)

DBH

Set 1

Bit Identifier

RESET Value

Read/Write

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

R/W

Addressing Mode

Register addressing mode only

.7–.0

Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction

pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH

register (DAH).

4-11

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

IPR— Interrupt Priority Register

FFH

Set 1

Bit Identifier

RESET Value

Read/Write

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

R/W

Addressing Mode

Register addressing mode only

.7, .4, and .1

Priority Control Bits for Interrupt Groups A, B, and C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Group priority undefined

B > C > A

A > B > C

B > A > C

C > A > B

C > B > A

A > C > B

Group priority undefined

.6

.5

.3

.2

.0

Interrupt Subgroup C Priority Control Bit

0

1

IRQ6 > IRQ7

IRQ7 > IRQ6

Interrupt Group C Priority Control Bit

0

1

IRQ5 > (IRQ6, IRQ7)

(IRQ6, IRQ7) > IRQ5

Interrupt Subgroup B Priority Control Bit ^(note)

0

1

IRQ4

Interrupt Group B Priority Control Bit ^(note)

0

1

IRQ4

Interrupt Group A Priority Control Bit

0

1

IRQ0 > IRQ1

IRQ1 > IRQ0

NOTE: The KS88C0416/C0424 interrupt structure uses only six levels: IRQ0, IRQ1, and IRQ4–IRQ7. Because IRQ2 and

IRQ3 are not recognized, the interrupt B group and the subgroup settings (IPR.2 and IPR.3) are not evaluated.

4-12

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

IRQ— Interrupt Request Register

DCH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

–

.2

–

.1

0

.0

0

RESET Value

Read/Write

R

–

R

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4

0

1

Not pending

Pending

Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0

0

1

Not pending

Pending

Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.3–P2.0

0

1

Not pending

Pending

Level 4 (IRQ4) Request Pending Bit; Counter A Interrupt

0

1

Not pending

Pending

.3 and .2

.1

Not used for the KS88C0416/C0424

Level 1 (IRQ1) Request Pending Bit; Timer 1 Match/Capture or Overflow

0

1

Not pending

Pending

.0

Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow

0

1

Not pending

Pending

NOTE: The interrupt levels, IRQ2 and IRQ3, are not used in the KS88C0416/C0424 interrupt structure.

4-13

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

P0CONH— Port 0 Control Register (High Byte)

E8H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

P0.7/INT4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.6/INT4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.5/INT4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.1 and .0

P0.4/INT4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTES:

1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector address

(E8H).

2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.

4-14

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

P0CONL— Port 0 Control Register (Low Byte)

E9H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

P0.3/INT3 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.2/INT2 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P0.1/INT1 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.1 and .0

P0.0/INT0 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTES:

1. The INT3–INT0 external interrupts at P0.3–P0.0 are in the interrupt level IRQ6. Each interrupt has a separate vector

address.

2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.

4-15

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

P0INT— Port 0 External Interrupt Enable Register

F1H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P0.7 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.6 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.5 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.4 External Interrupt (INT4) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.3 External Interrupt (INT3) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.2 External Interrupt (INT2) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.1 External Interrupt (INT1) Enable Bit

0

1

Disable interrupt

Enable interrupt

P0.0 External Interrupt (INT0) Enable Bit

0

1

Disable interrupt

Enable interrupt

4-16

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

P0PND— Port 0 External Interrupt Pending Register

F2H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

P0.7 External Interrupt (INT4) Pending Flag ^(note)

.7

.6

.5

.4

.3

.2

.1

.0

0

1

No P0.7 external interrupt pending (when read)

P0.7 external interrupt is pending (when read)

P0.6 External Interrupt (INT4) Pending Flag

0

1

No P0.6 external interrupt pending (when read)

P0.6 external interrupt is pending (when read)

P0.5 External Interrupt (INT4) Pending Flag

0

1

No P0.5 external interrupt pending (when read)

P0.5 external interrupt is pending (when read)

P0.4 External Interrupt (INT4) Pending Flag

0

1

No P0.4 external interrupt pending (when read)

P0.4 external interrupt is pending (when read)

P0.3 External Interrupt (INT3) Pending Flag

0

1

No P0.3 external interrupt pending (when read)

P0.3 external interrupt is pending (when read)

P0.2 External Interrupt (INT2) Pending Flag

0

1

No P0.2 external interrupt pending (when read)

P0.2 external interrupt is pending (when read)

P0.1 External Interrupt (INT1) Pending Flag

0

1

No P0.1 external interrupt pending (when read)

P0.1 external interrupt is pending (when read)

P0.0 External Interrupt (INT0) Pending Flag

0

1

No P0.0 external interrupt pending (when read)

P0.0 external interrupt is pending (when read)

NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag. Writing a “1” to an interrupt

pending flag (P0PND.0–.7) has no effect.

4-17

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

P0PUR— Port 0 Pull-Up Resistor Enable Register

E7H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P0.7 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.6 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.5 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.4 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.3 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.2 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.1 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P0.0 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

4-18

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

P1CONH— Port 1 Control Register (High Byte)

EAH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P1.7 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P1.6 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P1.5 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P1.4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

NOTE: Pull-up resistors can be assigned to individual port 1 pins by making the appropriate settings to the P1PUR control

register, location ECH, set 1.

4-19

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

P1CONL— Port 1 Control Register (Low Byte)

EBH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P1.3 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P1.2 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P1.1 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P1.0 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

NOTE: Pull-up resistors can be assigned to individual port 1 pins by making the appropriate settings to the P1PUR control

register, location ECH, set 1.

4-20

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

P1PUR— Port 1 Pull-Up Resistor Enable Register

ECH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P1.7 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P1.6 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P1.5 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P1.4 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P1.3 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P1.2 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P1.1 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P1.0 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

4-21

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

P2CONH— Port 2 Control Register (High Byte)

EEH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P2.7 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P2.6 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P2.5 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

P2.4 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode

Open-drain output mode

Push-pull output mode

Invalid selection

NOTE: Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control

register, location EDH, set 1.

4-22

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

P2CONL— Port 2 Control Register (Low Byte)

EFH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

.5 and .4

.3 and .2

.1 and .0

P2.3 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

Open-drain output mode

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.2 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

Open-drain output mode

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.1 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

Open-drain output mode

Push-pull output mode

C-MOS input mode; interrupt on rising edges

P2.0 Mode Selection Bits

0

1

0

1

0

1

C-MOS input mode; interrupt on falling edges

Open-drain output mode

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTE: Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control

register, location EDH, set 1.

4-23

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

P2INT— Port 2 External Interrupt Enable Register

E5H

Set 1

Bit Identifier

.7

–

.6

–

.5

–

.4

–

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

–

R/W

Addressing Mode

Register addressing mode only

.7–.4

.3

Not used for the KS88C0416/C0424

P2.3 External Interrupt (INT8) Enable Bit

0

1

Disable interrupt

Enable interrupt

.2

.1

.0

P2.2 External Interrupt (INT7) Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.1 External Interrupt (INT6) Enable Bit

0

1

Disable interrupt

Enable interrupt

P2.0 External Interrupt (INT5) Enable Bit

0

1

Disable interrupt

Enable interrupt

4-24

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

P2PND— Port 2 External Interrupt Pending Register

E6H

Set 1

Bit Identifier

.7

–

.6

–

.5

–

.4

–

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

–

R/W

Addressing Mode

Register addressing mode only

.7–.4

.3

Not used for the KS88C0416/C0424

P2.3 External Interrupt (INT8) Pending Flag

0

1

No P2.3 external interrupt pending (when read)

P2.3 external interrupt is pending (when read)

.2

.1

.0

P2.2 External Interrupt (INT7) Pending Flag

0

1

No P2.2 external interrupt pending (when read)

P2.2 external interrupt is pending (when read)

P2.1 External Interrupt (INT6) Pending Flag

0

1

No P2.1 external interrupt pending (when read)

P2.1 external interrupt is pending (when read)

P2.0 External Interrupt (INT5) Pending Flag

0

1

No P2.0 external interrupt pending (when read)

P2.0 external interrupt is pending (when read)

NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag. Writing a “1” to an interrupt

pending flag (P2PND.0–.3) has no effect.

4-25

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

P2PUR— Port 2 Pull-Up Resistor Enable Register

EDH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7

.6

.5

.4

.3

.2

.1

.0

P2.7 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.6 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.5 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.4 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.3 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.2 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.1 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

P2.0 Pull-Up Resistor Enable Bit

0

1

Disable pull-up resistor

Enable pull-up resistor

4-26

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

P3CON— Port 3 Control Register

F0H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.5

P3.1 Configuration Bits

0

1

0

1

x

0

1

0

1

C-MOS input mode (P3.1/T0CK)

C-MOS input mode with pull-up (P3.1/T0CK)

Push-pull output mode (P3.1/REM)

Open-drain output mode (P3.1/REM)

Open-drain output mode with pull-up (P3.1/REM)

.4

P3.1 Alternative Function Enable Bit

0

1

Normal I/O function (P3.1)

REM/T0CK

.3

P3.0 Alternative Function Enable Bit

0

1

Normal I/O function (P3.0)

T0PWM/T0_T1CAP

.2–.0

P3.0 Configuration Bits

0

1

0

1

x

0

1

0

1

C-MOS input mode (P3.0/T0_T1CAP)

C-MOS input mode with pull-up (P3.0/T0_T1CAP)

Push-pull output mode (P3.0/T0PWM)

Open-drain output mode (P3.0/T0PWM)

Open-drain output mode with pull-up (P3.0/T0PWM)

NOTES:

1. An "x" means that the bit setting is not evaluated (doesn’t matter).

2. The port 3 data register, P3, at location E3H, contains three bit values which correspond to the following port 3 pin

functions (other data register bits are not used for the KS88C0416/C0424):

a. P3, bit 5: carrier signal on (“1”) or off (“0”).

b. P3, bit 1: P3.1/REM/T0CK pin status.

c. P3, bit 0: P3.0/T0PWM/T0CAP/T1CAP pin level.

4-27

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

PP— Register Page Pointer

DFH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.4

.3–.0

Destination Register Page Selection Bits

Destination: page 0 ^(note)

0

Source Register Page Selection Bits

Source: page 0 ^(note)

0

NOTE: In the KS88C0416/C0424 microcontroller, a paged expansion of the internal register file is not implemented. For this

reason, only page 0 settings are valid. Register page pointer values for the source and the destination register page

are automatically set to "0000B" following a hardware reset. These values should not be changed during the normal

operation.

4-28

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

RP0— Register Pointer 0

D6H

Set 1

Bit Identifier

.7

1

.6

1

.5

0

.4

0

.3

0

.2

–

.1

–

.0

–

RESET Value

Read/Write

R/W

–

Addressing Mode

Register addressing only

.7–.3

.2–.0

Register Pointer 0 Address Value

Register pointer 0 can independently point to one of the 24 8-byte working register

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP0 points to the address C0H in the register set 1, selecting the 8-byte working

register slice C0H–C7H.

Not used for the KS88C0416/C0424

RP1— Register Pointer 1

D7H

Set 1

Bit Identifier

.7

1

.6

1

.5

0

.4

0

.3

1

.2

–

.1

–

.0

–

RESET Value

Read/Write

R/W

–

Addressing Mode

Register addressing only

.7–.3

.2–.0

Register Pointer 1 Address Value

Register pointer 1 can independently point to one of the 24 8-byte working register

areas in the register file. Using the register pointers RP0 and RP1, you can select

two 8-byte register slices at one time as active working register space. After a reset,

RP1 points to the address C8H in the register set 1, selecting the 8-byte working

register slice C8H–CFH.

Not used for the KS88C0416/C0424

4-29

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

SPL— Stack Pointer (Low Byte) D9H Set 1

Bit Identifier

.7

x

.6

x

.5

x

.4

x

.3

x

.2

x

.1

x

.0

x

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7–.0

Stack Pointer Address (Low Byte)

The SP value is undefined after a reset.

4-30

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

STOPCON— Stop Control Register

FBH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

W

Addressing Mode

Register addressing mode only

.7–.0

Stop Control Register enable bits

1

0

1

0

1

0

1

Enable STOP mode

NOTES:

1. To get into STOP mode, the stop control register must be enabled just before the STOP instruction.

2. When STOP mode is released, the stop control register (STOPCON) value is cleared automatically.

3. It is prohibited to write another value into STOPCON.

4-31

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

SYM— System Mode Register

DEH

Set 1

Bit Identifier

.7

0

.6

–

.5

–

.4

x

.3

x

.2

x

.1

0

.0

0

RESET Value

Read/Write

R/W

–

R/W

Addressing Mode

Register addressing mode only

Tri-State External Interface Control Bit ⁽¹⁾

.7

0

1

Normal operation (disable tri-state operation)

Set external interface lines to high impedance (enable tri-state operation)

.6 and .5

.4–.2

Not used for the KS88C0416/C0424

Fast Interrupt Level Selection Bits ⁽²⁾

0

1

0

1

0

1

0

1

0

1

0

1

0

1

IRQ0

IRQ1

Not used for the KS88C0416/C0424

IRQ4

IRQ5

IRQ6

IRQ7

Fast Interrupt Enable Bit ⁽³⁾

.1

0

1

Disable fast interrupt processing

Enable fast interrupt processing

Global Interrupt Enable Bit ⁽⁴⁾

.0

0

1

Disable global interrupt processing

Enable global interrupt processing

NOTES:

1. Because an external interface is not implemented for the KS88C0416/C0424, SYM.7 must always be "0".

2. You can select only one interrupt level at a time for fast interrupt processing.

3. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.

4. After a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"

to SYM.0).

4-32

KS88C0416/P0416/C0424/P0424

CONTROL REGISTERS

T0CON— Timer 0 Control Register

D2H

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

Timer 0 Input Clock Selection Bits

f_OSC/4096

f_OSC/256

f_OSC/8

0

1

0

1

0

1

External clock input (at the T0CK pin, P3.1)

.5 and .4

Timer 0 Operating Mode Selection Bits

0

1

0

1

0

1

Interval timer mode (counter cleared by match signal)

Capture mode (rising edges, counter running, OVF interrupt can occur)

Capture mode (falling edges, counter running, OVF interrupt can occur)

PWM mode (OVF interrupt can occur)

.3

.2

.1

.0

Timer 0 Counter Clear Bit

0

No effect (when write)

1

Clear T0 counter, T0CNT (when write)

Timer 0 Overflow Interrupt Enable Bit ^(note)

0

1

Disable T0 overflow interrupt

Enable T0 overflow interrupt

Timer 0 Match/Capture Interrupt Enable Bit

0

1

Disable T0 match/capture interrupt

Enable T0 match/capture interrupt

Timer 0 Match/Capture Interrupt Pending Flag

0

1

No T0 match/capture interrupt pending (when read)

Clear T0 match/capture interrupt pending condition (when write)

T0 match/capture interrupt is pending (when read)

No effect (when write)

NOTE: A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0 match/

capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine.

4-33

CONTROL REGISTERS

KS88C0416/P0416/C0424/P0424

T1CON— Timer 1 Control Register

FAH

Set 1

Bit Identifier

.7

0

.6

0

.5

0

.4

0

.3

0

.2

0

.1

0

.0

0

RESET Value

Read/Write

R/W

Addressing Mode

Register addressing mode only

.7 and .6

Timer 1 Input Clock Selection Bits

f_OSC/4

f_OSC/8

f_OSC/16

0

1

0

1

0

1

Internal clock (counter A flip-flop, T-FF)

.5 and .4

Timer 1 Operating Mode Selection Bits

0

1

0

1

0

1

Interval timer mode (counter cleared by match signal)

Capture mode (rising edges, counter running, OVF can occur)

Capture mode (falling edges, counter running, OVF can occur)

Capture mode (rising and falling edges, counter running, OVF can occur)

.3

.2

.1

.0

Timer 1 Counter Clear Bit

0

No effect (when write)

1

Clear T1 counter, T1CNT (when write)

Timer 1 Overflow Interrupt Enable Bit (see Note)

0

1

Disable T1 overflow interrupt

Enable T1 overflow interrupt

Timer 1 Match/Capture Interrupt Enable Bit

0

1

Disable T1 match/capture interrupt

Enable T1 match/capture interrupt

Timer 1 Match/Capture Interrupt Pending Flag

0

1

No T1 match/capture interrupt pending (when read)

Clear T1 match/capture interrupt pending condition (when write)

T1 match/capture interrupt is pending (when read)

No effect (when write)

NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/

capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine.

4-34

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

5

INTERRUPT STRUCTURE

OVERVIEW

The KS88-series interrupt structure has three basic components: levels, vectors, and sources. The SAM87 CPU

recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level

has more than one vector address, the vector priorities are established in hardware. A vector address can be

assigned to one or more sources.

Levels

Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks

can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight

possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an

interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from

device to device. The KS88C0416/C0424 interrupt structure recognizes six interrupt levels.

The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just

identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels

is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by

IPR settings lets you define more complex priority relationships between different levels.

Vectors

Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all.

The maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors

used for the KS88-series devices is always much smaller.) If an interrupt level has more than one vector address,

the vector priorities are set in hardware. The KS88C0416/C0424 use fifteen vectors. One vector address is

shared by four interrupt sources.

Sources

A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow.

Each vector can have several interrupt sources. In the KS88C0416/C0424 interrupt structure, there are eighteen

possible interrupt sources.

When a service routine starts, the respective pending bit should be either cleared automatically by hardware or

cleared "manually" by program software. The characteristics of the source's pending mechanism determine which

method would be used to clear its respective pending bit.

5-1

INTERRUPT STRUCTURE

INTERRUPT TYPES

KS88C0416/P0416/C0424/P0424

The three components of the KS88 interrupt structure described before — levels, vectors, and sources — are

combined to determine the interrupt structure of an individual device and to make full use of its available

interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1,

2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):

Type 1:

Type 2:

Type 3:

One level (IRQn) + one vector (V ) + one source (S )

1 1

One level (IRQn) + one vector (V ) + multiple sources (S – S )

1

n

One level (IRQn) + multiple vectors (V – V ) + multiple sources (S – S , S

n+1

– S )

n+m

1

n

1

n

In the KS88C0416/C0424 microcontroller, all three interrupt types are implemented.

LEVELS

VECTORS

SOURCES

V

1

S

1

IRQn

TYPE 1:

TYPE 2:

S

1

V

1

S

IRQn

2

3

n

V

S

1

V

S

IRQn

2

3

n

2

3

TYPE 3:

S

n

n + 1

:

NOTES

1. The number of S and V values is expandable.

2. In the KS88C0416/C0424 implementation, interrupt

types 1 and 3 are used.

n

S

n + 2

n + m

Figure 5-1. KS88-Series Interrupt Types

5-2

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

KS88C0416/C0424 INTERRUPT STRUCTURE

The KS88C0416/C0424 microcontrollers support eighteen interrupt sources. Fourteen of the interrupt sources

have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector

address. Six interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in

Figure 5-2.

When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which

contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt

with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a

single level are fixed in hardware).

When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the

program counter value and status flags are pushed to stack. The starting address of the service routine is fetched

from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the

service routine is executed.

5-3

INTERRUPT STRUCTURE

KS88C0416/P0416/C0424/P0424

LEVEL

VECTOR

100H

SOURCE

RESET/CLEAR

RESET

Basic timer overflow

H/W

S/W

1

0

1

0

FCH

Timer 0 match/capture

IRQ0

FAH

F6H

F4H

Timer 0 overflow

H/W

S/W

Timer 1 match/capture

IRQ1

IRQ4

Timer 1 overflow

Counter A

H/W

ECH

3

2

1

0

D6H

D4H

P2.3 external interrupt

P2.2 external interrupt

S/W

IRQ5

D2H

D0H

P2.1 external interrupt

P2.0 external interrupt

S/W

3

2

1

0

E6H

E4H

P0.3 external interrupt

P0.2 external interrupt

S/W

IRQ6

E2H

E0H

P0.1 external interrupt

S/W

P0.0 external interrupt

P0.7 external interrupt

P0.6 external interrupt

P0.5 external interrupt

P0.4 external interrupt

S/W

E8H

IRQ7

:

For interrupt levels with two or more vectors, the lowest vector address usually has

the highest priority. For example, FAH has higher priority (0) than FCH (1) within the

level IRQ0. These priorities are fixed in hardware.

NOTE

Figure 5-2. KS88C0416/C0424 Interrupt Structure

5-4

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

INTERRUPT VECTOR ADDRESSES

All interrupt vector addresses for the KS88C0416/C0424 interrupt structure are stored in the vector address area

of the internal 16/24-Kbyte ROM, 00H–FFH (see Figure 5-3).

You can allocate unused locations in the vector address area as normal program memory. If you do so, please be

careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).

The program reset address in the ROM is 0100H.

(DECIMAL)

24,575

(HEX)

5FFFH

Internal Program

Memory (ROM)

3FFFH

16,383

KS88C0424

(24-Kbyte)

KS88C0416

(16-Kbyte)

255

0

0FFH

0H

Interrupt

Vector Area

Figure 5-3. ROM Vector Address Area

5-5

INTERRUPT STRUCTURE

Vector Address

KS88C0416/P0416/C0424/P0424

Table 5-1. KS88C0416/C0424 Interrupt Vectors

Interrupt Source

Request

Reset/Clear

Decimal

Value

Hex

Interrupt

Level

Priority in

Level

H/W

S/W

Value

100H

FCH

FAH

F6H

F4H

ECH

E8H

E6H

E4H

E2H

E0H

D6H

D4H

D2H

D0H

254

252

250

246

244

236

232

230

228

226

224

214

212

210

208

Basic timer overflow

Timer 0 (match/capture)

Timer 0 overflow

–

1

0

1

0

–

RESET

IRQ0

Ö

Timer 1 (match/capture)

Timer 1 overflow

IRQ1

Ö

Counter A

IRQ4

IRQ7

P0.7 external interrupt

P0.6 external interrupt

P0.5 external interrupt

P0.4 external interrupt

P0.3 external interrupt

P0.2 external interrupt

P0.1 external interrupt

P0.0 external interrupt

P2.3 external interrupt

P2.2 external interrupt

P2.1 external interrupt

P2.0 external interrupt

Ö

IRQ6

IRQ5

3

2

1

0

3

2

1

0

NOTES:

1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.

2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has

priority over one with a higher vector address. The priorities within a given level are fixed in hardware.

5-6

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then

serviced as they occur, according to the established priorities.

NOTE

The system initialization routine executed after a reset must always contain an EI instruction to globally

enable the interrupt structure.

During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable

interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. Although you can

directly manipulate SYM.0 to enable or disable interrupts, it is recommended that you use the EI and DI

instructions instead.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt

processing:

— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to

each interrupt source).

— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable

fast interrupts and control the activity of external interface, if implemented).

Table 5-2. Interrupt Control Register Overview

Control Register

ID

R/W

Function Description

Interrupt mask register

IMR

R/W

Bit settings in the IMR register enable or disable interrupt

processing for each of the six interrupt levels: IRQ0, IRQ1,

and IRQ4–IRQ7.

Interrupt priority register

IPR

R/W

Controls the relative processing priorities of the interrupt

levels. The six levels of the KS88C0416/C0424 are organized

into three groups: A, B, and C. Group A is IRQ0 and IRQ1,

group B is IRQ4, and group C is IRQ5, IRQ6, and IRQ7.

Interrupt request register

System mode register

IRQ

R

This register contains a request pending bit for each interrupt

level.

SYM

R/W

Dynamic global interrupt processing enable/disable, fast

interrupt processing, and external interface control (An

external memory interface is not implemented in the

KS88C0416/C0424 microcontroller).

5-7

INTERRUPT STRUCTURE

KS88C0416/P0416/C0424/P0424

INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.

Among the system-level control points in the interrupt structure are:

— Global interrupt enabled and disabled (by EI and DI instructions or by direct manipulation of SYM.0 )

— Interrupt level enable/disable settings (IMR register)

— Interrupt level priority settings (IPR register)

— Interrupt source enable/disable settings in the corresponding peripheral control registers

NOTE

When writing an application program that deals with interrupt processing, be sure to include the

necessary register file address (register pointer) information.

Q

INTERRUPT REQUEST

REGISTER (Read-only)

POLLING

CYCLE

EI

S

R

RESET

IRQ0, IRQ1,

and IRQ4-IRQ7

INTERRUPTS

INTERRUPT PRIORITY

REGISTER

VECTOR

INTERRUPT

CYCLE

INTERRUPT MASK

REGISTER

GLOBAL INTERRUPT

CONTROL (EI, DI, or

SYM.0 manipulation)

a

Figure 5-4. Interrupt Function Diagram

5-8

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the

interrupt generated by that peripheral (see Table 5-3).

Table 5-3. Interrupt Source Control and Data Registers

Interrupt Source

Interrupt Level

Register(s)

Location(s) in Set 1

T0CON ^(note)

T0DATA

Timer 0 match/capture or

timer 0 overflow

IRQ0

D2H

D1H

T1CON ^(note)

T1DATAH, T1DATAL

Timer 1 match/capture or

timer 1 overflow

IRQ1

IRQ4

IRQ7

FAH

F8H, F9H

Counter A

CACON

CADATAH, CADATAL

F3H

F4H, F5H

P0.7 external interrupt

P0.6 external interrupt

P0.5 external interrupt

P0.4 external interrupt

P0CONH

P0INT

P0PND

E8H

F1H

F2H

P0.3 external interrupt

P0.2 external interrupt

P0.1 external interrupt

P0.0 external interrupt

IRQ6

IRQ5

P0CONL

P0INT

P0PND

E9H

F1H

F2H

P2.3 external interrupt

P2.2 external interrupt

P2.1 external interrupt

P2.0 external interrupt

P2CONL

P2INT

P2PND

EFH

E5H

E6H

NOTE: Because the timer 0 and timer 1 overflow interrupts are cleared by hardware, the T0CON and T1CON registers

control only the enable/disable functions. The T0CON and T1CON registers contain enable/disable and pending

bits for the timer 0 and timer 1 match/capture interrupts, respectively.

5-9

INTERRUPT STRUCTURE

KS88C0416/P0416/C0424/P0424

SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to

control fast interrupt processing (see Figure 5-5).

A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4–SYM.2,

is undetermined.

The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0

value of the SYM register. In order to enable interrupt processing, an Enable Interrupt (EI) instruction must be

included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly

to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions

for this purpose.

SYSTEM MODE REGISTER (SYM)

DEH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Global interrupt enable bit:

0 = Disable all interrupts

1 = Enable all interrupts

(note)

External interface tri-state enable bit:

0= Normal operation (Tri-state disabled)

1= High impedance (Tri-state enabled)

Fast interrupt enable bit:

0 = Disable fast interrupts

1 = Enable fast interrupts

Not used for the

KS88C0416/C0424

Fast interrupt level selection bits:

IRQ0

IRQ1

Not used

IRQ4

IRQ5

IRQ6

IRQ7

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Because an external memory interface is not implemented for the

KS88C0416/C0424, SYM.7 must always be “0”.

NOTE:

Figure 5-5. System Mode Register (SYM)

5-10

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual

interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required

settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit

of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a

level's IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to the register location DDH in set 1. Bit values can be read and written by

instructions using Register addressing mode.

INTERRUPT MASK REGISTER (IMR)

DDH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

IRQ0

IRQ1

Not

used

Not

used

IRQ4

IRQ5

Interrupt level enable bits (7–4, 1, 0):

0 = Disable (mask) interrupt level

1 = Enable (un-mask) interrupt level

IRQ6

IRQ7

Figure 5-6. Interrupt Mask Register (IMR)

5-11

INTERRUPT STRUCTURE

KS88C0416/P0416/C0424/P0424

INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels

in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore

be written to their required settings by the initialization routine.

When more than one interrupt sources are active, the source with the highest priority is serviced first. If two

sources belong to the same interrupt level, the source with the lower vector address usually has priority (This

priority is fixed in hardware).

To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by

the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register

priority definitions (see Figure 5-7):

Group A

Group B

Group C

IRQ0, IRQ1

IRQ4

IRQ5, IRQ6, IRQ7

IPR

GROUP A

GROUP B

GROUP C

A1

A2

C1

C2

C21

IRQ6

C22

IRQ7

IRQ0

IRQ1

IRQ4

IRQ5

Figure 5-7. Interrupt Request Priority Groups

As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of the interrupt groups A, B, and

C. For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting

"101B" would select the relationship C > B > A.

The functions of other IPR bit settings are as follows:

— IPR.5 controls the relative priorities of the group C interrupts.

— The interrupt group B includes a subgroup that has an additional priority relationship among the interrupt

levels 2, 3, and 4. IPR.3 defines the subgroup B relationship. IPR.2 controls the interrupt group B. In the

KS88C0416/C0424 implementation, the interrupt levels 2 and 3 are not used. Therefore, IPR.2 and IPR.3

settings are not evaluated, as IRQ4 is the only remaining level in the group.

— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

5-12

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

INTERRUPT PRIORITY REGISTER (IPR)

FFH, Set 1, Bank 0, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

GROUP PRIORITY:

D7 D4 D1

GROUP A

0 = IRQ0 > IRQ1

1 = IRQ1 > IRQ0

=

UNDEFINED

B > C > A

A > B > C

B > A > C

C > A > B

C > B > A

A > C > B

UNDEFINED

(note)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GROUP B

0 = IRQ4

1 = IRQ4

(note)

SUBGROUP B

0 = IRQ4

1 = IRQ4

GROUP C

0 = IRQ5 > (IRQ6, IRQ7)

1 = (IRQ6, IRQ7) > IRQ5

SUBGROUP C

0 = IRQ6 > IRQ7

1 = IRQ7 > IRQ6

:

In the KS88C0416/C0424 interrupt structure, only the levels IRQ0 and IRQ1, and IRQ4-IRQ7

are used. Setting for the group/subgroup B, which control relative priorities for the level IRQ2

and IRQ3 are therefore not evaluated.

NOTE

Figure 5-8. Interrupt Priority Register (IPR)

5-13

INTERRUPT STRUCTURE

KS88C0416/P0416/C0424/P0424

INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for

all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same

number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued

for that level; a "1" indicates that an interrupt request has been generated for that level.

IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of

the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of

specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”.

You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing

is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,

however, still detect a interrupt request by polling the IRQ register. In this way, you can determine which events

occurred while the interrupt structure was globally disabled.

INTERRUPT REQUEST REGISTER (IRQ)

DCH, Set 1, Read-only

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

IRQ0

IRQ1

Not

used

IRQ4

IRQ5

Interrupt level request pending bits:

0 = Interrupt level is not pending

1 = Interrupt level is pending

IRQ6

IRQ7

Figure 5-9. Interrupt Request Register (IRQ)

5-14

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: One type that is automatically cleared by hardware after the

interrupt service routine is acknowledged and executed; the other that must be cleared by the interrupt service

routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding

pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is

waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service

routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or

written by application software.

In the KS88C0416/C0424 interrupt structure, the timer 0 and timer 1 overflow interrupts (IRQ0 and IRQ1), and

the counter A interrupt (IRQ4) belong to this category of interrupts whose pending condition is cleared

automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit is the one that should be cleared by program software. The service routine must

clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must

be written to the corresponding pending bit location in the source’s mode or control register.

In the KS88C0416/C0424 interrupt structure, pending conditions for all interrupt sources, except the timer 0 and

timer 1 overflow interrupt and the counter A borrow interrupt, must be cleared by the interrupt service routine.

5-15

INTERRUPT STRUCTURE

KS88C0416/P0416/C0424/P0424

INTERRUPT SOURCE POLLING SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1. A source generates an interrupt request by setting the interrupt request bit to "1".

2. The CPU polling procedure identifies a pending condition for that source.

3. The CPU checks the source's interrupt level.

4. The CPU generates an interrupt acknowledge signal.

5. Interrupt logic determines the interrupt's vector address.

6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).

7. The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES

Before an interrupt request is serviced, the following conditions must be met:

— Interrupt processing must be globally enabled (EI, SYM.0 = "1")

— The interrupt level must be enabled (IMR register)

— The interrupt level must have the highest priority if more than one levels are currently requesting service

— The interrupt must be enabled at the interrupt's source (peripheral control register)

When all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction

cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.

2. Save the program counter (PC) and status flags to the system stack.

3. Branch to the interrupt vector to fetch the address of the service routine.

4. Pass control to the interrupt service routine.

When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores

the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request.

5-16

KS88C0416/P0416/C0424/P0424

INTERRUPT STRUCTURE

GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that

correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:

1. Push the program counter's low-byte value to the stack.

2. Push the program counter's high-byte value to the stack.

3. Push the FLAG register values to the stack.

4. Fetch the service routine's high-byte address from the vector location.

5. Fetch the service routine's low-byte address from the vector location.

6. Branch to the service routine specified by the concatenated 16-bit vector address.

NOTE

A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH.

NESTING OF VECTORED INTERRUPTS

It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,

you must follow these steps:

1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).

2. Load the IMR register with a new mask value that enables only the higher priority interrupt.

3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it

occurs).

4. When the lower-priority interrupt service routine ends except a DI instruction, return the IMR to its original

value by restoring the previous mask value from the stack (POP IMR).

5. Execute an IRET.

Depending on the application, you may be able to simplify the procedure above to some extent.

INSTRUCTION POINTER (IP)

The instruction pointer (IP) is adopted by all the KS88-series microcontrollers to control the optional high-speed

interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP

registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).

FAST INTERRUPT PROCESSING

The feature called fast interrupt processing allows an interrupt within a given level to be completed in

approximately six clock cycles rather than the usual 22 clock cycles. To select a specific interrupt level for fast

interrupt processing, you should write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt

processing for the selected level, you should set SYM.1 to “1”.

5-17

INTERRUPT STRUCTURE

KS88C0416/P0416/C0424/P0424

FAST INTERRUPT PROCESSING (Continued)

Two other system registers support fast interrupt processing:

— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the

program counter values), and

— When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated

register called FLAGS' (“FLAGS prime”).

NOTE

For the KS88C0416/C0424 microcontroller, the service routine for any one of the six interrupt levels,

IRQ0 and IRQ1, or IRQ4–IRQ7, can be selected for fast interrupt processing.

Procedure for Initiating Fast Interrupts

To initiate fast interrupt processing, follow these steps:

1. Load the start address of the service routine into the instruction pointer (IP).

2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)

3. Write a "1" to the fast interrupt enable bit in the SYM register.

Fast Interrupt Service Routine

When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:

1. The contents of the instruction pointer and the PC are swapped.

2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.

3. The fast interrupt status bit in the FLAGS register is set.

4. The interrupt is serviced.

5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction

pointer and PC values are swapped back.

6. The content of FLAGS' (“FLAGS prime”) is copied automatically back to the FLAGS register.

7. The fast interrupt status bit in FLAGS is cleared automatically.

Relationship to Interrupt Pending Bit Types

As described previously, there are two types of interrupt pending bits: One is the type that is automatically

cleared by hardware after the interrupt service routine is acknowledged and executed, and the other is the one

that must be cleared by the application program's interrupt service routine. You can select fast interrupt

processing for interrupts with either type of pending condition clear function — by hardware or by software.

Programming Guidelines

Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the

SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,

except fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast

interrupt service routine ends.

5-18

KS88C0416/P0416/C0424/P0424

CLOCK CIRCUITS

7

CLOCK CIRCUITS

OVERVIEW

The clock frequency generated for the KS88C0416/C0424 by an external crystal, or supplied by an external clock

source, can range from 1 MHz to 8 MHz. The maximum CPU clock frequency, as determined by CLKCON

register settings, is 8 MHz. The X_INand X_OUTpins connect the external oscillator or clock source to the on-chip

clock circuit.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

— External crystal or ceramic resonator oscillation source (or an external clock)

— Oscillator stop and wake-up functions

— Programmable frequency divider for the CPU clock (f_OSCdivided by 1, 2, 8, or 16)

— Clock circuit control register, CLKCON

X

IN

C1

C2

X

IN

EXTERNAL

CLOCK

KS88C0416

KS88C0424

KS88C0416

KS88C0424

OPEN PIN

X

OUT

X

OUT

Figure 7-1. Main Oscillator Circuit

Figure 7-2. External Clock Circuit

(External Crystal or Ceramic Resonator)

7-1

CLOCK CIRCUITS

KS88C0416/P0416/C0424/P0424

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

— In Stop mode, the main oscillator is halted. Stop mode is released and the oscillator is started, by a reset

operation, by an external interrupt with RC-delay filter, or by execution of SED and R circuit. To enter the

Stop mode, STOPCON (STOP Control register) has to be loaded with the value, #0A5H before an STOP

instruction execution. After recovering from the Stop mode by a reset or an interrupt, STOPCON register is

automatically cleared.

— In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the

interrupt structure, timer 0, and counter A. Idle mode is released by a reset or by an interrupt (externally or

internally generated).

STOPCON

STOP

CLKCON.3, .4

Instruction

CLKCON.0–.2

3-Bit Signature Code

(2)

Oscillator

Stop

1/2

1/8

M

U

X

M

U

X

MAIN

OSC

CPU CLOCK

Oscillator

Wake-up

1/16

NOISE

FILTER

NOTES:

1. An external interrupt with an RC-delay noise filter (for the KS88C0416/C0424,

INT0) is fixed to release Stop mode and "wake up" the main oscillator.

Because the KS88C0416/C0424 have no subsystem clock, the 3-bit

CLKCON signature code (CLKCON.2–CLKCON.0) has no meaning.

2.

(1)

INT Pin

Figure 7-3. System Clock Circuit Diagram

7-2

KS88C0416/P0416/C0424/P0424

CLOCK CIRCUITS

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and

has the following functions:

— Oscillator frequency divide-by value

— System clock signal selection

CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release

(This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7. In the

KS88C0416/C0424, this bit is no longer valid. In reality, bits 7, 6, 5, 2, 1, and 0 have no significance in the

KS88C0416/C0424.

After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the

f_OSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU

clock speed to f_OSC, f_OSC/2, or f_OSC/8.

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

D4H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Not used for the KS88C0416/C0424

Divide-by selection bits for

CPU clock frequency:

00 = f

01 = f

10 = f

11 = f

/16

/8

/2

OSC

(non-divided)

Figure 7-4. System Clock Control Register (CLKCON)

7-3

CLOCK CIRCUITS

KS88C0416/P0416/C0424/P0424

NOTES

7-4

KS88C0416/P0416/C0424/P0424

RESET and POWER-DOWN

8

RESET and POWER-DOWN

SYSTEM RESET

OVERVIEW

The reset pin supplies two operating modes: back-up mode input, and system reset input. Back-up mode input

automatically creates a chip stop state when the reset pin is set to a low level. When the reset pin is at a high

state, the rising edge detector becomes activated, the reset pulse generator makes a pulse, system reset occurs

and system operation starts.

System reset has three different sources: the rising edge signal of the external reset input pin, BT overflow for

the watch-dog timer, and the internal POR circuit. The internal POR is operated during powering-up stage.

Internal POR can detect the power-up condition through the internal schmitt trigger input, resistor and capacitor

circuit, but it cannot detect the low non-operating voltage range. Therefore, it is true that the internal POR circuit

sometimes can not generate the reset signal. Another reset source, the Watch-Dog Timer (WDT) is very useful

in this situation. Please refer to Chapter 10, "Basic Timer and Timer 0," for more information.

RESET/

NOISE

FILTER

BACK-UP

MODE

BACK-UP MODE

Rising Edge

Detector

Reset Pulse

Generator

RESET

SYSTEM

V

DD

POR

f

BT(WDT)

OSC

Figure 8-1. Reset Block Diagram

8-1

RESET and POWER-DOWN

POWER-ON RESET(POR)

KS88C0416/P0416/C0424/P0424

The power-on reset circuit is built on the KS88C0416/C0424 product. During a power-on reset, the voltage at

V_DDgoes to High level and the schmitt trigger input of POR circuit is forced to Low level and then to High level.

The power-on reset circuit makes a reset signal whenever the power supply voltage is powering-up and the

schmitt trigger input senses the Low level. This on-chip POR circuit consists of an internal resistor, an internal

capacitor, and a schmitt trigger input transistor. A resistor and capacitor circuit works as a delay circuit and

makes a Va signal (Schmitt trigger input signal) according to V_DDchanging. When the power is rising-up, the

schmitt trigger input can detect the low level of Va caused by the R-C delay circuit. After a few mili-seconds, Va

level rises to the Vdd level and the schmitt input can also detect the VIH level. That is, when powering-up, the

schmitt trigger input detects a low level and a high level in turn. The duration between VIL and VIH is equal to a

reset pulse time. For more information, please see the following examples.

Examples

1. When the power supply level is changed to V_DD= 3.3 V from V_DD= 2 V,

VIL £ 0.4 V_DD. VIH 0.85 V_DD, therefore VIL £ 0.4 x 3.3 V, VIL £ 1.32 V. 2 V is larger than VIL (1.32 V).

So, POR circuit can not detect the low level, and does not make a system reset.

2. When the power supply level is changed to V_DD= 3.3 V from V_DD= 1.3 V,

VIL £ 0.4 V_DD. VIH 0.85 V_DD, therefore VIL £ 0.4 x 3.3V, VIL £ 1.32 V. 1.3 V is smaller than VIL (1.32 V).

So, POR circuit can detect the low level, and, make a reset signal.

3. When the power supply level is changed to V_DD= 3.0 V from V_DD= 2 V,

VIL £ 0.4 V_DD. VIH 0.85 V_DD, therefore VIL £ 0.4 x 3.0 V, VIL £ 1. 2 V. 2 V is larger than VIL (1.2 V).

So, POR circuit can not detect the low level, and does not make a system reset.

4. When the power supply level is changed to V_DD= 3.0 V from V_DD= 1.3 V,

VIL £ 0.4 V_DD. VIH 0.85 V_DD, therefore VIL £ 0.4 x 3.0 V, VIL £ 1.2 V. 1.3 V is larger than VIL (1.32 V).

So, POR circuit can not detect the low level, and does not make a system reset.

V

DD

R: On-chip resistor

C: On-chip capacitor

R

RESET

Va

C

SYSTEM

Schmitt Trigger Inverter

V

SS

Figure 8-2. Power-On Reset Circuit

8-2

KS88C0416/P0416/C0424/P0424

RESET and POWER-DOWN

Voltage (V)

V

DD

TV

DD

V

(V

Rising Time)

DD

Va

DD

V

= 0.85 V

DD

IH

= 0.4

V

IL

DD

Reset Pulse Width

Reset Pulse

Time

If Va voltage is under 0.4 V , Reset fulse signal is generated.

DD

If Va voltage is over 0.4 V , Reset fulse signal is not generated.

DD

Figure 8-3. Timing Diagram for Power-On Reset Circuit

EXTERNAL RESET

An external reset occurs whenever the reset pin makes a rising edge signal, which takes place when the reset pin

switches to High level from Low level. Even though the chip has a built-in POR circuit, an external Resistor-

Capacitor circuit can do a reset while the power is on. An improvement in functions of the external POR circuit

depends on the quality of the external circuit to be added. The chip can also be operated without an additional

circuit to the reset pin. In that case, the reset pin should be connected to the V_DDlevel. In practice, the external

reset pin is connected to both system reset and back-up mode input. For further information on back-up mode,

please refer to the Power-down mode in the next page. To reset the system by using an external reset, the input

level of the reset pin should be lower than VIL, and you should hold the low level long enough to pass the noise

filter, and by then the input level of reset pin should rise higher than VIH. A system reset pulse is generated by

the reset pulse generator, if the sequence above is carried out satisfactorily.

WATCH-DOG TIMER RESET

The KS88C0416/C0424 contain a watch-dog timer that can recover normal operation from malfunction. A watch-

dog timer generates a system reset signal if the BT-Basic Counter is not cleared by the program within a

specification. System reset helps return to the normal operation of a chip. For more information on the watch-dog

timer function, please refer to Chapter 10, "Basic Timer and Timer 0."

8-3

RESET and POWER-DOWN

KS88C0416/P0416/C0424/P0424

SYSTEM RESET OPERATION

System reset starts the oscillation circuit, synchronizes a chip operation with the CPU clock, and initializes the

internal CPU and peripheral modules. This procedure brings the KS88C0416/C0424 into the normal operating

status. To allow some time for the internal CPU clock oscillation to stabilize, the reset pulse generator must be

held to an active level for a minimum time interval after the power supply comes within tolerance. The minimum

reset operation time required for oscillation stabilization is 16 oscillation clocks. All system and peripheral control

registers are then reset to their default hardware values (see Table 8-1).

In summary, the following sequence of events occurs during a reset operation:

— All interrupts are disabled.

— The watchdog function (basic timer) is enabled.

— Ports 0, 1, 2, and 3 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.

— Peripheral control and data register settings are disabled and reset to their default hardware values (see

Table 8-1).

— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in the ROM

location 0100H (and 0101H) is fetched and executed.

NOTE

To program the duration of the oscillation stabilization interval, you should make the appropriate settings

to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use

the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs),

you can disable it by writing "1010B" to the upper nibble of BTCON. But it is recommended to use it to

prevent a chip malfunction.

8-4

KS88C0416/P0416/C0424/P0424

HARDWARE RESET VALUES

RESET and POWER-DOWN

Table 8-1 lists the reset values for CPU and system registers, peripheral control registers, and peripheral data

registers after a reset operation. The following notations are used to represent reset values:

— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

— An "x" means that the bit value is undefined after a reset.

— A dash ("–") means that the bit is either "not used" or "not mapped" (but a "0" is read from the bit position)

Table 8-1. Set 1 Register Values After Reset

Register Name

Mnemonic

Address

Dec

Bit Values After Reset

Hex

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

7

0

1

0

–

x

1

6

0

1

0

–

x

1

5

0

1

0

–

x

0

4

0

1

0

x

0

3

0

1

0

x

0

1

2

0

1

0

x

–

-

1

0

1

0

-

0

1

0

-

Timer 0 counter (read-only)

Timer 0 data register

Timer 0 control register

Basic timer control register

Clock control register

System flags register

Register pointer 0

T0CNT

T0DATA

T0CON

BTCON

CLKCON

FLAGS

RP0

208

209

210

211

212

213

214

215

Register pointer 1

RP1

-

Location D8H (SPH) is not mapped.

Stack pointer (low byte)

Instruction pointer (high byte)

Instruction pointer (low byte)

Interrupt request register (read-only)

Interrupt mask register

System mode register

Register page pointer

Port 0 data register

SPL

IPH

IPL

IRQ

IMR

SYM

PP

217

218

219

220

221

222

223

224

225

226

227

D9H

DAH

DBH

DCH

DDH

DEH

DFH

E0H

E1H

E2H

E3H

x

0

x

0

-

x

0

x

-

x

0

x

-

x

0

x

0

-

x

0

–

x

0

-

x

0

–

x

0

-

x

0

x

0

x

0

x

0

-

0

P0

Port 1 data register

P1

Port 2 data register

P2

Port 3 data register

P3

Location E4H is not mapped.

Port 2 interrupt enable register

Port 2 interrupt pending register

Port 0 pull-up enable register

Port 0 control register (high byte)

Port 0 control register (low byte)

P2INT

P2PND

229

230

231

232

233

E5H

E6H

E7H

E8H

E9H

0

-

P0PUR

0

P0CONH

P0CONL

8-5

RESET and POWER-DOWN

KS88C0416/P0416/C0424/P0424

Table 8-1. Set 1 Register Values After Reset (Continued)

Register Name

Mnemonic

Address

Dec

Bit Values After Reset

Hex

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

F2H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

7

0

–

0

1

0

1

0

6

0

–

0

1

0

1

0

5

0

1

0

1

0

4

0

1

0

1

0

3

0

1

0

1

0

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Port 1 control register (high byte)

Port 1 control register (low byte)

Port 1 pull-up enable register

Port 2 pull-up enable register

Port 2 control register (high byte)

Port 2 control register (low byte)

Port 3 control register

P1CONH

P1CONL

P1PUR

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

P2PUR

P2CONH

P2CONL

P3CON

Port 0 interrupt enable register

Port 0 interrupt pending register

Counter A control register

P0INT

P0PND

CACON

CADATAH

CADATAL

T1CNTH

T1CNTL

T1DATAH

T1DATAL

T1CON

Counter A data register (high byte)

Counter A data register (low byte)

Timer 1 counter register (high byte)

Timer 1 counter register (low byte)

Timer 1 data register (high byte)

Timer 1 data register (low byte)

Timer 1 control register

Stop control register

STOPCON 251

Locations FCH is not mapped.

Basic timer counter

BTCNT

EMT

253

254

255

FDH

FEH

FFH

x

0

x

1

x

1

x

1

x

1

x

1

x

0

x

–

x

External memory timing register

Interrupt priority register

IPR

NOTES:

1. Although the SYM register is not used for the KS88C0416/C0424, SYM.5 should always be “0”. If you accidentally

write a "1" to this bit during the normal operation, a system malfunction may occur.

2. Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are read/write

addressable.

3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.

4. Interrupt pending flags are noted by shaded table cells.

8-6

KS88C0416/P0416/C0424/P0424

RESET and POWER-DOWN

POWER-DOWN MODES

BACK-UP MODE

An external reset pin can be used as both a Back-up mode input and an external reset input. When the external

reset pin is at a low state, the chip is changed to back-up mode, in which the CPU and peripheral operations are

stopped due to the oscillation stop. In back-up mode, the chip cannot released the stop state by any interrupt.

The stop mode can be released by a reset operation which is done by pulling-up the reset pin to V_DDpower

supply level - or VIH, a reset pin input high level. when reset pin is pulled below low input voltage level (VIL), the

chip returns to stop mode or back-up mode. The chip will remain in back-up mode as long as logic zero remains

on the reset pin. When logic one is applied to the reset pin, a reset operation occurs and releases back-up mode.

This feature is very useful in remote control applications with a low voltage detect circuit connected to the reset

pin. When the voltage detect circuit senses low power supply voltage, it pulls down the reset pin and activates

back-up mode to minimize the current consumption. The chip can keep the internal data for a long time. When a

new power supply is employed, the chip starts from the reset status.

RESET/

NOISE

FILTER

BACK-UP

MODE

BACK-UP MODE

Rising Edge

Detector

Reset Pulse

Generator

RESET

SYSTEM

Figure 8-4. Block Diagram for Back-Up Mode

8-7

RESET and POWER-DOWN

KS88C0416/P0416/C0424/P0424

Voltage (V)

V

DD

V

DD

Reset Input

V

= 0.85 V

)

IH

DD

(rising edge detect)

Low Voltage Detect

(Ex: 1.8 V)

Back-Up Mode

(Reset < 0.4 V

)

DD

Reset Pulse Width

(16 clock)

Reset Pulse

Time

If reset pin is under 0.4 V , back-up mode is activated.

DD

If reset pin is changed to over 0.85 V from a low level. reset pulse is generated.

DD

Figure 8-5. Timing Diagram for Back-Up Mode and External Reset

STOP MODE

Stop mode is invoked by the stop control register (STOPCON) setting and the STOP instruction. Another Stop

source is the back-up mode invoked by forcing the reset pin the Low state. In Stop mode, the operation of the

CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the current supply is reduced to

less than 1 µA. All system functions stop when the clock "freezes," but the data stored in the internal register file

is retained. Stop mode can be released in one of the following two ways: by a system reset or by an external

interrupt.

After releasing from STOP mode, the value of the stop control register (STOPCON) is cleared automatically.

8-8

KS88C0416/P0416/C0424/P0424

RESET and POWER-DOWN

+

PROGRAMMING TIP — To enter STOP mode.

This example shows how to enter the stop mode.

ORG

•

0000H

; Reset address

•

JP

T,START

ENTER_STOP:

LD

STOPCON,#0A5H

STOP

NOP

RET

ORG

JP

0100H-3

T,START

ORG

0100H

; Reset address

START

MAIN

LD

BTCON,#03

; Clear basic timer counter.

•

NOP

•

CALL

•

ENTER_STOP

; Enter the STOP mode

•

LD

JP

BTCON,#02H

T,MAIN

; Clear basic timer counter.

•

8-9

RESET and POWER-DOWN

KS88C0416/P0416/C0424/P0424

Using RESET to Release Stop Mode

Stop mode is released when the reset signal goes active (Low level to High level): all system and peripheral

control registers are reset to their default hardware values and the contents of all data registers are retained.

When the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization

routine by fetching the program instruction stored in the ROM location 0100H.

Using an External Interrupt to Release Stop Mode

External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. For the

KS88C0416/C0424 microcontroller, we recommend using the INT0–INT8 interrupt at P0 and P2.0–P2.3.

Please note the following conditions for Stop mode release:

— If you release Stop mode using an external interrupt, the current values in the system and peripheral control

registers are unchanged.

— If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation

stabilization interval. To do this, you must make the appropriate control and clock settings before entering

Stop mode.

— If you use an interrupt to release Stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains

unchanged and the currently selected clock value is used.

The external interrupt is serviced when a Stop mode release occurs. Following the IRET from the service routine,

the instruction immediately following the one that initiated Stop mode is executed.

Using a SED and R (Stop Error Detect and Recovery) to Release Stop Mode

The Stop Error Detect and Recovery circuit can be used to release stop mode and prevent abnormal status -

stop mode that can occur by battery bouncing. It executes two functions in relation to the internal logic of P0 and

P1:

Releasing from stop mode

The moment the level of the input port (P0 or P1) is switched, the chip is released from stop mode even though

an external interrupt is disabled.

Preventing the chip from entering stop mode in abnormal status

This circuit detects abnormal status by checking the port (P0 and P1) status. If the chip is in abnormal status, the

circuit prevents the chip from entering stop mode.

NOTE

Do not use stop mode if you are using an external clock source X_INinput must be cleared internally for

V_SSto reduce the current leakage.

8-10

KS88C0416/P0416/C0424/P0424

IDLE MODE

RESET and POWER-DOWN

Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some

peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all

but the following peripherals, which remain active:

— Interrupt logic

— Timer 0

— Timer 1

— Counter A

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.

Idle Mode Release

You can release Idle mode in one of the following two ways:

1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents

of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the

hardware reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a

reset is the only way you can release Idle mode.

2. Activate any enabled interrupt, internal or external. When you use an interrupt to release Idle mode, the 2-bit

CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The

interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction

immediately following the one which initiated Idle mode is executed.

NOTE

Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode. To

release Idle mode, you can use either an external interrupt or an internally-generated interrupt.

8-11

RESET and POWER-DOWN

KS88C0416/P0416/C0424/P0424

RECOMMENDATION FOR UNUSUED PINS

To reduce overall power consumption, please configure unused pins according to the guideline description Table

8-2.

Table 8-2. Guideline for Unused Pins to Reduced Power Consumption

Pin Name

Recommend

Set Input mode

Example

P0CONH ¬ # 00H or 01H

P0CONL ¬ # 00H or 01H

P0PUR ¬ # 0FFH

P1CONH ¬ # 55H

Port 0

Enable Pull-up Resister

No Connection for Pins

Port 1

Port 2

Port 3

TEST

Set Open-Drain Output mode

Set P1 Data Register to #00H.

Disable Pull-up Resister

No Connection for Pins

P1CONL ¬ # 55H

P1

¬ # 00H

P1PUR ¬ # 00H

P2CONH ¬ # 0AAH

P2CONL ¬ # 0AAH

Set Push-pull Output mode

Set P2 Data Register to #00H.

Disable Pull-up resister

P2

¬ # 00H

No Connection for Pins

P2PUR ¬ # 00H

P3CON ¬ # 21H

Set Push-pull Output mode

Disable Pull-up Resister

Set P3 Data Register to #00H.

No Connection for Pins

P3

¬ # 00H

Connect to V_SS

.

–

8-12

KS88C0416/P0416/C0424/P0424

RESET and POWER-DOWN

SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS

For further understanding, please see the description Table 8-3 below.

Table 8-3. Summary of each mode

Item/Mode

Back-up

Reset status

Stop

STOPCON ¬ # A5H

Approach

Condition

External reset pin is in low

level

External reset pin is on rising

edge. POR circuit is activated.

WDT overflow signal is

activated.

STOP

( LD STOPCON,#0A5H STOP)

PORT

Status

All ports are floating status. All All ports are input mode, and All ports are keep in the previous

ports enter input mode but are not blocked.

status.

blocked. All port data registers All port data registers set to

Input port data is not changed.

set to #00H. Disable all pull-

up resistor

#00H. Disable all pull-up

resistor

Control

All control registers and

–

Register

system registers are initialized system registers are initialized

as Table 8-1

as Table 8-1.

Releasing

Condition

External reset pin transition

(Rising edge)

After passing an oscillation

warming-up time

Interrupt, or reset SED and R

circuit.

Others

There is no current

consumption in the chip.

There can be input leakage

current in chip.

It depends on control program

8-13

RESET and POWER-DOWN

KS88C0416/P0416/C0424/P0424

NOTES

8-14

KS88C0416/P0416/C0424/P0424

I/O PORTS

9

I/O PORTS

OVERVIEW

The KS88C0416/C0424 microcontrollers have four bit-programmable I/O ports, P0–P3. Three ports, P0–P2, are

8-bit ports and P3 is a 2-bit port. This gives a total of 26 I/O pins. Each port is bit-programmable and can be

flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or

reading port registers. No special I/O instructions are required.

For IR universal remote controller applications, ports 0, 1, and 2 are usually configured to the keyboard matrix

and port 3 is used to transmit the remote controller carrier signal or to indicate operating status by turning on a

LED.

Table 9-1 gives you a general overview of the KS88C0416/C0424 I/O port functions.

Table 9-1. KS88C0416/C0424 Port Configuration Overview

Port

Configuration Options

0

8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling

edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt

enable/disable (P0INT) and pending control (P0PND); Pull-up resistors can be assigned to

individual P0 pins using P0PUR register settings. This port is dedicated for key input in remote

controller application.

1

2

8-bit general-purpose I/O port; Input, open-drain output, or push-pull output. Pull-up resistors

can be assigned to individual P1 pins using P1PUR register settings. This port is dedicated for

key output in remote controller application.

8-bit general-purpose I/O port; Input, open-drain output, or push-pull output. The low-byte P2

pins, P2.3–P2.0, can be used as external interrupt inputs and have noise filters. The P2INT

register (low-byte) is used to enable/disable interrupts and P2PND bits can be polled by

software for interrupt pending control. Pull-up resistors can be assigned to individual P2 pins

using P2PUR register settings.

3

2-bit I/O port; P3.0 and P3.1 are configured together using a 4-bit data value to support input

functions (Input mode, with or without pull-up, for T0CK, T0CAP, or T1CAP) or output functions

(push-pull or open-drain output mode, or open-drain with pull-up, for REM and T0PWM). Port 3

pins have high current drive capability to support LED applications. The port 3 data register

contains three status bits: two for P3.0 and P3.1 and one for carrier signal on/off status.

9-1

I/O PORTS

KS88C0416/P0416/C0424/P0424

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all four KS88C0416/C0424 I/O port data registers.

Data registers for ports 0, 1, and 2 have the general format shown in Figure 9-1.

NOTE

The data register for port 3, P3, contains two bits for P3.0 and P3.1, and an additional status bit for

carrier signal on/off.

Table 9-2. Port Data Register Summary

Register Name

Port 0 data register

Port 1 data register

Port 2 data register

Port 3 data register

Mnemonic

Decimal

224

Hex

E0H

E1H

E2H

E3H

Location

Set 1

R/W

P0

P1

P2

P3

225

Set 1

226

Set 1

227

Set 1

Because port 3 is a 2-bit I/O port, the port 3 data register only contains values for P3.0 and P3.1. The P3 register

also contains values for P3.0 and P3.1. The P3 register also contains a special carrier on/off bit (P3.5). See the

port 3 description for details. All other KS88C0416/C0424 I/O ports are 8-bit.

I/O Port Data Register Format (n = 0-3)

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pn.0

Pn.1

Pn.2

Pn.3

Pn.4

Pn.5

Pn.6

Pn.7

Because port 3 is a 2-bit I/O port, the port 3 data register

only contains values for P3.0 and P3.1.

NOTE:

The P3 register also contains a special carrier on/off bit (P3.5).

See the port 3 description for details. All other KS88C0416/C0424

I/O ports are 8-bit.

Figure 9-1. KS88C0416/C0424 I/O Port Data Register Format

9-2

KS88C0416/P0416/C0424/P0424

I/O PORTS

PULL-UP RESISTOR ENABLE REGISTERS

You can assign pull-up resistors to the pin circuits of individual pins in ports 0, 1, and 2. To do this, you should

make the appropriate settings to the corresponding pull-up resistor enable registers — P0PUR, P1PUR, and

P2PUR. These registers are located in set 1 at locations E7H, ECH, and EDH, respectively, and are read/write

accessible using Register addressing mode.

You can assign a pull-up to the port 3 pins, P3.0 and P3.1, in Input mode (T0CK/T0CAP/T1CAP) or in output

mode (REM/T0_PWM) using basic port configuration setting in the P3CON register.

Pull-Up Resistor Enable Registers (PnPUR, where n = 0–2)

Set 1, (E7H, ECH, EDH), R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Pn.0

Pn.1

Pn.2

Pn.3

Pn.4

Pn.5

Pn.6

Pull-up resistor enable bit:

Pn.7

0 = Disable pull-up resistor

1 = Enable pull-up resistor

: Pull-up resistors can be assigned to the port 3 pins,

P3.0 and P3.1, by making the appropriate setting to

the port 3 control register, P3CON.

NOTE

Figure 9-2. Pull-Up Resistor Enable Registers (Ports 0, 1, and 2 only)

9-3

I/O PORTS

PORT 0

KS88C0416/P0416/C0424/P0424

Port 0 is a general-purpose, 8-bit I/O port. It is bit-programmable. Port 0 pins are accessed directly by read/write

operations to the port 0 data register, P0 (set 1, E0H). The P0 pin circuits support pull-up resistor assignment

using P0PUR register settings and all pins have noise filters for external interrupt inputs.

Two 8-bit control registers are used to configure port 0 pins: P0CONH (set 1, E8H) for the upper nibble pins,

P0.7–P0.4, and P0CONL (set 1, E9H) for lower nibble pins, P0.3–P0.0. Each control register byte contains four

bit-pairs and each bit-pair configures one pin (see Figures 9-3 and 9-4). A hardware reset clears all P0 control

and data registers to "00H".

A separate register, the port 0 interrupt control register, P0INT (set 1, F1H), is used to enable and disable

external interrupt input. You can poll the port 0 interrupt pending register, P0PND, to detect and clear pending

conditions for these interrupts.

The lower-nibble pins, P0.3–P0.0, are used for INT3–INT0 input (IRQ6), respectively. The upper nibble pins,

P0.7–P0.4, are all used for INT4 input (IRQ7). Interrupts that are detected at any of these four pins are processed

using the same vector address (E8H).

PORT 0 CONTROL REGISTER, HITGH BYTE (P0CONH)

E8H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P0.4/INT4

P0.5/INT4

P0.6/INT4

P0.7/INT4

P0CONH Pin Configuration Settings:

00 Input mode; interrupt on falling edges

01 Input mode; interrupt on rising and falling edges

10 Push-pull output mode

11 Input mode; interrupt on rising edges

Figure 9-3. Port 0 High-Byte Control Register (P0CONH)

9-4

KS88C0416/P0416/C0424/P0424

I/O PORTS

PORT 0 CONTROL REGISTER, LOW BYTE (P0CONL)

E9H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3/INT3

P0CONL Pin Configuration Settings:

00 Input mode; interrupt on falling edges

01 Input mode; interrupt on rising and falling edges

10 Push-pull output mode

11 Input mode; interrupt on rising edges

Figure 9-4. Port 0 Low-Byte Control Register (P0CONL)

PORT 0 INTERRUPT ENABLE REGISTER (P0INT)

The port 0 interrupt control register, P0INT, is used to enable and disable external interrupt input at individual P0

pins (see Figure 9-5). To enable a specific external interrupt, you should set its P0INT.n bit to “1”. You must also

be sure to make the correct settings in the corresponding port 0 control register (P0CONH, P0CONL).

PORT 0 INTERRUPT PENDING REGISTER (P0PND)

The port 0 interrupt pending register, P0PND, contains pending bits (flags) for each port 0 interrupt (see Figure

9-6). When a P0 external interrupt is acknowledged by the CPU, the service routine must clear the pending

condition by writing a “0” to the appropriate pending flag in the P0PND register (Writing a “1” to the pending bit

has no effect).

NOTE

A hardware reset clears the P0INT and P0PND registers to "00H". For this reason, the application

program’s initialization routine must enable the required external interrupts for port 0, and for the other

I/O ports.

9-5

I/O PORTS

KS88C0416/P0416/C0424/P0424

PORT 0 INTERRUPT REGISTER (P0INT)

F1H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3/INT3

P0.4/INT4

P0.5/INT4

P0.6/INT4

P0.7/INT4

Port 0 Interrupt Enable Bits:

0 = Disable interrupt

1 = Enable interrupt

Figure 9-5. Port 0 External Interrupt Control Register (P0INT)

PORT 0 INTERRUPT PENDING REGISTER (P0PND)

F2H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P0.0/INT0

P0.1/INT1

P0.2/INT2

P0.3/INT3

P0.4/INT4

P0.5/INT4

P0.6/INT4

P0.7/INT4

Port 0 Interrupt Pending Bits:

0

1

Interrupt not pending

Clear P0.n pending condition (when write)

P0.n interrupt is pending

No effect (when write)

Figure 9-6. Port 0 External Interrupt Pending Register (P0PND)

9-6

KS88C0416/P0416/C0424/P0424

PORT 1

I/O PORTS

Port 1 is a bit-programmable 8-bit I/O port. Port 1 pins are accessed directly by read/write operations to the port 1

data register, P1 (set 1, E1H).

To configure port 1, the initialization routine writes the appropriate values to the two port 1 control registers:

P1CONH (set 1, EAH) for the upper nibble pins, P1.7–P1.4, and P1CONL (set 1, EBH) for the lower nibble pins,

P1.3–P1.0. Each 8-bit control register contains four bit-pairs and each 2-bit value configures one port pin (see

Figures 9-7 and 9-8).

After a hardware reset, the port 1 control registers are cleared to "00H", configuring port 0 initially to Input mode.

To assign pull-up resistors to P1 pins, you should make the appropriate settings to the port 1 pull-up resistor

enable register, P1PUR.

PORT 1 CONTROL REGISTER, HITGH BYTE (P1CONH)

EAH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P1.4

P1.5

P1.6

P1.7

P1CONH Pin Configuration Settings:

00 Input mode

01 Open-drain output mode

10 Push-pull output mode

11 Invalid setting

Figure 9-7. Port 1 High-Byte Control Register (P1CONH)

9-7

I/O PORTS

KS88C0416/P0416/C0424/P0424

PORT 1 CONTROL REGISTER, LOW BYTE (P1CONL)

EBH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P1.0

P1.1

P1.2

P1.3

P1CONH Pin Configuration Settings:

00 Input mode

01 Open-drain output mode

10 Push-pull output mode

11 Invalid setting

Figure 9-8. Port 1 Low-Byte Control Register (P1CONL)

9-8

KS88C0416/P0416/C0424/P0424

PORT 2

I/O PORTS

Port 2 is a bit-programmable 8-bit I/O port. Port 2 pins are accessed directly by read/write operations to the port 2

data register, P2 (set 1, E2H). You can configure port 2 pins individually to Input mode, open-drain output mode,

or push-pull output mode.

The low-byte P2 pins, P2.3–P2.0, can also be used as external interrupt inputs and have noise filters. P2INT

register lower nibble settings are used to enable/disable the INT8–INT5 interrupts, and the corresponding lower

nibble P2PND bits can be polled by software for interrupt pending control.

To configure port 2, the initialization routine writes the appropriate values to the two port 2 control registers:

P2CONH (set 1, EEH) for the upper nibble pins, P2.7–P2.4, and P2CONL (set 1, EFH) for the lower nibble pins,

P2.3–P2.0. Each 8-bit control register contains four bit-pairs and each 2-bit value configures one port pin (see

Figures 9-9 and 9-10).

To assign pull-up resistors to P2 pins, you should make the appropriate settings to the port 2 pull-up resistor

enable register, P2PUR.

After a hardware reset, the P2CONH and P2CONL registers are cleared to "00H". This initially configures all port

2 pins to input mode.

PORT 2 CONTROL REGISTER, HITGH BYTE (P2CONH)

EEH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.4

P2.5

P2.6

P2.7

P2CONH Pin Configuration Settings:

00

01

10

11

Input mode

Open-drain output mode

Push-pull output mode

Invalid setting

Figure 9-9. Port 2 High-Byte Control Register (P2CONH)

9-9

I/O PORTS

KS88C0416/P0416/C0424/P0424

PORT 2 CONTROL REGISTER, LOW BYTE (P2CONL)

EFH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.0/INT5

P2.1/INT6

P2.2/INT7

P2.3/INT8

P2CONL Pin Configuration Settings:

00

01

10

11

Input mode; interrupt on falling edge

Open-drain output mode

Push-pull output mode

Input mode; interrupt on rising edge

Figure 9-10. Port 2 Low-Byte Control Register (P2CONL)

PORT 2 INTERRUPT REGISTER (P2INT)

E5H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.0/INT5

Not used for the KS88C0416/C0424

P2.1/INT6

P2.2/INT7

P2.3/INT8

Port 2 Interrupt Enable Bits:

0 = Disable interrupt

1 = Enable interrupt

Figure 9-11. Port 2 Interrupt Enable Register (P2INT)

9-10

KS88C0416/P0416/C0424/P0424

I/O PORTS

PORT 2 INTERRUPT PENDING REGISTER (P2PND)

E6H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

P2.0/INT5

Not used for the KS88C0416/C0424

Port 2 Interrupt Pending Bits:

P2.1/INT6

P2.2/INT7

P2.3/INT8

0

1

Interrupt not pending

Clear P2.n pending condition (when write)

P2.n interrupt is pending

No effect (when write)

Figure 9-12. Port 2 Interrupt Pending Register (P2PND)

PORT 3

Port 3 is a bit-programmable 2-bit I/O port. The port 3 pins, P3.0 and P3.1, are accessed directly by read/write

operations to the port 3 data register, P3 (set 1, E3H).

P3.0 and P3.1 are configured by writing 6-bit data value to the port 3 control register, P3CON. You can configure

these pins to support input functions (Input mode, with or without pull-up, for T0CK/T0CAP/T1CAP) or output

functions (push-pull or open-drain output mode, or open-drain with pull-up, for T0 and timer 0 PWM).

Port 3 pins have high current drive capability to support LED applications.

A reset operation clears P3CON to "00H", selecting Input mode (T0CK/T0CAP/T1CAP) as the initial port 3

function.

9-11

I/O PORTS

KS88C0416/P0416/C0424/P0424

PORT 3 CONTROL REGISTER (P3CON)

F0H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Configuration bits for pin P3.1

Configuration bits for pin P3.0

Alternative function enable bit:

0 = Normal I/O function (P3.0)

1 = T0PWM/T0CAP/T1CAP

Alternative function enable bit:

0 = Normal I/O function (P3.1)

1 = REM/T0CK

2/7 1/6 0/5

Port selection

0

1

0

1

x

0

1

0

1

Input mode (P3.1/T0CK, P3.0/T0CAP/T1CAP)

Input, pull-up mode (P3.1/T0CK, P3.0/T0CAP/T1CAP)

Output, push-pull mode (P3.1/REM, P3.0/T0PWM)

Output, open-drain mode (P3.1/REM, P3.0/T0PWM)

Output, open-drain, pull-up mode (P3.1/REM, P3.0/T0PWM)

(“x” means ‘don’t care’.)

Figure 9-13. Port 3 Control Register (P3CON)

PORT 3 DATA REGISTER (P3)

E3H, Set 1, R/W

MSB

.7

.5

.4

.3

.2

.1

.0

LSB

.6

Not used for the

KS88C0416/C0424

P3.0/T0_PWM/

T0CAP/T1CAP

Carrier on/off for

remote controller

P3.1/REM/TOCK

Not used for the

KS88C0416/C0424

Figure 9-14. Port 3 Data Register (P3)

9-12

KS88C0416/P0416/C0424/P0424

P3.0 AND P3.1 CIRCUITS

I/O PORTS

The circuit diagram for port 3 pins shown in Chapter 1, “Overview,” (Figure 1-6) is a simplified version and does

not show some details of these circuits which may be useful when designing specific applications using the

KS88C0416/C0424 microcontroller. For this reason, supplemental information about the P3.0 and P3.1 circuits is

provided below in Figures 9-15 and 9-16.

V

DD

PULL-UP RESISTOR

(Typical 21 K )

W

PULL-UP ENABLE

SELECT

V

DD

M

U

X

DATA

PORT 3.1 DATA

CAOF (CACON.0)

CARRIER ON/OFF (P3.5)

P3.1/REM/T0CK

OPEN-DRAIN

OUTPUT DISABLE

V

SS

P3.1 INPUT

T0CK

NOISE

FILTER

Figure 9-15. P3.1 Circuit Diagram (Supplemental Information)

9-13

I/O PORTS

KS88C0416/P0416/C0424/P0424

V

DD

PULL-UP

RESISTOR

(Typical 21

KW)

PULL-UP

ENABLE

P3CON.3

V

DD

M

U

X

PORT 3.0 DATA

T0_PWM

DATA

P3.0/T0CAP/

T1CAP/T0PWM

OPEN-DRAIN

OUTPUT

DISABLE

V

SS

P3.0 INPUT

T0CAP or

T1CAP

NOISE FILTER

Figure 9-16. P3.0 Circuit Diagram (Supplemental Information)

9-14

KS88C0416/P0416/C0424/P0424

BASIC TIMER and TIMER 0

10 BASIC TIMER and TIMER 0

OVERVIEW

The KS88C0416/C0424 has two default timers: an 8-bit basic timer and an 8-bit general-purpose timer/counter.

The 8-bit timer/counter is called timer 0.

Basic Timer (BT)

You can use the basic timer (BT) in two different ways:

— As a watchdog timer providing an automatic reset mechanism in the event of a system malfunction, or

— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.

The functional components of the basic timer block are:

— Clock frequency divider (f_OSCdivided by 4096, 1024, or 128) with multiplexer

— 8-bit basic timer counter, BTCNT (set 1, FDH, read-only)

— Basic timer control register, BTCON (set 1, D3H, read/write)

Timer 0

Timer 0 has three operating modes, one of which you select using the appropriate T0CON setting:

— Interval timer mode

— Capture input mode with a rising or falling edge trigger at the P3.0 pin

— PWM mode

Timer 0 has the following functional components:

— Clock frequency divider (f_OSCdivided by 4096, 256, or 8 ) with multiplexer

— External clock input pin (P3.1, T0CK)

— 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)

— I/O pins for capture input (P3.0) or match output

— Timer 0 overflow interrupt (IRQ1, vector FAH) and match/capture interrupt (IRQ1, vector FCH) generation

— Timer 0 control register, T0CON (set 1, D2H, read/write)

10-1

BASIC TIMER and TIMER 0

KS88C0416/P0416/C0424/P0424

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer

counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,

address D3H, and is read/write addressable using Register addressing mode.

A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of

f_OSC/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer

register control bits BTCON.7–BTCON.4. For improved reliability, we recommend using the Watch-dog timer

function in remote controllers and hand-held product applications.

BASIC TIMER CONTROL REGISTER (BTCON)

D3H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Divider clear bit for basic

timer and timer 0:

0 = No effect

Watchdog function enable bits:

1010B = Disable watchdog timer

Others = Enable watchdog timer

1 = Clear both dividers

Basic timer counter clear bit:

0 = No effect

1 = Clear BTCNT

Basic timer input clock selection bits:

00 = f

01 = f

10 = f

/4096

/1024

/128

OSC

11 = Invalid selection

Figure 10-1. Basic Timer Control Register (BTCON)

10-2

KS88C0416/P0416/C0424/P0424

BASIC TIMER and TIMER 0

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to

any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to

"00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by

the current CLKCON register setting), divided by 4096, as the BT clock.

Reset whenever a basic timer counter overflow occurs. During the normal operation, the application program

must prevent the overflow and the accompanying reset operation from occurring. To do this, the BTCNT value

must be cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation

will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal

operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken

by a BTCNT clear instruction. If a malfunction occurs, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when Stop

mode has been released by an external interrupt.

In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts

increasing at the rate of f_OSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).

When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate

the clock signal off to the CPU so that it can resume the normal operation.

In summary, the following events occur when Stop mode is released:

1. During the Stop mode, a power-on reset or an external interrupt occurs to trigger a Stop mode release and

oscillation starts.

2. If a power-on reset occurs, the basic timer counter increases at the rate of f_OSC/4096. If an external interrupt

is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.

3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.

4. When a BTCNT.3 overflow occurs, the normal CPU operation resumes.

TIMER 0 CONTROL REGISTER (T0CON)

You use the timer 0 control register, T0CON, to

— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)

— Select the timer 0 input clock frequency

— Clear the timer 0 counter, T0CNT

— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt

— Clear timer 0 match/capture interrupt pending conditions

10-3

BASIC TIMER and TIMER 0

KS88C0416/P0416/C0424/P0424

T0CON is located in set 1, at address D2H, and is read/write addressable using Register addressing mode.

A reset clears T0CON to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency

of f_OSC/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during the normal

operation by writing a "1" to T0CON.3.

The timer 0 overflow interrupt (T0OVF) is in the interrupt level IRQ0 and has the vector address FAH. When a

timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by

hardware.

To enable the timer 0 match/capture interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a

match/capture interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a

timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending

condition must be cleared by software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.

TIMER 0 CONTROL REGISTER (T0CON)

D2H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 0 input clock selection bits:

Timer 0 match/capture

00 = f

01 = f

10 = f

/4096

/256

/8

interrupt pending bit:

OSC

0 = No interrupt pending

0 = Clear pending bit (when write)

1 = Interrupt is pending

11 = External clock (P3.1/T0CK)

Timer 0 match/capture interrupt

enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 0 operating mode selection bits:

00 = Interval mode

01 = Capture mode (capture on rising edge,

counter running, OVF can occur)

10 = Capture mode (capture on falling

edge, counter running, OVF can occur)

11 = PWM mode (OVF interrupt can occur)

Timer 0 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

Timer 0 counter clear bit:

0 = No effect

1 = Clear the timer 0 counter (when write)

Figure 10-2. Timer 0 Control Register (T0CON)

10-4

KS88C0416/P0416/C0424/P0424

BASIC TIMER and TIMER 0

TIMER 0 FUNCTION DESCRIPTION

Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)

The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/

capture interrupt (T0INT). T0OVF is in the interrupt level IRQ0, vector FAH. T0INT also belongs to the interrupt

level IRQ0, but is assigned the separate vector address, FCH.

A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.

The T0INT pending condition must, however, be cleared by the application’s interrupt service routine by writing a

"0" to the T0CON.0 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the

T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH)

and clears the counter.

If, for example, you write the value "10H" to T0DATA and "0BH" to T0CON, the counter will increment until it

reaches "10H". At this point, the T0 interrupt request is generated, the counter value is reset, and counting

resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-3).

IRQ0 (INT)

INTERRUPT

ENABLE/DISABLE

(T0CON.1)

PENDING

(T0CON.0)

R (Clear)

CLK

COUNTER

Match

COMPARATOR

CTL

P3.0/T0OUT

BUFFER REGISTER

T0CON.5

T0CON.4

Match Signal

T0CON.3

DATA REGISTER

Figure 10-3. Simplified Timer 0 Function Diagram: Interval Timer Mode

10-5

BASIC TIMER and TIMER 0

KS88C0416/P0416/C0424/P0424

Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the

T0OUT pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value

written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter. Instead,

it runs continuously, overflowing at "FFH", and then continues incrementing from "00H".

Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in

PWM-type applications. Instead, the pulse at the T0OUT pin is held to Low level as long as the reference data

value is less than or equal to ( £ ) the counter value and then the pulse is held to High level for as long as the data

value is greater than ( > ) the counter value. One pulse width is equal to t_CLK´ 256 (see Figure 10-4).

IRQ0

(T0INT)

PND

T0CON.0

INTERRUPT

ENABLE/DISABLE

(T0CON.1)

CLK

COUNTER

IRQ0 (T0OVF)

CTL

P3.0/T0OUT

COMPARATOR

Match

High level when

data > counter;

Low level when

T0CON.5

T0CON.4

data counter

£

BUFFER REGISTER

DATA REGISTER

Match Signal

T0CON.3

T0OVF

:

Interrupts are usually not used when timer 0 is configured to operate in PWM mode.

NOTE

Figure 10-4. Simplified Timer 0 Function Diagram: PWM Mode

10-6

KS88C0416/P0416/C0424/P0424

Capture Mode

BASIC TIMER and TIMER 0

In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter

value into the T0 data register. You can select rising or falling edges to trigger this operation.

Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You can select the capture input

by setting the value of the timer 0 capture input selection bit in the port 3 control register, P3CON.3, (set 1, bank

0, F0H). When P3CON.3 is “1”, the T0CAP input is selected. When P3CON.3 is set to “0”, normal I/O port (P3.0)

is selected.

Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever

a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded

into the T0 data register.

By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency,

you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 10-5).

T0CON.2

CLK

COUNTER

IRQ0 (T0OVF)

IRQ0 (T0INT)

PENDING

(T0CON.0)

P3.0/T0CAP

INTERRUPT ENABLE /

DISABLE (T0CON.1)

DATA REGISTER

T0CON.5

T0CON.4

Figure 10-5. Simplified Timer 0 Function Diagram: Capture Mode

10-7

BASIC TIMER and TIMER 0

KS88C0416/P0416/C0424/P0424

RESET

Bit 1

or STOP

Bits 3, 2

Basic Timer Control Register

(Write “1010xxxxB” to disable.)

Data Bus

Clear

1/4096

RESET

1/1024

1/128

8-Bit Basic Counter

(Read-Only)

X

DIV

R

MUX

Bits 7, 6

MUX

OVF

IN

Bit 2

T0OVF

OVF

Bit 0

Data Bus

Bit 3

1/4096

R

Clear

1/256

1/8

DIV

8-Bit Up-Counter

(Read-Only)

R

(2)

Match

Bit 1

T0CON.0

P3.1

8-Bit Comparator

T0INT

PND

T0PWM

P3.0

Timer 0 Buffer Reg

Bits 5, 4

Match Signal

T0CLR

T0OVF

Timer 0 Data Register

(Read/Write)

Basic Timer Control Register

Timer 0 Control Register

Data Bus

NOTES:

1. In a power-on reset operation, the CPU is idle during the required oscillation

stabilization interval (until bit 4 of the basic timer counter overflows).

2. It is available only in interval mode.

Figure 10-6. Basic Timer and Timer 0 Block Diagram

10-8

KS88C0416/P0416/C0424/P0424

BASIC TIMER and TIMER 0

+

PROGRAMMING TIP — Configuring the Basic Timer

This example shows how to configure the basic timer to sample specifications:

ORG

0100H

RESET

DI

LD

CLR

; Disable all interrupts

; Disable the watchdog timer

; Non-divided clock

; Disable global and fast interrupts

; Stack pointer low byte ¬ "0"

; Stack area starts at 0FFH

BTCON,#0AAH

CLKCON,#18H

SYM

SPL

•

SRP

#0C0H

; Set register pointer ¬ 0C0H

EI

•

; Enable interrupts

•

MAIN

LD

BTCON,#52H

; Enable the watchdog timer

; Basic timer clock: f_OSC/4096

; Clear basic timer counter

NOP

•

JP

T,MAIN

•

10-9

BASIC TIMER and TIMER 0

KS88C0416/P0416/C0424/P0424

+

PROGRAMMING TIP — Programming Timer 0

This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and

determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:

— Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds

— Oscillation frequency is 6 MHz

— General register 60H (page 0) ¬ 60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0

interrupt

ORG

0FAH

; Timer 0 overflow interrupt

VECTOR

ORG

T0OVER

0FCH

; Timer 0 match/capture interrupt

VECTOR

ORG

T0INT

0100H

RESET

DI

; Disable all interrupts

LD

CLR

BTCON,#0AAH

CLKCON,#18H

SYM

; Disable the watchdog timer

; Select non-divided clock

; Disable global and fast interrupts

; Stack pointer low byte ¬ "0"

; Stack area starts at 0FFH

SPL

•

LD

T0DATA,#5DH

T0CON,#4AH

; Set timer interval to 4 milliseconds

; (6 MHz/256) ÷ (93 + 1) = 0.25 kHz (4 ms)

; Write "01001010B"

LD

; Input clock is f_OSC/256

; Interval timer mode

; Enable the timer 0 interrupt

; Disable the timer 0 overflow interrupt

SRP

EI

#0C0H

; Set register pointer ¬ 0C0H

; Enable interrupts

•

T0INT

PUSH

SRP0

INC

ADD

ADC

RP0

#60H

R0

R2,R0

R3,R2

R4,R0

; Save RP0 to stack

; RP0 ¬ 60H

; R0 ¬ R0 + 1

; R2 ¬ R2 + R0

; R3 ¬ R3 + R2 + Carry

; R4 ¬ R4 + R0 + Carry

(Continued on next page)

10-10

KS88C0416/P0416/C0424/P0424

BASIC TIMER and TIMER 0

+

PROGRAMMING TIP — Programming Timer 0 (Continued)

CP

R0,#32H

JR

BITS

; 50 ´ 4 = 200 ms

ULT,NO_200MS_SET

R1.2

; Bit setting (61.2H)

NO_200MS_SET:

LD

POP

T0CON,#42H

RP0

; Clear pending bit

; Restore register pointer 0 value

T0OVER

IRET

; Return from interrupt service routine

10-11

BASIC TIMER and TIMER 0

KS88C0416/P0416/C0424/P0424

NOTES

10-12

KS88C0416/P0416/C0424/P0424

TIMER 1

11 TIMER 1

OVERVIEW

The KS88C0416/C0424 microcontrollers have a 16-bit timer/counter called timer 1 (T1). For universal remote

controller applications, timer 1 can be used to generate the envelope pattern for the remote controller signal.

Timer 1 has the following components:

— One control register, T1CON (set 1, FAH, R/W)

— Two 8-bit counter registers, T1CNTH and T1CNTL (set 1, F6H and F7H, read-only)

— Two 8-bit reference data registers, T1DATAH and T1DATAL (set 1, F8H and F9H, R/W)

— A 16-bit comparator

You can select one of the following clock sources as the timer 1 clock:

— Oscillator frequency (f_OSC) divided by 4, 8, or 16

— Internal clock input from the counter A module (counter A flip/flop output)

You can use Timer 1 in three ways:

— As a normal free run counter, generating a timer 1 overflow interrupt (IRQ1, vector F4H) at programmed time

intervals.

— To generate a timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit timer 1 count value matches the 16-

bit value written to the reference data registers.

— To generate a timer 1 capture interrupt (IRQ1, vector F6H) when a triggering condition exists at the P3.0 pin

(You can select a rising edge, a falling edge, or both edges as the trigger).

In the KS88C0416/C0424 interrupt structure, the timer 1 overflow interrupt has higher priority than the timer 1

match or capture interrupt.

11-1

TIMER 1

KS88C0416/P0416/C0424/P0424

TIMER 1 OVERFLOW INTERRUPT

Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the

16-bit up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt is

generated each time the 16-bit up counter reaches "FFFFH". After the interrupt request is generated, the counter

value is automatically cleared to "00H" and up counting resumes. By writing a “1” to T1CON.3, you can clear/reset

the 16-bit counter value at any time during the program operation.

TIMER 1 CAPTURE INTERRUPT

Timer 1 can be used to generate a capture interrupt (IRQ1, vector F6H) whenever a triggering condition is

detected at the P3.0 pin. The T1CON.5 and T1CON.4 bit-pair setting is used to select the trigger condition for

capture mode operation: rising edges, falling edges, or both signal edges.

P3.0 is used as the input pin for both the timer 0 and timer 1 capture functions. To set P3.0 as the input pin for the

timer 1 capture functions, it should be set to schmitt trigger input mode and T0PWM/T0CAP/T1CAP mode by

setting P3CON to "00001000B" or "00001100B". To start the capture function of the timer 1, T1CON should be

set to capture mode and T1CAP_MAT interrupt enable by setting T1CON to "00011111B" or etc.

In capture mode, program software can poll the timer 1 match/capture interrupt pending bit, T1CON.0, to detect

when a timer 1 capture interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is

acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear

the interrupt pending condition by writing a “0” to T1CON.0.

T1CON.2

CLK

16-BIT UP COUNTER

IRQ1 (T1OVF)

IRQ1 (T1INT)

PENDING

(T1CON.0)

P3.0/T1CAP

INTERRUPT ENABLE /

DISABLE (T1CON.1)

TIMER 1 DATA

T1CON.5

T1CON.4

Figure 11-1. Simplified Timer 1 Function Diagram: Capture Mode

11-2

KS88C0416/P0416/C0424/P0424

TIMER 1 MATCH INTERRUPT

TIMER 1

Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value

matches the value that is written to the timer 1 reference data registers, T1DATAH and T1DATAL. When a match

condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and

up counting resumes from "00H".

In match mode, program software can poll the timer 1 match/capture interrupt pending bit, T1CON.0, to detect

when a timer 1 match interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is

acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear

the interrupt pending condition by writing a “0” to T1CON.0.

IRQ1 (T1INT)

PENDING

(T1CON.0)

INTERRUPT

ENABLE/DISABLE

(T1CON.2)

R (Clear)

Match

16-BIT UP COUNTER

(Read Only)

CLK

16-BIT COMPARATOR

CTL

P3.0/T1CAP

TIMER 1 Hihg/Low

BUFFER REGISTER

T1CON.5

T1CON.4

Match Signal

T1CON.3

TIMER 1 DATA Hihg/Low

BUFFER REGISTER

Figure 11-2. Simplified Timer 1 Function Diagram: Interval Timer Mode

11-3

TIMER 1

KS88C0416/P0416/C0424/P0424

T1CON.2

OVF

T1OVF

T1CON.7, .6

T1CON.3

Clear

CAOF (T-F/F)

f

/4

/8

OSC

16-Bit Up Counter

(Read-Only)

MUX

R

(note)

Match

f

/16

OSC

T1CON.1

M

U

X

16-Bit Comparator

T1INT

T1CON.0

T1CAP

P3.0

Timer 1 High/Low

Buffer Register

T1CON.5, .4

T1CON.3

Match Signal

T1OVF

Timer 1 Data

High/Low Register

Data Bus

Match signal is occured only in interval mode.

NOTE:

Figure 11-3. Timer 1 Block Diagram

11-4

KS88C0416/P0416/C0424/P0424

TIMER 1

TIMER 1 CONTROL REGISTER (T1CON)

The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains

control settings for the following T1 functions:

— Timer 1 input clock selection

— Timer 1 operating mode selection

— Timer 1 16-bit down counter clear

— Timer 1 overflow interrupt enable/disable

— Timer 1 match or capture interrupt enable/disable

— Timer 1 interrupt pending control (read for status, write to clear)

A reset operation clears T1CON to "00H", selects f_OSCdivided by 4 as the T1 clock, configures timer 1 as a

normal interval timer, and disables the timer 1 interrupts.

TIMER 1 CONTROL REGISTER (T1CON)

FAH, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Timer 1 input clock selection bits:

Timer 1 interrupt pending bit:

0 = No interrupt pending

0 = Clear pending bit (when write)

1 = Interrupt is pending

00 = f

01 = f

10 = f

/4

/8

/16

OSC

11 = Internal clock (T-F/F)

Timer 1 interrupt match

and capture enable bit:

0 = Disable interrupt

1 = Enable interrupt

Timer 1 operating mode selection bits:

00 = Interval mode

01 = Capture mode (capture on rising edge,

counter running, OVF can occur)

Timer 1 overflow interrupt enable bit:

0 = Disable overflow interrupt

1 = Enable overflow interrupt

10 = Capture mode (capture on falling edge,

counter running, OVF can occur)

11 = Capture mode (capture on rising and

falling edge, OVF interrupt can occur)

Timer 1 counter clear bit:

0 = No effect

1 = Clear the timer 1 counter (when write)

Figure 11-4. Timer 1 Control Register (T1CON)

11-5

TIMER 1

KS88C0416/P0416/C0424/P0424

TIMER 1 COUNTER HIGH-BYTE REGISTER (T1CNTH)

F6H, Set1, R

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value : 00H

TIMER 1 COUNTER LOW-BYTE REGISTER (T1CNTL)

F7H, Set1, R

.6

.5

.4

.3

.2

.1

.0

Reset Value : 00H

TIMER 1 DATA HIGH-BYTE REGISTER (T1DATAH)

F8H, Set1, R/W

.6

.5

.4

.3

.2

.1

.0

Reset Value : FFH

TIMER 1 DATA LOW-BYTE REGISTER (T1DATAL)

F9H, Set1, R/W

.6

.5

.4

.3

.2

.1

.0

Reset Value : FFH

Figure 11-5. Timer 1 Registers

11-6

KS88C0416/P0416/C0424/P0424

COUNTER A

12 COUNTER A

OVERVIEW

The KS88C0416/C0424 microcontrollers have an 8-bit counter called counter A. Counter A, which can be used to

generate the carrier frequency, has the following components (see Figure 12-1):

— Counter A control register, CACON

— 8-bit down counter with auto-reload function

— Two 8-bit reference data registers, CADATAH and CADATAL

Counter A has two functions:

— As a normal interval timer, it generates a counter A interrupt (IRQ4, vector ECH) at programmed time

intervals.

— Supplies a clock source to the 16-bit timer/counter module, timer 1, for generating the timer 1 overflow

interrupt.

12-1

COUNTER A

KS88C0416/P0416/C0424/P0424

CACON.6-.7

DIV 1

DIV 2

DIV 4

DIV 8

CACON.O

(CAOF)

CLK

8-BIT

DOWN COUNTER

To Other Block

(P3.1/REM)

MUX

REPEAT

CONTROL

CACON.3

MUX

IRQ4

(CAINT)

INTERRUPT

CONTROL

INT. GEN.

COUNTER A Data

Low Byte Register

CACON.2

CACON.4-.5

f

OSC

COUNTER A Data

High Byte Register

Data Bus

:

The value of the CADATAL register is loaded into the 8-bit counter when the operation of the

NOTE

counter A starts. If a borrow occurs in the counter, the value of the CADATAH register is loaded

into the 8-bit counter .

However, if the next borrow occurs, the value of the CADATAL register is loaded into the 8-bit counter.

Figure 12-1. Counter A Block Diagram

12-2

KS88C0416/P0416/C0424/P0424

COUNTER A

COUNTER A CONTROL REGISTER (CACON)

The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON

contains control settings for the following functions (see Figure 12-2):

— Counter A clock source selection

— Counter A interrupt enable/disable

— Counter A interrupt pending control (read for status, write to clear)

— Counter A interrupt time selection

COUNTER A CONTROL REGISTER (CACON)

F3H, Set 1, R/W

MSB

.7

.6

.5

.4

.3

.2

.1

.0

LSB

Counter A input clock selection bits:

Counter A output flip-flop control bit:

0 = T-FF is Low

1 = T-FF is High

00 = f

01 = f

10 = f

11 = f

OSC

/2

/4

/8

Counter A mode selection bit:

0 = One-shot mode

1 = Repeating mode

Counter A interrupt time selection bits:

00 = Elapsed time for Low data value

01 = Elapsed time for High data value

10 = Elapsed time for Low and High

data values

Counter A start/stop bit:

0 = Stop counter A

1 = Start counter A

11 = Invalid setting

Counter A interrupt enable bit:

0 = Disable interrupt

1 = Enable interrut

Figure 12-2. Counter A Control Register (CACON)

12-3

COUNTER A

KS88C0416/P0416/C0424/P0424

COUNTER A DATA HIGH-BYTE REGISTER

(CADATAH) F4H, Set1, R/W

.7

.6

.5

.4

.3

.2

.1

.0

MSB

LSB

Reset Value : FFh

COUNTER A DATA LOW-BYTE REGISTER

(CADATAL) F5H, Set1, R/W

.6

.5

.4

.3

.2

.1

.0

LSB

Reset Value : FFh

Figure 12-3. Counter A Registers

COUNTER A PULSE WIDTH CALCULATIONS

t_HIGH

t_LOW

To generate the repeated waveform above, which consists of low period time, t_LOW, and high period time, t_HIGH

.

When CAOF = 0,

t_LOW= (CADATAL + 2) x 1/Fx , 0H < CADATAL < 100H, where Fx = The selected clock.

t_HIGH= (CADATAH + 2) x 1/Fx , 0H < CADATAH < 100H, where Fx = The selected clock.

When CAOF = 1,

t_LOW= (CADATAH + 2) x 1/Fx , 0H < CADATAH < 100H, where Fx = The selected clock.

t_HIGH= (CADATAL + 2) x 1/Fx , 0H < CADATAL < 100H, where Fx = The selected clock.

To make t_LOW= 24 ms and t_HIGH= 15 us. f_OSC= 4 MHz, Fx = 4 MHz / 4 = 1 MHz

[Method 1] When CAOF = 0,

t_LOW= 24 ms = (CADATAL + 2) / Fx = (CADATAL + 2) x 1ms, CADATAL = 22.

t_HIGH= 15 ms = (CADATAH + 2) / Fx = (CADATAH + 2) x 1ms, CADATAH = 13.

[Method 2] When CAOF = 1,

t_HIGH= 15 ms = (CADATAL + 2) / Fx = (CADATAL + 2) x 1ms, CADATAL = 13.

t_LOW= 24 ms = (CADATAH + 2) / Fx = (CADATAH + 2) x 1ms, CADATAH = 22.

12-4

KS88C0416/P0416/C0424/P0424

COUNTER A

0H

COUNTER A

CLOCK

CAOF = ‘0’

CADATAL = 01-FFH

CADATAH = 00H

HIGH

LOW

CAOF = ‘0’

CADATAL = 00H

CADATAH = 01-FFH

CAOF = ‘0’

CADATAL = 00H

CADATAH = 00H

LOW

HIGH

CAOF = ‘1’

CADATAL = 00H

CADATAH = 00H

0H

100H

200H

COUNTER A

CLOCK

E0H

CAOF = ‘1’

CADATAL = DEH

CADATAH = 1EH

20H

CAOF = ‘0’

CADATAL = DEH

CADATAH = 1EH

CAOF = ‘1’

CADATAL = 7EH

CADATAH = 7EH

80H

CAOF = ‘0’

CADATAL = 7EH

CADATAH = 7EH

80H

Figure 12-4. Counter A Output Flip-Flop Waveforms in Repeat Mode

12-5

COUNTER A

KS88C0416/P0416/C0424/P0424

+

PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1

This example sets Counter A to repeat mode the oscillation frequency as the Counter A clock source, and

CADATAH and CADATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are:

8.795

s

m

17.59

s

m

37.9 kHz 1/3Duty

— Counter A is used in repeat mode

— Oscillation frequency is 4 MHz (0.25 ms)

— CADATAH = 8.795 ms / 0.25 ms = 35.18, CADATAL = 17.59 ms / 0.25 ms = 70.36

— Set P3.1 C-Mos push-pull output and CAOF mode.

ORG

0100H

; Reset address

START

DI

•

LD

CADATAL,#(70–2)

CADATAH,#(35–2)

; Set 17.5 ms

; Set 8.75 ms

;

LD

P3CON,#00110001B

; Set P3 to C-Mos push-pull output.

; Set P3.1 to REM output

;

LD

CACON,#00000110B

; Clock Source ¬ f_OSC

; Disable Counter A interrupt.

; Select repeat mode for Counter A.

; Start Counter A operation.

; Set Counter A Output Flip-flop (CAOF) high.

;

LD

P3,#20H

; Set P3.5 (Carrier On/Off) to high.

; This command generates 38 kHz, 1/3 duty pulse signal

; through P3.1

;

•

12-6

KS88C0416/P0416/C0424/P0424

COUNTER A

+

PROGRAMMING TIP — To generate a one pulse signal through P3.1

This example sets Counter A to one shot mode the oscillation frequency as the Counter A clock source, and

CADATAH and CADATAL to make a 40 ms width pulse. The program parameters are:

40

s

m

— Counter A is used in one shot mode

— Oscillation frequency is 4 MHz ( 1 clock = 0.25 ms)

— CADATAH = 40 ms / 0.25 ms = 160, CADATAL = 1

— Set P3.1 C-Mos push-pull output and CAOF mode.

ORG

DI

0100H

; Reset address

START

•

LD

CADATAH,# (160–2)

CADATAL,# 1

; Set 40 ms

; Set any value except 00H

;

LD

P3CON,#00110001B

; Set P3 to C-Mos push-pull output.

; Set P3.1 to REM output

;

LD

CACON,#00000001B

; Clock Source ¬ f_OSC

; Disable Counter A interrupt.

; Select one shot mode for Counter A.

; Stop Counter A operation.

; Set Counter A Output Flip-Flop (CAOF) high

; Set P3.5(Carrier On/Off) to high.

LD

P3,#20H

•

Pulse_out: LD

CACON,#00000101B

; Start Counter A operation

; to make the pulse at this point.

•

; After the intsruction is executed, 0.75 ms is required

; before the falling edge of the pulse starts.

12-7

COUNTER A

KS88C0416/P0416/C0424/P0424

NOTES

12-8

KS88C0416/P0416/C0424/P0424

ELECTRICAL DATA

13 ELECTRICAL DATA

OVERVIEW

In this section, the KS88C0416/C0424 electrical characteristics are presented in tables and graphs. The

information is arranged in the following order:

— Absolute maximum ratings

— D.C. electrical characteristics

— Data retention supply voltage in Stop mode

— Stop mode release timing when initiated by an external interrupt

— Stop mode release timing when initiated by a Reset

— I/O capacitance

— A.C. electrical characteristics

— Input timing for external interrupts (port 0, P2.3–P2.0)

— Input timing for RESET

— Oscillation characteristics

— Oscillation stabilization time

— Operating voltage range

13-1

ELECTRICAL DATA

KS88C0416/P0416/C0424/P0424

Table 13-1. Absolute Maximum Ratings

°

(T_A= 25 C)

Parameter

Supply voltage

Input voltage

Symbol

Conditions

Rating

Unit

V

V_DD

–

– 0.3 to + 6.5

V_IN

V_O

– 0.3 to V_DD+ 0.3

V

Output voltage

Output current High

All output pins

One I/O pin active

V

I_OH

– 18

mA

All I/O pins active

One I/O pin active

– 60

+ 30

I_OL

Output current Low

mA

Total pin current for ports 0, 1, and 2

+ 100

+ 40

Total pin current for port 3

–

T_A

°

C

Operating

– 40 to + 85

temperature

T_STG

°

C

Storage

–

– 65 to + 150

temperature

Table 13-2. D.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

f_OSC= 8 MHz

Min

Typ

Max

Unit

V_DD

Operating Voltage

2.2

–

5.5

V

(Instruction clock = 1.33 MHz)

f_OSC= 4 MHz

2.0

–

5.5

(Instruction clock = 0.67 MHz)

All input pins except V_IH2and V_IH3

V_IH1

V_IH2

V_IH3

V_IL1

V_IL2

V_IL3

V_OH1

0.8 V_DD

0.85 V_DD

V_DD– 0.3

0

V_DD

Input High voltage

Input Low voltage

V

RESET

X_IN

V_DD

All input pins except V_IL2and V_IL3

0.2 V_DD

0.4 V_DD

0.3

–

RESET

X_IN

V_DD= 2.4 V; I_OH= – 6 mA

V_DD– 0.7

Output High

voltage

–

°

Port 3.1 only; T_A= 25 C

V_OH2

V_DD= 2.4 V; I_OH= – 3 mA

°

Port 3.0 only; T_A= 25 C

13-2

KS88C0416/P0416/C0424/P0424

ELECTRICAL DATA

Table 13-2. D.C. Electrical Characteristics (Continued)

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

°

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_OH3

V_DD= 5 V; I_OH= – 3 mA

V_DD– 0.25

Output High

voltage

–

V

°

Port 2.7 only; T_A= 25 C

V_DD= 2 V; I_OH= – 1 mA

°

Port 2.7 only; T_A= 25 C

V_OH4

V_DD= 3.0 V; I_OH= – 1 mA

V_DD– 1

All output pins except P3 and P2.7

°

port; T_A= 25 C

V_OL1

V_OL2

V_OL3

I_LIH1

V_DD= 2.4 V; I_OL= 15 mA

Output Low

voltage

–

0.4

–

0.5

1

V

°

Port 3.1 only; T_A= 25 C

V_DD= 2.4 V; I_OL= 5 mA

°

Port 3.0 only; T_A= 25 C

I_OL= 1 mA

°

Port 0, 1, and 2; T_A= 25 C

V_IN= V_DD

Input High

–

1

µA

leakage current

All input pins except X_INand X_OUT

I_LIH2

I_LIL1

V_IN= V_DD, X_IN, and X_OUT

20

V_IN= 0 V

Input Low

– 1

leakage current

All input pins except X_IN, X_OUT, and

RESET

I_LIL2

V_IN= 0 V

X_INand X_OUT

– 20

I_LOH

I_LOL

R_L1

V_OUT= V_DD

Output High

leakage current

1

All output pins

V_OUT= 0 V

Output Low

leakage current

– 1

143

All output pins

V_IN= 0 V; V_DD= 2.0 V

Pull-up resistors

65

15

95

21

KW

°

T_A= 25 C; Ports 0–3

V_DD= 5.5 V

32

13-3

ELECTRICAL DATA

KS88C0416/P0416/C0424/P0424

Table 13-2. D.C. Electrical Characteristics (Concluded)

°

(T_A= – 40 C to + 85 C, V_DD= 2 V to 5.5 V)

Parameter

Symbol

Conditions

Operating mode

Min

Typ

Max

Unit

I_DD1

Supply current

–

6

11

mA

V_DD= 5 V ± 10%

(note)

8 MHz crystal

4 MHz crystal

4.5

1.8

9

I_DD2

Idle mode

3.5

V_DD= 5 V ± 10%

8 MHz crystal

4 MHz crystal

1.6

0.3

3

I_DD3

Stop mode

µA

V_DD= 5 V ± 10%

V_DD= 3.6 V

0.1

1

NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current

loads.

Table 13-3. Data Retention Supply Voltage in Stop Mode

°

(T_A= – 40 C to + 85 C)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

V_DDDR

Data retention supply

voltage

–

1.0

–

5.5

V

I_DDDR

V_DDDR= 1.0 V

Stop mode

Data retention supply

current

–

1

µA

13-4

KS88C0416/P0416/C0424/P0424

ELECTRICAL DATA

IDLE MODE

(Basic Timer active)

NORMAL

OPERATING

MODE

STOP MODE

DATA RETENTION MODE

V

DD

V

DDDR

EXECUTION OF

STOP INSTRUCTION

EXT

INT

0.8 V

DD

0.2 V

DD

t

WAIT

Figure 13-1. Stop Mode Release Timing When Initiated by an External Interrupt

OSCILLATION

RESET

OCCURS

STABILIZATION

TIME

STOP MODE

NORMAL

OPERATING

MODE

DATA RETENTION MODE

V

DD

V

DDDR

EXECUTION OF

STOP INSTRUCTION

RESET

t

is the same as 4096 x 16 x 1/f

.

OSC

NOTE:

WAIT

Figure 13-2. Stop Mode Release Timing When Initiated by a Reset

13-5

ELECTRICAL DATA

KS88C0416/P0416/C0424/P0424

Table 13-4. Input/Output Capacitance

°

(T_A= – 40 C to + 85 C, V_DD= 0 V)

Parameter

Input

capacitance

Symbol

Conditions

Min

Typ

Max

Unit

C_IN

f = 1 MHz; unmeasured pins

are connected to V_SS

–

10

pF

C_OUT

C_IO

Output

capacitance

I/O capacitance

Table 13-5. A.C. Electrical Characteristics

°

(T_A= – 40 C to + 85 C)

Parameter

Symbol

t_INTH

t_INTL

Conditions

Min

Typ

Max

Unit

Interrupt input,

High, Low width

P0.0–P0.7, P2.3–P2.0

_DD= 5 V

200

300

–

ns

,

V

t_RSL

RESET input Low

width

Input

1000

–

V

_DD= 5 V

t

INTH

INTL

0.8 V

DD

0.2 V

DD

:

The unit t

means one CPU clock period.

CPU

NOTE

Figure 13-3. Input Timing for External Interrupts (Port 0, P2.3–P2.0)

13-6

KS88C0416/P0416/C0424/P0424

ELECTRICAL DATA

RESET

OCCRURRS

OSCILLATION

STABILIZATION

TIME

NORMAL

OPERATING

MODE

NORMAL

OPERATING

MODE

Back-Up Mode (STOP MODE)

V

DD

RESET

t

WAIT

t

is the same as 4096 x 16 x 1/f

.

OSC

NOTE:

WAIT

Figure 13-4. Input Timing for RESET

Table 13-6. Oscillation Characteristics

°

(T_A= – 40 C + 85 C)

Oscillator

Clock Circuit

Conditions

Min

Typ

Max

Unit

C1

Crystal

CPU clock oscillation

frequency

1

–

8

MHz

X

IN

X

OUT

C2

C1

Ceramic

CPU clock oscillation

frequency

1

–

8

MHz

X

IN

X

OUT

C2

X_INinput frequency

External clock

X

IN

EXTERNAL

CLOCK

OPEN PIN

X

OUT

13-7

ELECTRICAL DATA

KS88C0416/P0416/C0424/P0424

Table 13-7. Oscillation Stabilization Time

°

(T_A= – 40 C + 85 C, V_DD= 4.5 V to 5.5 V)

Oscillator

Test Condition

Min

Typ

Max

Unit

f_OSC> 400 kHz

Main crystal

–

20

ms

Oscillation stabilization occurs when V_DDis equal

to the minimum oscillator voltage range.

X_INinput High and Low width (t_XH, t_XL)

Main ceramic

–

10

ms

External clock

(main system)

25

–

500

–

ns

(1)

t_WAIT

2¹⁶/f_OSC

Oscillator

stabilization wait

time

ms

when released by a reset

(2)

–

ms

t_WAIT

when released by an interrupt

NOTES:

1.

f

is the oscillator frequency.

OSC

2. The duration of the oscillation stabilization time (t

in the basic timer control register, BTCON.

) when it is released by an interrupt is determined by the setting

WAIT

13-8

KS88C0416/P0416/C0424/P0424

ELECTRICAL DATA

f

OSC

Instruction

Clock

(Main oscillation

frequency)

1.33 MHz

8 MHz

6 MHz

4 MHz

1.00 MHz

670 kHz

500 kHz

250 kHz

8.32 kHz

400 kHz

1

2

3

4

5

6

7

2.2

Supply Voltage (V)

5.5

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

Figure 13-5. Operating Voltage Range

13-9

ELECTRICAL DATA

KS88C0416/P0416/C0424/P0424

NOTES

13-10

KS88C0416/P0416/C0424/P0424

MECHANICAL DATA

14 MECHANICAL DATA

OVERVIEW

The KS88C0416/C0424 microcontroller is currently available in a 32-pin SOP and SDIP package. The

KS88C0424 is available one more 40 DIP package.

#32

#17

32-SOP-450A

#1

#16

+0.10

- 0.05

0.25

19.90± 0.2

0.10 MAX

1.27

(0.43)

0.40

± 0.1

NOTE: Dimensions are in millimeters.

Figure 14-1. 32-Pin SOP Package Mechanical Data

14-1

MECHANICAL DATA

KS88C0416/P0416/C0424/P0424

#32

#17

0 – 15 *

32-SDIP-400

29.80 MAX

#1

#16

± 0.2

29.40

±

0.45 0.10

(1.37)

1.778

1.00 ± 0.10

NOTE: Dimensions are in millimeters.

Figure 14-2. 32-Pin SDIP Package Mechanical Data

14-2

KS88C0416/P0416/C0424/P0424

MECHANICAL DATA

#40

#21

40-DIP-600B

#1

#20

52.10 ± 0.2

0.46 ± 0.1

2.54

(1.92)

1.27 ± 0.1

NOTE

: Dimensions are in millimeters.

Figure 14-3. 40-Pin DIP Package Mechanical Data of KS88C0424

14-3

MECHANICAL DATA

KS88C0416/P0416/C0424/P0424

NOTES

14-4

KS88C0416/P0416/C0424/P0424

KS88P0416/P0424 OTP

15 KS88P0416/P0424 OTP

OVERVIEW

The KS88P0416/P0424 single-chip CMOS microcontrollers are the OTP (One Time Programmable) version of

the KS88C0416/C0424 microcontrollers. They have an on-chip EPROM instead of a masked ROM.

The KS88P0416/P0424 are fully compatible with the KS88C0416/C0424, both in function and in pin

configuration. Because of their simple programming requirements, the KS88P0416/P0424 are ideal as an

evaluation chip for the KS88C0416/C0424.

VSS

XIN

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VDD

RESET/

VPP

P3.1/REM/T0CK/

(2)

CE

/XOUT

/TEST

/P2.0/INT5

/P2.1/INT6

/P2.2/INT7

/P2.3/INT8

/P0.0/INT0

/P0.1/INT1

/P0.2/INT2

/P0.3/INT3

/P0.4/INT4

/P0.5/INT4

/P0.6/INT4

/P0.7/INT4

A14

P3.0/T0PWM/T0CAP/T1CAP/

MODE

OE

P2.7/

P2.6/

P2.5/

P2.4/

P1.7/

P1.6/

P1.5/

P1.4/

P1.3/

P1.2/

P1.1/

P1.0/

PGM

MEM_REG

A13

A12

A11

A10

D7

KS88P0416

KS88P0424

32-SOP/SDIP

A8

A9

A0

A1

A2

A3

A4

A5

A6

A7

9

10

11

12

13

14

15

16

D6

D5

D4

D3

D2

D1

D0

(Top View)

NOTES:

1. The bolds indicate an OTP pin name.

2. A14 is not valid in KS88P0416.

Figure 15-1. KS88P0416/P0424 Pin Assignments of 32SOP/32SDIP

15-1

KS88P0416/P0424 OTP

KS88C0416/P0416/C0424/P0424

VSS

XIN

/XOUT

A14

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

VDD

RESET/

P3.1/REM/T0CK/

P3.0/T0PWM/T0CAP/T1CAP/

NC

P2.7/

P2.6/

P2.5/

P2.4/

P1.7/

P1.6/

P1.5/

P1.4/

NC

VPP

CE

/TEST

MODE

OE

NC

/P2.0/INT5

PGM

/P2.1/INT6

/P2.2/INT7

A8

/P2.3/INT8

A9

/P0.0/INT0

A0

/P0.1/INT1

A1

/P0.2/INT2

A2

A13

A12

A11

A10

D7

MEM_REG

KS88P0416/

KS88P0424

40-DIP

9

10

11

12

13

14

15

16

17

18

19

20

D6

D5

D4

(Top View)

/P0.3/INT3

A3

NC

/P0.4/INT4

A4

/P0.5/INT4

A5

/P0.6/INT4

A6

/P0.7/INT4

A7

P1.3/

P1.2/

P1.1/

P1.0/

D3

D2

D1

D0

NOTES:

1. The bolds indicate an OTP pin name.

2. A14 is not valid in KS88P0416.

Figure 15-2. KS88P0424 Pin Assignments of 40DIP

15-2

KS88C0416/P0416/C0424/P0424

KS88P0416/P0424 OTP

Table 15-1. 32 SOP/SDIP Pin Descriptions used to read/write the EPROM

Pin Name

A0–A14

Pin No.

I/O

O

Function

3, 7–16, 25–28

Address lines to read/write EPROM

8-bit data input/output lines to read/write EPROM

Select EPROM mode.

D0–D7

MODE

CE

17–24

4

I/O

–

Chip enable (Connect to V_SS

, when read/write EPROM)

30

I

29

5

I

Output enable

OE

EPROM Program enable

Select Memory space of EPROM

Supply voltage (normally 5 V)

PGM

MEM_REG

V_DD

6

I

32

–

V_PP

V_SS

X_IN

31

1

–

EPROM Program/Verify voltage (normally 12.5 V)

Ground

2

System clock input pin

X_OUT

3

System clock output pin (when KS88P0416)

CHARACTERISTICS OF EPROM OPERATION

When +12.5 V is supplied to V and MODE pins of the KS88P0416/P0424, the EPROM programming mode is

PP

entered. The operating mode (read, write) is selected according to the input signals to the pins listed in Table 2

as below.

Table 15-2. Operating Mode Selection Criteria

V_DD

V_PP

MODE

Mode

PGM

MEM

OE

V_PP

5 V

12.5 V

1

0

READ

0

1

0

PROGRAM

PROGRAM VERIFY

NOTE: "0" means Low level; "1" means High level.

15-3

KS88P0416/P0424 OTP

KS88C0416/P0416/C0424/P0424

A14 A0

-

t

OED

D7 D0

-

t

ACC

t

OEH

OE

t

OEW

12.5V

MODE

Figure 15-3. OTP Read Timing

Table 15-3. OTP Read characteristics

°

(T_A= 25 C ± 5 C, V_DD= 5 V ± 5 %, V_PP= 12.5 V ± 0.25V)

Parameter

Address to Output Delay

to Address Delay

Symbol

Min

–

Typ

–

Max

75

–

Units

t_ACC

ns

t_OED

t_OEW

T_OEH

0

–

OE Pulse Width

75

0

–

Output hold from OE

whichever occurs first

–

15-4

KS88C0416/P0416/C0424/P0424

KS88P0416/P0424 OTP

PROGRAM

PROGRAM VERIFY

A14 A0

-

Data In Stable

Data Out Valid

D7 D0

-

t

DS

t

OEH

MODE

t

VS

t

DH

PGM

OE

t

OE

t

PW

t

OEW

Figure 15-4. Program Memory Write Timing

Table 15-4. OTP Program/Program Verify Characteristics

°

(T_A= 25 C ± 5 C, V_DD= 5 V ± 5 %, V_PP= 12.5 V ± 0.25V)

Parameter

Symbol

Min

–

Typ

2

Max

Units

V_PPSetup Time

t_VS

–

µs

t_DS

t_DH

t_PW

t_OE

t_OEW

t_OEH

Data Setup Time

Data Hold Time

Pulse Width

–

2

–

2

–

300

–

500

–

Data Valid from OE

OE Pulse Width

75

0

ns

–

Output Enable to Output Float

Delay

–

130

15-5

KS88P0416/P0424 OTP

KS88C0416/P0416/C0424/P0424

START

Address= First Location

V

=5V, V =12.5V

PP

DD

x = 0

Program One 1ms Pulse

Increment X

YES

x = 10

NO

FAIL

NO

Verify Byte

Verify 1 Byte

Last Address

Increment Address

V

= V = 5 V

PP

DD

FAIL

Compare All Byte

PASS

Device Failed

Device Passed

Figure 15-5. OTP Programming Algorithm

15-6

KS88C0416/P0416/C0424/P0424

KS88P0416/P0424 OTP

Table 15-5. D.C. Electrical Characteristics

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

°

Parameter

Symbol

Conditions

f_OSC= 8 MHz

Min

Typ

Max

Unit

V_DD

Operating Voltage

2.2

–

5.5

V

(Instruction clock = 1.33 MHz)

f_OSC= 4 MHz

2.0

–

5.5

(Instruction clock = 0.67 MHz)

All input pins except V_IH2and V_IH3

V_IH1

V_IH2

V_IH3

V_IL1

V_IL2

V_IL3

V_OH1

0.8 V_DD

0.85 V_DD

V_DD– 0.3

0

V_DD

Input High voltage

Input Low voltage

V

RESET

X_IN

V_DD

All input pins except V_IL2and V_IL3

0.2 V_DD

0.4 V_DD

0.3

–

RESET

X_IN

V_DD= 2.4 V; I_OH= – 6 mA

V_DD– 0.7

V_DD– 0.25

Output High

voltage

–

°

Port 3.1 only; T_A= 25 C

V_OH2

V_DD= 2.4 V; I_OH= – 3 mA

°

Port 3.0 only; T_A= 25 C

V_OH3

V_DD= 5 V; I_OH= – 3 mA

Output High

voltage

–

V

°

Port 2.7 only; T_A= 25 C

V_DD= 2 V; I_OH= – 1 mA

°

Port 2.7 only; T_A= 25 C

V_OH4

V_DD= 3.0 V; I_OH= – 1 mA

V_DD– 1

All output pins except P3 and P2.7

°

port; T_A= 25 C

V_OL1

V_OL2

V_OL3

V_DD= 2.4 V; I_OL= 15 mA

Output Low

voltage

–

0.4

–

0.5

1

V

°

Port 3.1 only; T_A= 25 C

V_DD= 2.4 V; I_OL= 5 mA

°

Port 3.0 only; T_A= 25 C

I_OL= 1 mA

°

Port 0, 1, and 2; T_A= 25 C

I_LIH1

I_LIH2

V_IN= V_DD

All input pins except X_INand X_OUT

Input High

leakage current

–

1

µA

V_IN= V_DD, X_IN,and X_OUT

20

15-7

KS88P0416/P0424 OTP

KS88C0416/P0416/C0424/P0424

Table 15-5. D.C. Electrical Characteristics (Continued)

°

(T_A= – 40 C to + 85 C, V_DD= 2.0 V to 5.5 V)

Parameter

Input Low

Symbol

Conditions

Min

Typ

Max

Unit

I_LIL1

V_IN= 0 V

–

– 1

µA

leakage current

All input pins except X_IN, X_OUT, and

RESET

I_LIL2

V_IN= 0 V

X_INand X_OUT

– 20

I_LOH

I_LOL

R_L1

V_OUT= V_DD

Output High

leakage current

1

All output pins

V_OUT= 0 V

Output Low

leakage current

– 1

143

All output pins

V_IN= 0 V; V_DD= 2.0 V

Pull-up resistors

65

95

kW

°

T_A= 25 C; Ports 0–3

V_DD= 5.5 V

15

–

21

6

32

11

I_DD1

I_DD2

I_DD3

Supply current

(note)

Operating mode

mA

V_DD= 5 V ± 10%

8 MHz crystal

4 MHz crystal

4.5

1.8

9

Idle mode

V_DD= 5 V ± 10%

3.5

8 MHz crystal

4 MHz crystal

1.6

0.3

3

Stop mode

µA

V_DD= 5 V ± 10%

V_DD= 3.6 V

0.1

1

NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads.

15-8

KS88C0416/P0416/C0424/P0424

KS88P0416/P0424 OTP

f

OSC

Instruction

Clock

(Main oscillation

frequency)

1.33 MHz

8 MHz

6 MHz

4 MHz

1.00 MHz

670 kHz

500 kHz

250 kHz

8.32 kHz

400 kHz

1

2

3

4

5

6

7

2.2

Supply Voltage (V)

5.5

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)

Figure 15-6. Operating Voltage Range

15-9

KS88P0416/P0424 OTP

KS88C0416/P0416/C0424/P0424

NOTES

15-10

KS88C0416/P0416/C0424/P0424

DEVELOPMENT TOOLS

16 DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The

development support system is composed of a host system, debugging tools, and supporting software. For a host

system, any standard computer that employs MS-DOS as its operating system can be used. A sophisticated

debugging tool is provided both in hardware and software: the powerful in-circuit emulator, SMDS2+, for the

KS57, KS86, and KS88 microcontroller families. SMDS2+ is a newly improved version of SMDS2. Samsung also

offers supporting software that includes, debugger, an assembler, and a program for setting options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE

provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked

help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be

easily sized, moved, scrolled, highlighted, added, or removed.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generating

an object code in the standard hexadecimal format. Assembled program codes include the object code used for

ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and

an auxiliary definition (DEF) file with device specific information.

SASM88

The SASM88 is an relocatable assembler for Samsung's KS88-series microcontrollers. The SASM88 takes a

source file containing assembly language statements and translates them into a corresponding source code, an

object code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS

operating system. As it produces relocatable object codes only, the user should link object files. Object files can

be linked with other object files and loaded into memory.

HEX2ROM

HEX2ROM file generates a ROM code from a HEX file which is produced by the assembler. A ROM code is

needed to fabricate a microcontroller which has a mask ROM. When generating a ROM code (.OBJ file) by

HEX2ROM, the value "FF" is automatically filled into the unused ROM area, upto the maximum ROM size of the

target device.

TARGET BOARDS

Target boards are available for all the KS88-series microcontrollers. All the required target system cables and

adapters are included on the device-specific target board.

OTPs

One time programmable microcontrollers (OTP) for the KS88C0416/C0424 and OTP programmer (Gang) are

now available.

16-1

DEVELOPMENT TOOLS

KS88C0416/P0416/C0424/P0424

IBM-PC AT or Compatible

RS-232C

SMDS2+

TARGET

APPLICATION

SYSTEM

PROM/OTP WRITER UNIT

RAM BREAK/ DISPLAY UNIT

TRACE/TIMER UNIT

PROBE

ADAPTER

TB880416A/24A

TB8801416A/24A

TARGET

POD

SAM8 BASE UNIT

BOARD

EVA

CHIP

POWER SUPPLY UNIT

Figure 16-1. SMDS Product Configuration (SMDS2+)

16-2

KS88C0416/P0416/C0424/P0424

DEVELOPMENT TOOLS

TB880416A/24A TARGET BOARD

The TB880416A/24A target board is used for the KS88C0416/C0424 and the KS88P0416/P0424 microcontroller.

It is supported by the SMDS2+ development system.

TB880416A/24A

TB8801416A/24A

To User_Vcc

OFF

ON

RESET

IDLE

STOP

+

74HC11

25

CN2

1

30

CN1

100 QFP

KS88E0400

EVA CHIP

1

30

EXTERNAL

TRIGGERS

15

16

CH1

CH2

SMDS2

SMDS2+

SM1304A

Figure 16-2. TB880416A/24A Target Board Configuration

16-3

DEVELOPMENT TOOLS

KS88C0416/P0416/C0424/P0424

Table 16-1. Power Selection Settings for TB880416A/24A

Operating Mode

"To User_Vcc"

Settings

Comments

SMDS2/SMDS2+ supplies

V_CCto the target board

(evaluation chip) and the

target system.

To User_Vcc

OFF

ON

TB880416A/24A

TB8801416A/24A

TARGET

SYSTEM

V

CC

V

SS

V

CC

SMDS2/SMDS2+

SMDS2/SMDS2+ supplies

V_CConly to the target board

(evaluation chip). The target

system must have a power

supply of its own.

To User_Vcc

OFF ON

TB880416A/24A

TB8801416A/24A

External

TARGET

SYSTEM

V

CC

V

SS

V

CC

SMDS2/SMDS2+

SMDS2+ Selection (SAM8)

In order to write data into program memory available in SMDS2+, the target board should be selected for

SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.

Table 16-2. The SMDS2+ Tool Selection Setting

"SW1" Setting

Operating Mode

SMDS2

SMDS2+

R/W*

SMDS2+

TARGET

BOARD

16-4

KS88C0416/P0416/C0424/P0424

DEVELOPMENT TOOLS

Table 16-3. Using Single Header Pins as the Input Path for External Trigger Sources

Target Board Part

Comments

EXTERNAL

TRIGGERS

Connector from

external trigger

sources of the

CH1

CH2

application system

You can connect an external trigger source to one of the two external

trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace

functions.

IDLE LED

This LED is ON when the evaluation chip (KS88E0400) is in idle mode.

STOP LED

This LED is ON when the evaluation chip (KS88E0400) is in stop mode.

16-5

DEVELOPMENT TOOLS

KS88C0416/P0416/C0424/P0424

CN2

1

2

3

4

5

6

7

8

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VSS

TEST

P2.0

P2.1

P2.2

P2.3

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

VDD

RESET

P3.1

P3.0

P2.7

P2.6

P2.5

P2.4

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

9

10

11

12

13

14

15

Figure 16-3. 30-Pin Connector (CN2) for TB880416A/24A

TARGET BOARD

CN2

30

TARGET SYSTEM

1

32

1

30

16

Part Name: AP32SD-A

Order Code: SM6506

15 16

15

16

17

Figure 16-4. TB880416A/24A Adapter Cable for 32-SDIP Package (KS88C0416/C0424)

16-6


型号：	KS88C0424N-XX
厂家：	SAMSUNG
描述：	Microcontroller, 8-Bit, MROM, CMOS, PDIP32, 0.400 INCH, SDIP-32 微控制器光电二极管
文件：	总184页 (文件大小：1196K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS88C0424N-XX [SAMSUNG]

相关型号：

KS88C0504P

KS88C0716

KS88C0716N

KS88C0716N-XX

KS88C0716Q

KS88C0716Q-XX

KS88C0808IFP

KS88C0808IS

KS88C0916

KS88C0916(SDIP)

KS88C0916(SOP)

KS88C0916N-XX