KS88C6232Q-XX [SAMSUNG]
Microcontroller, 8-Bit, MROM, CMOS, PQFP44, 10 X 10 MM, QFP-44;
| 型号： | KS88C6232Q-XX |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, MROM, CMOS, PQFP44, 10 X 10 MM, QFP-44 时钟 微控制器 外围集成电路 |
| 文件： | 总24页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide
range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.
KS88C6216/C6224/C6232/P6232 MICROCONTROLLERS
KS88C6216/C6224/C6232/P6232 single-chip 8-bit
microcontrollers are based on the powerful SAM8
CPU architecture. The internal register file is logically
expanded to increase the on-chip register space.
KS88C6216/C6224/C6232/P6232 contain 16/32 K
bytes of on-chip program ROM.
— One 12-bit counter with selectable clock sources,
including Hsync or Csync input
— One interval timer
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,
Csync input, and Clamp signal output)
In line with Samsung's modular design approach, the
following peripherals are integrated with the SAM8
core:
— DDC and normal Multi-master IIC-bus
— 4-channel A/D converter (8-bit resolution)
— Four programmable I/O ports (total 27 pins)
KS88C6216/C6224/C6232/P6232 are a versatile
microcontrollers which are ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, A/D converter, and multi-master
IIC-bus support with DDC. They are available in a 42-
pin SDIP or a 44-pin QFP package.
— One 8-bit basic timer for oscillation stabilization
and watchdog functions
— One 8-bit general-purpose timer/counter with
selectable clock sources
OTP
KS88C6216/C6224/C6232 microcontrollers are also available in OTP (One Time Programmable) version named,
KS88P6232. KS88P6232 microcontroller has an on-chip 32-Kbyte one-time-programmable EPROM instead of
masked ROM. KS88P6232 is comparable to KS88C6216/C6224/C6232, both in function and pin configuration
except its ROM size.
1-1
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
FEATURES
CPU
Pulse Width Modulator (PWM)
• 8-bit PWM: 7-CH
•
SAM8 CPU core
Memory
Sync-Processor Block
•
•
16/24/32-Kbyte internal program memory (ROM)
464-byte general-purpose register area
•
Vsync-I, Hsync-I, Csync-I input and Vsync-O,
Hsync-O, Clamp-O output pins
•
•
•
Pseudo sync signal output
Auto SOG detection
Instruction Set
•
•
78 instructions
Auto Hsync polarity detection
IDLE and STOP instructions added for
power-down modes
DDC Multi-Master IIC-Bus 1-Ch
•
•
Serial Peripheral Interface
Instruction Execution Time
Minimum 500 ns (with 12 MHz CPU clock)
Support for Display Data Channel
(DDC1/DDC2B/DDC2Bi/DDC2B+)
•
Interrupts
Normal Multi-Master IIC-Bus 1-Ch
Serial Peripheral Interface
•
Ten interrupt sources
•
•
•
•
Ten interrupt vectors
Seven interrupt level
Fast interrupt feature
A/D Converter
•
4-channel; 8-bit resolution
General I/O
Oscillator Frequency
•
Four I/O Ports (total 27pins)
•
•
8 MHz to 12 MHz crystal operation
Internal Max. 12 MHz CPU clock
8-Bit Basic Timer
Operating Temperature Range
– 40 °C to + 85 °C
•
Programmable timer for oscillation stabilization
interval control or watchdog timer function
•
•
Three selective internal clock frequencies
Operating Voltage Range
4.0 V to 5.5 V
•
Timer/Counters
•
•
•
One 8-bit Timer/Counter with several clock
sources (Capture mode)
Package Types
42-pin SDIP, 44-pin QFP
•
One 12-bit Counter with H-sync and several clock
sources
One Interval Timer
1-2
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0 P0.7/INT0 INT2
P2.0 P2.7
-
-
-
V
V
TEST
, AVREF
DD
RESET
PORT 0
PORT 2
, V
SS1 SS2
INT0-INT2
X
MAIN
OSC
IN
INTERNAL BUS
X
OUT
P1.0–P1.2
P3.0–P3.7
PORT 1
I/O PORT and INTERRUPT
CONTROL
PWM0
•
•
•
•
8-BIT
PWM
(7-CH)
PWM6
PORT3
ADC
SAM8 CPU
Vsync-I
Hsync-I
Csync-I
Vsync-O
Hsync-O
Clamp-O
Sync-
Processor
AD0 AD3
-
16/24/32-
Kbyte
464-Byte
Register File
ROM
Multi
Master
IIC-Bus
8-Bit
Counter
(Timer M0)
SCL1
SDA1
MT0CAP
Interval
Timer
(Timer M2)
12-Blt
Counter
(Timer M1)
Multi Master IIC-Bus
and DDC1/2B/2Bi/2B+
MT1CK
SCL0
SDA0
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
PIN ASSIGNMENTS
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.7
2
P3.6
3
P3.5
4
P3.4
P0.4/TM0CAP
P0.5/TM1CK
P0.6
5
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0/AD0
AVREF
6
7
P0.7
8
P1.0/SDA1
P1.1/SCL1
9
KS88C6216
/C6224/C6232
42-SDIP
10
11
12
13
14
15
16
17
18
19
20
21
V
SS2
P2.7/Csync-I
Hsync-I
V
DD
V
SS1
(Top View)
X
Vsync-I
OUT
X
Vsync-O
IN
TEST
SDA0
Hsync-O
Clamp-O
SCL0
RESET
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
P1.2
P2.0/PWM0
P2.1/PWM1
Figure 1-2. KS88C6216/C6224/C6232 42-SDIP Pin Assignment
1-4
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
P3.2/AD2
P3.1/AD1
P3.0/AD0
AVREF
VSS2
P2.7/Csync-I
Hsync-I
33
32
31
30
29
28
27
26
25
24
23
P0.5/TM1CK
1
2
3
4
5
6
7
8
P0.6
P0.7
P1.0/SDA1
P1.1/SCL1
VDD
KS88C6216/C6224
/C6232/P6232
44-QFP
VSS1
XOUT
XIN
TEST
Vsync-I
(Top View)
Vsync-O
Hsync-O
Clamp-O
9
10
11
SDA0
Figure 1-3. KS88C6224/C6232 44-QFP Pin Assignment
1-5
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
PIN DESCRIPTIONS
Table 1-1. KS88C6216/C6224/C6232/P6232 Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
SDIP Pin
Numbers
Shared
Functions
P0.0
I/O General-purpose, 8-bit I/O port. Shared
functions include three external interrupt
inputs and I/O for timer M0 and M1.
Selective configuration of port 0 pins to
input or output mode is supported.
D-1
D-1
D-1
D-1
D-1
D-1
D-1
D-1
1
2
3
4
5
6
7
8
INT0
INT1
INT2
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
TM0CAP
TM1CK
P1.0
P1.1
P1.2
I/O General-purpose, 3-bit I/O port. Selective
configuration is available for port 1 pins to
input, push-pull output, n-channel open-
drain mode, or IIC-bus clock and data I/O.
E-1
E-1
E-1
9
10
19
SDA1
SCL1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
I/O General-purpose, 8-bit I/O port Selective
configuration of port 2 pins to input or
output mode is supported. The port 2 pin
circuits are designed to push-pull PWM
output and Csync signal input.
D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1
20
21
22
23
24
25
26
32
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Csync-I
P3.0–P3.3
P3.4–P3.7
I/O General-purpose, 8-bit I/O port Selective
configuration port 3 pins to input or output
mode is supported. Multiplexed for
alternative use as A/D converter inputs
AD0–AD3.
D-1
E
35–38,
39–42
AD0–AD3
Hsync-I
Vsync-I
Clamp-O
Hsync-O
Vsync-O
SDA0
I
I
O
O
O
The pins are sync processor signal I/O, IIC-
bus clock, and data I/O.
A
A
A
A
A
31
30
27
28
29
16
17
–
I/O
I/O
G-3
G-3
SCL0
VDD, VSS1
AVREF, VSS2
,
–
Power pins
ADC power pins
–
–
11, 12
34, 33
–
X
, X
–
I
System clock I/O pins
System reset pin
–
B
–
14, 13
18
–
–
–
IN OUT
RESET
TEST
I
Factory test pin input
15
0V:Normal operation,5V:Factory test mode
1-6
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
PIN CIRCUITS
V
DD
V
DD
Data or
Other
Function
Output
Output
Data
Output
Disable
V
SS
Digital Input
TTL Input
V
SS
or ADC Input
Figure 1-6. Pin Circuit Type D-1
Figure 1-4. Pin Circuit Type A
V
DD
280 K
W
Noise Filter
RESET
Figure 1-5. Pin Circuit Type B (RESET)
1-7
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
V
DD
Typical
47-K
W
Pull-up Enable
V
DD
Data
Output
Open drain
Output Disable
V
SS
Input
Figure 1-7. Pin Circuit Type E
V
DD
Data
Output
Open drain
Output Disable
VSS
Input
Figure 1-8. Pin Circuit Type E-1
1-8
KS88C6216/C6224/C6232/P6232
PRODUCT OVERVIEW
Output
Data
V
SS
Input
Figure 1-9. Pin Circuit Type G-3
1-9
PRODUCT OVERVIEW
KS88C6216/C6224/C6232/P6232
NOTES
1-10
KS88C6216/C6224/C6232/P6232
ELECTRICAL DATA
19 ELECTRICAL DATA
OVERVIEW
In this section, KS88C6216/C6224/C6232 electrical characteristics are presented in tables and graphs. The
information is arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in stop mode
— Stop mode release timing when initiated by a reset
— I/O capacitance
— A/D Converter electrical characteristics
— A.C. electrical characteristics
— Input timing measurement points for P0.0–P0.2, TM0CAP, and TM1CK
— Oscillation characteristics
— Oscillation stabilization time
— Clock timing measurement points for X
IN
— Schmitt trigger characteristics
19-1
ELECTRICAL DATA
KS88C6216/C6224/C6232/P6232
Table 19-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Unit
V
Supply voltage
–
– 0.3 to + 6.5
V
DD
Input voltage
V
Type C (n-channel, open-drain)
– 0.3 to + 7.0
V
I1
V
All port pins except V
All output pins
– 0.3 to V
+ 0.3
+ 0.3
I1
DD
DD
I2
Output voltage
V
– 0.3 to V
V
O
Output current
High
I
One I/O pin active
– 10
mA
OH
All I/O pins active
One I/O pin active
– 60
+ 30
Output current
Low
I
mA
OL
Total pin current except port 3
+ 100
+ 150
Sync-processor I/O pins and IIC-bus
clock and data pins
Operating
temperature
T
–
– 40 to + 85
– 65 to + 150
°
°
C
C
A
Storage
temperature
T
–
STG
Table 19-2. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 4.0 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input High
voltage
V
All input pins except V
and V
0.8 V
–
V
V
IH1
IH2
IH3
DD
DD
V
X
2.7
2.0
–
V
IH2
IN
DD
V
TTL input (HsyncI, VsyncI, and CsyncI)
All input pins except V and V
V
IH3
DD
Input Low
voltage
V
–
–
0.2 V
DD
V
V
IL1
IL2
IL3
V
X
1.0
0.8
–
IL2
IN
V
TTL input (HsyncI, VsyncI, and CsyncI)
IL3
Output High
voltage
V
I
= – 8 mA; Port 3 only
V
– 1.0
OH1
OH
OH
DD
V
I
= – 2 mA
OH2
Ports 0, 2, ClampO, H, and VsyncO
V
I
OH
= – 6 mA; Port 1
OH3
19-2
KS88C6216/C6224/C6232/P6232
ELECTRICAL DATA
Table 19-2. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 4.0 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
= 8 mA; port 3 only
Min
Typ
Max
Unit
Output Low
voltage
V
I
I
–
–
0.4
V
OL1
OL
V
= 2 mA
0.4
0.6
3
OL2
OL
Port 0, 2, ClampO, H, and VsyncO
= 6 mA
V
I
OL
OL3
Port 1; SCL and SDA
= V
Input High
leakage current
I
V
–
–
µA
µA
LIH1
IN
DD
All input pins except X
X
,
IN OUT
I
V
V
= V
X only
;
DD OUT
–
2.5
–
–
6
–
20
20
LIH2
IN
IN
I
= V
X
only
;
LIH3
DD IN
Input Low
leakage current
I
V
X
V
= 0 V; All input pins except X
,
IN
– 3
LIL1
IN
and RESET
,
OUT
I
= 0 V; X only
OUT
–
– 2.5
–
–
– 6
–
– 20
– 20
3
LIL2
IN
IN
I
V
V
= 0 V; X only
LIL3
IN
Output High
leakage current
I
= V
DD
µA
µA
kW
LOH1
OUT
Output Low
leakage current
I
V
V
= 0 V
–
–
– 3
80
LOL1
OUT
Pull-up resistor
R
= 0 V
IN
20
47
L1
Ports 3.7–3.4
R
V
= 0 V
150
–
280
480
L2
IN
RESET only
Supply current
(note)
I
Operation mode; 12 MHz crystal
C1 = C2 = 22pF
15
5
30
10
10
mA
µA
DD1
I
Idle mode; 12 MHz crystal
C1 = C2 = 22pF
DD2
I
Stop mode
1
DD3
NOTE: Supply current does not include drawn internal pull–up resistors and external loads of output.
19-3
ELECTRICAL DATA
KS88C6216/C6224/C6232/P6232
Table 19-3. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
Stop mode
Min
Typ
Max
Unit
Data retention
supply voltage
V
2
–
5.5
V
DDDR
Data retention
supply current
I
Stop mode, V
= 2.0 V
DDDR
–
–
5
µA
DDDR
NOTES:
1. During the oscillator stabilization wait time (t
), all CPU operations must be stopped.
WAIT
2. Supply current does not include drawn through internal pull–up resistors and external output current loads.
OSCILLATION
STABILIZATION
TIME
RESET
OCCURS
STOP MODE
NORMAL
OPERATING
MODE
DATA RETENTION
MODE
V
DD
V
DDDR
EXECUTION OF
STOP INSTRUCTION
RESET
t
WAIT
:
t
is the same as 4,096 x x32 x 1/f
.
NOTE
WAIT
OSC
Figure 19-1. Stop Mode Release Timing When Initiated by a Reset
Table 19-4. Input/Output Capacitance
°
°
(T = –40 C to + 85 C, V
= 0 V)
A
DD
Parameter
Input
capacitance
Symbol
Conditions
Min
Typ
Max
10
Unit
C
f = 1 MHz; unmeasured pins
–
–
pF
IN
are connected to V
SS
Output
capacitance
C
OUT
I/O capacitance
C
IO
19-4
KS88C6216/C6224/C6232/P6232
ELECTRICAL DATA
Table 19-5. A/D Converter Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V = 4.0 V to 5.5 V, V = 0 V)
A
DD
SS
Parameter
Symbol
Conditions
Min
–
Typ
8
Max
–
Unit
bit
Resolution
Total accuracy
V
= 5 V
–
–
LSB
± 2
DD
Conversion time = 5 ms
AV = 5 V
Integral linearity error
ILE
–
–
± 1
± 1
REF
Differential linearity error
DLE
AV = 0 V
SS
Offset error of top
EOT
EOB
± 1
± 0.5
–
± 2
± 2
Offset error of bottom
(1)
t
8 bit conversion
17
170
ms
Conversion time
CON
(3) n=1,4,8,16
34 x n/f
,
OSC
Analog input voltage
Analog input impedance
Analog reference voltage
Analog ground
V
–
–
–
–
AV
–
1000
–
AV
V
IAN
SS
REF
R
2
–
mW
AN
AV
2.5
V
V
REF
DD
(4)
V
–
V
V
AV
SS
SS
SS
Analog input current
I
AV
= V = 5V
–
–
10
mA
mA
mA
nA
ADIN
REF
DD
(2)
I
AV
= V = 5V
–
1
3
Analog block Current
ADC
REF
DD
AV
= V = 3V
0.5
100
1.5
500
REF
DD
AV
= V
= 5V
When power down mode
REF
DD
NOTES:
1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.
2.
3.
4.
I
is an operating current during the A/D conversion.
ADC
f
is the main oscillator clock.
OSC
V
port shaves with the AV for KS88C6216/C6224/C6232.
SS
SS
19-5
ELECTRICAL DATA
KS88C6216/C6224/C6232/P6232
Table 19-6. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 4.0 V to 5.5V)
A
DD
Parameter
Noise Filter
Symbol
Conditions
Min
Typ
Max
Unit
t
INT0–2, TM0CAP and
TM1CK (RC delay)
300
–
–
ns
NF1H
t
NF1L
t
RESET only (RC delay)
800
–
–
NF2
t
t
NF1H
NF1L
t
NF2
0.8 V
DD
0.2 V
DD
Figure 19-2. Input Timing Measurement Points for P0.0–P0.2, TM0CAP, and TM1CK
19-6
KS88C6216/C6224/C6232/P6232
ELECTRICAL DATA
Table 19-7. Oscillation Characteristics
°
°
(T = – 40 C + 85 C)
A
Oscillator
Clock Circuit
Conditions
Min
Typ
Max
Unit
Main crystal or
ceramic
V
= 4.0 V to 5.5 V
8
–
12
MHz
C1
DD
DD
XIN
XOUT
C2
External clock
(main)
V
= 4.0 V to 5.5 V
8
–
12
MHz
XIN
XOUT
NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot
select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.
Table 19-8. Oscillation Stabilization Time
°
°
(T = – 40 C + 85 C, V
= 4.0 V to 5.5 V)
A
DD
Oscillator
Test Condition
Min
Typ
Max
Unit
Crystal
V
V
X
= 4.0 V to 5.5 V
= 4.0 V to 5.5V
–
–
20
ms
DD
Ceramic
–
–
–
10
DD
External clock
input high and low level width
25
500
ns
IN
(t , t )
XH XL
NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a
power-on occurs, or when Stop mode is released.
1 / f
X
t
t
XH
XL
V
0.5 V
-
X
DD
IN
0.4 V
Figure 19-3. Clock Timing Measurement Points for X
IN
19-7
ELECTRICAL DATA
KS88C6216/C6224/C6232/P6232
V
out
V
DD
A : 0.2 V
B : 0.4 V
C : 0.6 V
D : 0.8 V
DD
DD
DD
DD
V
SS
V
in
A
B
C
D
Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)
19-8
KS88C6216/C6224/C6232/P6232
MECHANICAL DATA
20 MECHANICAL DATA
OVERVIEW
The KS88C6216/C6224/C6232 microcontroller is available in a 42-pin SDIP package (Samsung part number 42-
SDIP-600) and a 44-QFP package (Samsung part number 44-QFP-1010B).
42
22
0 ~ 15 °
42-SDIP-600
#1
21
39.10 ± 0.2
(1.77)
1.778
0.50 ± 0.1
1.00 ± 0.1
: Dimensions are in millimeters.
NOTE
Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)
20-1
MECHANICAL DATA
KS88C6216/C6224/C6232/P6232
13.20
± 0.3
0~8°
10.00 ± 0.2
44-QFP-1010B
0.10 MAX
#44
0.05 MIN
2.05 ± 0.10
2.30 MAX
+0.10
- 0.05
#1
0.80
0.35
(1.00)
: Dimensions are in millimeters.
NOTE
Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
20-2
KS88C6216/C6224/C6232/P6232
KS88P6232 OTP
21 KS88P6232 OTP
OVERVIEW
The KS88P6232 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS88C6216/C6224/C6232 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is
accessed by serial data format.
The KS88P6232 is fully compatible with the KS88C6216/C6224/C6232, both in function and in pin configuration.
Because of its simple programming requirements, the KS88P6232 is ideal for use as an evaluation chip for the
KS88C6216/C6224/C6232.
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.7
2
P3.6
3
P3.5
4
P3.4
P0.4/TM0CAP
P0.5/TM1CK
P0.6
5
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0/AD0
AVREF
6
7
P0.7
8
/P1.0/SDA1
SDAT
9
/P1.1/SCL1
10
11
12
13
14
15
16
17
18
19
20
21
V
SCLK
SS2
KS88P6232
42-SDIP
(Top View)
P2.7/Csync-I
Hsync-I
V
DD
V
SS1
X
Vsync-I
OUT
X
Vsync-O
IN
/TEST
SDA0
SCL0
Hsync-O
V
PP
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
/RESET
P1.2
RESET
P2.0/PWM0
P2.1/PWM1
The bolds indicate an OTP pin name.
NOTE:
Figure 21-1. KS88P6232 Pin Assignments (42-SDIP Package)
21-1
KS88P6232 OTP
KS88C6216/C6224/C6232/P6232
P3.2/AD2
33
32
31
30
29
28
27
26
25
24
23
P0.5/TM1CK
1
2
3
4
5
6
7
8
P3.1/AD1
P3.0/AD0
AVREF
VSS2
P2.7/Csync-I
Hsync-I
P0.6
P0.7
SDAT/P1.0/SDA1
SCLK/P1.1/SCL1
VDD
KS88C6216/C6224
/C6232/P6232
(44-QFP)
VSS1
XOUT
XIN
VPP/TEST
SDA0
Vsync-I
Top View
Vsync-O
Hsync-O
Clamp-O
9
10
11
NOTE:
The bolds indicate an OTP pin name.
Figure 21-2. KS88P6232 Pin Assignments (44-QFP Package)
21-2
KS88C6216/C6224/C6232/P6232
KS88P6232 OTP
Table 21-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
Pin Name
P1.0
During Programming
I/O
Pin Name
Pin No.
Function
SDAT
9 (4)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P1.1
SCLK
10 (5)
I
I
Serial clock pin. Input only pin.
TEST
VPP (TEST)
15 (10)
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
RESET
RESET
18 (13)
I
I
Chip Initialization
VDD/VSS1
VDD/VSS1
11/12 (6/7)
Logic power supply pin. VDD should be tied to +5
V during programming.
NOTE: Parentheses indicate 44-QFP OTP pin number.
Table 21-2. Comparison of KS88P6232 and KS88C6216/C6224/C6232 Features
Characteristic KS88P6232 KS88C6216/C6224/C6232
32-Kbyte EPROM
Program Memory
16/24/32-Kbyte mask ROM
4.0 V to 5.5V
Operating Voltage (VDD
)
4.0 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (TEST)=12.5V
Pin Configuration
42SDIP, 44QFP
42SDIP, 44QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the KS88P6232, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 21-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
MEM
ADDRESS
(A15–A0)
R/W
MODE
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
21-3
KS88P6232 OTP
KS88C6216/C6224/C6232/P6232
D.C. ELECTRICAL CHARACTERISTICS
Table 21-4. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input High
leakage current
ILIH1
VIN = VDD
All input pins except XIN
–
–
3
µA
X
,
OUT
ILIH2
ILIH3
ILIL1
VIN = VDD
X
OUT only
–
2.5
–
–
6
–
20
20
;
VIN = VDD
XIN only
;
Input Low
leakage current
VIN = 0 V; All input pins except XIN
– 3
µA
,
and RESET
,
XOUT
ILIL2
ILIL3
VIN = 0 V; XOUT only
VIN = 0 V; XIN only
VOUT = VDD
–
– 2.5
–
–
– 6
–
– 20
– 20
3
Output High
leakage current
ILOH1
µA
µA
kW
Output Low
leakage current
ILOL1
RL1
VOUT = 0 V
–
–
– 3
80
Pull-up resistor
VIN = 0 V
20
47
Ports 3.7–3.4
RL2
VIN = 0 V
RESET only
150
–
280
480
Supply current
(note)
IDD1
IDD2
IDD3
Operation mode; 12 MHz crystal
C1 = C2 = 22pF
15
5
30
10
10
mA
µA
Idle mode; 12 MHz crystal
C1 = C2 = 22pF
Stop mode
1
NOTE: Supply current does not include drawn internal pull–up resistors and external loads of output.
21-4
相关型号：
KS88C8316
SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU
SAMSUNG
KS88C8324
SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU
SAMSUNG
KS88C8424
SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU
SAMSUNG
©2020 ICPDF网 联系我们和版权申明