M312L2923BZ0-CA2 [SAMSUNG]
DDR DRAM Module, 128MX72, 0.75ns, CMOS, DIMM-184;
| 型号： | M312L2923BZ0-CA2 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 128MX72, 0.75ns, CMOS, DIMM-184 动态存储器 双倍数据速率 |
| 文件： | 总20页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 512Mb B-die (x4, x8)
with 1,200mil Height & 72-bit ECC
60 FBGA with Pb-Free
(RoHS compliant)
Revision 1.2
Oct. 2004
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
Revision History
Revision 1.0 (Feburary, 2004)
- First release
Revision 1.1 (March, 2004)
- Added 512MB RDIMM.
Revision 1.2 (October, 2004)
- Corrected typo.
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
184Pin Registered DIMM based on 512Mb B-die FBGA (x4, x8)
Ordering Information
Part Number
Density
512MB
1GB
Organization
64Mx72
Component Composition
Height
1,125mil
1,125mil
1,125mil
1,200mil
M312L6523BZ0-CB3/A2/B0
M312L2923BZ0-CB3/A2/B0
M312L2920BZ0-CB3/A2/B0
M312L5720BZ0-CB3/A2/B0
64Mx8( K4H510838B) * 9EA
64Mx8( K4H510838B) * 18EA
128Mx4( K4H510438B) * 18EA
128Mx4( K4H510438B) * 36EA
128M x 72
128M x 72
256M x 72
1GB
2GB
Operating Frequencies
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Speed @CL2
Speed @CL2.5
CL-tRCD-tRP
133MHz
166MHz
2.5-3-3
133MHz
133MHz
2-3-3
100MHz
133MHz
2.5-3-3
Feature
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• SSTL_2 Interface Pb-Free
• RoHS compliant
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
Pin Configuration (Front side/back side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
/RESET
VSS
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
*CK2
*/CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
93
94
95
96
97
VSS
DQ4
DQ5
124
125
126
127
128
VSS
A6
DQ28
DQ29
VDDQ
154
155
156
157
158
/RAS
DQ45
VDDQ
/CS0
VDDQ
DM0/DQS9
DQ6
/CS1
DM5/DQS14
VSS
98
99
129 DM3/DQS12 159
DQ7
VSS
NC
NC
130
131
132
133
134
135
136
137
138
139
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
160
161
162
163
164
165
166
167
168
169
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VSS
A1
NC
DQ8
DQ9
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
DQS1
VDDQ
*CK1
*/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
/CK0
VSS
VDD
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
140 DM8/DQS17 170
141
142
143
144
A10
CB6
VDDQ
CB7
171
172
173
174
175
176
177
178
179
DQ60
DQ61
VSS
KEY
KEY
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
145
146
147
148
VSS
DQ36
DQ37
VDD
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
DQS7
DQ58
DQ59
VSS
NC
SDA
DQ21
A11
DM2/DQS11
VDD
A9
DQ18
A7
VDDQ
DQ19
149 DM4/DQS13 180
150
151
152
153
DQ38
DQ39
VSS
181
182
183
184
DQ22
A8
DQ23
SCL
DQ44
Note :
1. * : These pins are not used in this module.
2. Pins 111, 158 are NC for 1row module [M312L2920BZ0] & used for 2row module [M312L2923BZ0, M312L5720BZ0 ]
3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).
Pin Description
Pin Name
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Pin Name
DM0 ~ DM8
VDD
Function
A0 ~ A12
Data - in mask
BA0 ~ BA1
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
DQ0 ~ DQ63
VDDQ
VSS
DQS0 ~ DQS17
CK0,CK0 ~ CK2, CK2
Data Strobe input/output
Clock input
VREF
Power supply for reference
CKE0, CKE1(for double banks) Clock enable input
VDDSPD
SDA
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
CS0, CS1(for double banks)
Chip select input
RAS
Row address strobe
Column address strobe
Write enable
SCL
Serial clock
CAS
SA0 ~ 2
NC
Address in EEPROM
No connection
WE
CB0 ~ CB7
Check bit(Data-in/data-out)
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
512MB, 64M x 72 ECC Module (M312L6523BZ0) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
RCS0
DQS0
DM0
DQS4
DM4
DM
I/O 7
CS
DQS
DQS
CS
DM
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
D4
D0
DQS5
DM5
DQS1
DM1
DM
CS DQS
DQS
CS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ8
DQ9
D5
D1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS6
DM6
DQS2
DM2
DM
CS DQS
DM
CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D6
D2
DQS7
DM7
DQS3
DM3
DM
CS DQS
DM
CS
DQS
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D7
D3
DQS8
DM8
VDDSPD
SPD
VDD/VDDQ
DDR SDRAMs D0 - D8
DM
CS
DQS
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D8
VREF
VSS
DDR SDRAMs D0 - D8
DDR SDRAMs D0 - D8
Serial PD
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
SCL
WP
SDA
A0
A1
A2
SA0 SA1 SA2
RCS0
CS0
R
BA0 -BA1 : DDR SDRAMs D0 - D8
E
G
I
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
BA0-BA1
A0-A12
RAS
CAS
CKE0
WE
A0 -A12 : DDR SDRAMs D0 - D8
RAS : DDR SDRAMs D0 - D8
CAS : DDR SDRAMs D0 - D8
CKE : DDR SDRAMs D0 - D8
WE: DDR SDRAMs D0 - D8
S
T
E
R
RWE
PCK
PCK
RESET
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
1GB, 128M x 72 ECC Module (M312L2923BZ0) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
RCS1
RCS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
D9
D4
D13
D0
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
D2
D11
D6
D15
DQS3
DM3
DQS7
DM7
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
D3
D7
D12
D16
DQS8
DM8
DM/
CS DQS
DM/
CS DQS
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D8
D17
V
V
SPD
DDSPD
Serial PD
SCL
WP
D0 - D17
D0 - D17
/V
DD DDQ
SDA
A0
A1
A2
D0 - D17
D0 - D17
VREF
SA0 SA1 SA2
V
SS
RCS0
CS0
CS1
BA0-BA1
R
E
G
I
S
T
E
R
PLL*
* Wire per Clock Loading table/wiring Diagrams
CK0,CK0
RCS1
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
RCKE1
RWE
BA0 -BA1 : DDR SDRAM DQ0 - D17
A0 -A12 : DDR SDRAM D0 - D17
RAS : DDR SDRAM D0 - D17
CAS : DDR SDRAM DQ0 - D17
CKE : DDR SDRAM D0 - D8
CKE : DDR SDRAM D9 - D17
WE: DDR SDRAM D0 - D17
A0-A12
Notes:
RAS
CAS
CKE0
CKE1
WE
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
PCK
PCK
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RESET
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
1GB, 128M x 72 ECC Module (M312L2920BZ0) (Populated as 1 bank of x4 DDR SDRAM Module)
Functional Block Diagram
VSS
RCS0
DQS0
DQS1
DQS9
(DM0)
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D9
D0
DQS10
(DM1)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D10
D1
DQS11
(DM2)
DQS2
DQS3
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D11
D2
DQS12
(DM3)
DQS
DQS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
D12
D3
DQS13
(DM4)
DQS4
DQS5
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 2
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
D13
D4
DQS14
(DM5)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
D14
D5
DQS15
(DM6)
DQS6
DQS
DQS
CS
Serial PD
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
SCL
WP
D15
D6
SDA
A0
A1
A2
DQS7
DQS8
DQS16
(DM7)
DQS
DQS
CS
CS
SA0 SA1 SA2
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D16
D7
VDDSPD
SPD
DQS17
(DM8)
VDD/VDDQ
D0 - D17
D0 - D17
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
I/O 3
I/O 2
I/O 1
I/O 0
CB0
CB1
CB2
CB3
D17
D8
VREF
VSS
D0 - D17
D0 - D17
PLL*
CK0,CK0
RCS0_1
RCS0_2
CS0
R
E
G
I
S
T
E
R
* Wire per Clock Loading table/wiring Diagrams
RBA0 - RBA1
RA0 - RA12
RRAS
BA0 -BA1 : DDR SDRAM DQ0 - D17
A0 -A12 :DDR SDRAM D0 - D17
BA0-BA1
A0-A12
RAS
CAS
CKE0
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
RAS : DDR SDRAM D0 - D17
CAS : DDR SDRAM DQ0 - D17
CKE : DDR SDRAM D0 - D8
CKE : DDR SDRAM D9 - D17
RCAS
RCKE0A
RCKE0B
RWE
WE
WE:DDR SDRAM D0 - D17
3. DQ, DQS, DM resistors: 22 Ohms.
PCK
PCK
RESET
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
2GB, 256M x 72 ECC Module [M312L5720BZ0] (Populated as 2 bank of x4 DDR SDRAM Module)
Functional Block Diagram
V
SS
RCS1
RCS0
DQS0
DQS9
(DM0)
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D18
D9
D27
DQS1
DQS2
DQS3
DQS10
(DM1)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D19
D10
D28
DQS11
(DM2)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D2
D20
D11
D29
DQS12
(DM3)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ24
DQ25
DQ26
DQ27
D3
D21
D12
D30
DQS13
(DM4)
DQS4
DQS5
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
D4
D22
D13
D31
DQS14
(DM5)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
D5
D23
D14
D32
DQS15
(DM6)
DQS6
DQS7
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
D24
D15
D33
DQS16
(DM7)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS17
(DM8)
DQS8
DQS
CS
DQS
CS
DQS
DM
DQS
DM
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
CB4
CB5
CB6
CB7
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
D17
D35
D8
D26
VDDSPD
SPD
Serial PD
V
DD/VDDQ
D0 - D35
D0 - D35
SCL
WP
SDA
A0
A1
A2
VREF
VSS
D0 - D35
D0 - D35
SA0 SA1 SA2
CS0
RCS0
RCS1
R
E
G
I
S
T
E
R
CS1
BA0-BA1
A0-A12
PLL*
CK0,CK0
RBA0 - RBA1
RA0 - RA12
BA0-BA1: DDR SDRAM D0 - D35
A0-A12: DDR SDRAM D0 - D35
* Wire per Clock Loading table/wiring Diagrams
RRAS
RAS: DDR SDRAM D0 - D35
RAS
CAS
CKE0
CKE1
WE
Notes:
RCAS
CAS: DDR SDRAM D0 - D35
CKE: DDR SDRAM D0 - D17
CKE: DDR SDRAM D18 - D35
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RCKE0
RCKE1
RWE
WE: DDR SDRAM D0 - D35
PCK
PCK
RESET
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD,VDDQ
TSTG
Value
-0.5 ~ 3.6
Unit
V
-1.0 ~ 3.6
V
-55 ~ +150
1.5 * # of component
50
°C
W
Power dissipation
PD
Short circuit current
IOS
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions (Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
2.7
Unit
Note
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
I/O Supply voltage
VDDQ
VREF
VTT
2.3
2.7
V
V
I/O Reference voltage
I/O Termination voltage(system)
VDDQ/2-50mV VDDQ/2+50mV
1
2
4
4
VREF-0.04
VREF+0.04
V
Input logic high voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
II
VREF+0.15
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
2
V
Input logic low voltage
-0.3
-0.3
0.3
-2
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input leakage current
V
V
3
uA
uA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver)
;VOUT = VTT + 0.84V
IOH
IOL
IOH
IOL
-16.8
16.8
-9
mA
mA
mA
mA
Output High Current(Normal strengh driver)
;VOUT = VTT - 0.84V
Output High Current(Half strengh driver)
;VOUT = VTT + 0.45V
Output High Current(Half strengh driver)
;VOUT = VTT - 0.45V
9
Notes : 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on
VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise
coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz.
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
DDR SDRAM IDD spec table
M312L6523BZ0 [ (64M x 8) * 9 , 512MB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
B3 (DDR333@CL=2.5)
A2 (DDR266@CL=2)
B0 (DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1,880
2,100
420
1,490
1,720
350
1,490
1,720
350
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
1,020
600
770
770
480
480
650
570
570
1,200
2,370
2,420
3,000
420
950
950
1,850
1,900
2,660
350
1,850
1,900
2,660
350
IDD6
Normal
Low power
IDD7A
410
330
330
mA Optional
mA
4,260
3,560
3,560
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M312L2923BZ0 [ (64M x 8) * 18 , 1GB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
B3 (DDR333@CL=2.5)
A2 (DDR266@CL=2)
B0 (DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
2,450
2,680
590
2,190
2,370
540
2,190
2,370
540
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
1,420
950
1,290
810
1,290
810
1,040
1,780
2,810
3,040
3,580
590
990
990
1,650
2,420
2,550
3,360
540
1,650
2,420
2,550
3,360
540
IDD6
Normal
Low power
IDD7A
560
510
510
mA Optional
mA
4,930
4,170
4,170
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
DDR SDRAM IDD spec table
M312L2920BZ0 [ (128M x 4) * 18 , 1GB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
B3 (DDR333@CL=2.5)
A2 (DDR266@CL=2)
B0 (DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
3,000
3,450
470
2,610
2,970
420
2,610
2,970
420
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
1,290
830
1,170
690
1,170
690
920
870
870
1,650
3,720
4,170
5,250
670
1,530
3,060
3,330
4,950
420
1,530
3,060
3,330
4,950
420
IDD6
Normal
Low power
IDD7A
430
380
380
mA Optional
mA
7,950
6,570
6,570
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M312L5720BZ0 [ (128M x 4) * 36, 2GB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
B3 (DDR333@CL=2.5)
A2 (DDR266@CL=2)
B0 (DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
4,030
4,480
680
3,630
3,990
630
3,630
3,990
630
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
1,960
1,400
1,580
2,680
4,750
5,200
6,280
680
1,830
1,170
1,530
2,550
4,080
4,350
5,970
630
1,830
1,170
1,530
2,550
4,080
4,350
5,970
630
IDD6
Normal
Low power
IDD7A
610
560
560
mA Optional
mA
8,980
7,590
7,590
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
AC Operating Conditions
Max
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VREF + 0.31
3
3
1
2
VREF - 0.31
VDDQ+0.6
V
0.7
V
Input Crossing Point Voltage, CK and CK inputs
0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
M312L6523BZ0, M312L2920BZ0
Unit
Parameter
Symbol
Min
9
Max
11
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
9
11
Input capacitance( CS0)
9
11
Input capacitance( CLK0, CLK0 )
11
10
10
10
12
11
Input capacitance(DM0~DM8)
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
11
11
M312L2923BZ0, M312L5720BZ0
Unit
Parameter
Symbol
Min
9
Max
11
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
9
11
Input capacitance( CS0, CS1)
9
11
Input capacitance( CLK0, CLK0 )
11
13
13
13
12
15
15
15
Input capacitance(DM0~DM8)
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
AC Timming Parameters & Specifications
B3
A2
B0
Sym-
bol
Uni
t
(DDR333@CL=2.5))
(DDR266@CL=2)
(DDR266@CL=2.5)
Parameter
Note
Min
60
Max
Min
65
Max
Min
65
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
Refresh row cycle time
Row active time
72
75
75
42
70K
45
120K
45
120K
RAS to CAS delay
18
20
20
Row precharge time
Row active to Row active
18
20
20
tRRD
12
15
15
15
15
15
ns
ns
Write recovery time
tWR
tWTR
tCCD
Last data in to Read com-
mand
1
1
1
1
1
1
tCK
tCK
Col. address to Col. address
CL=2.0
Clock cycle time
CL=2.5
7.5
6
12
12
7.5
7.5
12
12
10
12
12
ns
ns
tCK
7.5
Clock high level width
Clock low level width
tCH
tCL
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
DQS-out access time from
tDQSCK
-0.6
-0.7
-
+0.6
+0.7
0.4
-0.75
-0.75
-
+0.75
+0.75
0.5
-0.75
-0.75
-
+0.75
+0.75
0.5
ns
ns
ns
Output data access time
Data strobe edge to ouput
tAC
tDQSQ
12
Read Preamble
tRPRE
tRPST
tDQSS
tWPRE
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
tCK
Read Postamble
CK to valid DQS-in
DQS-in setup time
0.75
1.25
0.75
1.25
0.75
1.25
0
0
0
ns
3
DQS-in hold time
tWPRE
tDSS
0.25
0.2
0.25
0.2
0.25
0.2
tCK
tCK
DQS falling edge to CK ris-
DQS falling edge from CK
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
DQS-in low level width
DQS-in cycle time
tDQSH
tDQSL
tDSC
tIS
0.35
0.35
0.9
0.35
0.35
0.9
0.35
0.35
0.9
tCK
tCK
tCK
1.1
1.1
1.1
Address and Control Input
i,5.7~
i,5.7~
0.75
0.75
0.8
0.9
0.9
1.0
1.0
0.9
0.9
1.0
1.0
ns
ns
Address and Control Input
Address and Control Input
Address and Control Input
tIH
tIS
tIH
ns i, 6~9
ns i, 6~9
0.8
Data-out high impedence
time from CK/CK
tHZ
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
ns
1
1
Data-out low impedence
time from CK/CK
tLZ
-0.7
0.5
0.5
-0.75
0.5
-0.75
0.5
ns
V/
Input Slew Rate(for input
tSL(I)
Input Slew Rate(for I/O pins) tSL(IO)
V/
ns
0.5
0.5
Output Slew Rate(x4,x8)
tSL(O)
tSLMR
V/
1.0
4.5
1.5
1.0
4.5
1.5
1.0
4.5
1.5
Output Slew Rate Matching
0.67
0.67
0.67
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
B3
A2
B0
(DDR266@CL=2.5)
(DDR333@CL=2.5))
(DDR266@CL=2)
Parameter
Symbol
Unit Note
Min
12
Max
Min
15
Max
Min
15
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
ns
0.45
0.5
0.5
ns
ns
j, k
j, k
tDH
0.45
2.2
0.5
2.2
0.5
2.2
Control & Address input
tIPW
ns
8
8
DQ & DM input pulse width
Power down exit time
tDIPW
tPDEX
1.75
6
1.75
7.5
1.75
7.5
ns
ns
Exit self refresh to non-Read
tXSNR
75
75
75
ns
Exit self refresh to read com- tXSRD
200
200
200
tCK
us
Refresh interval time
tREFI
tQH
7.8
-
7.8
-
7.8
-
4
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
ns
11
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
Clock half period
tHP
-
-
-
ns 10, 11
Data hold skew factor
tQHS
0.5
0.6
0.75
0.6
0.75
0.6
ns
11
2
DQS write postamble time
tWPST
0.4
18
0.4
20
0.4
20
tCK
Active to Read with Auto pre-
charge
command
tRAP
tDAL
Autoprecharge write recov-
ery +
(tWR/tCK)
+
(tWR/tCK)
+
(tWR/tCK)
+
tCK
13
Precharge time
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure
proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR333
DDR266
DDR200
PARAMETER
SYMBOL
DCSLEW
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
MIN
0.5
MAX
4.0
Units
V/ns
Notes
a, m
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tIS
0
tIH
0
Units
ps
Notes
i
i
i
0.4 V/ns
+50
+100
0
ps
0.3 V/ns
0
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tDS
0
tDH
0
Units
ps
Notes
k
k
k
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
+/- 0.0 V/ns
tDS
0
tDH
0
Units
ps
Notes
j
j
j
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g,h
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g,h
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS DDR333
DDR266
PARAMETER
Output Slew Rate Matching Ratio (Pullup to Pulldown)
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
Notes
e,m
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
Test point
Output
50Ω
VSSQ
Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
VDDQ
50Ω
Output
Test point
Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotony.
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Command Truth Table
A0 ~ A9
Note
COMMAND
CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP
A11, A12
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
X
3
Bank Active & Row Addr.
H
V
Row Address
(A0~A9, A11,A12)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
4
4
Column
Address
H
X
L
H
L
H
V
V
H
Write &
Column Address
L
4
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
H
L
Entry
H
Precharge Power Down Mode
X
H
L
Exit
L
H
H
H
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
X
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
Physical Dimensions: 64Mx72 (M312L6523BZ0)
Units : Millimeters
133.35 A
128.95 A
1.27 +/-0.1
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
2x DIA. 2.50 +0.1/-0.00 N
1
a
b
92
2.99 MAX
6.35
64.77 P2
49.53 P3
120.65 P1
93
184
6.35 X
X1
X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
1.27
MAX 0.178 D1
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8 DDR SDRAM, FBGA
DDR SDRAM Part No. : K4H510838B-Z***,
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
Physical Dimensions: 128Mx72 (M312L2923BZ0), (M312L2920BZ0)
Units : Millimeters
133.35 A
128.95 A
1.27 +/-0.1
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
2x DIA. 2.50 +0.1/-0.00 N
1
a
b
92
3.99 MAX
6.35
64.77 P2
49.53 P3
120.65 P1
93
184
6.35 X
X1
X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
1.27
MAX 0.178 D1
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8, 128Mx4 DDR SDRAM, FBGA
DDR SDRAM Part No. : K4H510838B-Z***, K4H510438B-Z***
Revision 1.2 Oct. 2004
512MB, 1GB, 2GB Registered DIMM Pb-Free
DDR SDRAM
Physical Dimensions: 256Mx72 (M312L5720BZ0)
Units : Millimeters
133.35 A
128.95 A
1.27 +/-0.1
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
1 2x DIA. 2.50 +0.1/-0.00 N
a
b
92
3.99 MAX
6.35
64.77 P2
49.53 P3
120.65 P1
93
184
6.35 X
X1 X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
1.27
MAX 0.178 D1
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 128Mx4 DDR SDRAM, FBGA
DDR SDRAM Part No : K4H510438B-Z***
Revision 1.2 Oct. 2004
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