M312L3310CT0-LA2 [SAMSUNG]

DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184;


型号：	M312L3310CT0-LA2
厂家：	SAMSUNG
描述：	DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184 时钟动态存储器双倍数据速率内存集成电路
文件：	总14页 (文件大小：93K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

256MB DDR SDRAM MODULE

(32Mx72 based on 32Mx4 DDR SDRAM)

Registered 184pin DIMM

72-bit ECC/Parity

Revision 0.1

May. 2002

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

Revision History

Revision 0.0 (Oct. 2001)

1. First release

Revision 0.1 (May. 2002)

1.Change pin location of A13 from pin 103 to pin 167

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

M312L3310CT0 DDR SDRAM 184pin DIMM

32Mx72 DDR SDRAM 184pin DIMM based on 32Mx4

GENERAL DESCRIPTION

FEATURE

• Performance range

The Samsung M312L3310CT0 is 32M bit x 72 Double Data

Rate SDRAM high density memory modules based on first

generation of 128Mb DDR SDRAM respectively. The Samsung

M312L3310CT0 consists of eighteen CMOS 32M x 4 bit with

4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)

packages, mounted on a 184pin glass-epoxy substrate. Four

0.1uF decoupling capacitors are mounted on the printed circuit

board in parallel for each DDR SDRAM. The M312L3310CT0

is Dual In-line Memory Modules and intended for mounting into

184pin edge connector sockets.

Part No.

Max Freq.

Interface

M312L3310CT0-C(L)A2

133MHz(7.5ns@CL=2)

M312L3310CT0-C(L)B0 133MHz(7.5ns@CL=2.5)

M312L3310CT0-C(L)A0 100MHz(10ns@CL=2)

SSTL_2

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

Synchronous design allows precise cycle control with the use

of system clock. Data I/O transactions are possible on both

edges of DQS. Range of operating frequencies, programmable

latencies and burst lengths allow the same device to be useful

for a variety of high bandwidth, high performance memory sys-

tem applications.

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)

• Serial presence detect with EEPROM

•

PCB : Height 1700 (mil), double sided component

PIN CONFIGURATIONS (Front side/back side)

PIN DESCRIPTION

Pin Front Pin Front Pin

Front

Back

Pin Name

Function

VREF

DQ0

DQ24

VSS

DQ25

DQS3

VDDQ

/WE

VSS

DQ4

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

VSS

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

/RAS

DQ45

VDDQ

/CS0

A0 ~ A11

Address input (Multiplexed)

Bank Select Address

Data input/output

BA0 ~ BA1

DQ0 ~ DQ63

CB0 ~ CB7

DQS0 ~ DQS17

CK0,CK0

CKE0

VSS

DQ41

/CAS

VSS

DQ5

DQ28

DQ29

VDDQ

DQS12

DQ1

VDDQ

DQS9

DQ6

Check bit(Data-in/data-out)

Data Strobe input/output

Clock input

DQS0

DQ2

*/CS1

DQS14

VSS

DQS5

DQ42

DQ43

VDD

DQ26

DQ27

DQ7

DQ3

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

VSS

DQ30

VSS

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

*A13

Clock enable input

Chip select input

CS0

/RESET

VSS

*/CS2

DQ48

DQ49

VSS

DQ31

CB4

RAS

Row address strobe

Column address strobe

Write enable

VSS

DQ8

CAS

VDDQ

DQ12

DQ13

DQS10

VDD

DQ14

DQ15

*CKE1

VDDQ

*BA2

DQ20

*A12

VSS

CB5

DQ9

CB0

CB1

VDD

DQS8

VDDQ

CK0

DQS1

VDDQ

*/CK2

*CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDD

Power supply (2.5V)

Power Supply for DQS(2.5V)

Ground

/CK0

VSS

VDD

VDDQ

16 *CK1

17 */CK1 48

DQS15

DQ54

DQ55

VDDQ

VSS

DQS17

A10

CB2

VSS

CB3

BA1

VSS

VREF

Power supply for reference

DQ10

DQ11

CKE0

CB6

Serial EEPROM Power

Supply ( 2.3V to 3.6V )

VDDSPD

VDDQ

CB7

KEY

VSS

DQ36

DQ37

VDD

DQ60

DQ61

VSS

VDDID

DQ56

DQ57

VDD

SDA

Serial data I/O

KEY

DQ32

VDDQ 85

22 VDDQ

SCL

Serial clock

145

146

147

148

149

150

151

152

153

DQ16

DQ17

DQS2

VSS

DQS16

DQ62

DQ63

VDDQ

SA0

SA0 ~ 2

VDDID

RESET

Address in EEPROM

VDD identification flag

Reset enable

DQ33

DQS4

DQ34

VSS

DQ21

A11

DQS7

DQ58

DQ59

VSS

DQS11

VDD

DQ22

DQS13

DQ38

DQ39

VSS

No connection

DQ18

* These pins are not used in this module.

BA0

SA1

DQ35

DQ40

SA2

VDDQ

DQ19

SDA

DQ23

DQ44

VDDSPD

SCL

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

Functional Block Diagram

VSS

RS0

DQS0

DQS9

(DM0)

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DQS2

DQS10

(DM1)

DQS

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D10

DQS11

(DM2)

DQS

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ20

DQ16

DQ17

DQ18

DQ19

DQ21

DQ22

DQ23

D11

DQS12

(DM3)

DQS3

DQS4

DQS5

DQS

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ28

DQ29

DQ30

DQ31

DQ24

DQ25

DQ26

DQ27

D12

DQS13

(DM4)

DQS

DQ36

DQ37

DQ38

DQ39

I/O 3

I/O 2

I/O 1

I/O 0

DQ32

DQ33

DQ34

DQ35

I/O 3

I/O 2

I/O 1

I/O 0

D13

DQS14

(DM5)

DQS

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ44

DQ45

DQ46

DQ47

DQ40

DQ41

DQ42

DQ43

D14

DQS15

(DM6)

DQS6

DQS

Serial PD

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

SCL

D15

SDA

DQS7

DQS8

DQS16

(DM7)

DQS

SA0 SA1 SA2

I/O 3

I/O 2

I/O 1

I/O 0

DQ56

DQ57

DQ58

DQ59

I/O 3

I/O 2

I/O 1

I/O 0

DQ60

DQ61

DQ62

DQ63

D16

V_DDSPD

SPD

DQS17

(DM8)

V_DD/V_DDQ

D0 - D17

DQS

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

CB4

CB5

CB6

CB7

CB0

CB1

CB2

CB3

D17

VREF

V_SS

D0 - D17

V_DDID

Strap: see Note 4

PLL*

CK0,CK0

RS0A

RS0B

RBA0 - RBAn

RA0 - RA12

RRAS

* Wire per Clock Loading table/wiring Diagrams

BA0 -BAn : SDRAMs DQ0 - D17

A0 -An : SDRAMs D0 - D17

BA0-BAN

A0-A12

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD ¹ VDDQ.

RAS : SDRAMs D0 - D17

CAS : SDRAMs DQ0 - D17

CKE : SDRAMs D0 - D8

CKE : SDRAMs D9 - D17

RAS

CAS

CKE0

RCAS

RCKE0A

RCKE0B

RWE

WE: SDRAMs D0 - D17

PCK

RESET

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

Absolute Maximum Rate

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V

, V

OUT

-0.5 ~ 3.6

Voltage on V

& V

supply relative to V

, V

-1.0 ~ 3.6

-55 ~ +150

°C

DDQ

Storage temperature

Power dissipation

Short circuit current

STG

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter

Supply voltage(for device with a nominal VDD of 2.5V)

I/O Supply voltage

Symbol

VDD

Min

2.3

Max

2.7

Unit

Note

VDDQ

2.3

2.7

I/O Reference voltage

VREF

VDDQ/2-50mV VDDQ/2+50mV

I/O Termination voltage(system)

Input logic high voltage

VREF-0.04

VREF+0.04

VDDQ+0.3

VREF-0.15

VDDQ+0.3

VDDQ+0.6

1.35

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

VIX(DC)

VREF+0.15

Input logic low voltage

-0.3

0.3

1.15

-2

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

Input crossing point voltage, CK and CK inputs

Input leakage current

Output leakage current

IOZ

-5

Output High Current(Normal strengh driver)

IOH

IOL

IOH

-16.8

16.8

-9

= V + 0.84V

OUT

Output High Current(Normal strengh driver)

;V = V - 0.84V

OUT

Output High Current(Half strengh driver)

;V = V + 0.45V

OUT

Output High Current(Half strengh driver)

;V = V - 0.45V

IOL

OUT

Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled

TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.

2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

DDR SDRAM SPEC Items and Test Conditions

Conditions

Symbol

IDD0

Operating current - One bank Active-Precharge;

tRC=tRCmin;

DQ,DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating current - One bank operation ; One bank open, BL=4, Reads

IDD1

- Refer to the following page for detailed test condition

Percharge power-down standby current; All banks idle; power - down mode;

CKE = <VIL(max); Vin = Vref for DQ,DQS and DM

IDD2P

IDD2F

Precharge Floating standby current; CS# > =VIH(min);All banks idle;

CKE > = VIH(min); Address and other control inputs changing once per clock cycle;

Vin = Vref for DQ,DQS and DM

Precharge Quiet standby current; CS# > = VIH(min); All banks idle;

CKE > = VIH(min);

IDD2Q

Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);

Vin = Vref for DQ ,DQS and DM

Active power - down standby current ; one bank active; power-down mode;

CKE=< VIL (max); Vin = Vref for DQ,DQS and DM

IDD3P

IDD3N

Active standby current; CS# >= VIH(min); CKE>=VIH(min);

one bank active; active - precharge; tRC=tRASmax;

DQ, DQS and DM inputs changing twice per clock cycle;

address and other control inputs changing once per clock cycle

Operating current - burst read; Burst length = 2; reads; continguous burst;

One bank active; address and control inputs changing once per clock cycle;

50% of data changing at every burst; lout = 0 m A

IDD4R

IDD4W

Operating current - burst write; Burst length = 2; writes; continuous burst;

One bank active address and control inputs changing once per clock cycle;

DQ, DM and DQS inputs changing twice

per clock cycle, 50% of input data changing at every burst

Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,

IDD5

10*tCK for DDR266A & DDR266B at 133Mhz ; distributed refresh

Self refresh current; CKE =< 0.2V; External clock should be on;

IDD6

tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B

Orerating current - Four bank operation ; Four bank interleaving with BL=4

IDD7A

-Refer to the following page for detailed test condition

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

DDR SDRAM I_DDspec table

(Vdd = 2.7V, T= 10’ C)

A2( DDR266@CL=2 )

B0(DDR266@CL=2.5)

Symbol

B3(DDR333@CL=2.5)

A0(DDR200@CL=2)

Unit

Notes

IDD0

IDD1

3001

3476

1163

1615

1417

1773

2130

4189

4506

4743

1140

1120

7119

2704

3060

1171

1555

1377

1813

2090

3694

4070

4466

1140

1120

6248

2605

2961

1169

1469

1377

1734

2011

3318

3595

4308

1140

1120

5654

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

IDD6

Normal

Low power

IDD7A

Optional

* Module I_DDwas calculated on the basis of component I_DDand can be differently measured according to DQ loading cap.

< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >

IDD1 : Operating current: One bank operation

1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. lout = 0mA

2. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

IDD7A : Operating current: Four bank operation

1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not

changing. lout = 0mA

2. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK

Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK,Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

AC Operating Conditions

Max

Parameter/Condition

Symbol

Min

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

VIH(AC) VREF + 0.31

VIL(AC)

VREF - 0.31

VDDQ+0.6

VID(AC) 0.7

Input Crossing Point Voltage, CK and CK inputs

VIX(AC) 0.5*VDDQ-0.2

0.5*VDDQ+0.2

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.

DDQ

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-

tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)

Parameter

Input reference voltage for Clock

Input signal maximum peak swing

Value

0.5 * VDDQ

1.5

Unit

Note

Input Levels(VIH/VIL)

VREF+0.31/VREF-0.31

Input timing measurement reference level

Output timing measurement reference level

Output load condition

VREF

Vtt

See Load Circuit

Vtt=0.5*VDDQ

RT=50W

Output

Z0=50W

VREF

=0.5*VDDQ

CLOAD=30pF

Output Load Circuit (SSTL_2)

Input/Output CAPACITANCE (VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE )

CIN1

Input capacitance(CKE0)

CIN2

CIN3

Input capacitance(CS0)

Input capacitance(CLK0, CLK0)

Input capacitance(DM0~DM8)

CIN4

CIN5

Data & DQS input/output capacitance(DQ0~DQ63)

Data input/output capacitance(CB0~CB7)

COUT1

COUT2

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)

-TCA2(DDR266A) -TCB0(DDR266B) -TCA0 (DDR200)

Parameter

Symbol

Unit

Note

Min

Max

Min

Max

Min

Max

Row cycle time

tRC

tRFC

tRAS

tRCD

tRP

Refresh row cycle time

Row active time

120K

RAS to CAS delay

Row precharge time

Row active to Row active delay

Write recovery time

tRRD

tWR

Last data in to Read command

Col. address to Col. address delay

tCDLR

tCCD

tCK

CL=2.0

CL=2.5

7.5

0.45

-0.75

Clock cycle time

tCK

7.5

0.45

-0.75

Clock high level width

tCH

tCL

0.55

+0.75

0.5

0.55

+0.75

0.5

0.45

-0.8

0.55

+0.8

0.6

tCK

Clock low level width

DQS-out access time from CK/CK

tDQSCK

tAC

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPRE

tDSS

0.9

0.4

0.75

1.1

0.9

0.4

0.75

1.1

0.9

0.4

0.75

1.1

tCK

Read Postamble

0.6

CK to valid DQS-in

1.25

DQS-in setup time

DQS-in hold time

0.25

0.2

0.35

0.25

0.2

0.35

0.25

0.2

0.35

tCK

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold time

DQS-in high level width

tDSH

tDQSH

DQS-in low level width

tDQSL

tDSC

tIS

0.35

0.9

0.35

0.9

0.35

0.9

1.1

-0.8

0.5

1.0

0.7

tCK

DQS-in cycle time

1.1

Address and Control Input setup time(fast)

Address and Control Input hold time(fast)

Address and Control Input setup time(slow)

Address and Control Input hold time(slow)

Data-out high impedence time from CK/CK

Data-out low impedence time from CK/CK

Input Slew Rate(for input only pins)

Input Slew Rate(for I/O pins)

0.9

tIH

0.9

tIS

1.0

tIH

1.0

tHZ

-0.75

0.5

+0.75

-0.75

0.5

+0.75

+0.8

tLZ

tSL(I)

tSL(IO)

tSL(O)

V/ns

0.5

Output Slew Rate(x4,x8)

1.0

4.5

1.0

4.5

Output Slew Rate(x16)

tSL

0.7

(O)

Output Slew Rate Matching Ratio(rise to fall)

0.67

1.5

0.67

1.5

0.67

1.5

SLMR

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

-TCA2(DDR266A)

-TCB0(DDR266B)

-TCA0 (DDR200)

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

Mode register set cycle time

DQ & DM setup time to DQS

DQ & DM hold time to DQS

tMRD

tDS

0.5

1.75

7.5

0.5

1.75

7.5

0.6

7,8,9

tDH

DQ & DM input pulse width

tDIPW

tPDEX

tXSNR

tXSRD

tREFI

Power down exit time

Exit self refresh to non-Read command

Exit self refresh to read command

200

15.6

7.8

200

15.6

7.8

200

15.6

7.8

tCK

64Mb, 128Mb

Refresh interval time

256Mb

tHP

Output DQS valid window

Clock half period

tQH

tHP

-tQHS

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

Data hold skew factor

tQHS

0.75

0.6

0.75

0.6

0.8

0.6

DQS write postamble time

tWPST

0.4

tCK

Autoprecharge write recovery +

Precharge time

(tWR/tCK)

tDAL

tCK

(tRP/tCK)

1. Maximum burst refresh of 8

2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from

High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,

DQS could be High at this time, depending on tDQSS.

3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,

but system performance (bus turnaround) will degrade accordingly.

4. A write command can be applied with tRCD satisfied after this command.

5. For registered DIMMs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period

jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

6. Input Setup/Hold Slew Rate Derating

Input Setup/Hold Slew Rate

DtIS

(ps)

DtIH

(ps)

(V/ns)

0.5

0.4

+50

0.3

+100

This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate

IS IH

based on the lesser of AC-AC slew rate and DC-DC slew rate.

7. I/O Setup/Hold Slew Rate Derating

I/O Setup/Hold Slew Rate

DtDS

(ps)

DtDH

(V/ns)

0.5

(ps)

0.4

+75

+150

+75

0.3

+150

This derating table is used to increase t /t

in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate

DS DH

based on the lesser of AC-AC slew rate and DC-DC slew rate.

8. I/O Setup/Hold Plateau Derating

I/O Input Level

(mV)

DtDS

(ps)

DtDH

(ps)

± 280

+50

This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of

up to 2ns.

9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating

Delta Rise/Fall Rate

DtDS

(ps)

DtDH

(ps)

(ns/V)

±0.25

±0.5

+50

+100

+50

+100

This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate

is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall

Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.

10. This parameter is fir system simulation purpose. It is guranteed by design.

11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.

<Note>

The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.

CK slew rate

DtIH/tIS

DtDSS/tDSH

DtAC/tDQSCK

DtLZ(min)

DtHZ(max)

(Single ended)

(ps)

1.0V/ns

0.75V/ns

0.5V/ns

+50

+100

+50

+100

+50

+100

-50

-100

+50

+100

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

Command Truth Table

COMMAND

(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)

A11

A9 ~ A0

CKEn-1

CKEn

RAS

CAS

BA0,1

A10/AP

Note

Extended MRS

OP CODE

1, 2

Mode Register Set

Auto Refresh

Entry

Refresh

Self

Refresh

Exit

Bank Active & Row Addr.

Row Address

Column

Address

Read &

Column Address

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

(A0~A9 , A1 1)

Column

Address

Write &

Column Address

(A0~A9, A11 )

4, 6

Burst Stop

Precharge

Bank Selection

All Banks

Entry

Exit

Active Power Down

Entry

Precharge Power Down Mode

Exit

No operation (NOP) : Not defined

Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

PACKAGE DIMENSIONS

Units : Inches (Millimeters)

5.25 ± 0.006

(133.350 ± 0.15)

0.118

(3.00)

5.171

(131.350)

5.077

(128.950)

REG

PLL

0.0787

R (2.00)

0.78

(19.80)

2.500

0.10

0.157 Max

(3.99 Max)

REG

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

(6.350)

0.157

(4.00)

0.039 ± 0.002

(1.000 ± 0.050)

0.26

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00)

Detail A

0.10 M

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 32Mx4 SDRAM, TSOP

SDRAM Part NO : K4H280438C

Rev. 0.1 May. 2002

184pin 1U Registered DDR SDRAM MODULE

M312L3310CT0

184 Pin DDR Registered DIMM Clock Topolgy

0ns (nominal)

SDRAM

stack

PLL

R=120

OUT1

CK0

120W

Probe point

CK0

Reg1 SDRAM

stack

Clock Reference Net

R=240

120

OUT ‘N’

0.266

128

1.0

Reg2

feedback

1.5pF

R=240

Note : Lenghts in inches

Z0=60

tD=2.2ns/ft

Note *

Notes* :

1. The Clock delay from the input of the PLL clock to the input of any SDRAM or register will be set to 0ns(nominal).

2. Input,output, and feedback clock lines are terminated from line to leine as shown, and not from line to ground.

3. Only one PLL output is shown per output type. Any addtional PLL outputs will be wired in a similar maner.

4. termination resistors for the PLL feedback path clocks are loacted after the pins of the PLL.

Rev. 0.1 May. 2002

M312L3310CT0-LA2 [SAMSUNG]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E