M368L3223HUS-CCCT_技术文档

256MB, 512MB Unbuffered DIMM

DDR SDRAM

DDR SDRAM Unbuffered Module

184pin Unbuffered Module based on 256Mb H-die

with 64/72-bit Non ECC/ECC

66 TSOP-II with Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

Table of Contents

1.0 Ordering Information................................................................................................................... 4

2.0 Operating Frequencies ............................................................................................................... 4

3.0 Feature ......................................................................................................................................... 4

4.0 Pin Configuration (Front side/back side) ................................................................................ 5

5.0 Pin Description ........................................................................................................................... 5

6.0 Functional Block Diagram ......................................................................................................... 6

6.1 256MB, 32M x 64 Non ECC Module (M368L3223HUS) ...................................................................... 6

6.2 256MB, 32M x 72 ECC Module (M381L3223HUM) ............................................................................ 7

6.3 512MB, 64M x 64 Non ECC Module (M368L6423HUN) ....................................................................... 8

6.4 512MB, 64M x 72 ECC Module (M381L6423HUM) ............................................................................ 9

7.0 Absolute Maximum Ratings ..................................................................................................... 10

8.0 DC Operating Conditions ......................................................................................................... 10

9.0 DDR SDRAM IDD spec table .................................................................................................... 11

9.1 M368L3223HUS [ (32M x 8) * 8, 256MB Non ECC Module ] ............................................................. 11

9.2 M381L3223HUM [ (32M x 8) * 9, 256MB ECC Module ] .................................................................... 11

9.3 M368L6423HUN [ (32M x 8) * 16, 512MB Non ECC Module ] ............................................................ 12

9.4 M381L6423HUM [ (32M x 8) * 18, 512MB ECC Module ]................................................................... 12

10.0 AC Operating Conditions........................................................................................................ 13

11.0 Input/Output Capacitance ...................................................................................................... 13

12.0 AC Timming Parameters & Specifications ........................................................................... 14

13.0 System Characteristics for DDR SDRAM ............................................................................. 15

14.0 Component Notes ................................................................................................................... 16

15.0 System Notes: ......................................................................................................................... 17

16.0 Command Truth Table ............................................................................................................ 18

17.0 Physical Dimensions .............................................................................................................. 19

17.1 32Mx64 (M368L3223HUS) ........................................................................................................ 20

17.2 32Mx72 (M381L3223HUM) ....................................................................................................... 21

17.3 64Mx64 (M368L6423HUS) ........................................................................................................ 22

17.4 64Mx72 (M381L6423HUM) ....................................................................................................... 23

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

Revision History

Revision

0.0

Month

July

Year

2005

History

- First version for internal review.

- Revision 1.0

1.0

November

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

184Pin Unbuffered DIMM based on 256Mb H-die (x8)

1.0 Ordering Information

Part Number

Density

Organization

32M x 64

32M x 72

64M x 64

64M x 72

Component Composition

Height

1,250mil

M368L3223HUS-C(L)CC/B3

M381L3223HUM-C(L)CC/B3

M368L6423HUN-C(L)CC/B3

M381L6423HUM-C(L)CC/B3

32Mx8 (K4H560838H) * 8EA

32Mx8 (K4H560838H) * 9EA

32Mx8 (K4H560838H) * 16EA

32Mx8 (K4H560838H) * 18EA

256MB

512MB

2.0 Operating Frequencies

CC(DDR400@CL=3)

B3(DDR333@CL=2.5)

Speed @CL2

Speed @CL2.5

Speed @CL3

CL-tRCD-tRP

-

133MHz

166MHz

-

166MHz

200MHz

3-3-3

2.5-3-3

3.0 Feature

• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333

• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1,250 (mil) & single (128MB, 256MB), double (512GB) sided

• SSTL_2 Interface

• 66pin TSOP II Pb-Free package

• RoHS compliant

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

4.0 Pin Configuration (Front side/back side)

1

Front

VREF

DQ0

VSS

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

Front

A5

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

Front

VDDQ

WE

93

Back

VSS

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

Back

VSS

A6

DQ28

DQ29

VDDQ

DM3

A3

DQ30

VSS

DQ31

CB4

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

RAS

DQ45

VDDQ

CS0

CS1

DM5

2

3

4

5

6

7

8

9

DQ24

VSS

DQ25

DQS3

A4

VDD

DQ26

DQ27

A2

VSS

A1

CB0

CB1

VDD

DQS8

A0

94

95

96

97

98

99

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

NC

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

*BA2

DQ20

A12

VSS

DQ21

A11

DM2

VDD

DQ22

A8

DQ41

CAS

VSS

DQ1

DQS0

DQ2

VDD

DQ3

NC

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

DQS5

DQ42

DQ43

VDD

*CS2

DQ48

DQ49

VSS

*CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

VSS

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

DQ46

DQ47

*CS3

VDDQ

DQ52

DQ53

*A13

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

CB5

VDDQ

CK0

VDD

DM6

VSS

DM8

A10

CB6

VDDQ

CB7

CK1

VSS

DQ54

DQ55

VDDQ

NC

DQ60

DQ61

VSS

CB2

VSS

CB3

BA1

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

KEY

53

54

55

56

57

58

59

60

61

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

145

146

147

148

149

150

151

152

153

VSS

DQ36

DQ37

VDD

DM7

DQS7

DQ58

DQ59

VSS

NC

SDA

DQ62

DQ63

VDDQ

SA0

SA1

SA2

A9

DQ18

A7

VDDQ

DQ19

DM4

DQ38

DQ39

VSS

SCL

DQ23

DQ44

VDDSPD

Note :

1. * : These pins are not used in this module.

2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module ( M381~ ), and are not used on x64 module.

3. Pins 111, 158 are NC for 1row modules & used for 2row modules.

4. Pins 137, 138 are NC for x16 1Row module.

5.0 Pin Description

Pin Name

Function

Pin Name

Function

A0 ~ A12

Address input (Multiplexed)

DM0 ~7,8(for ECC) Data - in mask

Power supply

BA0 ~ BA1A

Bank Select Address

VDD

(2.5V for DDR333, 2.6V for DDR400)

Power Supply for DQS

(2.5V for DDR333, 2.6V for DDR400)

DQ0 ~ DQ63

Data input/output

VDDQ

DQS0 ~ DQS8

CK0,CK0 ~ CK2, CK2

CKE0, CKE1(for double banks) Clock enable input

CS0, CS1(for double banks)

Data Strobe input/output

Clock input

VSS

VREF

VDDSPD

SDA

Ground

Power supply for reference

Serial EEPROM Power/Supply ( 2.3V to 3.6V )

Serial data I/O

Chip select input

RAS

CAS

WE

Row address strobe

Column address strobe

Write enable

SCL

Serial clock

SA0 ~ 2

VDDID

NC

Address in EEPROM

VDD, VDDQ level detection

No connection

CB0 ~ CB7(for x72 module)

Check bit(Data-in/data-out)

Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

6.0 Functional Block Diagram

6.1 256MB, 32M x 64 Non ECC Module (M368L3223HUS)

(Populated as 1 bank of x8 DDR SDRAM Module)

CS0

DQS0

DM0

DQS4

DM4

DM/

CS DQS

DM/

CS DQS

Serial PD

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 6

I/O 4

I/O 2

I/O 0

I/O 7

I/O 5

I/O 3

I/O 1

I/O 7

SCL

WP

I/O 4

I/O 1

I/O 3

I/O 6

I/O 5

I/O 0

I/O 2

D0

D4

SDA

A0

A1

A2

SA0 SA1

SA2

DQS1

DM1

DQS5

DM5

DM/

CS DQS

DM/

CS DQS

V

SPD

DDSPD

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 5

I/O 1

I/O 0

I/O 6

I/O 4

I/O 3

I/O 2

I/O 6

I/O 4

I/O 3

I/O 1

I/O 7

I/O 5

I/O 2

I/O 0

D0 - D7

DQ9

/V

D1

D5

DD DDQ

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D0 - D7

VREF

D0 - D7

V

SS

DQS2

DM2

DQS6

DM6

D3/D0/D5

DM/

CS DQS

DM/

CS DQS

Cap/Cap/Cap

Cap/D1/D6

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 6

I/O 5

I/O 3

I/O 0

I/O 7

I/O 4

I/O 2

I/O 1

I/O 7

I/O 5

I/O 1

I/O 0

I/O 6

I/O 4

I/O 3

I/O 2

D2

D6

R=120Ω

CK0/1/2

Card

Edge

CK0/1/2

Cap/Cap/Cap

D4/D2/C7

DQS3

DM3

DQS7

DM7

Cap

Cap/Cap/Cap

DM/

CS DQS

DM/

CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 4

I/O 2

I/O 1

I/O 6

I/O 5

I/O 3

I/O 0

I/O 5

I/O 4

I/O 1

I/O 0

I/O 7

I/O 6

I/O 3

I/O 2

D3

D7

Notes :

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

* Clock Wiring

DDR SDRAMs

BA0 - BA1

A0 - A12

RAS

BA0-BA1 : DDR SDRAMs D0 - D7

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

Clock

Input

A0-A12 : DDR SDRAMs D0 - D7

RAS : DDR SDRAMs D0 - D7

CAS : DDR SDRAMs D0 - D7

CKE : DDR SDRAMs D0 - D7

WE : DDR SDRAMs D0 - D7

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +

5%

*CK0/CK0 2 DDR SDRAMs

*CK1/CK1 3 DDR SDRAMs

*CK2/CK2 3 DDR SDRAMs

CAS

CKE0

WE

*Clock Net Wiring

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

6.2 256MB, 32M x 72 ECC Module (M381L3223HUM)

(Populated as 1 bank of x8 DDR SDRAM Module)

CS0

DQS0

DM0

DQS4

DM4

DM/

CS DQS

DM/

CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 6

I/O 4

I/O 2

I/O 0

I/O 7

I/O 5

I/O 3

I/O 1

I/O 7

Serial PD

I/O 4

I/O 3

I/O 0

I/O 6

I/O 5

I/O 2

I/O 1

D0

D4

SCL

WP

SDA

SPD

A0

A1

A2

SA0 SA1 SA2

DQS1

DM1

DQS5

DM5

DM/

CS DQS

DM/

CS DQS

V

DDSPD

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 5

I/O 1

I/O 0

I/O 6

I/O 4

I/O 3

I/O 2

I/O 6

I/O 4

I/O 3

I/O 2

I/O 7

I/O 5

I/O 1

I/O 0

D0 - D8

V

/V

DQ9

DD DDQ

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D0 - D8

VREF

D0 - D8

V

SS

DQS2

DM2

DQS6

DM6

D3/D0/D6

DM/

CS DQS

DM/

CS DQS

Cap/Cap/Cap

D4/D1/D7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 6

I/O 5

I/O 3

I/O 0

I/O 7

I/O 4

I/O 2

I/O 1

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D2

D6

R=120Ω

CK0/1/2

Card

Edge

Cap/Cap/Cap

D5/D2/D8

DQS3

DM3

DQS7

DM7

Cap/Cap/Cap

DM/

CS DQS

DM/

CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 4

I/O 3

I/O 1

I/O 6

I/O 5

I/O 2

I/O 0

I/O 5

I/O 4

I/O 1

I/O 0

I/O 7

I/O 6

I/O 3

I/O 2

D3

D7

DQS8

DM8

DM/

CS DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 5

I/O 4

I/O 3

I/O 1

I/O 7

I/O 6

I/O 2

I/O 0

D8

BA0 - BA1

A0 - A12

RAS

BA0-BA1 : DDR SDRAMs D0 - D8

A0-A12 : DDR SDRAMs D0 - D8

RAS : DDR SDRAMs D0 - D8

CAS : DDR SDRAMs D0 - D8

CKE : DDR SDRAMs D0 - D8

WE : DDR SDRAMs D0 - D8

Notes :

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

* Clock Wiring

DDR SDRAMs

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

Clock

Input

CAS

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +

5%

*CK0/CK0 3 DDR SDRAMs

*CK1/CK1 3 DDR SDRAMs

*CK2/CK2 3 DDR SDRAMs

CKE0

WE

*Clock Net Wiring

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

6.3 512MB, 64M x 64 Non ECC Module (M368L6423HUN)

(Populated as 2 bank of x8 DDR SDRAM Module)

CS1

CS0

DQS0

DM0

DQS4

DM4

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 0

I/O 1

I/O 6

I/O 5

I/O 2

I/O 3

I/O 4

I/O 7

I/O 6

I/O 1

I/O 2

I/O 5

I/O 4

I/O 3

I/O 0

D8

D4

D12

D0

DQS1

DM1

DQS5

DM5

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 5

I/O 6

I/O 1

I/O 0

I/O 7

I/O 4

I/O 3

I/O 2

I/O 1

I/O 6

I/O 7

I/O 0

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ9

D1

D9

D5

D13

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 5

I/O 4

I/O 1

I/O 0

I/O 7

I/O 6

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 2

I/O 5

I/O 4

I/O 3

I/O 0

I/O 2

I/O 3

I/O 6

I/O 7

I/O 0

I/O 1

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 5

I/O 2

I/O 3

I/O 4

I/O 7

D2

D10

D6

D14

DQS3

DM3

DQS7

DM7

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 5

I/O 6

I/O 1

I/O 0

I/O 7

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 1

I/O 6

I/O 7

I/O 0

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D3

D7

D11

D15

D3/D0/D5

V

SPD

DDSPD

D11/D8/D13

Serial PD

D0 - D15

/V

DD DDQ

R=120Ω

SCL

WP

*

Cap/D1/D6

CK0/1/2

SDA

D0 - D15

VREF

A0

A1

A2

Card

Edge

*

Cap/D9/D14

D0 - D15

V

SA0 SA1

SA2

SS

D4/D2/D7

D12/D10/D15

BA0 - BA1

A0 - A12

RAS

BA0-BA1 : DDR SDRAMs D0 - D15

A0-A12: DDR SDRAMs D0 - D15

RAS : DDR SDRAMs D0 - D15

Notes :

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

* Clock Wiring

DDR SDRAMs

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

Clock

Input

CAS

CKE 0/1

WE

CAS : DDR SDRAMs D0 - D15

CKE : DDR SDRAMs D0 - D15

WE : DDR SDRAMs D0 - D15

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors: 3 Ohms +

5%

*CK0/CK0 4 DDR SDRAMs

*CK1/CK1 6 DDR SDRAMs

*CK2/CK2 6 DDR SDRAMs

*Clock Net Wiring

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

6.4 512MB, 64M x 72 ECC Module (M381L6423HUM)

(Populated as 2 bank of x8 DDR SDRAM Module)

CS1

CS0

DQS0

DM0

DQS4

DM4

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D9

D4

D13

D0

DQS1

DM1

DQS5

DM5

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ9

D1

D10

D5

D14

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D2

D11

D15

D6

DQS3

DM3

DQS7

DM7

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D3

D7

D12

D16

DQS8

DM8

DM/

CS DQS

DM/

CS DQS

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D8

D17

D3/D0/D5

D12/D9/D14

R=120Ω

D8/D1/D6

V

SPD

DDSPD

Serial PD

CK0/1/2

SCL

WP

Card

Edge

D0 - D17

/V

DD DDQ

D17/D10/D15

D4/D2/D7

SDA

A0

A1

A2

D0 - D17

VREF

SA0 SA1

SA2

D0 - D17

V

D13/D11/D16

SS

Notes :

BA0 - BA1

A0 - A12

RAS

BA0-BA1 : DDR SDRAMs D0 - D17

A0-A12 : DDR SDRAMs D0 - D17

RAS : DDR SDRAMs D0 - D17

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

* Clock Wiring

DDR SDRAMs

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

Clock

Input

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors:3 Ohms +

5%

CAS

CKE0/1

WE

CAS : DDR SDRAMs D0 - D17

CKE : DDR SDRAMs D0 - D17

WE : DDR SDRAMs D0 - D17

*CK0/CK0 6 DDR SDRAMs

*CK1/CK1 6 DDR SDRAMs

*CK2/CK2 6 DDR SDRAMs

*Clock Net Wiring

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

7.0 Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V_SS

V_IN,V_OUT

-0.5 ~ 3.6

V

Voltage on V_DD& V_DDQsupply relative to V_SS

Storage temperature

Power dissipation

V_DD,V_DDQ

T_STG

P_D

-1.0 ~ 3.6

V

-55 ~ +150

°C

1.5 * # of component

50

W

Short circuit current

I_OS

mA

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

8.0 DC Operating Conditions

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter

Symbol

Min

Max

Unit Note

Supply voltage(for device with a nominal VDD of 2.5V for DDR333)

VDD

2.3

2.7

V

Supply voltage(for device with a nominal VDD of 2.6V for DDR400)

VDD

2.5

2.7

V

I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR333)

I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400)

I/O Reference voltage

VDDQ

VREF

V_TT

2.3

2.5

0.49*VDDQ

VREF-0.04

0.51*VDDQ

VREF+0.04

1

2

I/O Termination voltage(system)

Input logic high voltage

Input logic low voltage

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

V-I Matching: Pullup to Pulldown Current Ratio

Input leakage current

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

VI(Ratio)

II

VREF+0.15

-0.3

VDDQ+0.3

VREF-0.15

VDDQ+0.3

VDDQ+0.6

1.4

V

-0.3

0.36

0.71

-2

3

4

-

2

5

uA

mA

Output leakage current

Output High Current(Normal strengh driver) ;V_OUT= V_TT+ 0.84V

IOZ

-5

IOH

-16.8

Output High Current(Normal strengh driver) ;V_OUT= V_TT- 0.84V

Output High Current(Half strengh driver) ;V_OUT= V_TT+ 0.45V

Output High Current(Half strengh driver) ;V_OUT= V_TT- 0.45V

Note :

IOL

IOH

IOL

16.8

-9

mA

9

1. V_REFis expected to be equal to 0.5*V_DDQof the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on V_REFmay

not exceed +/-2% of the dc value.

2. V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to V_REF, and must track

variations in the DC level of V_REF

.

3. V_IDis the magnitude of the difference between the input level on CK and the input level on CK.

4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,

for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers

due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to

source voltages from 0.1 to 1.0.

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

9.0 DDR SDRAM IDD spec table

9.1 M368L3223HUS [ (32M x 8) * 8, 256MB Non ECC Module ]

(V_DD=2.7V, T = 10°C)

Symbol

IDD0

IDD1

CC(DDR400@CL=3)

B3(DDR333@CL=2.5)

Unit

Notes

840

1,040

32

720

920

24

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

240

200

280

440

1,200

1,360

24

200

400

520

1,360

1,440

24

Normal

Low power

IDD7A

IDD6

12

Optional

2,400

2,240

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

9.2 M381L3223HUM [ (32M x 8) * 9, 256MB ECC Module ]

(V_DD=2.7V, T = 10°C)

Symbol

IDD0

IDD1

CC(DDR400@CL=3)

B0(DDR333@CL=2.5)

Unit

Notes

945

1,170

36

810

1,035

27

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

270

225

450

315

585

495

1,530

1,620

27

1,350

1,530

27

Normal

Low power

IDD7A

IDD6

14

Optional

2,700

2,520

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

9.3 M368L6423HUN [ (32M x 8) * 16, 512MB Non ECC Module ]

(V_DD=2.7V, T = 10°C)

Symbol

IDD0

IDD1

CC(DDR400@CL=3)

B0(DDR333@CL=2.5)

Unit

mA

Notes

1,360

1,560

64

1,160

1,360

48

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

480

400

800

560

1,040

1,880

1,960

48

880

1,640

1,800

48

Normal

Low power

IDD7A

IDD6

24

Optional

2,920

2,680

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

9.4 M381L6423HUM [ (32M x 8) * 18, 512MB ECC Module ]

(V_DD=2.7V, T = 10°C)

Symbol

IDD0

IDD1

CC (DDR400@CL=3)

B3 (DDR333@CL=2.5)

Unit

Notes

1,530

1,755

72

1,305

1,530

54

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

540

450

900

630

1,170

2,115

2,205

54

990

1,845

2,025

54

Normal

Low power

IDD7A

IDD6

27

Optional

3,285

3,015

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

10.0 AC Operating Conditions

Parameter/Condition

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

Input Crossing Point Voltage, CK and CK inputs

Note :

Symbol

VIH(AC)

VIL(AC)

VID(AC)

Min

VREF + 0.31

Max

Unit

V

Note

3

1

2

VREF - 0.31

VDDQ+0.6

0.7

VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2

1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V_IXis expected to equal 0.5*V_DDQof the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in

simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

Vtt=0.5*VDDQ

RT=50Ω

Output

Z0=50Ω

CLOAD=30pF

VREF

=0.5*VDDQ

Output Load Circuit (SSTL_2)

11.0 Input/Output Capacitance

(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)

M368L3223HUS

Min Max

49 57

M381L3223HUM

Unit

Parameter

Symbol

Min

51

44

25

6

Max

60

53

30

7

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1

Input capacitance(CKE0)

Input capacitance( CS0)

Input capacitance( CLK0, CLK1,CLK2)

Input capacitance(DM0~DM7, DM8(for ECC))

Data & DQS input/output capacitance(DQ0~DQ63)

Data input/output capacitance (CB0~CB7)

pF

CIN2

CIN3

CIN4

CIN5

Cout1

Cout2

42

25

6

-

50

30

7

6

7

-

6

7

M368L6423HUN

Min Max

65 81

M381L6423HUM

Parameter

Symbol

Unit

Min

69

44

28

10

Max

87

53

34

12

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1

Input capacitance(CKE0,CKE1)

Input capacitance( CS0, CS1)

Input capacitance( CLK0, CLK1,CLK2)

Input capacitance(DM0~DM7, DM8(for ECC))

Data & DQS input/output capacitance(DQ0~DQ63)

Data input/output capacitance (CB0~CB7)

pF

CIN2

CIN3

CIN4

CIN5

Cout1

Cout2

42

28

10

-

50

34

12

-

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

12.0 AC Timming Parameters & Specifications

CC

(DDR400@CL=3.0)

B3

(DDR333@CL=2.5)

Parameter

Symbol

Unit

Note

Min

Max

Min

60

Max

Row cycle time

Refresh row cycle time

Row active time

RAS to CAS delay

Row precharge time

tRC

tRFC

tRAS

tRCD

tRP

55

ns

tCK

ns

70

40

15

72

70K

42

70K

18

Row active to Row active delay

Write recovery time

Last data in to Read command

tRRD

tWR

tWTR

10

15

2

-

6

5

12

15

1

7.5

6

CL=2.0

CL=2.5

CL=3.0

-

12

10

12

-

Clock cycle time

tCK

-

Clock high level width

Clock low level width

DQS-out access time from CK/CK

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

Read Postamble

CK to valid DQS-in

DQS-in setup time

DQS-in hold time

tCH

tCL

tDQSCK

tAC

0.45

-0.55

-0.65

-

0.9

0.4

0.72

0

0.25

0.2

0.35

0.6

0.7

-0.65

10

0.55

+0.55

+0.65

0.4

1.1

0.6

1.28

0.45

-0.6

-0.7

-

0.9

0.4

0.75

0

0.25

0.2

0.35

0.75

0.8

-0.7

12

0.55

+0.6

+0.7

0.45

1.1

tCK

ns

tCK

ns

tCK

ns

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPRE

tDSS

tDSH

tDQSH

tDQSL

tIS

tIH

tIS

tIH

tHZ

tLZ

tMRD

tDS

22

13

0.6

1.25

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold time

DQS-in high level width

DQS-in low level width

Address and Control Input setup time(fast)

Address and Control Input hold time(fast)

Address and Control Input setup time(slow)

Address and Control Input hold time(slow)

Data-out high impedence time from CK/CK

Data-out low impedence time from CK/CK

Mode register set cycle time

DQ & DM setup time to DQS

15, 17~19

16~19

11

+0.65

+0.7

11

0.4

0.45

j, k

ns

DQ & DM hold time to DQS

tDH

0.4

0.45

Control & Address input pulse width

DQ & DM input pulse width

Exit self refresh to non-Read command

Exit self refresh to read command

Refresh interval time

tIPW

tDIPW

tXSNR

tXSRD

tREFI

2.2

1.75

75

2.2

1.75

75

ns

tCK

us

18

200

7.8

-

7.8

-

14

21

tHP

-tQHS

tCLmin

or tCHmin

tHP

-tQHS

tCLmin

or tCHmin

Output DQS valid window

Clock half period

tQH

tHP

ns

-

20, 21

Data hold skew factor

DQS write postamble time

Active to Read with Auto precharge

command

tQHS

tWPST

0.5

0.6

0.55

0.6

ns

tCK

21

12

0.4

15

0.4

18

tRAP

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

Autoprecharge write recovery +

Precharge time

tDAL

tCK

23

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

13.0 System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR333 devices to ensure proper system performance. these

characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

AC CHARACTERISTICS

PARAMETER

DDR400

DDR333

SYMBOL

Units

Notes

MIN

MAX

MIN

MAX

DQ/DM/DQS input slew rate measured between

VIH(DC), VIL(DC) and VIL(DC), VIH(DC)

DCSLEW

TBD

V/ns

a, l

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Input Slew Rate

∆tIS

∆tIH

Units

Notes

0.5 V/ns

0

ps

i

0.4 V/ns

+50

+100

ps

0.3 V/ns

ps

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

Input Slew Rate

∆tDS

∆tDH

Units

Notes

0.5 V/ns

0

ps

k

0.4 V/ns

+75

+150

+75

+150

ps

0.3 V/ns

ps

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Delta Slew Rate

∆tDS

∆tDH

Units

Notes

+/- 0.0 V/ns

0

ps

j

+/- 0.25 V/ns

+/- 0.5 V/ns

+50

+100

+50

+100

ps

Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)

Typical Range

Minimum

Maximum

Slew Rate Characteristic

Notes

(V/ns)

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

1.0

4.5

a,c,d,f,g,h

b,c,d,f,g,h

Table 6 : Output Slew Rate Characteristice (X16 Devices only)

Typical Range

Minimum

Maximum

Slew Rate Characteristic

Notes

(V/ns)

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

0.7

5.0

a,c,d,f,g,h

b,c,d,f,g,h

Table 7 : Output Slew Rate Matching Ratio Characteristics

AC CHARACTERISTICS

PARAMETER

Output Slew Rate Matching Ratio (Pullup to Pulldown)

DDR400

DDR333

Notes

e, l

MIN

TBD

MAX

TBD

MIN

MAX

TBD

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

14.0 Component Notes

1. All voltages referenced to Vss.

2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related speci-

fications and device operation are guaranteed for the full voltage range specified.

3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise rep-

resentation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or

other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions

(generally a coaxial transmission line terminated at the tester electronics).

VDDQ

50Ω

Output

(Vout)

30pF

Figure 1 : Timing Reference Load

4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the cross-

ing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew

rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).

5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing

the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level.

6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is recognized as LOW.

7. Enables on.chip refresh and address counters.

8. IDD specifications are tested after the device is properly initialized.

9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other

than CK/CK, is VREF.

10. The output timing reference voltage level is VTT.

11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage

level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance

(bus turnaround) will degrade accordingly.

13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is

defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will

be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this

time, depending on tDQSS.

14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

15. For command/address input slew rate ≥ 1.0 V/ns

16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns

17. For CK & CK slew rate ≥ 1.0 V/ns

18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester

correlation.

19. Slew Rate is measured between VOH(ac) and VOL(ac).

20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater

than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the

clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.

21. tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration dis-

tortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transi-

tion, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers.

22. tDQSQ - Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.

23. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15

ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

15.0 System Notes:

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.

Test point

50Ω

Output

VSSQ

Figure 2 : Pullup slew rate test load

b. Pulldown slew rate is measured under the test conditions shown in Figure 3.

VDDQ

50Ω

Output

Test point

Figure 3 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process

Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process

Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range.

For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. Only intended for operation up to 266 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is

based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate

is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either

VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of

the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or

VIH(DC) to VIL(DC), and similarly for rising transitions.

l. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC

region must be monotonic.

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

16.0 Command Truth Table

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

A0 ~ A9

Note

COMMAND

CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP

A11, A12

Register

Extended MRS

Mode Register Set

Auto Refresh

H

X

H

L

OP CODE

1, 2

3

H

L

H

X

Entry

Refresh

Self

Refresh

L

H

X

H

X

H

X

Exit

L

H

X

3

Row Address

(A0~A9, A11,A12)

Bank Active & Row Addr.

L

H

V

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

H

L

4

4, 6

7

Read &

Column Address

Column

Address

L

H

L

H

Write &

Column Address

Column

Address

H

X

L

H

L

H

L

V

H

Burst Stop

X

Bank Selection

All Banks

V

X

L

H

Precharge

X

5

H

L

X

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

H

L

H

L

Active Power Down

X

Exit

Entry

H

Precharge Power Down Mode

DM

H

L

Exit

L

H

X

8

9

H

L

X

H

X

H

No operation (NOP) : Not defined

Note :

1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

17.0 Physical Dimensions

17.1 32Mx64 (M368L3223HUS)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118 Min

(3.00Min)

5.077

(128.950)

1.25 ± 0.006

±0.15)

(31.75

A

B

2.500 +0.1/-0.0

0.10 M

C

B A

0.07 Max

(1.20 Max)

2.55

(64.77)

1.95

(49.53)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118 Min

(3.00Min)

0.250

(6.350)

0.039 ± 0.002

(1.000 ± 0.050)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

Detail A

0.071

(1.80)

0.050

(1.270)

0.1575 ± 0.004

(4.00 ± 0.1)

C

0.10

B

AM

M

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 32Mx8 DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H560838H

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

17.2 32Mx72 (M381L3223HUM)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118 Min

(3.00 Min)

5.077

(128.950)

1.25 ± 0.006

±0.15)

(31.75

A

B

2.500 +0.1/-0.0

0.10 M

C

B A

0.07 Max

(1.20 Max)

2.55

(64.77)

1.95

(49.53)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118 Min

(3.00 Min)

0.250

(6.350)

0.039 ± 0.002

(1.000 ± 0.050)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

Detail A

0.071

(1.80)

0.050

(1.270)

0.1575 ± 0.004

(4.00 ± 0.1)

C

0.10

B

AM

M

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 32Mx8 DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H560838H

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

17.3 64Mx64 (M368L6423HUS)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118 Min

(3.00 Min)

5.077

(128.950)

1.25 ± 0.006

±0.15)

(31.75

A

B

2.500 +0.1/-0.0

0.10 M

C

B A

2.55

(64.77)

0.145 Max

(3.67 Max)

1.95

(49.53)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118 Min

(3.00 Min)

0.250

(6.350)

0.039 ± 0.002

(1.000 ± 0.050)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

Detail A

0.071

(1.80)

0.050

(1.270)

0.1575 ± 0.004

(4.00 ± 0.1)

C

0.10

B

AM

M

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 32Mx8 DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H560838H

Rev. 1.0 November 2005

256MB, 512MB Unbuffered DIMM

DDR SDRAM

17.4 64Mx72 (M381L6423HUM)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118 Min

(3.00 Min)

5.077

(128.950)

1.25 ± 0.006

±0.15)

(31.75

A

B

2.500 +0.1/-0.0

0.10 M

C

B A

2.55

(64.77)

0.145 Max

(3.67 Max)

1.95

(49.53)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118 Min

(3.00 Min)

0.250

(6.350)

0.039 ± 0.002

(1.000 ± 0.050)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

Detail A

0.071

(1.80)

0.050

(1.270)

0.1575 ± 0.004

(4.00 ± 0.1)

C

0.10 M

AM

B

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 32Mx8 DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H560838H

Rev. 1.0 November 2005


型号：	M368L3223HUS-CCCT
厂家：	SAMSUNG
描述：	DDR DRAM Module, 32MX64, 0.65ns, CMOS, PDMA184 时钟动态存储器双倍数据速率光电二极管内存集成电路
文件：	总22页 (文件大小：466K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M368L3223HUS-CCCT [SAMSUNG]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E