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M372C3200BJ0-C50 [SAMSUNG]

Fast Page DRAM Module, 32MX72, 50ns, CMOS, DIMM-168;
M372C3200BJ0-C50
型号： M372C3200BJ0-C50
厂家： SAMSUNG    SAMSUNG
描述：

Fast Page DRAM Module, 32MX72, 50ns, CMOS, DIMM-168

动态存储器 内存集成电路
文件： 总20页 (文件大小：445K)
中文：  中文翻译
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DRAM MODULE  
M372C320(8)0BJ0-C  
Buffered 32Mx72 DIMM  
(16Mx4 base)  
Revision 0.1  
June 1998  
DRAM MODULE  
M372C320(8)0BJ0-C  
Revision History  
Version 0.0 (Sept. 1997)  
• Removed two AC parameters tCACP(access time from CAS) and tAAP(access time from col. addr.) in AC CHARACTERISTICS.  
Version 0.1 (June 1998)  
• The 3rd. generation of 64M DRAM components are applied for this module.  
DRAM MODULE  
M372C320(8)0BJ0-C  
M372C320(8)0BJ0-C Fast Page Mode  
32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 5V  
GENERAL DESCRIPTION  
FEATURES  
• Part Identification  
Part number  
The Samsung M372C320(8)0BJ0-C is a 32Mx72bits Dynamic  
RAM high density memory module. The Samsung  
M372C320(8)0BJ0-C consists of thirty-six CMOS 16Mx4bits  
DRAMs in SOJ 400mil packages and two 16 bits driver IC in  
TSSOP package mounted on a 168-pin glass-epoxy sub-  
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on  
the printed circuit board for each DRAM. The  
M372C320(8)0BJ0-C is a Dual In-line Memory Module and is  
intended for mounting into 168 pin edge connector sockets.  
PKG  
SOJ  
SOJ  
Ref.  
4K  
CBR Ref.  
ROR Ref.  
8K/64ms  
M372C3200BJ0-C  
M372C3280BJ0-C  
4K/64ms  
8K  
4K/64ms  
• Fast Page Mode Operation  
• CAS-before-RAS Refresh capability  
• RAS-only and Hidden refresh capability  
• TTL compatible inputs and outputs  
• Single 5V±10% power supply  
PERFORMANCE RANGE  
• JEDEC standard pinout & Buffered PDpin  
• Buffered input except RAS and DQ  
• PCB : Height(2000mil), double sided component  
Speed  
-C50  
tRAC  
50ns  
60ns  
tCAC  
18ns  
20ns  
tRC  
tPC  
90ns  
110ns  
35ns  
40ns  
-C60  
PIN NAMES  
PIN CONFIGURATIONS  
Pin  
Pin Front Pin Front  
Front Pin Back Pin Back Pin Back  
Pin Names  
Function  
A0, B0, A1 - A11 Address Input(4K ref.)  
A0, B0, A1 - A12 Address Input(8K ref.)  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
1
2
3
4
5
6
7
8
9
VSS  
29 *CAS2  
DQ22 85  
DQ23 86 DQ36 114 RAS1 142 DQ59  
87 DQ37 115 RFU 143 VCC  
DQ24 88 DQ38 116 VSS 144 DQ60  
VSS 113 *CAS3 141 DQ58  
DQ0 30 RAS0  
DQ1 31  
DQ2 32  
DQ3 33  
OE0  
VSS  
A0  
VCC  
DQ0 - DQ71  
W0, W2  
OE0, OE2  
RAS0 - RAS3  
CAS0, 1,4,5  
VCC  
Data In/Out  
Read/Write Enable  
Output Enable  
RFU 89 DQ39 117  
RFU 90 VCC 118  
RFU 91 DQ40 119  
RFU 92 DQ41 120  
DQ25 93 DQ42 121  
A1  
A3  
A5  
A7  
A9  
145 RFU  
146 RFU  
147 RFU  
148 RFU  
149 DQ61  
VCC  
34  
A2  
Row Address Strobe  
Column Address Strobe  
Power(+5V)  
DQ4 35  
DQ5 36  
DQ6 37  
A4  
A6  
A8  
10 DQ7 38  
11 DQ8 39  
12  
13 DQ9 41 RFU  
14 DQ10 42 RFU  
15 DQ11 43  
16 DQ12 44  
17 DQ13 45 RAS2  
18 46 CAS4  
19 DQ14 47 *CAS6  
20 DQ15 48  
21 DQ16 49  
A10  
A12  
VCC  
DQ26 94 DQ43 122 A11 150 DQ62  
VSS  
Ground  
67 DQ27 95 DQ44 123 *A13 151 DQ63  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
VSS  
40  
VSS  
96  
DQ28 97 DQ45 125 RFU 153 DQ64  
DQ29 98 DQ46 126 B0 154 DQ65  
VSS 124 VCC 152 VSS  
NC  
No Connection  
Presence Detect Enable  
Presence Detect  
ID bit  
PDE  
PD1 - 8  
ID0 - 1  
VSS  
OE2  
DQ30 99 DQ47 127 VSS 155 DQ66  
DQ31 100 DQ48 128 RFU 156 DQ67  
VCC 101 DQ49 129 RAS3 157 VCC  
DQ32 102 VCC 130 CAS5 158 DQ68  
DQ33 103 DQ50 131 *CAS7 159 DQ69  
DQ34 104 DQ51 132 PDE 160 DQ70  
DQ35 105 DQ52 133 VCC 161 DQ71  
VSS 106 DQ53 134 RSVD 162 VSS  
PD1 107 VSS 135 RSVD 163 PD2  
PD3 108 RSVD 136 DQ54 164 PD4  
PD5 109 RSVD 137 DQ55 165 PD6  
PD7 110 VCC 138 VSS 166 PD8  
ID0 111 RFU 139 DQ56 167 ID1  
VCC 112 CAS1 140 DQ57 168 VCC  
RSVD  
Reserved Use  
VCC  
RFU  
Reserved for Future Use  
Pins marked ¢*¢ are not used in this module.  
W2  
VCC  
PD & ID Table  
22 DQ17 50 RSVD 78  
Pin  
50NS  
60NS  
79  
80  
81  
82  
83  
84  
23  
VSS  
51 RSVD  
PD1  
PD2  
PD3  
PD4  
PD5  
PD6  
PD7  
PD8  
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
24 RSVD 52 DQ18  
25 RSVD 53 DQ19  
26  
27  
VCC  
W0  
54  
VSS  
55 DQ20  
28 CAS0 56 DQ21  
NOTE : A12 is used for only M372C3280BJ0-C (8K Ref.)  
ID0  
ID1  
0
0
0
0
PD Note :PD & ID Terminals must each be pulled up through a resistor to VCC at the next higher  
level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits.  
ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer.  
PD : 0 for Vol of Drive IC & 1 for N.C  
ID : 0 for Vss & 1 for N.C  
DRAM MODULE  
M372C320(8)0BJ0-C  
FUNCTIONAL BLOCK DIAGRAM  
RAS0  
CAS0  
OE0  
RAS3  
CAS5  
OE2  
W2  
RAS1  
CAS1  
RAS2  
CAS4  
W0  
A0  
B0  
DQ0-35  
DQ36-71  
A1-A11(A12)  
A1-A11(A12)  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
U0  
U1  
U2  
U3  
U18  
U19  
U20  
U21  
U9  
U27  
U28  
U29  
U30  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
U10  
U11  
U12  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
U22  
U23  
U4  
U5  
U13  
U14  
U31  
U32  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
U6  
U7  
U24  
U25  
U15  
U16  
U33  
U34  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
DQ0  
DQ1  
DQ2  
DQ3  
U8  
U26  
U17  
U35  
NOTE : A12 is used for only M372C3280BJ0-C (8K Ref.)  
Vcc  
A0  
B0  
U0-U8, U18-U26  
U9-U17, U27-U35  
U0-U35  
U0-U8, U18-U26  
U9-U17, U27-U35  
A1-A11(A12)  
0.1 or 0.22uF Capacitor  
under each DRAM  
To all DRAMs  
W0, OE0  
W2, OE2  
Vss  
DRAM MODULE  
M372C320(8)0BJ0-C  
ABSOLUTE MAXIMUM RATINGS *  
Item  
Symbol  
Rating  
Unit  
Voltage on any pin relative VSS  
Voltage on VCC supply relative to VSS  
Storage Temperature  
VIN, VOUT  
VCC  
-1 to +7.0  
-1 to +7.0  
-55 to +125  
36  
V
V
°C  
W
Tstg  
PD  
Power Dissipation  
Short Circuit Output Current  
IOS  
50  
mA  
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to  
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended  
periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)  
Item  
Symbol  
Min  
Typ  
Max  
Unit  
4.5  
0
2.4  
5.5  
0
Supply Voltage  
Ground  
Input High Voltage  
Input Low Voltage  
VCC  
VSS  
VIH  
VIL  
5.0  
0
-
V
V
V
V
*1  
VCC  
*2  
-
-1.0  
0.8  
*1 : VCC+2.0V at pulse width£20ns, which is measured at VCC.  
*2 : -2.0V at pulse width£20ns, which is measured at VSS.  
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)  
M372C3200BJ0  
M372C3280BJ0  
Symbol  
Speed  
Unit  
Min  
Max  
Min  
Max  
-50  
-60  
2260  
2080  
-
-
1720  
1540  
mA  
mA  
-
-
ICC1  
ICC2  
ICC3  
Don¢t care  
-
100  
-
100  
mA  
-50  
-60  
-
-
2260  
2080  
-
-
1720  
1540  
mA  
mA  
-50  
-60  
-
-
1360  
1180  
-
-
1180  
1000  
mA  
mA  
ICC4  
ICC5  
ICC6  
Don¢t care  
-
30  
-
30  
mA  
-50  
-60  
-
-
2260  
2080  
-
-
1720  
1540  
mA  
mA  
II(L)  
IO(L)  
-10  
-10  
10  
10  
-10  
-10  
10  
10  
uA  
uA  
Don¢t care  
Don¢t care  
VOH  
VOL  
2.4  
-
-
2.4  
-
-
V
V
0.4  
0.4  
ICC1*  
ICC2  
ICC3*  
ICC4*  
ICC5  
ICC6*  
I(IL)  
: Operating Current * (RAS, CAS, Address cycling @tRC=min)  
: Standby Current (RAS=CAS=W=VIH)  
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)  
: Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min)  
: Standby Current (RAS=CAS=W=Vcc-0.2V)  
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)  
: Input Leakage Current (Any input 0£VIN£Vcc+0.5V, all other pins not under test=0 V)  
: Output Leakage Current(Data Out is disabled, 0V£VOUT£Vcc)  
: Output High Voltage Level (IOH = -5mA)  
I(OL)  
VOH  
VOL  
: Output Low Voltage Level (IOL = 4.2mA)  
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.  
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,  
address can be changed maximum once within one Fast page mode cycle time, tPC.  
DRAM MODULE  
M372C320(8)0BJ0-C  
CAPACITANCE (TA = 25°C, f = 1MHz)  
Item  
Symbol  
Min  
Max  
Unit  
Input capacitance[A0, B0, A1 - A12]  
Input capacitance[W0, W2, OE0, OE2]  
Input capacitance[RAS0 - RAS3]  
Input capacitance[CAS0, 1, 4, 5]  
Input/Output capacitance[DQ0 - 71]  
CIN1  
CIN2  
CIN3  
CIN4  
CDQ  
20  
20  
73  
20  
24  
pF  
pF  
pF  
pF  
pF  
-
-
-
-
-
AC CHARACTERISTICS (0°C £TA£70°C , VCC=5.0V±10%. See notes 1,2.)  
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF  
-50  
-60  
Parameter  
Symbol  
Unit  
Note  
Min  
90  
Max  
Min  
110  
155  
Max  
Random read or write cycle time  
Read-modify-write cycle time  
Access time from RAS  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
ns  
tRC  
133  
tRWC  
tRAC  
tCAC  
tAA  
50  
18  
30  
60  
20  
35  
3,4  
Access time from CAS  
3,4,5,11  
3,10,11  
3,11  
Access time from column address  
CAS to output in Low-Z  
5
5
tCLZ  
tOFF  
tT  
Output buffer turn-off delay  
Transition time(rise and fall)  
RAS precharge time  
5
18  
50  
5
20  
50  
6,11  
1
1
2
30  
50  
18  
45  
13  
18  
13  
10  
5
40  
60  
20  
55  
15  
18  
13  
10  
5
tRP  
RAS pulse width  
10K  
10K  
tRAS  
tRSH  
tCSH  
tCAS  
tRCD  
tRAD  
tCRP  
tASR  
tRAH  
tASC  
tCAH  
tRAL  
tRCS  
tRCH  
tRRH  
tWCH  
tWP  
RAS hold time  
11  
11  
CAS hold time  
CAS pulse width  
10K  
32  
10K  
40  
RAS to CAS delay time  
4,11  
10,11  
11  
RAS to column address delay time  
CAS to RAS precharge time  
Row address set-up time  
Row address hold time  
20  
25  
11  
8
8
11  
Column address set-up time  
Column address hold time  
Column address to RAS lead time  
Read command set-up time  
Read command hold referencde to CAS  
Read command hold referenced to RAS  
Write command hold time  
Write command pulse width  
Write command to RAS lead time  
Write command to CAS lead time  
Data in set-up time  
0
0
10  
30  
0
10  
35  
0
11  
0
0
8
-2  
10  
10  
20  
13  
-2  
15  
-2  
10  
10  
20  
15  
-2  
15  
8,11  
11  
tRWL  
tCWL  
tDS  
9,11  
9,11  
Data in hold time  
tDH  
Refresh period(4K & 8K)  
Write command set-up time  
CAS to W delay time  
64  
64  
tREF  
tWCS  
tCWD  
tAWD  
tCPWD  
tRWD  
0
0
7
7
36  
48  
53  
73  
40  
55  
60  
85  
Column address to W delay time  
CAS prechange to W delay time  
RAS ro W delay time  
7
7
7,11  
DRAM MODULE  
M372C320(8)0BJ0-C  
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)  
-50  
-60  
Parameter  
Symbol  
Unit  
Note  
Min  
10  
8
Max  
Min  
10  
8
Max  
40  
CAS setup time(CAS-before-RAS refresh)  
CAS hold time(CAS-before-RAS refresh)  
RAS to CAS precharge time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
11  
11  
tCSR  
tCHR  
tRPC  
tCPA  
tPC  
3
3
11  
Access time from CAS precharge  
Fast page mode cycle time  
35  
3,11  
35  
76  
10  
50  
35  
15  
8
40  
85  
10  
60  
40  
15  
8
Fast page mode read-modify-write cycle time  
CAS precharge time(Fast page cycle)  
RAS pulse width(Fast page cycle)  
RAS hold time from CAS precharge  
W to RAS precharge time(C-B-R refresh)  
W to RAS hold time(C-B-R refresh)  
OE access time  
tPRWC  
tCP  
200K  
200K  
tRASP  
tRHCP  
tWRP  
tWRH  
tOEA  
tOED  
tOEZ  
tOEH  
11  
11  
11  
11  
11  
11  
18  
18  
20  
20  
OE to data delay  
18  
5
20  
5
Output buffer turn off delay time from OE  
OE command hold time  
13  
15  
Present Detect Read Cycle  
PDE to Valid PD bit  
10  
7
10  
7
ns  
ns  
tPD  
PDE to PD bit Inactive  
2
2
tPDOFF  
NOTES  
An initial pause of 200us is required after power-up followed  
by any 8 RAS-only or CAS-before-RAS refresh cycles before  
proper device operation is achieved.  
7.  
1.  
tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operat-  
ing parameter. They are included in the data sheet as electri-  
cal characteristics only. If tWCS³ tWCS(min) the cycle is an  
early write cycle and the data out pin will remain high imped-  
ance for the duration of the cycle. If tRWD³ tRWD(min),  
tCWD³ tCWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD(min).  
The cycle is a read-modify-write cycle and the data out will  
contain data read from the selected cell. If neither of the  
above sets of conditions is satisfied, the condition of data  
out(at access time) is indeterminate.  
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-  
erence levels for measuring timing of input signals. Transition  
times are measured between VIH(min) and VIL(max) and are  
assumed to be 5ns for all inputs.  
3.  
Measured with a load equivalent to 2 TTL loads and 100pF.  
4. Operation within the tRCD(max) limit insures that tRAC(max)  
can be met. tRCD(max) is specified as a reference point only.  
If tRCD is greater than the specified tRCD(max) limit, then  
access time is controlled exclusively by tCAC.  
8. Either tRCH or tRRH must be satisfied for a read cycle.  
9.  
These parameters are referenced to the CAS leading edge in  
early write cycles.  
5.  
6.  
Assumes that tRCD³ tRCD(max).  
10.  
Operation within the tRAD(max) limit insures that tRAC(max)  
can be met. tRAD(max) is specified as reference point only. If  
tRAD is greater than the specified tRAD(max) limit, then  
access time is controlled by tAA.  
This parameter defines the time at which the output achieves  
the open circuit condition and is not referenced to VOH or  
VOL.  
11.  
The timing skew from the DRAM to the DIMM resulted from  
the addition of buffers.  
DRAM MODULE  
M372C320(8)0BJ0-C  
READ CYCLE  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tASR  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
CAS  
VIL -  
tRAD  
tRAL  
tRAH  
tASC  
tRCS  
tCAH  
VIH -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
VIL -  
tRCH  
tRRH  
VIH -  
W
VIL -  
tOFF  
tOEZ  
tAA  
VIH -  
OE  
tOEA  
VIL -  
tCAC  
tCLZ  
tRAC  
VOH -  
DQ  
OPEN  
DATA-OUT  
VOL -  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
CAS  
VIL -  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
tCWL  
tRWL  
tWCS  
tWCH  
tWP  
VIH -  
VIL -  
W
VIH -  
VIL -  
OE  
DQ  
tDS  
tDH  
DATA-IN  
VIH -  
VIL -  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
WRITE CYCLE ( OE CONTROLLED WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRP  
tRAS  
VIH -  
RAS  
VIL -  
tCSH  
tCRP  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
VIL -  
CAS  
tRAD  
tRAL  
tASR  
tRAH  
tASC  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
tCWL  
tRWL  
VIH -  
VIL -  
tWP  
W
VIH -  
VIL -  
OE  
DQ  
tOED  
tOEH  
tDS  
tDH  
DATA-IN  
VIH -  
VIL -  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
READ - MODIFY - WRTIE CYCLE  
tRWC  
tRAS  
tRP  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tRSH  
tCAS  
VIH -  
CAS  
VIL -  
tRAD  
tRAH  
tASR  
tASC  
tCAH  
tCSH  
VIH -  
VIL -  
ROW  
ADDR  
COLUMN  
ADDRESS  
A
tRWL  
tAWD  
tCWD  
tCWL  
VIH -  
VIL -  
tWP  
W
tRWD  
tOEA  
VIH -  
VIL -  
OE  
tCLZ  
tCAC  
tOED  
tOEZ  
tAA  
tDS  
tDH  
tRAC  
VI/OH -  
VI/OL -  
VALID  
DATA-OUT  
VALID  
DATA-IN  
DQ  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
FAST PAGE READ CYCLE  
NOTE : DOUT = OPEN  
tRP  
tRASP  
¡ó  
VIH -  
RAS  
tRHCP  
VIL -  
tPC  
tCRP  
tCP  
tRCD  
tRAD  
tCP  
tRSH  
tCAS  
tCAS  
¡ó  
VIH -  
CAS  
tCAS  
VIL -  
tASC  
tCSH  
tASR  
ROW  
tASC  
tCAH  
tASC  
tCAH  
tRAH  
tCAH  
tRCH  
¡ó  
¡ó  
VIH -  
VIL -  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
COLUMN  
A
W
ADDR  
ADDRESS  
tRCS  
tRRH  
tRCS  
tRCS  
tRCH  
¡ó  
VIH -  
VIL -  
tCAC  
tOEA  
tCAC  
tOEA  
tCAC  
tOEA  
¡ó  
¡ó  
VIH -  
VIL -  
OE  
tAA  
tOFF  
tAA  
tOFF  
tCLZ  
tAA  
tOFF  
tOEZ  
tRAC  
tCLZ  
tCLZ  
tOEZ  
VALID  
tOEZ  
VALID  
VOH -  
VOL -  
VALID  
DATA-OUT  
DQ  
DATA-OUT  
DATA-OUT  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
FAST PAGE WRITE CYCLE ( EARLY WRITE )  
NOTE : DOUT = OPEN  
tRP  
tRASP  
¡ó  
VIH -  
RAS  
tRHCP  
VIL -  
tPC  
tPC  
tCRP  
tCP  
tRCD  
tCP  
tRSH  
tCAS  
tCAS  
¡ó  
VIH -  
VIL -  
tCAS  
CAS  
tRAD  
tASC  
tRAH  
ROW  
tCStHCAH  
tASC  
tCAH  
tASC  
tCAH  
tASR  
¡ó  
¡ó  
VIH -  
VIL -  
COLUMN  
COLUMN  
ADDRESS  
COLUMN  
ADDRESS  
A
ADDRESS  
ADDR  
tWCS  
tWCS  
tWCH  
tWP  
tWCS  
tWCH  
¡ó  
tWCH  
tWP  
VIH -  
VIL -  
tWP  
W
tCWL  
tRWL  
tCWL  
tCWL  
¡ó  
VIH -  
VIL -  
OE  
DQ  
¡ó  
tDS  
tDH  
tDS  
tDH  
tDS  
tDH  
¡ó  
¡ó  
VIH -  
VIL -  
VALID  
DATA-IN  
VALID  
DATA-IN  
VALID  
DATA-IN  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
FAST PAGE READ - MODIFY - WRITE CYCLE  
tRP  
tRASP  
tCP  
VIH -  
VIL -  
tCSH  
RAS  
CAS  
tRSH  
tCAS  
tRCD  
tRAD  
tCRP  
VIH -  
VIL -  
tCAS  
tPRWC  
tCAH  
tRAH  
tRAL  
tCAH  
tASR  
ROW  
tASC  
tASC  
VIH -  
VIL -  
COL.  
ADDR  
COL.  
ADDR  
A
ADDR  
tRWL  
tWP  
tRCS  
tCWL  
tCWL  
VIH -  
VIL -  
tWP  
W
tCWD  
tAWD  
tRWD  
tCWD  
tAWD  
tCPWD  
tOEA  
VIH -  
VIL -  
tOEA  
OE  
tOED  
tCAC  
tAA  
tOED  
tCAC  
tDH  
tDH  
tAA  
tDS  
tOEZ  
tDS  
tOEZ  
tRAC  
VI/OH -  
VI/OL -  
DQ  
tCLZ  
tCLZ  
VALID  
VALID  
DATA-IN  
VALID  
VALID  
DATA-OUT  
DATA-IN  
DATA-OUT  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
RAS - ONLY REFRESH CYCLE  
NOTE : W, OE, DIN = Don¢t care  
DOUT = OPEN  
tRC  
tRP  
tRAS  
VIH -  
RAS  
VIL -  
tRPC  
tCRP  
tCRP  
VIH -  
CAS  
VIL -  
tASR  
tRAH  
VIH -  
VIL -  
ROW  
ADDR  
A
CAS - BEFORE - RAS REFRESH CYCLE  
NOTE : OE, A = Don¢t care  
tRC  
tRP  
tRAS  
tRP  
VIH -  
RAS  
tRPC  
tCP  
VIL -  
tRPC  
VIH -  
VIL -  
tCSR  
tWRP  
CAS  
W
tCHR  
tWRH  
VIH -  
VIL -  
tOFF  
VOH -  
VOL -  
DQ  
OPEN  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
HIDDEN REFRESH CYCLE ( READ )  
tRC  
tRC  
tRP  
tRP  
tRAS  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tRSH  
tCHR  
VIH -  
VIL -  
CAS  
tRAD  
tASR  
tRAH  
tASC  
tRCS  
tCAH  
COLUMN  
ADDRESS  
VIH -  
VIL -  
ROW  
ADDRESS  
A
tWRH  
tWRP  
tRRH  
VIH -  
VIL -  
W
tAA  
VIH -  
VIL -  
OE  
tOEA  
tOFF  
tCAC  
tCLZ  
tRAC  
tOEZ  
DATA-OUT  
VOH -  
VOL -  
DQ  
OPEN  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
HIDDEN REFRESH CYCLE ( WRITE )  
NOTE : DOUT = OPEN  
tRC  
tRC  
tRP  
tRP  
tRAS  
tRAS  
VIH -  
RAS  
VIL -  
tCRP  
tRCD  
tRSH  
tCHR  
VIH -  
CAS  
VIL -  
tRAD  
tASR  
tRAH  
tASC  
tCAH  
VIH -  
VIL -  
ROW  
ADDRESS  
COLUMN  
ADDRESS  
A
tWRH  
tWRP  
tWCS  
tWCH  
VIH -  
VIL -  
W
tWP  
VIH -  
VIL -  
OE  
tDS  
tDH  
VIH -  
VIL -  
DQ  
DATA-IN  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE  
tRP  
VIH -  
VIL -  
tRAS  
RAS  
CAS  
tCPT  
tRSH  
tCAS  
tCSR  
VIH -  
VIL -  
tCHR  
tRAL  
tASC  
tCAH  
VIH -  
VIL -  
COLUMN  
ADDRESS  
A
tRRH  
tRCH  
tAA  
tWRP  
tWRH  
READ CYCLE  
tRCS  
tCAC  
VIH -  
W
VIL -  
VIH -  
OE  
VIL -  
tOFF  
tOEZ  
tOEA  
tCLZ  
VOH -  
DQ  
DATA-OUT  
VOL -  
WRITE CYCLE  
tRWL  
tWRP  
tWRH  
tCWL  
VIH -  
W
tWCS  
tWCH  
tWP  
VIL -  
VIH -  
OE  
VIL -  
tDS  
tDH  
DATA-IN  
VIH -  
DQ  
VIL -  
READ-MODIFY-WRITE  
tAWD  
tCWL  
tRWL  
tWRP  
tWRH  
tRCS  
tCWD  
VIH -  
tWP  
W
tCAC  
tOEA  
VIL -  
tAA  
VIH -  
OE  
tOED  
tOEZ  
VIL -  
tDH  
tCLZ  
tDS  
VI/OH -  
DQ  
VI/OL -  
VALID  
DATA-OUT  
VALID  
DATA-IN  
Don¢t care  
Undefined  
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.  
DRAM MODULE  
M372C320(8)0BJ0-C  
CAS - BEFORE - RAS SELF REFRESH CYCLE  
NOTE : OE, A = Don¢t care  
tRP  
tRASS  
tRPS  
tRPC  
VIH -  
RAS  
tRPC  
tCP  
VIL -  
tCHS  
VIH -  
VIL -  
tCSR  
CAS  
DQ  
tOFF  
VOH -  
VOL -  
OPEN  
tWRP  
tWRH  
VIH -  
VIL -  
W
TEST MODE IN CYCLE  
NOTE : OE, A = Don¢t care  
tRC  
tRP  
tRAS  
tRP  
VIH -  
RAS  
tRPC  
tCP  
VIL -  
tRPC  
VIH -  
CAS  
VIL -  
tCSR  
tWTS  
tCHR  
tWTH  
VIH -  
W
VIL -  
tOFF  
VOH -  
DQ  
OPEN  
VOL -  
Don¢t care  
Undefined  
DRAM MODULE  
M372C320(8)0BJ0-C  
PACKAGE DIMENSIONS  
Units : Inches (millimeters)  
5.250  
(133.350)  
0.054  
(1.372)  
R 0.079  
5.014  
(127.350)  
0.118  
(3.000)  
(R 2.000)  
0.157±0.004  
(4.000±0.100)  
B
C
A
.118DIA±.004  
(3.000DIA±.100)  
0.250  
(6.350)  
0.250  
(6.350)  
1.450  
2.150  
0.350  
(8.890)  
(36.830)  
(54.61)  
.450  
(11.430)  
4.550  
(115.57)  
( Front view )  
0.350Max  
(8.89Max)  
SOJ  
0.050±0.0039  
(1.270±0.10)  
( Back view )  
0.250  
(6.350)  
0.250  
(6.350)  
0.039±.002  
(1.000±.050)  
0.1230±.0050  
(3.125±.125)  
0.1230±.0050  
(3.125±.125)  
0.01Max  
(0.25 Max)  
0.050  
(1.270)  
0.079±.0040  
(2.000±.100)  
0.079±.0040  
(2.000±.100)  
Detail A  
Detail B  
Detail C  
Tolerances : ±.005(.13) unless otherwise specified  
The used device is 16Mx4 DRAM with Fast Page mode, SOJ  
DRAM Part No. : M372C3200BJ0 - K4F640411B  
M372C3280BJ0 - K4F660411B  

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