M377S0823CT2-C1L [SAMSUNG]

Synchronous DRAM Module, 8MX72, 6ns, CMOS, DIMM-168;


型号：	M377S0823CT2-C1L
厂家：	SAMSUNG
描述：	Synchronous DRAM Module, 8MX72, 6ns, CMOS, DIMM-168 时钟动态存储器内存集成电路
文件：	总10页 (文件大小：171K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PC100 Registered DIMM

M377S0823CT2

M377S0823CT2 SDRAM DIMM (Intel 1.1 ver. Base)

8Mx72 SDRAM DIMM with PLL & Register based on 8Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD

FEATURE

GENERAL DESCRIPTION

• Performance range

The Samsung M377S0823CT2 is a 8M bit x 72 Synchronous

Dynamic RAM high density memory module. The Samsung

M377S0823CT2 consists of nine CMOS 8Mx8 bit Synchronous

DRAMs in TSOP-II 400mil packages, two 18-bits Drive ICs for

input control signal, one PLL in 24-pin TSSOP package for

clock and one 2K EEPROM in 8-pin TSSOP package for Serial

Presence Detect on a 168pin glass-epoxy substrate. Two

0.22uF and one 0.0022uF decoupling capacitors are mounted

on the printed circuit board in parallel for each SDRAM. The

M377S0823CT2 is a Dual In-line Memory Module and is

intented for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable latencies

allows the same device to be useful for a variety of high band-

width, high performance memory system applications.

Part No.

Max Freq. (Speed)

100MHz (10ns @ CL=2)

100MHz (10ns @ CL=3)

M377S0823CT2-C1H

M377S0823CT2-C1L

• Burst mode operation

• Auto & self refresh capability (4096 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V ± 0.3V power supply

• MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB : Height (1,500mil) , double sided component

PIN CONFIGURATIONS (Front side/back side)

PIN NAMES

Pin Front Pin Front

Front Pin Back Pin Back Pin Back

Pin Name

A0 ~ A11

BA0 ~ BA1

DQ0 ~ DQ63

CB0 ~ CB7

CLK0

Function

Address input (Multiplexed)

Select bank

VSS

DQ0

DQ1

DQ2

DQ3

VDD

DQ4

DQ5

DQ6

DQ7

DQ8

VSS

29 DQM1

DQ18 85

VSS

113 DQM5 141 DQ50

CS0

VSS

DQ19 86 DQ32 114 *CS1 142 DQ51

Data input/output

Check bit (Data-in/data-out)

Clock input

VDD

87 DQ33 115 RAS 143

VDD

DQ20 88 DQ34 116

NC 89 DQ35 117

*VREF 90 118

*CKE1 91 DQ36 119

92 DQ37 120

DQ21 93 DQ38 121

VSS

144 DQ52

145

VDD

146 *VREF

147 REGE

CKE0

Clock enable input

Chip select input

Row address strobe

Colume address strobe

Write enable

VSS

148

VSS

CS0, CS2

RAS

149 DQ53

38 A10/AP

DQ22 94 DQ39 122 BA0 150 DQ54

CAS

BA1

VDD

DQ23 95 DQ40 123

96 124

A11

VDD

151 DQ55

152

VSS

DQ9

DQ24 97 DQ41 125 *CLK1 153 DQ56

DQ25 98 DQ42 126 *A12 154 DQ57

DQM0 ~ 7

VDD

DQM

14 DQ10 42 CLK0

Power supply (3.3V)

Ground

15 DQ11 43

16 DQ12 44

17 DQ13 45

VSS

CS2

DQ26 99 DQ43 127

DQ27 100 DQ44 128 CKE0 156 DQ59

VDD 101 DQ45 129 *CS3 157

DQ28 102 VDD 130 DQM6 158 DQ60

VSS

155 DQ58

VSS

VDD

*VREF

Power supply for reference

Serial data I/O

VDD

46 DQM2

REGE

SDA

19 DQ14 47 DQM3

DQ29 103 DQ46 131 DQM7 159 DQ61

DQ30 104 DQ47 132 *A13 160 DQ62

20 DQ15 48

VDD

SCL

Serial clock

CB0

CB1

VSS

VDD

DQ31 105 CB4 133

VDD

161 DQ63

162

163 *CLK3

137 CB7 165 **SA0

138 166 **SA1

VSS

106 CB5 134

VSS

SA0 ~ 2

Address in EEPROM

Don¢t use

*CLK2 107

NC 108

VSS

135

CB2

CB3

VSS

136 CB6 164

No connection

WP 109

**SDA 110

VDD

VSS

Write protection

55 DQ16

**SCL 111 CAS 139 DQ48 167 **SA2

VDD 112 DQM4 140 DQ49 168

These pins are not used in this module.

28 DQM0 56 DQ17

VDD

** These pins should be NC in the system

which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

PIN CONFIGURATION DESCRIPTION

Name

System clock

Input Function

CLK

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock enable

CKE should be enabled 1CLK+tss prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA8

A0 ~ A11

BA0 ~ BA1

RAS

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank select address

Row address strobe

Column address strobe

Write enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

DQM0 ~ 7

Data input/output mask

The device operates in the transparent mode when REGE is low. When REGE is high,

the device operates in the registered mode. In registered mode, the Address and con-

trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in

the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm

Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-

istered mode.

REGE

DQ0 ~ 63

CB0 ~ 7

Data input/output

Check bit

Data inputs/outputs are multiplexed on the same pins.

Check bits for ECC.

WP pin is connected to VSS through 47KW Resistor.

When WP is "high", EEPROM Programming will be inhibited and the entire memory will

be write-protected.

Write protection

VDD/VSS

Power supply/ground

Power and ground for the input buffers and the core logic.

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

FUNCTIONAL BLOCK DIAGRAM

PCLK0

BCS0

BCKE0

CLK

CKE

Add,CTL

DQM

DQ0~7

B0A0~B0A11,BBA0~1,BRAS,BCAS,BWE

BDQM0

DQ0~7

10W

CLK

CKE

Add,CTL

DQM

DQ0~7

DQ8~15

10W

PCLK1

CLK

CKE

Add,CTL

DQM

DQ0~7

BDQM1

CB0~7

10W

CLK

CKE

Add,CTL

DQM

DQ0~7

BCS2

BDQM2

DQ16~23

10W

CLK

CKE

Add,CTL

DQM

DQ0~7

PCLK3

BDQM3

DQ24~31

DQ32~39

10W

CLK

CKE

Add,CTL

DQM

DQ0~7

BDQM4

10W

CLK

CKE

Add,CTL

DQM

DQ0~7

BDQM5

DQ40~47

10W

CLK

CKE

Add,CTL

DQM

DQ0~7

BDQM6

DQ48~55

DQ56~63

10W

CLK

CKE

Add,CTL

DQM

DQ0~7

BDQM7

10W

Notes : Address/Control Signals are connected to D2 through 100 ohms resistor.

VSS

B0A0~B0A9

A0~A9

1Y0

1Y1

1Y2

1Y3

1Y4

2Y0

2Y1

2Y2

SN74ALVC162835

BRAS,BCAS,BWE

BDQM0,1,4,5

BCS0

RAS,CAS,WE

DQM0,1,4,5

CS0

CDC2509

PCLK0

PCLK1

PCLK2

PCLK3

REGE

CLK

CLK0

FBOU

12pF

PCLK2

10kW

* Note

1. The actual values of Cb will depend upon the PLL chosen.

SN74ALVC162835

A10,A11,BA0~1

CS2

B0A10,B0A11,BBA0~1

BCS2

Serial PD

CKE0

BCKE0

DQM2,3,6,7

BDQM2,3,6,7

SCL

SDA

A0 A1 A2

47K

SA0 SA1 SA2

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)

REG

DOUT

Control Signal(RAS,CAS,WE)

*1. Register Input

CLK

RAS

CAS

*2. Register Output

RAS

CAS

*3. SDRAM

CAS latency(refer to *1)

=2CLK+1CLK

1CLK

tSAC

tRAC(refer to *1)

tRAC(refer to *2)

Qa0 Qa1 Qa2 Qa3

Db0 Db1 Db2 Db3

CAS latency(refer to *2)

=2CLK

tRDL

Row Active

Precharge

Command

Row Active

Read

Command

Precharge

Command

Write

Command

td, tr = Delay of register (SN74ALVC162835)

Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal

because of the buffering in register (SN74ALVC162835). Therefore, Input/Output signals of read/write function should be

issued 1CLK earlier as compared to Unbuffered DIMMs.

2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.

: Don¢t care

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

Unit

°C

Power dissipation

Short circuit current

IOS

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended Operating Conditions (Voltage Referenced to VSS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD

VIH

Min

3.0

2.0

-0.3

2.4

Typ

Max

Unit

Note

3.3

3.6

Input high voltage

3.0

VDDQ+0.3

Input low voltage

VIL

0.8

IOH = -2mA

IOL = 2mA

Output high voltage

VOH

VOL

IIL

Output low voltage

0.4

Input leakage current (Inputs)

Input leakage current (I/O pins)

-2

IIL

-1.5

1.5

3,4

Notes :

1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

3. Any input 0V £ VIN £ VDDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. Dout is disabled, 0V £ VOUT £ VDDQ

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Parameter

Symbol

Min

Max

Unit

Input capacitance (A0 ~ A11)

CIN1

CIN2

Input capacitance (RAS, CAS, WE)

Input capacitance (CKE0)

CIN3

Input capacitance (CLK0)

CIN4

Input capacitance (CS0, CS2)

CIN5

Input capacitance (DQM0 ~ DQM7)

Input capacitance (BA0 ~ BA1)

Data input/output capacitance (DQ0 ~ DQ63)

Data input/output capacitance (CB0 ~ CB7)

CIN6

CIN7

COUT

COUT1

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Version

CAS

Latency

Parameter

Symbol

Test Condition

Burst length = 1

tRC ³ tRC(min)

IOL = 0 mA

Unit Note

-1H

-1L

Operating current

(One bank active)

ICC1

780

ICC2P

CKE £ VIL(max), tCC = 15ns

Precharge standby current in

power-down mode

ICC2PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

ICC2N

110

Precharge standby current in

non power-down mode

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC2NS

ICC3P

CKE £ VIL(max), tCC = 15ns

Active standby current in

power-down mode

ICC3PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

ICC3N

182

Active standby current in non

power-down mode

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC3NS

IOL = 0mA

Page burst

2Banks activated

tCCD=2CLK

825

780

Operating current

(Burst mode)

ICC4

Refresh current

ICC5

ICC6

tRC ³ tRC(min)

CKE £ 0.2V

1,126

Self refresh current

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Measured with 1 PLL & 2 Drive ICs.

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter

AC input levels (Vih/Vil)

Value

2.4/0.4

1.4

Unit

Input timing measurement reference level

Input rise and fall time

tr/tf = 1/1

1.4

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200W

50W

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Output

Z0 = 50W

50pF

870W

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

-1H

-1L

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

Row precharge time

tRAS(min)

tRAS(max)

tRC(min)

Row active time

100

Row cycle time

Last data in to new col. address delay

Last data in to row precharge

Last data in to burst stop

tCDL(min)

tRDL(min)

tBDL(min)

tCCD(min)

CLK

Col. address to col. address delay

CAS latency=3

CAS latency=2

Number of valid output data

Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write in Reg. DIMM (1 CLK earlier than Unbuff. DIMM)

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

-1H

-1L

Parameter

Symbol

Unit

Note

Min

Max

Min

Max

CAS latency=3

CLK cycle time

tCC

1000

CAS latency=2

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

CLK to valid

output delay

tSAC

1,2

Output data

hold time

tOH

CLK high pulse width

CLK low pulse width

Input setup time

tCH

tCL

tSS

tSH

tSLZ

Input hold time

CLK to output in Low-Z

CAS latency=3

CAS latency=2

CLK to output

in Hi-Z

tSHZ

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

SIMPLIFIED TRUTH TABLE

A11,

A9 ~ A0

Command

CKEn-1

CKEn

RAS

CAS

DQM BA0,1

A10/AP

Note

Refresh

Mode register set

Auto refresh

OP code

1,2

Entry

Self

refresh

Exit

Bank active & row addr.

Row address

Column

address

(A0 ~ A8)

Read &

column address

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

4,5

Column

address

(A0 ~ A8)

Write &

column address

4,5

Burst stop

Precharge

Bank selection

All banks

Entry

Clock suspend or

active power down

Exit

Entry

Precharge power down mode

Exit

DQM

No operation command

(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)

1. OP Code : Operand code

Notes :

A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 clock cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 0.0 Jun. 1999

PC100 Registered DIMM

M377S0823CT2

PACKAGE DIMENSIONS

Units : Inches (Millimeters)

5.250

(133.350)

0.054

(1.372)

5.014

0.118

(3.000)

(127.350)

R 0.079

(R 2.000)

0.157 ± 0.004

(4.000 ± 0.100)

PLL

.118DIA ± 0.004

(3.000DIA ± 0.100)

0.250

(6.350)

0.250

(6.350)

0.350

(8.890)

1.450

(36.830)

2.150

(54.61)

.450

(11.430)

4.550

(115.57)

0.150 Max

(3.81 Max)

REG

0.050 ± 0.0039

(1.270 ± 0.10)

0.250

(6.350)

0.250

(6.350)

0.039 ± 0.002

(1.000 ± 0.050)

0.123 ± 0.005

(3.125 ± 0.125)

0.123 ± 0.005

(3.125 ± 0.125)

0.008 ±0.006

(0.200 ±0.150)

0.050

(1.270)

0.079 ± 0.004

(2.000 ± 0.100)

0.079 ± 0.004

(2.000 ± 0.100)

Detail A

Detail B

Detail C

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 8Mx8 SDRAM, TSOP

SDRAM Part No. : K4S640832C

Rev. 0.0 Jun. 1999

M377S0823CT2-C1L [SAMSUNG]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E