M378T2953BG0-CCC_技术文档

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

DDR2 Unbuffered SDRAM MODULE

240pin Unbuffered Module based on 512Mb B-die

64/72-bit Non-ECC/ECC

sINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

DDR2 Unbuffered DIMM Ordering Information

Part Number

Density

Organization

Component Composition

x64 Non ECC

Number of Rank

Height

M378T3354BG(Z)3-CD5/CC

M378T3354BG(Z)0-CD5/CC

M378T6553BG(Z)3-CD5/CC

M378T6553BG(Z)0-CD5/CC

M378T2953BG(Z)3-CD5/CC

M378T2953BG(Z)0-CD5/CC

256MB

512MB

1GB

32Mx64

64Mx64

128Mx64

32Mx16(K4T51163QB)*4

64Mx8(K4T51083QB)*8

64Mx8(K4T51083QB)*16

1

2

30mm

1GB

x72 ECC

M391T6553BG(Z)3-CD5/CC

M391T6553BG(Z)0-CD5/CC

M391T2953BG(Z)3-CD5/CC

M391T2953BG(Z)0-CD5/CC

512MB

1GB

64Mx72

128Mx72

64Mx8(K4T51083QB)*9

64Mx8(K4T51083QB)*18

1

2

30mm

1GB

Note: “Z” of Part number(11th digit) stand for Lead-free products.

Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.

Features

•

Performance range

D5(DDR2-533)

CC(DDR2-400)

Unit

Speed@CL3

Speed@CL4

Speed@CL5

CL-tRCD-tRP

400

533

-

400

-

Mbps

CK

4-4-4

3-3-3

•

JEDEC standard 1.8V ± 0.1V Power Supply

= 1.8V ± 0.1V

V

DDQ

•

200 MHz f for 400Mb/sec/pin, 267MHz f for 533Mb/sec/pin

CK CK

•

4 Banks

Posted CAS

Programmable CAS Latency: 3, 4, 5

Programmable Additive Latency: 0, 1 , 2 , 3 and 4

Write Latency(WL) = Read Latency(RL) -1

Burst Length: 4 , 8(Interleave/nibble sequential)

Programmable Sequential / Interleave Burst Mode

Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

Off-Chip Driver(OCD) Impedance Adjustment

On Die Termination

Average Refresh Period 7.8us at lower than a T

85°C, 3.9us at 85°C < T

< 95 °C

CASE

- support High Temperature Self-Refresh rate enable feature

•

Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16

All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

Address Configuration

Organization

Row Address

A0-A13

Column Address

A0-A9

Bank Address

BA0-BA1

Auto Precharge

64Mx8(512Mb) based Module

A10

32Mx16(512Mb) based Module

A0-A12

A0-A9

BA0-BA1

A10

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

x64 DIMM Pin Configurations (Front side/Back side)

1

Front

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Back

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

Front

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Back

61

Front

181

182

183

184

Back

91

92

93

94

95

96

97

98

Front

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

DM5

NC

V

DQ19

A4

REF

SS

DDQ

SS

V

2

3

4

5

6

7

8

9

DQ4

DQ5

V

DQ28

DQ29

V

62

63

64

A3

A1

DQS5

SS

DDQ

V

DQ0

DQ1

V

DQ24

DQ25

A2

SS

V

DQ46

DQ47

SS

DD

SS

V

DM0

NC

V

DM3

NC

V

KEY

DQ42

DQ43

SS

V

DQS0

V

DQS3

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

CK0

SS

V

DQ52

DQ53

SS

V

DQ6

DQ7

V

DQ30

DQ31

V

DQ48

DQ49

SS

DD

V

DQ2

DQ3

V

DQ26

DQ27

NC

A0

99

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

CK2

SS

DD

SS

V

DQ12

DQ13

V

NC

V

A10/AP

BA0

BA1

SA2

SS

2

V

DQ8

DQ9

V

NC

NC, TEST

DDQ

SS

V

RAS

S0

DM6

NC

SS

DDQ

SS

V

DM1

NC

V

NC

V

WE

CAS

DQS6

SS

V

DQS1

V

NC

DDQ

SS

V

ODT0

DQ54

DQ55

SS

DDQ

SS

1

V

CK1

V

NC

V

S1

ODT1

DQ50

DQ51

A13

SS

V

NC

V

NC

DD

SS

V

DQ60

DQ61

SS

DDQ

SS

V

DQ14

DQ15

V

DQ36

DQ37

DQ56

DQ57

SS

DDQ

SS

V

DQ10

DQ11

V

CKE1

DQ32

DQ33

DDQ

SS

V

CKE0

DM7

NC

SS

DD

SS

V

DQ20

DQ21

V

NC

DM4

NC

DQS7

SS

DD

SS

V

DQ16

DQ17

V

NC

DQS4

SS

V

DQ62

DQ63

SS

DDQ

SS

V

DM2

NC

V

A12

A9

DQ38

DQ39

DQ58

DQ59

SS

DDQ

SS

V

DQS2

V

A11

A7

DQ34

DQ35

SS

V

VDDSPD

SA0

SA1

SS

DD

SS

V

DQ22

DQ23

A8

A6

DQ44

DQ45

SDA

SCL

SS

DD

SS

DQ18

A5

DQ40

DQ41

V

SS

NC = No Connect, RFU = Reserved for Future Use

1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.

2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

x72 DIMM Pin Configurations (Front side/Back side)

1

Front

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Back

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

Front

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Back

61

Front

181

182

183

184

Back

DDQ

91

92

93

94

95

96

97

98

Front

SS

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

DM5

NC

V

DQ19

A4

REF

SS

V

2

3

4

5

6

7

8

9

DQ4

DQ5

DQ28

DQ29

62

63

64

A3

A1

DQS5

SS

DDQ

V

DQ0

DQ1

V

DQ24

DQ25

A2

SS

V

DQ46

DQ47

SS

DD

SS

V

DM0

NC

DM3

NC

KEY

DQ42

DQ43

SS

V

DQS0

V

DQS3

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

CK0

SS

V

DQ52

DQ53

SS

V

DQ6

DQ7

DQ30

DQ31

DQ48

DQ49

SS

DD

V

DQ2

DQ3

V

DQ26

DQ27

NC

A0

99

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

CK2

SS

DD

SS

V

DQ12

DQ13

CB4

CB5

A10/AP

BA0

BA1

SA2

SS

2

V

DQ8

DQ9

V

CB0

CB1

NC, TEST

DDQ

SS

V

RAS

S0

DM6

NC

SS

DDQ

SS

V

DM1

NC

DM8

NC

WE

CAS

DQS6

SS

V

DQS1

V

DQS8

DDQ

SS

V

ODT0

A13

DQ54

DQ55

SS

DDQ

SS

V

CK1

CB6

CB7

S1

ODT1

DQ50

DQ51

SS

V

NC

V

CB2

CB3

DD

SS

V

DQ60

DQ61

SS

DDQ

SS

V

DQ14

DQ15

DQ36

DQ37

DQ56

DQ57

SS

DDQ

SS

V

DQ10

DQ11

V

CKE1

DQ32

DQ33

DDQ

SS

V

CKE0

DM7

NC

SS

DD

SS

V

DQ20

DQ21

NC

DM4

NC

DQS7

SS

DD

SS

V

DQ16

DQ17

V

NC

DQS4

SS

V

DQ62

DQ63

SS

DDQ

SS

V

DM2

NC

A12

A9

DQ38

DQ39

DQ58

DQ59

SS

DDQ

SS

V

DQS2

V

A11

A7

DQ34

DQ35

SS

V

VDDSPD

SA0

SA1

SS

DD

SS

V

DQ22

DQ23

A8

A6

DQ44

DQ45

SDA

SCL

SS

DD

SS

DQ18

A5

DQ40

DQ41

V

SS

NC = No Connect, RFU = Reserved for Future Use

1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.

2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)

Pin Description

Pin Name

Description

Pin Name

CK0, CK1, CK2

SCL

Description

A0-A13

DDR2 SDRAM address bus

DDR2 SDRAM bank select

DDR2 SDRAM row address strobe

DDR2 SDRAM column address strobe

DDR2 SDRAM wirte enable

DIMM Rank Select Lines

DDR2 SDRAM clocks (positive line of differential pair)

DDR2 SDRAM clocks (negative line of differential pair)

BA0, BA1

RAS

2

I C serial bus clock for EEPROM

2

CAS

SDA

I C serial bus data line for EEPROM

2

WE

SA0-SA2

I C serial address select for EEPROM

S0, S1

V

*

DDR2 SDRAM core power supply

DDR2 SDRAM I/O Driver power supply

DDR2 SDRAM I/O reference supply

Power supply return (ground)

Serial EEPROM positive power supply

Spare Pins(no connect)

DD

CKE0,CKE1

ODT0, ODT1

DQ0 - DQ63

CB0 - CB7

DQS0 - DQS8

DM(0-8)

DDR2 SDRAM clock enable lines

On-die termination control lines

DIMM memory data bus

*

DDQ

REF

SS

DIMM ECC check bits

SPD

DD

DDR2 SDRAM data strobes

DDR2 SDRAM data masks

DDR2 SDRAM differential data strobes

NC

RESET

TEST

Not used on UDIMM

DQS0-DQS8

Used by memory bus analysis tools (unused on memory DIMMs)

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Input/Output Functional Description

Symbol

Type

Function

CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge

of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of

crossing)

CK0-CK2

Input

Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks,

CKE low initiates the Powe Down mode, or the Self-Refresh mode

CKE0-CKE1

S0-S1

Input

Enables the associated SDRAM command decoder when low and disables the command decoder when high. When

the command decoder is disbled, new command are ignored but previous operations continue. This signal provides

for external rank selection on systems with multiple ranks

RAS, CAS, WE

ODT0-ODT1

Input

RAS, CAS, and WE (ALONG WITH CS) define the command being entered.

When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the

Extended Mode Register Set (EMRS).

V

Supply

Input

Reference voltage for SSTL 18 inputs.

REF

Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuf-

fered DIMM designs, VDDQ shares the same power plane as VDD pins.

V

DDQ

BA0-BA1

A0-A13

Selects which SDRAM BANK of four is activated.

During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)

During a Read or Write command cycle, Address input defines the colum address, In addition to the column address,

AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge

is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a pre-

charge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high,

all banks will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank

to precharge.

Input

DQ0-DQ63

CB0-CB7

In/Out

Input

Data and Check Bit Input/Output pins.

DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input

data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading

matches the DQ and DQS loading.

DM0-DM8

Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to V /V

planes

DD DDQ

V

,V

Supply

In/Out

Input

DD SS

on these modules.

DQS0-DQS8

Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of

the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM

These signals and tied at the system planar to either V or V

SS

to configure the serial SPD EERPOM address

DD

SA0-SA2

SDA

range.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the

SDA bus line to VDD to act as a pullup on the system board.

In/Out

Input

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus

time to VDD to act as a pullup onthe system board.

SCL

Power supply for SPD EEPROM. This supply is separate from the V /V

power plane. EEPROM supply is oper-

DD DDQ

V

SPD

Supply

DD

able from 1.7V to 3.6V.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Functional Block Diagram: 512MB, 64Mx64 Module(Populated as 1 rank of x8 DDR2 SDRAMs)

M378T6553BG(Z)3 / M378T6553BG(Z)0

S0

DQS0

DM0

DQS4

DM4

DM

I/O 0

CS DQS DQS

DM

I/O 0

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D4

DQS1

DM1

DQS5

DM5

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ9

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D6

DQS3

DM3

DQS7

DM7

DM

NU/ CS DQS DQS

DM

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D7

V

Serial PD

DDSPD

Serial PD

SCL

WP

* Clock Wiring

/V

D0 - D7

DD DDQ

SDA

Clock Input DDR2 SDRAMs

VREF

A0

A1

A2

*CK0/CK0 2 DDR2 SDRAMs

*CK1/CK1 3 DDR2 SDRAMs

*CK2/CK2 3 DDR2 SDRAMs

V

SA0 SA1 SA2

SS

BA0 - BA1

A0 - A13

RAS

BA0-BA1 : DDR2 SDRAMs D0 - D7

A0-A13 : DDR2 SDRAMs D0 - D7

RAS : DDR2 SDRAMs D0 - D7

CAS : DDR2 SDRAMs D0 - D7

CKE : DDR2 SDRAMs D0 - D7

WE : DDR2 SDRAMs D0 - D7

ODT : DDR2 SDRAMs D0 - D7

*Wire per Clock Loading

Table/Wiring Diagrams

CAS

Notes :

CKE0

WE

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.

ODT0

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Functional Block Diagram: 512MB, 64Mx72 ECC Module(Populated as 1 rank of x8 DDR2 SDRAMs)

M391T6553BG(Z)3 / M391T6553BG(Z)0

S0

DQS0

DM0

DQS4

DM4

DM

I/O 0

CS DQS DQS

DM

I/O 0

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D4

DQS1

DM1

DQS5

DM5

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ9

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D6

DQS3

DM3

DQS7

DM7

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D7

DQS8

DM8

Serial PD

SCL

WP

DM

CS DQS DQS

SDA

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A0

A1

A2

D8

SA0 SA1

SA2

* Clock Wiring

Clock Input DDR2 SDRAMs

V

Serial PD

D0 - D8

DDSPD

/V

DD DDQ

*CK0/CK0 3 DDR2 SDRAMs

*CK1/CK1 3 DDR2 SDRAMs

*CK2/CK2 3 DDR2 SDRAMs

VREF

BA0 - BA1

A0 - A13

RAS

BA0-BA1 : DDR2 SDRAMs D0 - D8

A0-A13 : DDR2 SDRAMs D0 - D8

RAS : DDR2 SDRAMs D0 - D8

CAS : DDR2 SDRAMs D0 - D8

CKE : DDR2 SDRAMs D0 - D8

WE : DDR2 SDRAMs D0 - D8

ODT : DDR2 SDRAMs D0 - D8

V

SS

*Wire per Clock Loading

Table/Wiring Diagrams

CAS

Notes :

CKE0

WE

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.

ODT0

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs)

M378T2953BG(Z)3 / M378T2953BG(Z)0

S1

S0

DQS0

DM0

DQS4

DM4

DM

I/O 0

CS DQS DQS

DM

I/O 0

CS DQS DQS

DM

I/O 0

CS DQS DQS

DM

I/O 0

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D8

D4

D12

DQS1

DM1

DQS5

DM5

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ9

D1

D9

D5

D13

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D10

D6

D14

DQS3

DM3

DQS7

DM7

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D11

D7

D15

V

Serial PD

DDSPD

Serial PD

/V

D0 - D15

DD DDQ

SCL

WP

SDA

VREF

A0

A1

A2

SA2

* Clock Wiring

Clock Input DDR2 SDRAMs

V

SS

SA0 SA1

BA0 - BA1

A0 - A13

CKE0

BA0-BA1 : DDR2 SDRAMs D0 - D15

A0-A13 : DDR2 SDRAMs D0 - D15

CKE : DDR2 SDRAMs D0 - D7

CKE : DDR2 SDRAMs D8 - D15

RAS : DDR2 SDRAMs D0 - D15

CAS : DDR2 SDRAMs D0 - D15

*CK0/CK0 4 DDR2 SDRAMs

*CK1/CK1 6 DDR2 SDRAMs

*CK2/CK2 6 DDR2 SDRAMs

CKE1

RAS

CAS

*Wire per Clock Loading

Table/Wiring Diagrams

Notes :

WE

ODT0

ODT1

WE : DDR2 SDRAMs D0 - D15

ODT : DDR2 SDRAMs D0 - D7

ODT : DDR2 SDRAMs D8 - D15

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Functional Block Diagram: 1GB, 128Mx72 ECC Module^{(Populated as 2 ranks of x8 DDR2 SDRAMs)}

M391T2953BG(Z)3 / M391T2953BG(Z)0

S1

S0

DQS0

DM0

DQS4

DM4

DM

I/O 0

CS DQS DQS

DM

I/O 0

CS DQS DQS

DM

I/O 0

CS DQS DQS

DM

I/O 0

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D9

D4

D13

DQS1

DM1

DQS5

DM5

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ9

D1

D10

D5

D14

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D11

D6

D15

DQS3

DM3

DQS7

DM7

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D12

D7

D16

DQS8

DM8

Serial PD

SCL

WP

DM

CS DQS DQS

DM

CS DQS DQS

SDA

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A0

A1

A2

D8

D17

SA0 SA1 SA2

* Clock Wiring

Clock Input

DDR2 SDRAMs

V

Serial PD

DDSPD

BA0 - BA1

A0 - A13

CKE0

BA0-BA1 : DDR2 SDRAMs D0 - D17

A0-A13 : DDR2 SDRAMs D0 - D17

CKE : DDR2 SDRAMs D0 - D8

*CK0/CK0 6 DDR2 SDRAMs

*CK1/CK1 6 DDR2 SDRAMs

*CK2/CK2 6 DDR2 SDRAMs

V

/V

D0 - D17

DD DDQ

VREF

CKE1

RAS

CAS

CKE : DDR2 SDRAMs D9 - D17

RAS : DDR2 SDRAMs D0 - D17

CAS : DDR2 SDRAMs D0 - D17

*Wire per Clock Loading

Table/Wiring Diagrams

V

SS

Notes :

WE

ODT0

ODT1

WE : DDR2 SDRAMs D0 - D17

ODT : DDR2 SDRAMs D0 - D8

ODT : DDR2 SDRAMs D9 - D17

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Functional Block Diagram: 256MB, 32Mx64 Module^{(Populated as 1 rank of x16 DDR2 SDRAMs)}

M378T3354BG(Z)3 / M378T3354BG(Z)0

S0

CS

DQS1

DM1

DQS5

DM5

LDQS

LDOS

LDM

LDQS

LDOS

LDM

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ9

D0

D2

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS0

DM0

DQS4

DM4

UDQS

UDOS

UDM

UDQS

UDOS

UDM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

DQS3

DM3

DQS7

DM7

LDQS

LDOS

LDM

LDQS

LDOS

LDM

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D3

DQS2

DM2

DQS6

DM6

UDQS

UDOS

UDM

UDQS

UDOS

UDM

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

* Clock Wiring

V

Serial PD

DDSPD

Clock Input

DDR2 SDRAMs

V

/V

D0 - D3

DD DDQ

Serial PD

*CK0/CK0

*CK1/CK1

*CK2/CK2

NC

SCL

WP

VREF

2 DDR2 SDRAMs

SDA

V

A0

A1

A2

SS

*Wire per Clock Loading

Table/Wiring Diagrams

SA0 SA1

SA2

BA0 - BA1

A0 - A12

CKE0

BA0-BA1 : DDR2 SDRAMs D0 - D3

A0-A12 : DDR2 SDRAMs D0 - D3

CKE : DDR2 SDRAMs D0 - D3

RAS : DDR2 SDRAMs D0 - D3

CAS : DDR2 SDRAMs D0 - D3

Notes :

RAS

CAS

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

4. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.

WE

ODT0

WE : DDR2 SDRAMs D0 - D3

ODT : DDR2 SDRAMs D0 - D3

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Absolute Maximum DC Ratings

Symbol

Parameter

Rating

Units

Notes

Voltage on V pin relative to V

- 1.0 V ~ 2.3 V

V

1

V

DD

SS

DD

Voltage on V

pin relative to V

- 0.5 V ~ 2.3 V

-55 to +100

V

1

V

DDQ

DDL

SS

DDQ

pin relative to V

V

SS

DDL

Voltage on any pin relative to V

Storage Temperature

V

1

V

SS

IN, OUT

T

°C

1, 2

STG

Note :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.

AC & DC Operating Conditions

Recommended DC Operating Conditions (SSTL - 1.8)

Rating

Typ.

1.8

Symbol

Parameter

Units

Notes

Min.

1.7

Max.

1.9

V

Supply Voltage

V

DD

V

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

1.8

1.9

4

DDL

V

1.7

1.8

1.9

V

4

DDQ

V

0.49*V

0.50*V

0.51*V

DDQ

mV

V

1,2

REF

DDQ

V

-0.04

V

V +0.04

REF

3

TT

REF

Note : There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V

must be less than or equal

DDQ

DD

to V

.

DD

1. The value of V

may be selected by the user to provide optimum noise margin in the system. Typically the value of V

is expected to be about 0.5

REF

x V

of the transmitting device and V

is expected to track variations in V

.

DDQ

REF

2. Peak to peak AC noise on V

may not exceed +/-2% V

(DC).

REF

3. V of transmitting device must track V

of receiving device.

REF

TT

4. AC parameters are measured with V , V

and V

tied together.

DDL

DD

DDQ

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Operating Temperature Condition

Symbol

Parameter

Rating

Units

Notes

TOPER

Operating Temperature

0 to 95

°C

1, 2, 3

Note :

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2

standard.

2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.

3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self

refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

Input DC Logic Level

Symbol

V_IH(DC)

V_IL(DC)

Parameter

Min.

V_REF+ 0.125

- 0.3

Max.

Units

Notes

DC input logic high

DC input logic low

V_DDQ+ 0.3

V_REF- 0.125

V

Input AC Logic Level

Symbol

V_IH(AC)

V_IL(AC)

Parameter

Min.

Max.

Units

AC input logic high

AC input logic low

V_REF+ 0.250

-

V

V_REF- 0.250

AC Input Test Conditions

Symbol

Condition

Value

Units

V

Notes

V_REF

Input reference voltage

0.5 * V

1.0

1

DDQ

V

Input signal maximum peak to peak swing

Input signal minimum slew rate

V

SWING(MAX)

SLEW

1.0

V/ns

2, 3

Notes:

1. Input waveform timing is referenced to the input signal crossing through the V

(AC) level applied to the device under test.

IH/IL

2. The input signal minimum slew rate is to be maintained over the range from V

to V (AC) min for rising edges and the range from V

to V (AC)

REF IL

REF

IH

max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative

IL

IH

IL

transitions.

V

DDQ

(AC) min

IH

(DC) min

IH

V

SWING(MAX)

REF

(DC) max

IL

(AC) max

SS

delta TF

V

delta TR

Rising Slew =

- V (AC) max

IL

V

(AC) min - V

delta TR

REF

IH

REF

Falling Slew =

delta TF

< AC Input Test Signal Waveform >

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

IDD Specification Parameters Definition

(IDD values are for full operating range of Voltage and Temperature)

Symbol

Proposed Conditions

Units Notes

Operating one bank active-precharge current;

CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

t

IDD0

mA

Operating one bank active-read-precharge current;

t

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =

IDD1

mA

t

RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern

is same as IDD4W

Precharge power-down current;

All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

t

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

t

mA

Precharge quiet standby current;

t

All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

Precharge standby current;

t

All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Active power-down current;

mA

Fast PDN Exit MRS(12) = 0mA

t

All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus

Slow PDN Exit MRS(12) = 1mA

inputs are STABLE; Data bus inputs are FLOATING

Active standby current;

t

mA

All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst write current;

t

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP

IDD4W

IDD4R

t

= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus

inputs are SWITCHING

Operating burst read current;

t

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-

mA

t

max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-

ING; Data pattern is same as IDD4W

Burst auto refresh current;

t

IDD5B

IDD6

CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current;

Normal

mA

CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Low Power

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC =

t

IDD7

t

mA

RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow-

ing page for detailed timing conditions

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Operating Current Table(1-1) (TA=0^oC, VDD= 1.9V)

M378T6553BG(Z)3 / M378T6553BG(Z)0 : 512MB(64Mx8 *8) Module

D5

CC

Symbol

Unit

Notes

(DDR2-533@CL=4)

(DDR2-400@CL=3)

IDD0

IDD1

800

760

mA

880

800

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

64

200

240

120

560

520

1,600

1,440

1,560

44

1,160

1,480

44

IDD6

Normal

IDD7

2,200

2,160

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M378T2953BG(Z)3 / M378T2953BG(Z)0 : 1GB(64Mx8 *16) Module

D5

CC

Symbol

Unit

Notes

(DDR2-533@CL=4)

(DDR2-400@CL=3)

IDD0

IDD1

1,360

1,440

128

1,280

1,320

128

mA

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

400

480

240

1,120

2,160

2,000

2,120

88

1,040

1,680

2,000

88

IDD6

Normal

IDD7

2,760

2,680

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Operating Current Table(1-2) (TA=0^oC, VDD= 1.9V)

M378T3354BG(Z)3 / M378T3354BG(Z)0 : 256MB(32Mx16 *4) Module

D5

CC

Symbol

Unit

Notes

(DDR2-533@CL=4)

(DDR2-400@CL=3)

IDD0

IDD1

480

580

32

460

500

32

mA

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

100

120

60

100

120

60

280

920

820

780

22

260

740

680

740

22

IDD6

Normal

IDD7

1,560

1,500

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M391T6553BG(Z)3 / M391T6553BG(Z)0 : 512MB(64Mx8 *9) ECC Module

D5

CC

Symbol

Unit

Notes

(DDR2-533@CL=4)

(DDR2-400@CL=3)

IDD0

IDD1

900

855

mA

990

900

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

72

225

270

135

630

585

1,800

1,620

1,755

50

1,305

1,665

50

IDD6

Normal

IDD7

2,475

2,430

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Operating Current Table(1-3) (TA=0^oC, VDD= 1.9V)

M391T2953BG(Z)3 / M391T2953BG(Z)0 : 1GB(64Mx8 *18) ECC Module

D5

CC

Symbol

Unit

Notes

(DDR2-533@CL=4)

(DDR2-400@CL=3)

IDD0

IDD1

1,530

1,620

144

1,440

1,485

144

mA

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

450

540

270

1,260

2,430

2,250

2,385

99

1,170

1,890

2,250

99

IDD6

Normal

IDD7

3,105

3,015

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

o

Input/Output Capacitance (VDD=1.8V, VDDQ=1.8V, TA=25 C)

Parameter

Min

Max

Min

Max

Min

Max

Symbol

Units

M378T2953BG(Z)3

M378T2953BG(Z)0

M378T6553BG(Z)3

M378T6553BG(Z)0

M378T3354BG(Z)3

M378T3354BG(Z)0

Non-ECC

CCK0

CCK1

CCK2

CI1

-

24

25

42

6

-

26

28

42

10

-

22

24

34

6

Input capacitance, CK and CK

pF

Input capacitance, CKE and CS

-

Input capacitance, Addr, RAS, CAS, WE

CI2

Input/output capacitance, DQ, DM, DQS, DQS CIO

M391T2953BG(Z)3

M391T2953BG(Z)0

M391T6553BG(Z)3

M391T6553BG(Z)0

ECC

Symbol

Units

CCK0

CCK1

CCK2

-

25

44

-

28

44

Input capacitance, CK and CK

pF

CI

Input capacitance, CKE and CS

-

1

CI

Input capacitance, Addr, RAS, CAS, WE

44

6

44

10

2

Input/output capacitance, DQ, DM, DQS, DQS CIO

* DM is internally loaded to match DQ and DQS identically.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM

(0 °C < T

< 95 °C; V

= 1.8V + 0.1V; V = 1.8V + 0.1V)

DDQ DD

CASE

Refresh Parameters by Device Density

Parameter

Symbol

256Mb

512Mb

1Gb

2Gb

4Gb

Units

Refresh to active/Refresh command time

tRFC

tREFI

75

105

127.5

195

tbd

ns

0 °C ≤ T

≤ 85°C

≤ 95°C

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

µs

CASE

Average periodic refresh interval

85 °C < T

CASE

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed

DDR2-533(D5)

DDR2-400(CC)

3 - 3 - 3

Bin (CL - tRCD - tRP)

4 - 4 - 4

Units

Parameter

tCK, CL=3

tCK, CL=4

tCK, CL=5

tRCD

min

5

max

min

5

max

8

-

8

-

ns

3.75

-

5

-

15

55

40

15

55

40

tRP

tRC

tRAS

70000

Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

DDR2-533

min max

DDR2-400

min max

Symbol

Units

Notes

Parameter

DQ output access time from CK/CK

tAC

-500

-450

0.45

+500

-600

+600

ps

DQS output access time from CK/CK

CK high-level width

tDQSCK

tCH

+450

-500

+500

0.55

0.45

0.55

tCK

ps

CK low-level width

tCL

0.55

0.45

0.55

CK half period

tHP

min(tCL, tCH)

x

min(tCL, tCH)

x

20,21

24

Clock cycle time, CL=x

tCK

3750

8000

5000

8000

ps

DQ and DM input hold time

tDH

225

x

275

x

ps

15,16,17

DQ and DM input setup time

tDS

100

x

150

x

ps

Control & Address input pulse width for each input

DQ and DM input pulse width for each input

Data-out high-impedance time from CK/CK

DQS low-impedance time from CK/CK

DQ low-impedance time from CK/CK

DQS-DQ skew for DQS and associated DQ signals

DQ hold skew factor

tIPW

0.6

x

0.6

x

tCK

ps

tDIPW

tHZ

0.35

x

0.35

x

tAC max

x

tAC max

tLZ(DQS)

tLZ(DQ)

tDQSQ

tQHS

tQH

tAC min

tAC max

tAC min

tAC max

ps

2* tACmin

tAC max

2* tACmin

tAC max

ps

x

300

x

350

ps

x

tHP - tQHS

WL-0.25

0.35

400

x

tHP - tQHS

WL-0.25

0.35

450

ps

DQ/DQS output hold time from DQS

Write command to first DQS latching transition

DQS input high pulse width

x

ps

tDQSS

tDQSH

tDQSL

tDSS

tDSH

tMRD

WL+0.25

tCK

x

DQS input low pulse width

0.35

DQS falling edge to CK setup time

DQS falling edge hold time from CK

0.2

Mode register set command cycle time

2

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

DDR2-533

DDR2-400

Symbol

Units

Notes

Parameter

min

max

0.6

x

min

max

0.6

x

Write postamble

Write preamble

tWPST

tWPRE

tIH

0.4

0.35

375

250

0.9

0.4

0.35

475

350

0.9

tCK

ps

Address and control input hold time

x

Address and control input setup time

Read preamble

tIS

x

ps

tRPRE

tRPST

tRRD

1.1

0.6

x

1.1

0.6

x

tCK

ns

Read postamble

0.4

Active to active command period for 1KB page size products

Active to active command period for 2KB page size products

Four Activate Window for 1KB page size products

Four Activate Window for 2KB page size products

CAS to CAS command delay

7.5

tRRD

tFAW

10

x

10

x

ns

37.5

50

37.5

50

ns

tFAW

ns

tCCD

tWR

2

tCK

ns

Write recovery time

15

x

15

x

Auto precharge write recovery + precharge time

Internal write to read command delay

Internal read to precharge command delay

Exit self refresh to a non-read command

Exit self refresh to a read command

tDAL

tWR+tRP

7.5

tWR+tRP

10

tCK

ns

tWTR

tRTP

7.5

ns

tXSNR

tXSRD

tXP

tRFC + 10

200

2

tRFC + 10

200

2

ns

tCK

Exit precharge power down to any non-read command

Exit active power down to read command

x

tXARD

tXARDS

2

Exit active power down to read command

(Slow exit, Lower power)

6 - AL

t

CKE minimum pulse width

(high and low pulse width)

tCK

3

CKE

t

ODT turn-on delay

2

tCK

ns

AOND

t

ODT turn-on

tAC(min)

tAC(max)+1

tAC(min)

tAC(max)+1

AON

t

ODT turn-on(Power-Down mode)

tAC(min)+2 2tCK+tAC(m tAC(min)+2

ax)+1

2tCK+tAC

(max)+1

ns

AONPD

t

ODT turn-off delay

ODT turn-off

2.5

tCK

ns

AOFD

t

tAC(min)

tAC(max)+ 0.6

tAC(min)

AOF

2.5tCK+

t

ODT turn-off (Power-Down mode)

tAC(min)+2

ns

AOFPD

tAC(max)+1

ODT to power down entry latency

tANPD

tAXPD

tOIT

3

tCK

ns

ODT power down exit latency

8

OCD drive mode output delay

0

12

0

12

Minimum time clocks remains ON after CKE asynchronously drops LOW

tDelay

tIS+tCK +tIH

ns

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Physical Dimensions: 64Mbx8 based 64Mx64/x72 Module(1 Rank)

M378T6553BG(Z)3 / M391T6553BG(Z)3

Units : Millimeters

M378T6553BG(Z)0 / M391T6553BG(Z)0

133.35

131.35

128.95

N/A

(for x64)

SPD

ECC

(for x72)

30.00

(2)

2.50

B

A

2.7

63.00

55.00

1.270 ± 0.10

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 64M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QB

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Physical Dimensions: 64Mbx8 based 128Mx64/x72 Module(2 Ranks)

M378T2953BG(Z)3 / M391T2953BG(Z)3

M378T2953BG(Z)0 / M391T2953BG(Z)0

Units : Millimeters

133.35

131.35

128.95

N/A

(for x64)

SPD

ECC

30.00

(for x72)

(2)

2.50

B

A

4.00

63.00

55.00

N/A

(for x64)

ECC

(for x72)

1.270 ± 0.10

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

Detail B

1.50±0.10

Detail A

The used device is 64M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QB

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Physical Dimensions: 32Mbx16 based 32Mx64 Module(1 Rank)

M378T3354BG(Z)3 / M378T3354BG(Z)0

Units : Millimeters

133.35

131.35

128.95

SPD

30.00

(2)

2.50

B

A

2.7

63.00

55.00

1.270 ± 0.10

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 32M x16 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51163QB

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered DIMMs

DDR2 SDRAM

Revision History

Revision 1.0 (Jan. 2004)

- Initial Release

Revision 1.1 (Jun. 2004)

- Added lead-free part number in the ordering information

- Changed IDD2P

Revision 1.2 (Jul. 2004)

- Added current values and part number of low power product

Revision 1.3 (Feb. 2005)

- Added the detail information for mechanical dimension

Revision 1.4 (Mar. 2005)

- Changed 1GB Functional Block Diagram

Revision 1.5 (Aug. 2005)

- Added Dummy Pad PCB product part number in the ordering information

Rev. 1.5 Aug. 2005


型号：	M378T2953BG0-CCC
厂家：	SAMSUNG
描述：	DDR DRAM Module, 128MX64, 0.6ns, CMOS, DIMM-240 时钟动态存储器双倍数据速率内存集成电路
文件：	总22页 (文件大小：466K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M378T2953BG0-CCC [SAMSUNG]

相关型号：

M378T2953BG0-CD5/CC

M378T2953BG0-CE6

M378T2953BG0-LD5

M378T2953BG3-CCC

M378T2953BG3-CD5

M378T2953BGZ0-CD5/CC

M378T2953BGZ3-CD5/CC

M378T2953BZ0-CCC

M378T2953BZ0-CD5

M378T2953BZ0-CE6

M378T2953BZ3-CCC

M378T2953BZ3-CD5