M381L6423CT1-CLB30_技术文档

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

512MB DDR SDRAM MODULE

(64Mx72(32Mx72*2 bank) based on 32Mx8 DDR SDRAM)

Unbuffered 184pin DIMM

72-bit ECC/Parity

Revision 0.0

September. 2001

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

Revision History

Revision 0 (Sep 2001)

1. First release for internal usage

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

M381L6423CT1 DDR SDRAM 184pin DIMM

64Mx72 DDR SDRAM 184pin DIMM based on 32Mx8

FEATURE

GENERAL DESCRIPTION

• Performance range

The Samsung M381L6423CT1 is 64M bit x 72 Double Data

Rate SDRAM high density memory modules based on 4th

gen. of 256Mb DDR SDRAM respectively.

Part No.

Max Freq.

Interface

M381L6423CT1-C(L)B3 167MHz(6.0ns@CL=2.5)

M381L6423CT1-C(L)A2 133MHz(7.5ns@CL=2)

M381L6423CT1-C(L)B0 133MHz(7.5ns@CL=2.5)

M381L6423CT1-C(L)A0 100MHz(10ns@CL=2)

The Samsung M381L6423CT1 consists of eighteen CMOS

32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin

TSOP-II(400mil) packages mounted on a 184pin glass-epoxy

substrate. Four 0.1uF decoupling capacitors are mounted on

the printed circuit board in parallel for each DDR SDRAM. The

M381L6423CT1 is Dual In-line Memory Modules and intended

for mounting into 184pin edge connector sockets.

SSTL_2

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

Synchronous design allows precise cycle control with the use

of system clock. Data I/O transactions are possible on both

edges of DQS. Range of operating frequencies, programmable

latencies and burst lengths allow the same device to be useful

for a variety of high bandwidth, high performance memory sys-

tem applications.

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1250 (mil), double sided component

PIN CONFIGURATIONS (Front side/back side)

PIN DESCRIPTION

Pin Front Pin Front Pin Front Pin Back Pin Back Pin

Back

Pin Name

A0 ~ A12

Function

Address input (Multiplexed)

1

2

3

4

5

6

7

8

9

10

11

12

13

VREF 32

A5

33 DQ24 63

34 VSS 64

35 DQ25 65

62

VDDQ 93

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

NC

124

125

126

127

VSS

A6

DQ28

DQ29

154

155

156

157

/RAS

DQ45

VDDQ

/CS0

/CS1

DM5

DQ0

VSS

DQ1

/WE

DQ41

/CAS

VSS

94

95

96

97

BA0 ~ BA1

Bank Select Address

Data input/output

DQ0 ~ DQ63

CB0 ~ CB7

Check bit(Data-in/data-out)

Data Strobe input/output

DQS0 36 DQS3 66

128 VDDQ 158

DQ2

VDD

DQ3

NC

37

A4

67

68

DQS5 98

DQ42 99

DQ43 100

VDD 101

*/CS2 102

DQ48 103

129

130

131

132

133

134

135

DM3

A3

159

160

161

162

163

164

165

DQS0 ~ DQS8

38 VDD

39 DQ26 69

40 DQ27 70

VSS

CK0,CK0 ~ CK2, CK2 Clock input

DQ30

VSS

DQ31

CB4

CB5

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

NC

CKE0,CKE1

CS0, CS1

RAS

Clock enable input

Chip select input

NC

41

42

43

44

A2

VSS

A1

CB0

CB1

71

72

73

74

75

76

NC

*A13

VSS

DQ8

DQ9

Row address strobe

Column address strobe

Write enable

DQ49 104 VDDQ

CAS

VSS

/CK2

CK2

105

106

107

DQ12

DQ13

DM1

136 VDDQ 166

WE

14 DQS1 45

15 VDDQ 46 VDD

16

17

18

19 DQ10 50

20 DQ11 51

21 CKE0 52

22 VDDQ

23 DQ16 53 DQ32 84

24 DQ17 54 VDDQ 85

25 DQS2 55 DQ33 86

137

138

139

140

141

142

CK0

/CK0

VSS

DM8

A10

167

168

169

170

171

172

DM0 ~ DM8

VDD

Data - in mask

VDD

DM6

CK1

/CK1 48

VSS 49

47 DQS8 77

VDDQ 108

DQS6 109

DQ50 110

DQ51 111

VDD

Power supply (2.5V)

Power Supply for DQS(2.5V)

Ground

A0

78

79

80

81

DQ14

DQ15

CKE1

DQ54

DQ55

VDDQ

NC

DQ60

DQ61

VSS

VDDQ

VSS

CB2

VSS

CB3

BA1

CB6

VSS

112 VDDQ

143 VDDQ 173

144

VREF

Power supply for reference

82 VDDID 113

*BA2

DQ20

A12

VSS

DQ21

A11

DM2

VDD

DQ22

A8

CB7

KEY

174

175

176

177

178

179

180

181

182

183

VDDSPD

Serial EEPROM Power

Supply (2.3V to 3.6V)

KEY

83

DQ56 114

DQ57 115

145

146

147

148

149

150

151

152

153

VSS

DQ36

DQ37

VDD

SDA

Serial data I/O

VDD

116

DM7

SCL

Serial clock

DQS7 117

DQ58 118

DQ59 119

DQ62

DQ63

VDDQ

SA0

SA1

SA2

26

27

VSS

A9

56 DQS4 87

57 DQ34 88

SA0 ~ 2

VDDID

NC

Address in EEPROM

VDD identification flag

No connection

DM4

28 DQ18 58

29 A7 59

30 VDDQ 60 DQ35 91

31 DQ19 61 DQ40 92

VSS

BA0

89

90

VSS

NC

SDA

SCL

120

121

122

123

DQ38

DQ39

VSS

*

These pins are not used in this module.

DQ23

DQ44

184 VDDSPD

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

Functional Block Diagram

CS1

CS0

DQS4

DM4

DQS0

DM0

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

DM

I/O 0

DQS

CS

D4

CS

DM

I/O 7

DQS

CS

D0

DM

CS DQS

D9

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D13

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS5

DM5

DQS1

DM1

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

D5

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS

DQS

DM

DQS

CS

D1

DM

DQS

CS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D14

DQ9

D10

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS6

DM6

DQS2

DM2

DM

DQS

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

D6

DM

I/O 0

I/O 1

CS DQS

D15

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

D 2

CS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

D11

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS7

DM7

DQS3

DM3

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

D 7

DM

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CS DQS

D16

DM

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

D3

DM

CS DQS

D12

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS8

DM8

DM

I/O 7

CS DQS

D8

CS DQS

D17

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

*Clock Net Wiring

Dram1

Dram2

Dram3

R=120W

Serial PD

* Clock Wiring

SCL

WP

Clock

Input

SDRAMs

SDA

Card

Edge

Dram4

A0

A1

A2

6 SDRAMs

CK0/CK0

CK1/CK1

CK2/CK2

Dram5

SA0 SA1 SA2

Dram6

BA0-BA1: SDRAMs D0 - D17

A0-A13: SDRAMs D0 - D17

BA0 - BA1

A0 - A13

V_DDSPD

V_DD/V_DDQ

RAS

CAS

RAS: SDRAMs D0 - D17

CAS: SDRAMs D0 - D17

SPD

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

3. DQ, DQS, DM resistors: 22 Ohms.

4. VDDID strap connections

(for memory device VDD, VDDQ):

STRAP OUT (OPEN): VDD = VDDQ

STRAP IN (VSS): VDD ¹ VDDQ.

D0 - D17

CKE1

CKE0

WE

CKE: SDRAMs D9 - D17

CKE: SDRAMs D0 - D8

WE: SDRAMs D0 - D17

VREF

V_SS

D0 - D17

V_DDID

Strap: see Note 4

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Voltage on VDDQ supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD

Value

-0.5 ~ 3.6

-1.0 ~ 3.6

-0.5 ~ 3.6

-55 ~ +150

18

Unit

V

VDDQ

TSTG

V

°C

W

Power dissipation

PD

Short circuit current

IOS

50

mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter

Supply voltage(for device with a nominal VDD of 2.5V)

I/O Supply voltage

Symbol

VDD

Min

2.3

Max

2.7

Unit

Note

VDDQ

2.3

2.7

V

I/O Reference voltage

VREF

VDDQ/2-50mV VDDQ/2+50mV

1

2

4

I/O Termination voltage(system)

Input logic high voltage

V

VREF-0.04

VREF+0.04

VDDQ+0.3

VREF-0.15

VDDQ+0.3

VDDQ+0.6

1.35

V

TT

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

VIX(DC)

II

VREF+0.15

V

Input logic low voltage

-0.3

0.3

1.15

-2

V

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

Input crossing point voltage, CK and CK inputs

Input leakage current

V

3

5

V

2

uA

Output leakage current

IOZ

-5

5

Output High Current(Normal strengh driver)

IOH

IOL

IOH

-16.8

16.8

-9

mA

;V

= V + 0.84V

TT

OUT

Output High Current(Normal strengh driver)

;V = V - 0.84V

OUT

TT

Output High Current(Half strengh driver)

;V = V + 0.45V

OUT

TT

Output High Current(Half strengh driver)

;V = V - 0.45V

IOL

9

mA

OUT

TT

Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled

TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.

2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to

TT

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.

5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

DDR SDRAM SPEC Items and Test Conditions

Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C)

Conditions

Symbol

IDD0

Typical

Worst

Operating current - One bank Active-Precharge;

-

tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

DQ,DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

Operating current - One bank operation ; One bank open, BL=4, Reads

- Refer to the following page for detailed test condition

IDD1

-

Percharge power-down standby current; All banks idle; power - down mode;

CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Vin = Vref for DQ,DQS and DM

IDD2P

Precharge Floating standby current; CS# > =VIH(min);All banks idle;

CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Address and other control inputs changing once per clock cycle;

Vin = Vref for DQ,DQS and DM

IDD2F

IDD2Q

-

Precharge Quiet standby current; CS# > = VIH(min); All banks idle;

CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);

Vin = Vref for DQ ,DQS and DM

Active power - down standby current ; one bank active; power-down mode;

CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;

Vin = Vref for DQ,DQS and DM

IDD3P

IDD3N

-

Active standby current; CS# >= VIH(min); CKE>=VIH(min);

one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,

133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice

per clock cycle; address and other control inputs changing once

per clock cycle

Operating current - burst read; Burst length = 2; reads; continguous burst;

One bank active; address and control inputs changing once per clock cycle;

CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =

133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A

IDD4R

IDD4W

-

Operating current - burst write; Burst length = 2; writes; continuous burst;

One bank active address and control inputs changing once per clock cycle;

CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,

CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice

per clock cycle, 50% of input data changing at every burst

Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,

IDD5

-

10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh

Self refresh current; CKE =< 0.2V; External clock should be on;

tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B

IDD6

Orerating current - Four bank operation ; Four bank interleaving with BL=4

IDD7A

-Refer to the following page for detailed test condition

Typical case: VDD = 2.5V, T = 25’ C

Worst case : VDD = 2.7V, T = 10’ C

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

DDR SDRAM I_DDspec table

B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) A0(DDR200@CL=2)

Symbol

Unit

Notes

typical

TBD

worst

1485

1800

576

typical

TBD

worst

1215

1575

477

typical

TBD

worst

1215

1575

477

typical

TBD

worst

1125

1485

432

IDD0

IDD1

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

828

693

612

TBD

873

TBD

738

TBD

738

TBD

675

1080

2070

2205

2295

54

900

810

1845

1710

1935

54

1845

1710

1935

54

1620

1485

1755

54

Normal

Low power

IDD7A

IDD6

TBD

3690

TBD

3105

TBD

3105

TBD

2565

Optional

* Module I_DDwas calculated on the basis of component I_DDand can be differently measured according to DQ loading cap.

< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >

IDD1 : Operating current: One bank operation

1. Typical Case : Vdd = 2.5V, T=25’ C

2. Worst Case : Vdd = 2.7V, T= 10’ C

3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once

per clock cycle. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK

Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK

Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing

*50% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

IDD7A : Operating current: Four bank operation

1. Typical Case : Vdd = 2.5V, T=25’ C

2. Worst Case : Vdd = 2.7V, T= 10’ C

3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not

changing. lout = 0mA

4. Timing patterns

- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK

Read with autoprecharge

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK

Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing

*100% of data changing at every burst

Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP

AC Operating Conditions

Max

Parameter/Condition

Symbol

Min

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

VIH(AC) VREF + 0.31

VIL(AC)

V

3

1

2

VREF - 0.31

VDDQ+0.6

VID(AC) 0.7

Input Crossing Point Voltage, CK and CK inputs

VIX(AC) 0.5*VDDQ-0.2

0.5*VDDQ+0.2

Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.

IX

DDQ

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-

tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)

Parameter

Value

Unit

Note

Input reference voltage for Clock

0.5 * VDDQ

V

Input signal maximum peak swing

Input Levels(VIH/VIL)

1.5

VREF+0.31/VREF-0.31

VREF

V

Input timing measurement reference level

Output timing measurement reference level

Output load condition

Vtt

See Load Circuit

Vtt=0.5*VDDQ

RT=50W

Output

Z0=50W

VREF

=0.5*VDDQ

CLOAD=30pF

Output Load Circuit (SSTL_2)

Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)

Parameter

Symbol

CIN1

Min

69

44

27

6

Max

Unit

pF

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE )

Input capacitance(CKE0,CKE1)

87

53

34

8

CIN2

Input capacitance( CS0, CS1)

CIN3

Input capacitance( CLK0, CLK1, CLK2)

Input capacitance(DM0~DM8)

CIN4

CIN5

Data & DQS input/output capacitance(DQ0~DQ63)

Data input/output capacitance(CB0~CB7)

COUT1

COUT2

6

8

6

8

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)

-TCA2(DDR266A) -TCB0(DDR266B) -TCA0 (DDR200)

Parameter

Symbol

Unit

Note

Min

65

Max

Min

65

Max

Min

70

80

48

20

15

2

Max

Row cycle time

tRC

tRFC

tRAS

tRCD

tRP

ns

Refresh row cycle time

Row active time

75

45

120K

45

120K

ns

RAS to CAS delay

20

ns

Row precharge time

20

ns

Row active to Row active delay

Write recovery time

tRRD

tWR

15

ns

2

tCK

ns

Last data in to Read command

Col. address to Col. address delay

tCDLR

tCCD

1

CL=2.0

CL=2.5

7.5

0.45

-0.75

-

12

10

12

10

12

5

Clock cycle time

tCK

7.5

0.45

-0.75

-

12

ns

Clock high level width

tCH

tCL

0.55

+0.75

+0.5

1.1

0.55

+0.75

+0.5

1.1

0.45

-0.8

-

0.55

+0.8

+0.6

1.1

tCK

ns

Clock low level width

DQS-out access time from CK/CK

tDQSCK

tAC

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

ns

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPREH

tDSS

ns

5

2

0.9

0.4

0.75

0

0.9

0.4

0.75

0

0.9

0.4

0.75

0

tCK

ns

Read Postamble

0.6

CK to valid DQS-in

1.25

DQS-in setup time

DQS-in hold time

0.25

0.2

0.35

0.25

0.2

0.35

0.25

0.2

0.35

tCK

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold time

DQS-in high level width

tDSH

tDQSH

tCK

ns

DQS-in low level width

tDQSL

tDSC

tIS

0.35

0.9

0.35

0.9

0.35

0.9

DQS-in cycle time

1.1

Address and Control Input setup time

Address and Control Input hold time

Data-out high impedence time from CK/CK

0.9

1.1

6

tIH

0.9

1.1

ns

tHZ

tACmin - tACmax tACmin tACmax tACmin tACmax

400ps - 400ps - 400ps - 400ps - 400ps - 400ps

ps

Data-out low impedence time from CK/CK

tLZ

tACmin - tACmax tACmin tACmax tACmin tACmax

400ps

- 400ps - 400ps - 400ps - 400ps - 400ps

Input Slew Rate(for input only pins)

Input Slew Rate(for I/O pins)

Output Slew Rate(x4,x8)

tSL(I)

tSL(IO)

tSL(O)

0.5

1.0

0.7

0.5

1.0

0.7

V/ns

6

7

0.5

1.0

4.5

5

4.5

5

4.5

5

10

Output Slew Rate(x16)

tSL

0.7

(O)

Output Slew Rate Matching Ratio(rise to fall)

t

0.67

1.5

0.67

1.5

0.67

1.5

SLMR

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

-TCA2(DDR266A)

-TCB0(DDR266B)

-TCA0 (DDR200)

Parameter

Symbol

Unit Note

Min

15

Max

Min

15

Max

Min

16

Max

Mode register set cycle time

DQ & DM setup time to DQS

DQ & DM hold time to DQS

tMRD

tDS

ns

0.5

0.6

ns

7,8,9

tDH

0.5

1.75

10

0.5

1.75

10

0.6

2

DQ & DM input pulse width

tDIPW

tPDEX

tXSW

tXSA

tXSR

ns

Power down exit time

10

Exit self refresh to write command

Exit self refresh to bank active command

Exit self refresh to read command

95

116

80

ns

75

200

15.6

7.8

ns

4

200

15.6

7.8

200

15.6

7.8

Cycle

us

64Mb, 128Mb

Refresh interval time

256Mb

tREF

1

us

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

Output DQS valid window

Clock half period

tQH

tHP

-

ns

5

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

-

Data hold skew factor

tQHS

0.75

0.8

ns

DQS write postamble time

tWPST

0.25

tCK

3

Note : 1. Maximum burst refresh of 8

2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from

High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,

DQS could be High at this time, depending on tDQSS.

3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,

but system performance (bus turnaround) will degrade accordingly.

4. A write command can be applied with tRCD satisfied after this command.

5. For registered DINNs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half

period jitter due to crosstalk (t JIT(crosstalk)) on the DIMM.

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

6. Input Setup/Hold Slew Rate Derating

Input Setup/Hold Slew Rate

DtIS

(ps)

0

DtIH

(ps)

0

(V/ns)

0.5

0.4

+50

+100

+50

+100

0.3

This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate

IS IH

based on the lesser of AC-AC slew rate and DC-DC slew rate.

7. I/O Setup/Hold Slew Rate Derating

I/O Setup/Hold Slew Rate

DtDS

(ps)

0

DtDH

(ps)

0

(V/ns)

0.5

0.4

+75

+150

+75

+150

0.3

This derating table is used to increase t /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate

DS DH

based on the lesser of AC-AC slew rate and DC-DC slew rate.

8. I/O Setup/Hold Plateau Derating

I/O Input Level

(mV)

DtDS

(ps)

DtDH

(ps)

+50

± 280

+50

This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of

up to 2ns.

9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating

Delta Rise/Fall Rate

DtDS

(ps)

0

DtDH

(ps)

0

(ns/V)

0

±0.25

±0.5

+50

+100

+50

+100

This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate

is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall

Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.

10. This parameter is fir system simulation purpose. It is guranteed by design.

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)

-TCB3(DDR333)

Parameter

Symbol

Unit

Note

Min

60

Max

Row cycle time

tRC

tRFC

tRAS

tRCD

tRP

ns

Refresh row cycle time

Row active time

72

42

70K

ns

RAS to CAS delay

18

ns

Row precharge time

18

ns

Row active to Row active delay

Write recovery time

tRRD

tWR

12

ns

15

ns

Last data in to Read command

tCDLR

1

tCK

ns

CL=2.0

CL=2.5

7.5

6

12

4

Clock cycle time

tCK

12

ns

Clock high level width

tCH

tCL

0.45

-0.6

-0.7

-

0.55

+0.6

+0.7

0.45

1.1

tCK

ns

Clock low level width

DQS-out access time from CK/CK

tDQSCK

tAC

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

ns

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPRE

tWPST

tDSS

ns

4

0.9

0.4

0.75

0

tCK

ns

Read Postamble

0.6

CK to valid DQS-in

1.25

DQS-in setup time

2

3

Write Preamble

0.25

0.4

0.2

0.35

tCK

Write Postamble

0.6

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold time

DQS-in high level width

DQS-in low level width

tDSH

tDQSH

tDQSL

Address and Control Input setup/hold time

(fast slew rate)

tIS/tIH

0.75

0.8

ns

Address and Control Input setup/hold time

(slow slew rate)

DQ and DM input setup time

tDS

tDH

tHZ

tLZ

0.45

-0.7

ns

ps

DQ and DM input hold time

Data-out high impedence time from CK/CK

Data-out low impedence time from CK/CK

+0.7

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

-TCB3(DDR333)

Unit Note

Parameter

Symbol

Min

Max

Mode register set cycle time

tMRD

tIPW

2

tCK

ns

Control & Address input pulse width

(for each input)

2.2

DQ & DM input pulse width(for each input)

Exit self refresh to non read command

Exit self refresh to read command

tDIPW

tXSNR

tXSRD

1.75

75

ns

200

tCK

us

64Mb, 128Mb

Refresh interval time

256Mb

15.6

1

4

tREFI

7.8

us

Output DQS valid window

tQH

tHP

tHP-tQHS

-

ns

tCLmin

or tCHmin

Clock half period

ns

Data hold skew factor

tQHS

tRAP

0.55

DQS write postamble time

tRCD or

3

tRAS min

Auto Precharge Write recovery +

Precharge time

tDAL

(tWR/tCK) +

(tRP/tCK)

tCK

1. Maximum burst refresh of 8

2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from

High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,

DQS could be High at this time, depending on tDQSS.

3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,

but system performance (bus turnaround) will degrade accordingly.

4. For registered DINNs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period

jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)

Command Truth Table

A11, A12

A9 ~ A0

COMMAND

CKEn-1

CKEn

CS

RAS

CAS

WE

BA0,1

A10/AP

Note

Register

Extended MRS

H

X

H

L

OP CODE

1, 2

3

Mode Register Set

Auto Refresh

H

L

H

X

Entry

Exit

3

Refresh

Self

Refresh

L

H

L

H

X

L

H

X

H

X

H

3

L

H

X

3

Bank Active & Row Addr.

V

Row Address

Column

Address

(A0~A9 )

Read &

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

H

L

4

L

H

L

H

Column Address

Column

Address

(A0~A9 )

Write &

Column Address

4

H

X

L

H

L

H

L

V

H

4, 6

7

Burst Stop

Precharge

X

Bank Selection

All Banks

V

X

L

X

H

5

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

Active Power Down

X

H

L

Entry

H

Precharge Power Down Mode

H

L

Exit

L

H

X

DM

X

8

9

H

L

X

H

X

H

No operation (NOP) : Not defined

Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Rev. 0.0 Sep. 2001

184pin Unbuffered DDR SDRAM MODULE

M381L6423CT1

PACKAGE DIMENSIONS

Units : Inches (Millimeters)

5.25 ± 0.006

(133.350 ± 0.15)

0.118

(3.00)

5.077

(128.950)

1.25 ± 0.006

±0.15)

(31.75

A

B

2.500

0.10 M

C

B A

0.145 Max

(3.67 Max)

1.95

(49.53)

2.55

(64.77)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

0.157

(4.00)

0.039 ± 0.002

(1.000 ± 0.050)

(6.350)

0.26

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ±0.006

(0.20 ±0.15)

2.175

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00)

0.10

Detail A

M C A M B

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 32Mx8 SDRAM, TSOP.

SDRAM Part NO : K4H560838C-TC

Rev. 0.0 Sep. 2001


型号：	M381L6423CT1-CLB30
厂家：	SAMSUNG
描述：	DDR DRAM Module, 64MX72, 0.7ns, CMOS, DIMM-184 动态存储器双倍数据速率
文件：	总16页 (文件大小：100K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M381L6423CT1-CLB30 [SAMSUNG]

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