M390S1723ET1-C7A [SAMSUNG]
Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, DIMM-168;
| 型号： | M390S1723ET1-C7A |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM Module, 16MX72, 5.4ns, CMOS, DIMM-168 时钟 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128MB, 256MB Registered DIMM
SDRAM
SDRAM Registered Module
168pin Registered Module based on 128Mb E-die (x4, x8)
1,700 / 1,500 / 1,200mil Height & 72-bit ECC
Revision 1.1
May. 2003
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
Revision History
Revision 1.0 (Nov., 2002)
- First release
Revision 1.1 (May, 2003)
- Merged Spec.
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
168Pin Unbuffered DIMM based on 128Mb E-die (x4, x8)
Ordering Information
Part Number
Density
128MB
128MB
256MB
256MB
256MB
Organization
16M x 72
16M x 72
32M x 72
32M x 72
32M x 72
Component Composition
16Mx8(K4S280832E) * 9EA
16Mx8(K4S280832E) * 9EA
32Mx4(K4S280432E)*18EA
32Mx4(K4S280432E)*18EA
16Mx8(K4S280832E)*18EA
Interface
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
M390S1723ETU-C7A
M390S1723ET1-C7A
M390S3320ETU-C7A
M390S3320ET1-C7A
M390S3323ET1-C7A
Operating Frequencies
- 7A
Speed @CL3
CL-tRCD-tRP
133MHz(7.5ns)
3 - 3 - 3
Feature
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
• PCB : Height(1,200mil/1,500mil/1,700mil) , double sided
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
PIN CONFIGURATIONS (Front side/back side)
Pin
Pin
Front
Pin
Front
Front
Pin
Back
Pin
Back
Pin
Back
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10/AP
BA1
VDD
VDD
***CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
*VREF
***CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
CB4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ50
DQ51
VDD
DQ52
NC
*VREF
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
***CLK3
NC
**SA0
**SA1
**SA2
VDD
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
BA0
A11
VDD
***CLK1
*A12
VSS
***CKE0
CS3
DQM6
DQM7
*A13
VDD
NC
CB1
VSS
NC
NC
VDD
WE
CB5
VSS
NC
NC
VDD
CAS
DQM4
***CLK2
NC
NC
**SDA
**SCL
VDD
NC
CB6
CB7
VSS
DQ48
DQ49
DQM0
Pin Description
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0
Function
Pin Name
Function
Address input (Multiplexed)
Select bank
DQM0 ~ 7
VDD
DQM
Power supply (3.3V)
Ground
Data input/output
Check bit (Data-in/data-out)
Clock input
VSS
*VREF
REGE
SDA
Power supply for reference
Register enable
Serial data I/O
Serial clock
CKE0
Clock enable input
Chip select input
CS0, CS2
RAS
SCL
Row address strobe
Colume address strobe
Write enable
SA0 ~ 2
DU
Address in EEPROM
Don′t use
CAS
WE
NC
No connection
1. * These pins are not used in this module.
2. ** These pins should be NC in the system which does not support SPD.
3. *** About these pins, Refer the Block Diagram.
3. pins 114, 129 are used only for M390S3323ET1.
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9, CA11
A0 ~ A11
BA0 ~ BA1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data input/output mask
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
REGE
Register enable
DQ0 ~ 63
CB0 ~ 7
VDD/VSS
Data input/output
Check bit
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
Power supply/ground
Power and ground for the input buffers and the core logic.
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
128MB, 16Mx72 ECC Module (M390S1723ETU(1)) (Populated as 1 bank of x8 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
BCKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
D0
D1
D2
D3
•
•
•
•
•
•
•
B0A0~B0A11,BBA0~1,BRAS,BCAS,BWE
BDQM0
DQ0~7
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
PCLK1
•
DQ8~15
CB0~7
10Ω
PCLK2
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM1
•
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
PCLK3
BCS2
•
•
•
BDQM2
DQ16~23
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
PCLK4
D4
D5
•
•
BDQM3
DQ24~31
DQ32~39
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
BDQM4
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
D7
D8
•
•
BDQM5
DQ40~47
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
•
BDQM6
DQ48~55
DQ56~63
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM7
10Ω
VSS
VDD
B0A0~B0A6
10Ω
1Y0
A0~A6
74ALVCF162835
PCLK4
PCLK5
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
CLK1,2,3
CLK0
BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0
RAS,CAS,WE
DQM0,1,4,5
CS0
12pF
CDCF2509
PCLK0
PCLK1
PCLK2
PCLK3
10Ω
LE
REGE
CLK
FIBIN
FBOUT
OE
PCLK2
12pF
10kΩ
*1
Cb
Note
1. The actual values of Cb will depend upon the PLL chosen.
VDD
74ALVCF162835
A7~A11
CS2
B0A7~B0A12,BBA0~BBA1
BCS2
Serial PD
SCL
CKE0
DQM2,3,6,7
BCKE0
BDQM2,3,6,7
WP
SDA
A0 A1 A2
47KΩ
LE
OE
SA0 SA1 SA2
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
256MB, 32Mx72 ECC Module (M390S3320ETU(1)) (Populated as 1 bank of x4 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
B0CKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D0
D1
D2
D3
D9
D10
D11
D12
D13
D14
D15
D16
D17
B1CKE0
BDQM4
B0A0~B0A10,BBA0,BBA1,BRAS,BCAS,BWE
BDQM0
DQ0~3
DQ32~35
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
DQ4~7
DQ8~11
DQ12~15
DQ36~39
DQ40~43
10Ω
PCLK1
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM1
BDQM5
10Ω
PCLK2
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
10Ω
DQ44~47
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D4
10Ω
CB4~7
CB0~3
10Ω
PCLK3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
D5
D6
D7
D8
BCS2
DQ48~51
DQ52~55
DQ16~19
DQ20~23
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
PCLK4
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM6
BDQM2
10Ω
10Ω
10Ω
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
DQ56~59
DQ60~63
DQ24~27
DQ28~31
10Ω
PCLK5
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
CLK
CS
CKE
Add,CTL
DQM
DQ0~3
BDQM7
BDQM3
10Ω
10Ω
VSS
VDD
B0A3~B0A10,B0BA0
A3,~A10,BA0
IY0
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
10Ω
74ALVCF162835
IY1
IY2
IY3
IY4
2Y0
2Y1
CLK1,2,3
CLK0
VDD
12pF
CDCF2510
10kΩ
PCLK6
REGE
10Ω
12pF
OE
OE
OE
LE
74ALVC162835
CLK
FIBIN
FBOUT
A11,BA1
CS2
CKE0
B0A11.B0BA1
BCS2
B0CKE0
B1CKE0
BDQM2,3,6,7
*1
Cb
DQM2,3,6,7
Note
1. The actual values of Cb will depend upon the PLL chosen.
LE
74ALVC162835
A0,A1,A2
RAS,CAS,WE,CS0
DQM0,1,4,5
B0A0,B0A1,B0A2
Serial PD
SCL
BRAS, BCAS, BWE,BCS0
BDQM0,1,4,5
SDA
WP
A0 A1 A2
47K
Ω
LE
SA0 SA1 SA2
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
256MB, 32Mx72 ECC Module (M390S3323ET1) (Populated as 2 bank of x8 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
BCS1
BCS0
•
•
•
BDQM4
•
BDQM0
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U5
CS
CS
U0
CS
U9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U14
•
•
BDQM1
BDQM5
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U6
CS
CS
U1
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ1
0
U15
U10
DQ11
DQ1
2
DQ1
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U2
CS
BDQM6
•
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U7
CS
U11
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
U16
BCS3
•
•
BDQM7
•
BCS2
•
BDQM2
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U8
CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U3
CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U17
U12
•
BDQM3
BnA0 ~ BnAn, BnBA0 & 1
SDRAM U0 ~ U17
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U4
CS
SDRAM U0,U1,U5,U6,U9,U10,U11,U14,U15
SDRAM U2,U3,U4,U7,U8,U12,U13,U16,U17
SDRAM U0,U1,U2,U3,U4,U5,U6,U7,U8
B0RAS, B0CAS, B0WE
B1RAS, B1CAS, B1WE
BCKE0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U13
BCKE1
SDRAM U9,U10,U11,U12,U13,U14,U15,U16,U17
BCKE0
3.3pF
BCKE1
SDRAM U11
SDRAM U2
3.3pF
VSS
V
DD
B0A0~B0A11,B0BA0,B0BA1
A0~A11,BA0,BA1
IDT74ALVCF162835A
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
NC
IY0
IY1
IY2
IY3
IY4
1Y5
1Y6
1Y7
1Y8
1Y9
RAS,CAS
B0RAS, B0CAS
VDD
10kΩ
CDCF2510
REGE
PCLK5
LE
OE
10Ω
5pF
NC
NC
CLK
FIBIN
CLK0
B1A0~B1A11,B1BA0,B1BA1
B1RAS, B1CAS
FBOUT
IDT74ALVCF162835A
Cb*2
* Note
1. Unused clock termination : 10
2. The actual values of Cb will depend upon the PLL cho-
DQM2,3,6,7
Ω
and 5pF
LE
OE
VDD
10kΩ
BCKE1
CKE1
WE
IDT74ALVCF162835A
Serial PD
SCL
B0WE
B1WE
BDQM0~BDQM7
BCS0~BCS3
BCKE0
SDA
WP
DQM0~DQM7
CS0~CS3
CKE0
A0 A1 A2
47KΩ
LE
OE
SA0 SA1 SA2
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2
REG
*1
DOUT
Control Signal(RAS,CAS,WE)
*3
*1. Register Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
RAS
CAS
WE
*2. Register Output
RAS
td
tr
td
tr
CAS
WE
*3. SDRAM
CAS latency(refer to *1)
=2CLK+1CLK
1CLK
tSAC
tRAC(refer to *1)
tRAC(refer to *2)
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
DQ
CAS latency(refer to *2)
=2CLK
tRDL
Row Active
Precharge
Command
Write
Command
Row Active
Read
Command
Precharge
Command
td, tr = Delay of register
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register. Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don′t care
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
Unit
V
-1.0 ~ 4.6
V
-55 ~ +150
1.0 * # of component
50
°C
W
Power dissipation
PD
Short circuit current
IOS
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input high voltage
Input low voltage
3.0
VDDQ+0.3
V
1
VIL
0
-
0.8
-
V
2
Output high voltage
Output low voltage
Input leakage current
VOH
VOL
ILI
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
M390S1723ETU(1) M390S3320ETU(1)
M390S3323ET1
Unit
Sym-
bol
Parameter
Min
Max
Min
Max
Min
Max
Input capacitance (A0 ~ A11)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
-
-
-
-
-
-
-
-
15
15
15
23
15
15
15
16
-
-
-
-
-
-
-
-
15
15
15
20
15
15
15
16
-
-
-
-
-
-
-
-
19
19
33
12
12
12
12
19
pF
pF
pF
pF
pF
pF
pF
pF
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0)
Input capacitance (CLK0)
Input capacitance (CS0, CS2)
Input capacitance (DQM0 ~ DQM7)
Input capacitance (BA0 ~ BA1)
Data input/output capacitance (DQ0 ~ DQ63)
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
DC CHARACTERISTICS
M390S1723ETU(1) (16M x 72, 128MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
-7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
Operating current
(One bank active)
ICC1
1310
mA
mA
1
3
ICC2P
ICC2PS
370
20
Precharge standby current
in power-down mode
ICC2N
530
95
Precharge standby current
in non power-down mode
mA
3
ICC2NS
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
400
50
Active standby current in
power-down mode
mA
mA
mA
3
3
3
ICC3N
620
230
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
ICC4
1500
mA
1
tCCD = 2CLKs
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
2300
370
mA
mA
2
3
M390S3320ETU(1) (32M x 72, 256MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
-7A
Parameter
Symbol
Test Condition
Unit
mA
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
2120
1
3
ICC2P
ICC2PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
390
40
Precharge standby current
in power-down mode
mA
ICC2N
710
190
Precharge standby current
in non power-down mode
mA
3
ICC2NS
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
440
100
Active standby current in
power-down mode
mA
mA
mA
3
3
3
ICC3N
890
460
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
ICC4
2480
mA
1
tCCD = 2CLKs
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
4100
390
mA
mA
2
3
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
DC CHARACTERISTICS
M390S3323ET1 (32M x 72, 256MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
-7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
Operating current
(One bank active)
ICC1
1580
mA
mA
1
3
ICC2P
ICC2PS
390
40
Precharge standby current
in power-down mode
ICC2N
710
190
Precharge standby current
in non power-down mode
mA
3
ICC2NS
ICC3P
ICC3PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
440
100
Active standby current in
power-down mode
mA
mA
mA
3
3
3
ICC3N
890
460
Active standby current in
non power-down mode
(One bank active)
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
ICC4
1760
mA
1
tCCD = 2CLKs
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
2570
390
mA
mA
2
3
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
- 7A
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
15
ns
ns
1
1
1
1
20
Row precharge time
20
ns
tRAS(min)
tRAS(max)
tRC(min)
45
ns
Row active time
100
us
Row cycle time
65
ns
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + tRP
1
1
1
2
1
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
- 7A
Parameter
Symbol
Unit
ns
Note
1
Min
7.5
10
Max
CAS latency=3
CLK cycle
time
tCC
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5.4
6
CLK to valid
output delay
tSAC
ns
1,2
2
3
Output data
hold time
tOH
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
A0 ~ A9,
A11
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
Mode register set
Register
Refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
Auto refresh
H
L
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
L
Read &
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
4
4,5
4
Column
L
L
H
H
L
L
H
L
column address
address
H
L
Write &
Column
address
H
X
X
V
column address
H
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 16Mx72 (M390S1723ET1)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
PLL
REG
REG
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
0.123 ± 0.005
0.008 ± 0.006
(3.125 ± 0.125)
(3.125 ± 0.125)
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S280832E
This module is based on JEDEC PC133 Specification
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 16Mx72 (M390S1723ETU)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
R 0.079
(1.372)
5.014
0.118
(3.000)
(R 2.000)
(127.350)
0.157 ± 0.004
(4.000 ± 0.100)
PLL
REG
REG
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
0.123 ± 0.005
0.008 ± 0.006
(3.125 ± 0.125)
(3.125 ± 0.125)
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S280832E
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 32Mx72 (M390S3320ET1)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
REG
REG
PLL
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 32Mx4 SDRAM, TSOPII
SDRAM Part No. : K4S280432E
This module is based on JEDEC PC133 Specification
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 32Mx72 (M390S3320ETU)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
R 0.079
5.014
0.118
(R 2.000)
(127.350)
(3.000)
0.157 ± 0.004
PLL
(4.000 ± 0.100)
REG
REG
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ± 0.006
(0.200 ± 0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 32Mx4 SDRAM, TSOPII
SDRAM Part No. : K4S280432E
This module is based on JEDEC PC133 Specification
Rev. 1.1 May. 2003
128MB, 256MB Registered DIMM
SDRAM
PACKAGE DIMENSIONS : 32Mx72 (M390S3323ET1)
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
REG
REG
PLL
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ±0.006
(0.200 ±0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances :± 0.005(.13) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S280832E
This module is based on JEDEC PC133 Specification
Rev. 1.1 May. 2003
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