M392B5173FM0-YK0 [SAMSUNG]
DDR DRAM Module, 512MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240;
| 型号： | M392B5173FM0-YK0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 512MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240 动态存储器 双倍数据速率 |
| 文件： | 总46页 (文件大小：921K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR3L SDRAM
VLP Registered DIMM
DDR3L SDRAM Specification
240pin VLP Registered DIMM based on 1Gb F-die
72-bit ECC
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
Table Contents
1.0 DDR3L Registered DIMM Ordering Information ........................................................................5
2.0 Key Features .................................................................................................................................5
3.0 Address Configuration .................................................................................................................5
4.0 Registered DIMM Pin Configurations (Front side/Back side) ...................................................6
5.0 Pin Description .............................................................................................................................7
6.0 ON DIMM Thermal Sensor ............................................................................................................7
7.0 Input/Output Functional Description ..........................................................................................8
8.0 Pinout comparison Based on Module Type ...............................................................................9
9.0 Registering Clock Driver Specification ....................................................................................10
9.1 Timing & Capacitance values .......................................................................................................10
9.2 Clock driver Characteristics ........................................................................................................10
10.0 Functional Block Diagram: ......................................................................................................11
10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) .................................................11
10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................12
10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) .................................................13
10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ................................................14
10.5 4GB, 512Mx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) ................................................15
11.0 Absolute Maximum Ratings .....................................................................................................16
11.1 Absolute Maximum DC Ratings ..................................................................................................16
11.2 DRAM Component Operating Temperature Range ........................................................................16
12.0 AC & DC Operating Conditions ...............................................................................................16
12.1 Recommended DC Operating Conditions (SSTL) ..........................................................................16
13.0 AC & DC Input Measurement Levels .......................................................................................17
13.1 AC & DC Logic Input Levels for Single-ended Signals ...................................................................17
13.2 V
Tolerances .......................................................................................................................18
REF
13.3 AC and DC Logic Input Levels for Differential Signals ...................................................................19
13.3.1 Differential Signals Definition ..............................................................................................19
13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................19
13.3.3 Single-ended Requirements for Differential Signals ...............................................................20
13.3.4 Differential Input Cross Point Voltage ...................................................................................21
13.4 Slew Rate Definition for Single Ended Input Signals .....................................................................21
13.5 Slew Rate Definition for Differential Input Signals .........................................................................21
14.0 AC and DC Output Measurement Levels ................................................................................22
14.1 Single Ended AC and DC Output Levels ......................................................................................22
14.2 Differential AC and DC Output Levels ..........................................................................................22
14.3 Single Ended Output Slew Rate ..................................................................................................22
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VLP Registered DIMM
14.4 Differential Output Slew Rate .....................................................................................................23
15.0 IDD specification definition .....................................................................................................24
15.1 IDD SPEC Table ........................................................................................................................26
16.0 Input/Output Capacitance ........................................................................................................29
17.0 Electrical Characteristics and AC timing ...............................................................................30
17.1 Refresh Parameters by Device Density ........................................................................................30
17.2 Speed Bins and CL, tRCD, tRC and tRAS for Corresponding Bin ....................................................30
17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ..............................................31
17.3.1 Speed Bin Table Notes .......................................................................................................34
18.0 Timing Parameters for DDR3-800, DDR3-1066, DDR3-1333 and DDR3-1600 ......................35
18.1 Jitter Notes ..............................................................................................................................38
18.2 Timing Parameter Notes ............................................................................................................39
19.0 Physical Dimensions : ..............................................................................................................40
19.1 128Mbx8 based 128Mx72 Module(1 Rank) ....................................................................................40
19.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs .............................................40
19.2 128Mbx8 based 256Mx72 Module(2 Ranks) .................................................................................41
19.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs ............................................41
19.3 256Mbx4 based 256Mx72 Module(1 Rank) ....................................................................................42
19.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs .............................................42
19.4 256Mbx4(DDP) based 512Mx72 Module(2 Ranks) ..........................................................................43
19.4.1 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs ..................................................43
19.5 512Mbx8(DDP) based 512Mx72 Module(4 Ranks) ..........................................................................44
19.5.1 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs .................................................44
19.5.2 Heat Spreader Design Guide ...............................................................................................45
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Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
Revision History
Revision
Month
Year
History
0.9
September
2009
- Initial Release
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Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
1.0 DDR3L Registered DIMM Ordering Information
Number of
Height
Part Number
Density
Organization
Component Composition
Rank
M392B2873FH0-YF8/H9/K0
M392B5673FH0-YF8/H9/K0
M392B5670FH0-YF8/H9/K0
M392B5170FM0-YF8/H9/K0
M392B5173FM0-YF8/H9/K0
1GB
2GB
2GB
4GB
4GB
128Mx72
256Mx72
256Mx72
512Mx72
512Mx72
128Mx8(K4B1G0846F-HY##)*9
128Mx8(K4B1G0846F-HY##)*18
256Mx4(K4B1G0446F-HY##)*18
512Mx4(K4B2G0446F-MY##)*18
256Mx8(K4B2G0846F-MY##)*18
1
2
1
2
4
30mm
30mm
30mm
30mm
30mm
* Note
- "##" - F8/H9/K0
- F7 - F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9 & K0 - 1600Mbps 11-11-11
2.0 Key Features
DDR3-1066
7-7-7
DDR3-1333
DDR3-1600
11-11-11
1.25
Speed
Unit
9-9-9
1.5
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
1.875
7
ns
tCK
ns
9
11
13.125
13.125
37.5
13.5
13.5
36
13.75
13.75
35
ns
tRAS(min)
tRC(min)
ns
50.625
49.5
48.75
ns
•
•
•
•
•
•
•
•
•
JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V) Power Supply
VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 6,7,8,9,10, 11
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
•
•
•
•
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
•
Asynchronous Reset
3.0 Address Configuration
Organization
Row Address
A0-A13
Column Address
A0-A9, A11
A0-A9
Bank Address
BA0-BA2
Auto Precharge
A10/AP
256Mx4(1Gb) based Module
128Mx8(1Gb) based Module
512Mx4(2Gb DDP) based Module
256Mx8(2Gb DDP) based Module
A0-A13
BA0-BA2
A10/AP
A0-A13
A0-A9, A11
A0-A9
BA0-BA2
A10/AP
A0-A13
BA0-BA2
A10/AP
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Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
4.0 Registered DIMM Pin Configurations (Front side/Back side)
Pin
1
Front
Pin
121
Back
Pin
42
Front
DQS8
Pin
162
Back
Pin
82
Front
Pin
Back
V
NC,DQS17
,TDQS17
V
V
DQ33
202
REFDQ
SS
SS
DM4,DQS13
,TDQS13
V
V
V
2
3
4
5
122
123
124
125
DQ4
DQ5
43
44
45
46
47
48
DQS8
163
164
165
166
167
168
83
84
85
86
203
204
205
206
SS
SS
SS
NC,DQS13
V
DQ0
DQ1
CB6,NC
CB7,NC
DQS4
DQS4
SS
,TDQS13
V
V
CB2,NC
CB3,NC
SS
SS
DM0,DQS9
,TDQS9
V
V
V
DQ38
DQ39
SS
SS
SS
NC,DQS9
V
6
7
DQS0
DQS0
126
127
128
129
130
131
NC(TEST)
RESET
87
88
89
90
91
92
DQ34
DQ35
207
208
209
210
211
212
SS
,TDQS9
V
V
V
, NC
V
SS
TT
SS
V
V
8
DQ6
DQ7
KEY
DQ44
DQ45
SS
SS
, NC
9
DQ2
DQ3
49
50
51
169
170
171
CKE1, NC
DQ40
DQ41
TT
V
V
V
10
11
CKE0
SS
DD
SS
DM5,DQS14
,TDQS14
V
V
V
DQ12
DQ13
A15
A14
SS
DD
SS
NC,DQS14
12
13
14
DQ8
DQ9
132
133
134
52
53
54
BA2
172
173
174
93
94
95
DQS5
DQS5
213
214
215
,TDQS14
V
V
V
Err_Out/NC
SS
DD
SS
DM1,DQS10
,TDQS10
V
V
V
A12/BC
A9
DQ46
DQ47
SS
DD
SS
NC,DQS10
15
16
17
18
19
20
DQS1
DQS1
135
136
137
138
139
140
55
56
57
58
59
60
A11
A7
175
176
177
178
179
180
96
97
DQ42
DQ43
216
217
218
219
220
221
,TDQS10
V
V
V
SS
DD
SS
V
V
V
DQ14
DQ15
A8
A6
98
DQ52
DQ53
SS
DD
SS
DQ10
DQ11
A5
A4
99
DQ48
DQ49
V
V
V
100
101
SS
DD
SS
DM6,DQS15
,TDQS15
V
V
V
DQ20
DQ21
A3
A1
SS
DD
SS
NC,DQS15
21
22
23
DQ16
DQ17
141
142
143
61
62
63
A2
181
182
183
102
103
104
DQS6
DQS6
222
223
224
,TDQS15
V
V
V
V
SS
DD
DD
SS
DM2,DQS11
,TDQS11
V
V
V
NC, CK1
NC, CK1
DQ54
DQ55
SS
DD
SS
NC,DQS11
24
25
26
27
28
29
30
31
32
DQS2
DQS2
144
145
146
147
148
149
150
151
152
64
65
66
67
68
69
70
71
72
184
185
186
187
188
189
190
191
192
CK0
CK0
105
106
107
108
109
110
111
DQ50
DQ51
225
226
227
228
229
230
231
232
233
,TDQS11
V
V
V
SS
DD
SS
V
V
V
V
DQ22
DQ23
DQ60
DQ61
SS
DD
DD
SS
V
DQ18
DQ19
EVENT,NC
A0
DQ56
DQ57
REFCA
V
V
NC/Par_In
SS
SS
DM7/DQS16
TDQS16
V
V
V
V
DQ28
DQ29
SS
DD
DD
SS
DM7,DQS16
DQ24
DQ25
A10/AP
BA0
BA1
DQS7
DQS7
,TDQS16
V
V
V
112
113
SS
DD
SS
DM3,DQS12
,TDQS12
V
V
V
RAS
S0
DQ62
DQ63
SS
DD
SS
NC,DQS12
33
34
35
36
37
38
39
40
41
DQS3
DQS3
153
154
155
156
157
158
159
160
161
73
74
75
76
77
78
79
80
81
WE
193
194
195
196
197
198
199
200
201
114
115
116
117
118
119
120
DQ58
DQ59
234
235
236
237
238
239
240
,TDQS12
V
V
V
CAS
SS
DD
SS
V
V
V
V
DQ30
DQ31
ODT0
A13
SS
DD
SS
DDSPD
DQ26
DQ27
S1,NC
SA0
SCL
SA2
SA1
SDA
V
V
ODT1,NC
SS
DD
V
V
V
CB4,NC
CB5,NC
S3,NC
SS
DD
SS
V
V
V
CB0,NC
CB1,NC
S2,NC
SS
TT
TT
V
V
DQ36
DQ37
SS
SS
DM8,DQS17
TDQS17,NC
V
DQ32
SS
NC = No Connect
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
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Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
5.0 Pin Description
Pin Name
CK0
Description
Number
Pin Name
ODT[1:0]
DQ[63:0]
CB[7:0]
Description
On Die Termination Inputs
Number
Clock Input, positive line
1
1
2
1
1
2
64
8
CK0
Clock Input, negative line
Clock Enables
Data Input/Output
CKE[1:0]
RAS
Data check bits Input/Output
Data strobes
Row Address Strobe
Column Address Strobe
DQS[8:0]
DQS[8:0]
9
CAS
Data strobes, negative line
9
DM[8:0]/
DQS[17:9]
TDQS[17:9]
Data Masks/ Data strobes,
Termination data strobes
WE
Write Enable
1
9
DQS[17:9] Data strobes, negative line, Termination data
TDQS[17:9] strobes
S[3:0]
Chip Selects
4
2\14
1
9
2
1
1
A[9:0],A11,
A[15:13]
Address Inputs
RFU
EVENT
TEST
Reserved for Future Use
Reserved for optional hardware temperature
sensing
A10/AP
A12/BC
Address Input/Autoprecharge
Address Input/Burst chop
Memory bus test toll (Not Connected and Not
Usable on DIMMs)
1
BA[2:0]
SCL
SDRAM Bank Addresses
3
1
1
3
1
RESET
VDD
Register and SDRAM control pin
Power Supply
1
22
59
1
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
VSS
SDA
Ground
VREFDQ
VREFCA
SA[2:0]
Par_In
SPD Address Inputs
Reference Voltage for DQ
Reference Voltage for CA
Parity bit for the Address and Control bus
1
Parity error found on the Address and Control
bus
VTT
Err_Out
1
Termination Voltage
4
VDDSPD
SPD Power
Total
1
240
*The VDD and VDDQ pins are tied common to a single power-plane on these designs.
6.0 ON DIMM Thermal Sensor
SCL
SDA
EVENT
WP/EVENT
R1
0 Ω
SA0
SA1
SA1
SA2
SA2
R2
0 Ω
SA0
Temperature Sensor Characteristics
Grade
Temperature Sensor Accuracy
Range
Units
Notes
Min.
Typ.
+/- 0.5
+/- 1.0
+/- 2.0
0.25
Max.
75 < Ta < 95
40 < Ta < 125
-20 < Ta < 125
-
-
-
+/- 1.0
+/- 2.0
+/- 3.0
-
-
-
-
B
°C
Resolution
°C /LSB
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Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
7.0 Input/Output Functional Description
Symbol
Type
Polarity
Function
Positive
Edge
CK0
Input
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.
Negative
Edge
CK0
Input
Input
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers
CKE[1:0]
Active High and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when high.
When decoder is disabled, new commands are ignored and previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both
S[3:0]
Input
Active Low
inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in
the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg-
ister outputs.
ODT[1:0]
Input
Input
Active High On-Die Termination control signals
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be exe-
RAS, CAS, WE
Active Low
cuted by the SDRAM.
VREFDQ
VREFCA
Supply
Supply
Reference voltage for DQ0-DQ63 and CB0-CB7
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank
address also determines mode register is to be accessed during an MRS cycle.
BA[2:0]
Input
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/
Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur-
ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8
identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during
Mode Register Set commands.
A[15:13,
12/BC,11,
10/AP,9:0]
Input
I/O
DQ[63:0],
CB[7:0]
Data and Check Bit Input/Output pins
Active High Masks write data when high, issued concurrently with input data.
V
DD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.
DM[8:0]
VTT Supply Termination Voltage for Address/Command/Control/Clock nets.
DQS[17:0]
DQS[17:0]
I/O
I/O
Positive Edge Positive line of the differential data strobe for input and output data.
Negative Edge Negative line of the differential data strobe for input and output data.
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will
enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When dis-
abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.
X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1
TDQS[17:9],
TDQS[17:9]
OUT
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM
address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up.
SA[2:0]
SDA
IN
I/O
IN
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from the SCL bus time to VDDSPD on the system planar to act as a pull-up.
SCL
OUT
(open
drain)
This signal indicates that a thermal event has been detected in the thermal sensing device.The system
should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.
EVENT
VDDSPD
Active Low
Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from
3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
Supply
The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When
low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set
to low level (the Clock Driver will remain synchronized with the input clock)
RESET
Par_In
Err_Out
TEST
IN
IN
OUT
(open
drain)
Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)
Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out
bus line to VDD on the system planar to act as a pull up.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
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Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
8.0 Pinout comparison Based on Module Type
RDIMM
UDIMM
Pin
Signal
Notes
Signal
Notes
Additional connection for Termination Voltage for
VTT
48, 49
120, 240
53
NC
Not used on UDIMMs
Address/Command/Control/Clock nets.
Termination Voltage for Address/Command/Con-
trol/Clock nets.
Termination Voltage for Address/Command/Con-
trol/Clock nets.
VTT
VTT
NC
Connected to the register on all RDIMMs NC Not
used on UDIMMs
Err_Out
NC Not used on UDIMMs
63
64
68
NC
NC
CK1
CK1
NC
Used for 2 rank UDIMMs, not used on single-
rank UDIMMs, but terminated
Not used on RDIMMs
Par_In
Connected to the register on all RDIMMs
Connected to the register on all RDIMMs
Not used on RDIMMs
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
76
77
S1
S1
Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
ODT1, NC
ODT1,NC
Connected to the register on quad-rank
RDIMMs, not connected on single or dual rank
RDIMMs
79
S2, NC
NC
NC
Not used on UDIMMs
TEST input used only on bus analysis
probes
167
169
NC
TEST input used only on bus analysis probes
Connected to the register on dual- and quadrank
RDIMMs; NC on single-rank RDIMMs
CKE1,
NC
Used for dual-rank UDIMMs, not connected
on single-rank UDIMMs
CKE1
171
172
196
A15
A14
A13
A15, NC
A14
Depending on device density, may not be
connected to SDRAMs on UDIMMs. However,
these signals are terminated on
Connected to the register on all RDIMMs
A13
UDIMMs. A15 not routed on some RCs
Connected to the register on quad-rank
RDIMMs, not connected on single-or dual-rank
RDIMMs
198
S3, NC
CBn
NC
NC, CBn
DMn
Not used on UDIMMs
39, 40, 45, 46,
158, 159, 164,
165
Used on x72 UDIMMs, (n = 0...7); not
used on x64 UDIMMs
Used on all RDIMMs; (n = 0...7)
125, 134, 143,
152, 161, 203,
212, 221, 230
Connected to DM on x8 DRAMs, UDM or
LDM on x16 DRAMs on UDIMMs;
(n = 0...8)
DQSn,
TDQSn
Connected to DQS on x4 SDRAMs,
TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)
126, 135, 144,
153, 162, 204,
213, 222, 231
DQSn,
TDQSn
Connected to DQS on x4 DRAMs, TDQS on x8
SDRAMs on RDIMMs; (n=9...17)
NC
Not used on UDIMMs
Connected to optional thermal sensing compo-
EVENT
NC
nent.
187
NC
Not used on UDIMMs
NC on Modules without a thermal sensing
component.
Note : NC = no internal connection
9 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
9.0 Registering Clock Driver Specification
9.1 Timing & Capacitance values
TC = TBD
VDD = 1.35V(1.28V~1.45V)
& 1.5V(1.425~1.575V)
Symbol
Parameter
Conditions
Units Notes
Min
300
0.4
Max
670
-
fclock
Input Clock Frequency
application frequency
MHz
tCK
tCH/tCL
Pulse duration, CK, CK HIGH or LOW
Inputs active time4 before RESET is taken HIGH
Setup time
DCKE0/1 = LOW and
DCS0/1 = HIGH
tACT
tSU
tCK
ps
8
-
-
-
Input valid before CK/CK
100
175
Input to remain Valid after
CK/CK
tH
Hold time
tPDM
Propagation delay, single-bit switching
output disable time(1/2-Clock pre-launch)
output disable time(3/4-Clock pre-launch)
output enable time(1/2-Clock pre-launch)
output enable time(3/4-Clock pre-launch)
Data Input Capacitance
CK/CK to output
0.65
0.5
0.25
-
1.0
-
ns
tDIS
tCK
CK/CK to output float
-
0.5
0.25
2.5
tEN
tCK
pF
CK/CK to output driving
-
CIN(DATA)
1.5
C
IN(CLOCK)
IN(RST)
Data Input Capacitance
Reset Input Capacitance
2
-
3
3
C
9.2 Clock driver Characteristics
TC = TBD
VDD = 1.35V(1.28V~1.45V)
& 1.5V(1.425~1.575V)
Symbol
Parameter
Conditions
Units Notes
Min
0
Max
40
6
tjit (cc)
tSTAB
Cycle-to-cycle period jitter
Stabilization time
ps
us
ps
ps
ps
ps
-
tfdyn
Dynamic phase offset
Clock Output skew
Yn Clock Period jitter
Half period jitter
-50
50
50
40
tCKsk
tjit(per)
tjit(hper)
-40
-50
-100
-100
-100
-100
-80
50
200
300
200
300
80
Output Inversion enabled
OUtput Inversion disabled
Output Inversion enabled
OUtput Inversion disabled
Qn Output to clock tolerance (Standard 1/2 -Clock
Pre-Launch)
tQsk1
ps
tQsk1
Output clock tolerance (3/4 Clock Pre-Launch)
Maximum re-driven dynamic clock off-set
ps
ps
tdynoff
10 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
10.0 Functional Block Diagram:
10.1 1GB, 128Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
DQS8
DQS8
DQS4
DQS4
DQS
DQS
DQS
DQS
DM8/DQS17
DQS17
DM4/DQS13
DQS13
TDQS
TDQS
DQ[7:0]
TDQS
TDQS
DQ[7:0]
D8
D3
D2
D1
D0
D4
D5
D6
D7
CB[7:0]
DQ[39:32]
Thermal sensor with SPD
DQS3
DQS3
DQS5
DQS5
DQS
DQS
SCL
EVENT
DQS
DQS
SDA
DM3/DQS12
DQS12
DM5/DQS14
DQS14
TDQS
TDQS
DQ[7:0]
TDQS
TDQS
DQ[7:0]
EVENT
A0 A1 A2
DQ[31:24]
DQ[47:40]
SA0 SA1 SA2
DQS2
DQS2
DQS6
DQS6
DQS
DQS
DQS
DQS
DM2/DQS11
DQS11
DM6/DQS15
DQS15
TDQS
TDQS
DQ[7:0]
TDQS
TDQS
DQ[7:0]
DQ[23:16]
DQ[55:48]
V
V
V
Serial PD
D0 - D8
DDSPD
DD
DQS1
DQS1
DQS7
DQS7
DQS
DQS
TT
DQS
DQS
DM1/DQS10
DQS10
DM7/DQS16
DQS16
TDQS
TDQS
DQ[7:0]
TDQS
TDQS
DQ[7:0]
V
V
V
D0 - D8
D0 - D8
D0 - D8
REFCA
REFDQ
SS
DQ[15:8]
DQ[63:56]
Vtt
DQS0
DQS0
DQS
DQS
DM0/DQS9
DQS9
TDQS
TDQS
DQ[7:0]
Note :
DQ[7:0]
1. DQ-to-I/O wiring may be changed within a byte.
2. ZQ resistors are 240 1% For all other resistor values refer to the appro-
priate wiring diagram.
Vtt
S0*
RS0A-> CS0 : SDRAMs D[3:0], D8
RS0B-> CS0 : SDRAMs D[7:4]
S1*
BA[N:0]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D8
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4]
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D8
RA[N:0]B -> A[N:0] : SDRAMs D[7:4]
RRASA -> RAS : SDRAMs D[3:0], D8
RRASB -> RAS : SDRAMs D[7:4]
RCASA -> CAS : SDRAMs D[3:0], D8
RCASB -> CAS : SDRAMs D[7:4]
RWEA -> WE : SDRAMs D[3:0], D8
RWEB -> WE : SDRAMs D[7:4]
A[N:0]
RAS
1:2
R
E
G
I
CAS
WE
S
T
CKE0
ODT0
E
R
RCKE0A -> CKE0 : SDRAMs D[3:0], D8
RCKE0B -> CKE0 : SDRAMs D[7:4]
RODT0A -> ODT0 : SDRAMs D[3:0], D8
RODT0B -> ODT0 : SDRAMs D[7:4]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0A -> CK : SDRAMs D[7:4]
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0A -> CK : SDRAMs D[7:4]
Err_out
CK0
CK0
QERR
RST
PAR_IN
RESET**
PST** : SDRAMs D[8:0]
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
(Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground)
11 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
10.2 2GB, 256Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
DQS8
DQS8
DQS4
DQS4
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DM8/DQS17
DQS17
DM4/DQS13
DQS13
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
D8
D3
D2
D1
D0
D17
D12
D11
D10
D9
D4
D5
D6
D7
D13
CB[7:0]
DQ[39:32]
DQS3
DQS3
DQS5
DQS5
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DM3/DQS12
DQS12
DM5/DQS14
DQS14
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
D14
D15
D16
DQ[31:24]
DQ[47:40]
DQS2
DQS2
DQS6
DQS6
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DM2/DQS11
DQS11
DM6/DQS15
DQS15
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
DQ[23:16]
DQ[55:48]
DQS1
DQS1
DQS7
DQS7
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DM1/DQS10
DQS10
DM7/DQS16
DQS16
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
DQ[15:8]
DQ[63:56]
Vtt
DQS0
DQS0
DQS
DQS
DQS
DQS
DM0/DQS9
DQS9
TDQS
TDQS
DQ[7:0]
ZQ
TDQS
TDQS
DQ[7:0]
ZQ
DQ[7:0]
S0*
RS0A-> CS0 : SDRAMs D[3:0], D8
RS0B-> CS0 : SDRAMs D[7:4]
S1*
RS1A-> CS1 : SDRAMs D[12:9], D17
RS1B-> CS1 : SDRAMs D[16:13]
BA[N:0]
A[N:0]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17
RA[N:0]B -> A[N:0] : SDRAMs D[7:4, D[16:13]]
Vtt
RAS
RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17
RRASB -> RAS : SDRAMs D[7:4], D[16:13]
RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17
RCASB -> CAS : SDRAMs D[7:4], D[16:13]
RWEA -> WE : SDRAMs D[3:0], D[12:8], D17
RWEB -> WE : SDRAMs D[7:4], D[16:13]
RCKE0A -> CKE0 : SDRAMs D[3:0], D8
RCKE0B -> CKE0 : SDRAMs D[7:4]
RCKE1A -> CKE1 : SDRAMs D[12:9], D17
RCKE1B -> CKE1 : SDRAMs D[16:13]
RODT0A -> ODT0 : SDRAMs D[3:0], D8
RODT0B -> ODT0 : SDRAMs D[7:4]
RODT1A -> ODT1 : SDRAMs D[12:9], D17
RODT1A -> ODT1 : SDRAMs D[16:13]
V
V
V
Thermal sensor with SPD
CAS
Serial PD
D0 - D17
DDSPD
DD
SCL
EVENT
1:2
R
E
G
I
WE
SDA
EVENT
A0 A1 A2
CKE0
CKE1
ODT0
ODT1
TT
S
T
SA0 SA1 SA2
V
V
V
D0 - D17
D0 - D17
D0 - D17
REFCA
REFDQ
SS
E
R
CK0
CK0
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0B -> CK : SDRAMs D[7:4]
Note :
PCK1A -> CK : SDRAMs D[12:9], D17
PCK1B -> CK : SDRAMs D[16:13]
1. DQ-to-I/O wiring may be changed within a byte.
2. Unless otherwise noted, resistor values are 15Ω ± 5%.
3. RS0 and RS1 alternate between the back and front sides of the
DIMM.
PCK0A -> CK : SDRAMs D[3:0], D8
PCK0B -> CK : SDRAMs D[7:4]
PCK1A -> CK : SDRAMs D[12:9], D17
PCK1B -> CK : SDRAMs D[16:13]
QERR
RST
PAR_IN
Err_out
4. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the
RESET**
appropriate wiring diagram.
PST** : SDRAMs D[8:0]
5. See the wiring diagrams for all resistors associated with the command,
address and control bus.
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
12 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
10.3 2GB, 256Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
DQS8
DQS8
VSS
DQS17
DQS17
VSS
DQS8
DQS8
DQS17
DQS17
VSS
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
VSS
D8
D3
D2
D1
D0
D17
D12
D11
D10
D9
D4
D5
D6
D7
D13
D14
D15
D16
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
CB[3:0]
CB[7:4]
DQ[35:32]
DQ[39:36]
DQS3
DQS3
DQS17
DQS17
VSS
DQS8
DQS8
DQS17
DQS17
VSS
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
VSS
VSS
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[27:24]
DQ[31:28]
DQ[43:40]
DQ[47:44]
DQS8
DQS8
DQS17
DQS17
VSS
DQS8
DQS8
DQS17
DQS17
VSS
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
VSS
VSS
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[19:16]
DQ[23:20]
DQ[51:48]
DQ[55:52]
DQS8
DQS8
DQS17
DQS17
VSS
DQS8
DQS8
DQS17
DQS17
VSS
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
VSS
VSS
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[11:8]
DQ[15:12]
DQ[59:56]
DQ[63:60]
Vtt
DQS8
DQS8
VSS
DQS17
DQS17
VSS
DQS
DQS
DM
DQS
DQS
DM
DQ[3:0]
DQ[3:0]
S0*
S1*
RS0A-> CS0 : SDRAMs D[3:0], D[12:8], D17
RS0B-> CS0 : SDRAMs D[7:4], D[16:13]]
DQ[3:0]
DQ[7:4]
BA[N:0]
A[N:0]
RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]
RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17
RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13]
RAS
CAS
WE
RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17
RRASB -> RAS : SDRAMs D[7:4], D[16:13]
RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17
RCASB -> CAS : SDRAMs D[7:4], D[16:13]
RWEA -> WE : SDRAMs D[3:0], D[12:8], D17
RWEB -> WE : SDRAMs D[7:4], D[16:13]
Vtt
1:2
R
E
G
I
Thermal sensor with SPD
VDDSPD
VDD
Serial PD
SCL
EVENT
D0 - D17
SDA
CKE0
ODT0
RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17
RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13]
EVENT
A0 A1 A2
VTT
S
T
RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17
RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13]
SA0 SA1 SA2
VREFCA
VREFDQ
VSS
D0 - D17
D0 - D17
D0 - D17
E
R
CK0
CK0
PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK : SDRAMs D[7:4], D[16:13]
PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17
PCK0B -> CK : SDRAMs D[7:4], D[16:13]
Note :
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15Ω ± 5%.
3. See the wiring diagrams for all resistors associated with the command,
address and control bus.
QERR
RST
PAR_IN
Err_out
RESET**
PST** : SDRAMs D[17:0]
4. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the
appropriate wiring diagram.
*S[3:2], CKE1, ODT1, CK1 and CK1 are NC
(Unused register inputs ODT1 and CKE1 have a 330
Ω resistor to ground)
13 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
10.4 4GB, 512Mx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)
VSS
RS0
RS1
DM CS ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM CS ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM CS ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM CS ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQS0
DQS0
DQS9
DQS9
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D0
D18
D9
D27
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[4:7]
DM CS ZQ
DM CS ZQ
D19
DM CS ZQ
D10
DM CS ZQ
D28
DQS1
DQS1
DQS10
DQS10
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D1
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[11:8]
DQ[12:15]
DM CS ZQ
DM CS ZQ
DM CS ZQ
DM CS ZQ
DQS2
DQS2
DQS11
DQS11
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D2
D20
D11
D29
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[16:19]
DQ[20:23]
DM CS ZQ
DM CS ZQ
D21
DM CS ZQ
D12
DM CS ZQ
D30
DQS3
DQS3
DQS12
DQS12
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D3
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[24:27]
DQ[28:31]
DM CS ZQ
DM CS ZQ
DM CS ZQ
DM CS ZQ
DQS4
DQS4
DQS13
DQS13
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D4
D22
D13
D31
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[32:35]
DQ[36:39]
DM CS ZQ
DM CS ZQ
D23
DM CS ZQ
D14
DM CS ZQ
D32
DQS5
DQS5
DQS14
DQS14
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D5
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[40:43]
DQ[44:47]
DM CS ZQ
DM CS ZQ
DM CS ZQ
DM CS ZQ
DQS6
DQS6
DQS15
DQS15
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D6
D24
D15
D33
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[48:51]
DQ[52:55]
DM CS ZQ
DM CS ZQ
D25
DM CS ZQ
D16
DM CS ZQ
D34
DQS7
DQS7
DQS16
DQS16
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D7
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[56:59]
DQ[60:63]
DM CS ZQ
DM CS ZQ
DM CS ZQ
DM CS ZQ
DQS8
DQS8
DQS17
DQS17
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
D8
D26
D17
D35
DQ[3:0]
DQ[3:0]
DQ[3:0]
DQ[3:0]
CB[3:0]
CB[7:4]
S0[1:0]
S0[3:2]
RS0A-> CS0A : SDRAMs D[9:0]
RS1A-> CS1A : SDRAMs D[27:18]
RS0B-> CS0B : SDRAMs D[17:10]
RS1B-> CS1B : SDRAMs D[35:28]
RBA[2:0]A -> BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RBA[2:0]B -> BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RA[15:0]A -> A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RA[15:0]B -> A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RRASA -> RAS: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA -> CAS: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RCASB -> CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RWEA -> WE: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RWEB -> WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCKE0A -> CKE0A: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RCKE0B -> CKE0B: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RODT[1:0]A -> ODT0: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RODT[1:0]B -> ODT0: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
CK0A_R0 -> CK: SDRAMs D[4:0], D[22:18]
CK0B_R0 -> CK: SDRAMs D[13:10], D[31:28]
CK0C_R1 -> CK: SDRAMs D[9:5], D[27:23]
CK0D_R1 -> CK: SDRAMs D[17:14], D[35:32]
Thermal sensor with SPD
BA[2:0]
SCL
EVENT_n
SDA
EVENT_n
A[15:0]
RAS
A0 A1 A2
SA0 SA1 SA2
CAS
Serial PD w/integrated Thermal Sensor
1:2
R
E
G
I
WE
CKE0
V
Serial PD
D0 - D17
DDSPD
ODT0
S
T
V
DD
E
R
V
TT
CK0
V
V
V
D0 - D17
D0 - D17
D0 - D17
REFCA
REFDQ
SS
CK0A_R0 -> CK: SDRAMs D[4:0], D[22:18]
CK0B_R0 -> CK: SDRAMs D[13:10], D[31:28]
CK0C_R1 -> CK: SDRAMs D[9:5], D[27:23]
CK0
CK0D_R1 -> CK: SDRAMs D[17:14], D[35:32]
PAR_IN
RESET
Err_out
QERR
RST
Note :
1. DQ-to-I/O wiring may be changed within a nibble.
RST : SDRAMs D[35:0]
2. ZQ resitors are 240Ω ± 1% . For all other resistor values refer to the appropriate wiring diagram.
3. The connection of the Serial PD to EVENT_n (Option 1) or to ground (Option 2) is realized by resistor options.
14 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
10.5 4GB, 512Mx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs)
DQS0
DQS0
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
U0
U1
U2
U3
U4
U9
U18
U19
U20
U21
U22
U27
U28
U29
U30
U31
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
S0
S1
S2
S3
RS0-> CS0 : SDRAMs D[8:0]
DQS1
DQS1
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
RS1-> CS1 : SDRAMs D[17:9]
RS2-> CS2 : SDRAMs D[26:18]
RS3-> CS3 : SDRAMs D[35:27]
WBA[N:0] -> BA[N:0]: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
EBA[N:0] -> BA[N:0]: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
U10
U11
U12
U13
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[15:8]
BA[N:0]
WA[N:0] -> A[N:0]: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
EA[N:0] -> A[N:0]: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
WRAS -> RAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
ERAS -> RAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
A[N:0]
RAS
DQS2
DQS2
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
WCAS -> CAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
ECAS -> CAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
CAS
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[23:16]
1:2
R
E
G
I
WWE -> WE: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]
EWE -> WE: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]
WCKE0 -> CKE0: SDRAMs D[4:0], D[22:18]
WE
CKE0
ECKE0 -> CKE0: SDRAMs D[8:5], D[26:23]
WCKE1 -> CKE1: SDRAMs D[13:9], D[31:27]
ECKE1 -> CKE1: SDRAMs D[17:14], D[35:32]
WODT0 -> ODT0: SDRAMs D[4:0]
EODT0 -> ODT0: SDRAMs D[8:5]
WODT1 -> ODT1: SDRAMs D[22:18]
EODT1 -> ODT1: SDRAMs D[26:23]
CKE1
S
T
DQS3
DQS3
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
ODT0
ODT1
E
R
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[31:24]
PCK0 -> CK: SDRAMs D[4:0], D[13:9]
PCK1 -> CK: SDRAMs D[8:5], D[26:23]
PCK2 -> CK: SDRAMs D[22:18], D[31:27]
PCK3 -> CK: SDRAMs D[17:14], D[35:32]
CK0
PCK0 -> CK: SDRAMs D[4:0], D[13:9]
PCK1 -> CK: SDRAMs D[8:5], D[26:23]
PCK2 -> CK: SDRAMs D[22:18], D[31:27]
PCK3 -> CK: SDRAMs D[17:14], D[35:32]
DQS8
DQS8
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
CK0
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
CB[7:0]
QERR
RST
PAR_IN
RESET
Err_out
RST : SDRAMs D[35:0]
Vtt
Thermal sensor with SPD
SCL
SDA
EVENT
EVENT
A0 A1 A2
SA0 SA1 SA2
DQS4
DQS4
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
V
Serial PD
D0 - D35
DDSPD
U5
U6
U7
U8
U14
U15
U16
U17
U23
U24
U25
U26
U32
U33
U34
U35
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[39:32]
V
V
DD
TT
V
V
V
D0 - D35
D0 - D35
D0 - D35
DQS5
DQS5
REFCA
REFDQ
SS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[47:40]
DQS6
DQS6
Note :
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15Ω ± 5%.
3. See the wiring diagrams for all resistors associated with
the command, address and control bus.
4. ZQ resistors are 240Ω ± 1% . For all other resistor val-
ues refer to the appropriate wiring diagram.
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[55:48]
DQS3
DQS3
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[7:0]
ZQ
DQ[31:24]
Vtt
15 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
11.0 Absolute Maximum Ratings
11.1 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to Vss
-0.4V~1.975V
V
1,3
VDDQ
Voltage on VDDQ pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
-0.4V~1.975V
-0.4V~1.975V
-55 to +100
V
V
1,3
1
V
IN, VOUT
TSTG
Note :
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
3. VDD and VDDQ must be within TBD of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than TBD;
VREF may be equal to or less than TBD.
11.2 DRAM Component Operating Temperature Range
Symbol
Parameter
rating
Unit
Notes
TOPER
Operating Temperature Range
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the
JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case tem-
perature must be maintained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaran-
teed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component
with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with
Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7
= 0b)
12.0 AC & DC Operating Conditions
12.1 Recommended DC Operating Conditions (SSTL)
Rating
Symbol
Parameter
Operation Voltage
Units
Notes
Min.
1.2825
1.475
1.2825
1.475
Typ.
1.35
1.5
Max.
1.4500
1.575
1.4500
1.575
1.35V
1.5V
V
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
VDD
Supply Voltage
1.35V
1.5V
1.35
1.5
VDDQ
Supply Voltage for Output
Note :
1. Under all conditions VDDQ must be less than or equal to VDD
.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. VDD & VDDQ rating are determinied by operation voltage.
16 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
13.0 AC & DC Input Measurement Levels
13.1 AC & DC Logic Input Levels for Single-ended Signals
Single Ended AC and DC Input for Command and Address
DDR3-1066
DDR3-1333/1600
Min.
Symbol
Parameter
Unit Notes
Min.
Max.
1.35V
Max.
VIH.CA(DC)
VREF + 90
VDD
VREF + 90
VSS
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic lowM
mV
mV
mV
mV
mV
mV
1
V
IL.CA(DC)
IH.CA(AC)
IL.CA(AC)
IH.CA(AC135)
IL.CA(AC135)
VSS
VREF - 90
VREF - 90
1
V
VREF + 160
VREF + 160
-
-
1,2
1,2
1,2
1,2
V
VREF - 160
VREF - 160
-
-
-
-
V
VREF+135
-
-
-
V
VREF-135
-
Reference Voltage for ADD,
CMD inputs
V
REFCA(DC)
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
1.5V
VIH.CA(DC)
VREF + 100
VDD
VREF + 100
VSS
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic lowM
mV
mV
mV
mV
mV
mV
1
V
IL.CA(DC)
IH.CA(AC)
IL.CA(AC)
IH.CA(AC150)
IL.CA(AC150)
VSS
VREF - 100
VREF - 100
1
V
VREF + 175
VREF + 175
-
-
1,2
1,2
1,2
1,2
V
VREF - 175
VREF - 175
-
-
-
-
V
VREF+150
-
-
-
V
VREF-150
-
Reference Voltage for ADD,
CMD inputs
V
REFCA(DC)
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
Note :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 13.5mV)
4. For reference : approx. VDD/2 ± 13.5mV
Single Ended AC and DC input levels for DQ and DM
DDR3-1066
DDR3-1333/1600
Min.
Symbol
Parameter
Unit Notes
Min.
Max.
1.35V
Max.
VIH.DQ(DC)
VREF + 90
VSS
VDD
VREF + 90
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
1
V
IL.DQ(DC)
IH.DQ(AC)
IL.DQ(AC)
IH.DQ(AC135)
IL.DQ(AC135)
VREF - 90
VSS
VREF - 90
1
V
VREF + 160
VREF + 135
Note 2
Note 2
1,2,5
1,2,5
1,2,5
1,2,5
V
VREF - 160
VREF - 135
Note 2
Note 2
V
VREF + 135
Note 2
-
-
-
-
V
VREF - 135
Note 2
Reference Voltage for DQ,
DM inputs
VREFDQ(DC)
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
1.5V
VIH.DQ(DC)
VREF + 100
VSS
VDD
VREF + 100
VSS
VDD
DC input logic high
DC input logic low
mV
mV
mV
mV
V
1
V
IL.DQ(DC)
IH.DQ(AC)
IL.DQ(AC)
VREFDQ(DC)
VREF - 100
VREF - 100
1
V
VREF + 175
VREF + 150
AC input logic high
AC input logic low
-
-
1,2,5
1,2,5
3,4
V
VREF - 175
0.51*VDD
VREF - 150
0.51*VDD
-
-
0.49*VDD
0.49*VDD
I/O Reference Voltage(DQ)
17 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
Note :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 13.5mV)
4. For reference : approx. VDD/2 ± 13.5mV
5. Single ended swing requirement for DQS - DQS is 270mV (peak to peak). Differential swing for DQS - DQS is 540mV (peak to peak).
13.2 V
Tolerances
REF
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 2. It shows a valid reference voltage
REF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
REF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF. Fur-
V
V
thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD
.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF
.
"VREF" shall be understood as VREF(DC), as defined in Figure 1.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
18 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
13.3 AC and DC Logic Input Levels for Differential Signals
13.3.1 Differential Signals Definition
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
DDR3-1066/1333/1600
Symbol
Parameter
unit
Note
min
+0.2
max
note 3
VIHdiff
VILdiff
differential input high
differential input low
V
V
V
V
1
1
2
2
note 3
-0.2
V
IHdiff(AC)
ILdiff(AC)
2 x (VIH(AC)-VREF)
differential input high ac
differential input low ac
note 3
V
2 x (VREF - VIL(AC))
note 3
Notes:
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a
reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet
Specification ".
Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS.
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
Slew Rate [V/ns]
min
75
57
50
38
34
29
22
13
0
max
min
175
170
167
163
162
161
159
155
150
150
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
0
19 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
13.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle
proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig-
nals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSEL max
VSEL
VSS or VSSQ
time
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3-1066/1333/1600
Symbol
Parameter
Unit
Notes
Min
Max
Note3
Note3
(VDD/2)+0.175
(VDD/2)+0.175
Note3
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
V
V
V
V
1, 2
1, 2
1, 2
1, 2
VSEH
(VDD/2)-0.175
(VDD/2)-0.175
VSEL
Note3
Notes:
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a
signal group, then the reduced level applies also here
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
Specification"
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DDR3L SDRAM
VLP Registered DIMM
13.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS
.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
Figure 4. VIX Definition
Cross point voltage for differential input signals (CK, DQS)
DDR3-1066/1333/1600
Symbol
Parameter
Unit
Notes
Min
Max
150
175
150
-150
-175
-150
mV
mV
mV
VIX
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
1
Note :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL
VSEH of at least VDD/2 =/-250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
/
13.4 Slew Rate Definition for Single Ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.tDH nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF
13.5 Slew Rate Definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
Differential input slew rate definition
Measured
Description
Defined by
From
To
VIHdiffmin - VILdiffmax
Delta TRdiff
VIHdiffmin - VILdiffmax
VILdiffmax
VIHdiffmin
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
Differential input slew rate for falling edge (CK-CK and DQS-DQS)
VIHdiffmin
VILdiffmax
Delta TFdiff
Note : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
V
IHdiffmin
ILdiffmax
0
V
delta TFdiff
delta TRdiff
Figure 5. Differential Input Slew Rate definition for DQS, DQS and CK, CK
21 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
14.0 AC and DC Output Measurement Levels
14.1 Single Ended AC and DC Output Levels
Single Ended AC and DC output levels
Symbol Parameter
DDR3-1066/1333/1600
Units
Notes
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
V
OM(DC) DC output mid measurement level (for IV curve linearity)
OL(DC) DC output low measurement level (for IV curve linearity)
OH(AC) AC output high measurement level (for output SR)
OL(AC) AC output low measurement level (for output SR)
0.5 x VDDQ
0.2 x VDDQ
V
V
V
V
V
V
VTT + 0.1 x VDDQ
VTT - 0.1 x VDDQ
1
1
V
Note : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2.
14.2 Differential AC and DC Output Levels
Differential AC and DC output levels
Symbol
Parameter
DDR3-1066/1333/1600
Units
Notes
V
OHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
V
OLdiff(DC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
Note : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.
14.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
Single Ended Output slew rate definition
Measured
Description
Defined by
From
To
VOH(AC)-VOL(AC)
Delta TRse
V
OL(AC)
VOH(AC)
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
VOH(AC)-VOL(AC)
Delta TFse
V
OH(AC)
VOL(AC)
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
Single Ended Output slew rate
DDR3-1066
DDR3-1333
DDR3-1600
Operation
Voltage
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
51)
1.35V
1.5V
1.75
2.5
-
-
V/ns
V/ns
Single ended output slew rate
Description : SR : Slew Rate
SRQse
5
2.5
5
TBD
5
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
se : Singe-ended Signals, For Ron = RZQ/7 setting
Note 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all
remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respec-
tively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
22 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
V
TT
delta TFse
delta TRse
Figure 6. Single Ended Output Slew Rate definition
14.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
VOHdiff(AC) for differential signals as shown in below.
Differential Output slew rate definition
Measured
Description
Defined by
From
To
VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
V
OLdiff(AC)
VOHdiff(AC)
Differential output slew rate for rising edge
Differential output slew rate for falling edge
VOHdiff(AC)-VOLdiff(AC)
Delta TFdiff
V
OHdiff(AC)
VOLdiff(AC)
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output slew rate
DDR3-1066
DDR3-1333
Min Max
DDR3-1600
Operation
Voltage
Parameter
Symbol
Units
Min
3.5
5
Max
10
Min
Max
1.35V
1.5V
-
-
V/ns
V/ns
Single ended output slew rate
Description : SR : Slew Rate
SRQse
10
5
10
TBD
10
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
diff : Singe-ended Signals
For Ron = RZQ/7 setting
V
(AC)
(AC)
OHdiff
V
V
TT
OLdiff
delta TFdiff
delta TRdiff
Figure 7. Differential Output Slew Rate definition
23 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
15.0 IDD specification definition
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT and PRE;
Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
a)
IDD0
b)
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT, RD
and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:
a)
IDD1
b)
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-
tern
Precharge Standby Current
a)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Regis-
b)
ters ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Standby ODT Current
a)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
DD2NT
DDQ2NT
IDD2P0
Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Regis-
b)
ters ; ODT Signal: toggling according to Table 35 ; Pattern Details: Refer to Component Datasheet for detail pattern
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
a)
b)
;
;
c)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
a)
IDD2P1
IDD2Q
IDD3N
IDD3P
b)
;
c)
Precharge Quiet Standby Current
a)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers
ODT Signal: stable at 0
b)
Active Standby Current
a)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 34 on page 36 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and
b)
RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Active Power-Down Current
a)
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers ; ODT
Signal: stable at 0
b)
Operating Burst Read Current
a)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank
Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable
IDD4R
IDDQ4R
IDD4W
b)
at 0; Pattern Details: Refer to Component Datasheet for detail pattern
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
a)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank
Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT: Enabled in Mode Registers ; ODT
b)
Signal: stable at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern
Burst Refresh Current
a)
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output
Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
IDD5B
IDD6
b)
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Normal ; CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
d)
e)
a)
b)
24 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
Symbol
Description
f)
Self-Refresh Current: Extended Temperature Range (optional)
d)
e)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Extended ; CKE: Low; External clock: Off; CK and CK:
IDD6ET
IDD6TC
a)
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;
b)
Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
f)
Auto Self-Refresh Current (optional)
d)
e)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabled ; Self-Refresh Temperature Range (SRT): Normal ; CKE: Low; External clock: Off; CK and CK:
LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0;
Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
a)
b)
Operating Bank Interleave Read Current
a)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: CL-1; CS: High
IDD7
IDD8
between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and
the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:
b)
Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
RESET Low Current
RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :
FLOATING
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
g) Read Burst type : Nibble Sequential, set MR0 A[3]=0B
25 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
15.1 IDD SPEC Table
M392B2873FH0 : 1GB (128Mx72) Module
CF8
CH9
CK0
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
(DDR3-1333@CL=11)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2NT
IDDQ2NT
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
M392B5673FH0 : 2GB (256Mx72) Module
CF8
CH9
CK0
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
(DDR3-1333@CL=11)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2NT
IDDQ2NT
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
26 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
M392B5670FH0 : 2GB (256Mx72) Module
CF8
CH9
CK0
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
(DDR3-1333@CL=11)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2NT
IDDQ2NT
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
M392B5170FM0 : 4GB (512Mx72) Module
CF8
CH9
CK0
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
(DDR3-1333@CL=11)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2NT
IDDQ2NT
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
27 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
M392B5173FM0 : 4GB (512Mx72) Module
CF8
CH9
CK0
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
(DDR3-1333@CL=11)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2NT
IDDQ2NT
IDD2Q
IDD3P(fast exit)
IDD3N
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD7
IDD8
28 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
16.0 Input/Output Capacitance
M392B2873FH0
DDR3-1333
Parameter
Symbol
DDR3-1066
Min Max
DDR3-1600
Min Max
Units Notes
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M392B5673FH0
DDR3-1333
Parameter
Symbol
DDR3-1066
Min Max
DDR3-1600
Min Max
Units Notes
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M392B5670FH0
DDR3-1333
Parameter
Symbol
DDR3-1066
Min Max
DDR3-1600
Min Max
Units Notes
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M392B5170FM0
DDR3-1333
Parameter
Symbol
DDR3-1066
Min Max
DDR3-1600
Min Max
Units Notes
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M392B5173FM0
DDR3-1333
Parameter
Symbol
DDR3-1066
Min Max
DDR3-1600
Min Max
Units Notes
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
29 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
17.0 Electrical Characteristics and AC timing
[0 °C<TCASE ≤95 °C, VDDQ = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V); VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]
17.1 Refresh Parameters by Device Density
Parameter
All Bank Refresh to active/refresh cmd time
Symbol
tRFC
1Gb
110
7.8
2Gb
160
7.8
4Gb
300
7.8
8Gb
350
7.8
Units
ns
Note
0 °C ≤ TCASE ≤ 85°C
µs
Average periodic refresh interval
tREFI
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
3.9
µs
1
Note :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or
requirements referred to in this material.
17.2 Speed Bins and CL, tRCD, tRC and tRAS for Corresponding Bin
Speed
DDR3-1066
7-7-7
min
DDR3-1333
9-9-9
min
9
DDR3-1600
11-11-11
min
Units
Note
Bin (CL - tRCD - tRP)
Parameter
CL
7
11
tCK
ns
ns
ns
ns
ns
ns
tRCD
tRP
13.13
13.13
37.5
13.5
13.5
36
13.75
13.75
35
tRAS
tRC
50.63
7.5
49.5
6.0
48.75
6.0
tRRD
tFAW
37.5
30
30
30 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
17.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
Speed
CL-nRCD-nRP
DDR3-800
6 - 6 - 6
Units
Note
Parameter
Symbol
tAA
min
15
max
20
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ns
ns
tRCD
tRP
15
-
15
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
CL = 6 / CWL = 5
tRC
52.5
37.5
2.5
ns
tRAS
9*tREFI
3.3
ns
8
tCK(AVG)
ns
1,2,3
Supported CL Settings
6
5
nCK
nCK
Supported CWL Settings
DDR3-1066 Speed Bins
Speed
DDR3-1066
7 - 7 - 7
CL-nRCD-nRP
Units
Note
Parameter
Symbol
tAA
min
13.125
13.125
13.125
50.625
37.5
max
20
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ns
ns
tRCD
-
tRP
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
ns
tRAS
9*tREFI
3.3
ns
8
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
ns
1,2,3,6
1,2,3,4
4
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
Reserved
Reserved
ns
ns
1.875
1.875
<2.5
<2.5
ns
1,2,3,4
4
Reserved
ns
ns
1,2,3
Supported CL Settings
Supported CWL Settings
6,7,8
5,6
nCK
nCK
31 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
DDR3-1333 Speed Bins
Speed
CL-nRCD-nRP
DDR3-1333
9 -9 - 9
Units
Note
Parameter
Symbol
tAA
min
max
20
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
ACT to PRE command period
CWL = 5
13.5 (13.125)5,9
13.5 (13.125)5,9
13.5 (13.125)5,9
49.5 (49.125)5,9
36
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRCD
-
tRP
-
-
tRC
tRAS
9*tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
CL = 6
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
1.875
<2.5
<2.5
CL = 7
CWL = 6
tCK(AVG)
ns
(Optional) Note 5,9
Reserved
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5,6
CWL = 7
CWL = 5,6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
ns
ns
Reserved
CL = 8
CL = 9
CL = 10
1.875
ns
Reserved
Reserved
ns
ns
1.5
1.5
<1.875
<1.875
ns
Reserved
ns
ns
CWL = 7
tCK(AVG)
(Optional)
6,7,8,9
5,6,7
ns
Supported CL Settings
Supported CWL Settings
nCK
nCK
32 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
DDR3-1600 Speed Bins
Speed
DDR3-1600
11-11-11
CL-nRCD-nRP
Parameter
Units
Note
Symbol
min
max
13.75
Intermal read command to first data
ACT to internal read or write delay time
PRE command period
tAA
20
ns
ns
ns
ns
(13.125)5,9
13.75
tRCD
tRP
-
-
-
(13.125)5,9
13.75
(13.125)5,9
48.75
ACT to ACT or REF command period
tRC
(48.125)5,9
ACT to PRE command period
CWL = 5
tRAS
35
9*tREFI
3.3
ns
ns
ns
ns
ns
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
1,2,3,8
CL = 6
CWL = 6
CWL = 7, 8
CWL = 5
Reserved
Reserved
Reserved
1,2,3,4,8
4
4
1.875
<2.5
CWL = 6
tCK(AVG)
ns
1,2,3,4,8
CL = 7
(Optional) Note 5,9
Reserved
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5,6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
ns
ns
ns
ns
ns
ns
ns
1,2,3,4,8
Reserved
4
4
Reserved
1.875
1.5
<2.5
1,2,3,8
1,2,3,4,8
1,2,3,4
4
CL = 8
CL = 9
Reserved
Reserved
Reserved
<1.875
CWL = 7
tCK(AVG)
ns
1,2,3,4,8
(Optional) Note 9,10
TBD
CWL = 8
tCK(AVG)
tCK(AVG)
ns
ns
1,2,3,4
4
CWL = 5,6
Reserved
1.5
<1.875
CL = 10
CL = 11
CWL = 7
tCK(AVG)
ns
1,2,3,8
(Optional) Note 9,10
Reserved
CWL = 8
CWL = 5,6,7
CWL = 8
tCK(AVG)
tCK(AVG)
tCK(AVG)
ns
ns
1,2,3,4
4
Reserved
1.25
<1.5
ns
1,2,3,5
Supported CL Settings
Supported CWL Settings
6,7,8,9,10,11
5,6,7,8
nCK
nCK
33 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
17.3.1 Speed Bin Table Notes
Absolute Specification [TOPER; VDDQ = VDD = 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)]:
Note :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be ful-
filled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequen-
cies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns
or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data sheet and/
or the DIMM SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to
match. For example, DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte
16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should pro-
gram 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRC-
min (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and
48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
34 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
18.0 Timing Parameters for DDR3-800, DDR3-1066, DDR3-1333 and DDR3-1600
Timing Parameters by Speed Bin
Speed
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Note
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Clock Timing
tCK(DLL_OF
F)
Minimum Clock Cycle Time (DLL off mode)
8
-
8
-
8
-
8
-
ns
6
Average Clock Period
Clock Period
tCK(avg)
tCK(abs)
See Speed Bins Table
ps
ps
tCK(avg)min + tJIT(per)min
tCK(avg)max + tJIT(per)max
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.47
-100
-90
0.53
0.53
100
90
0.47
0.47
-90
0.53
0.53
90
0.47
0.47
-80
0.53
0.53
80
0.47
0.47
-70
0.53
0.53
70
tCK(avg)
Average low pulse width
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-80
80
-70
70
-60
60
ps
200
180
180
160
160
140
140
120
ps
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
147
175
194
209
222
232
241
249
257
263
269
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
132
157
175
188
200
209
217
224
231
237
242
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
118
140
155
168
177
186
193
200
205
210
215
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
103
122
136
147
155
163
169
175
180
184
188
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
ps
24
Absolute clock HIGH pulse width
Absolute clock Low pulse width
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
25
26
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to
tDQSQ
tQH
-
200
-
-
150
-
-
125
-
-
100
-
ps
tCK(avg)
ps
13
0.38
-800
-
0.38
-600
-
0.38
-500
-
0.38
-450
-
13, g
tLZ(DQ)
tHZ(DQ)
400
400
300
300
250
250
225
225
13,14, f
13,14, f
ps
tDS(base)
75
-
25
-
30
-
10
ps
d, 17
V
(AC)V (AC) levels
IL
IH
Data hold time to DQS, DQS referenced to
(AC)V (AC) levels
tDH(base)
tDIPW
150
600
100
490
65
-
45
ps
ps
d, 17
28
-
-
-
-
V
IH
IL
DQ and DM Input pulse width for each input
Data Strobe Timing
400
360
-
DQS, DQS READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS output high time
tRPRE
tRPST
tQSH
0.9
0.3
Note 19
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
tCK
tCK
13, 19, g
11, 13, b
13, g
Note 11
Note 11
Note 11
Note 11
0.38
0.38
0.9
-
-
-
-
0.38
0.38
0.9
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK
DQS, DQS output low time
tQSL
13, g
DQS, DQS WRITE Preamble
DQS, DQS WRITE Postamble
tWPRE
tWPST
0.3
0.3
tCK
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
-400
-800
-
400
400
400
-300
-600
-
300
300
300
-255
-500
-
255
250
250
-225
-450
-
225
225
225
ps
ps
ps
13,f
DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS)
13,14,f
13,14,f
DQS, DQS high-impedance time (Referenced from
tHZ(DQS)
RL+BL/2)
DQS, DQS differential input low pulse width
tDQSL
tDQSH
tDQSS
tDSS
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.27
0.18
0.18
0.55
0.55
0.27
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
29, 31
30, 31
c
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
c, 32
c, 32
tDSH
0.2
-
0.2
-
0.2
-
-
35 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Note
Parameter
Command and Address Timing
DLL locking time
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tDLLK
tRTP
512
-
-
512
-
-
512
-
-
512
-
-
nCK
max
max
max
internal READ Command to PRECHARGE Command
delay
max
(4nCK,7.5ns
)
(4nCK,7.5ns
)
(4nCK,7.5ns
)
e
(4nCK,7.5ns)
max
max
max
Delay from start of internal write transaction to internal
read command
max
tWTR
(4nCK,7.5ns
)
-
(4nCK,7.5ns
)
-
(4nCK,7.5ns
)
-
-
e,18
e,18
(4nCK,7.5ns)
WRITE recovery time
tWR
15
4
-
-
15
4
-
-
15
4
-
-
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
nCK
max
max
max
max
Mode Register Set command update delay
tMOD
(12nCK,15ns
)
-
-
(12nCK,15ns
)
-
(12nCK,15ns
)
-
-
(12nCK,15ns
)
-
-
CAS# to CAS# command delay
tCCD
tDAL(min)
tMPRR
tRAS
4
4
-
4
4
nCK
nCK
nCK
ns
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
WR + roundup (tRP / tCK(AVG))
1
-
1
-
1
-
1
-
22
e
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 40
max
max
max
max
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRD
-
(4nCK,7.5ns
)
-
-
-
-
e
e
(4nCK,10ns)
(4nCK,6ns)
(4nCK,6ns)
max
max
max
max
-
-
(4nCK,7.5ns
)
-
(4nCK,10ns)
(4nCK,10ns)
(4nCK,7.5ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK refer-
tFAW
tFAW
40
50
-
-
37.5
50
-
-
30
45
-
-
30
40
-
-
ns
ns
e
e
tIS(base)
tIH(base)
200
275
125
200
65
-
-
45
-
-
ps
ps
b,16
b,16
-
-
-
-
enced to V (AC) / V (AC) levels
IH
IL
Command and Address hold time from CK, CK refer-
enced to V (AC) / V (AC) levels
140
120
IH
IL
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
tIS(base)
AC150
200 + 150
900
125 + 150
780
65+125
620
-
-
45+125
560
-
-
ps
ps
b,16,27
28
-
-
-
-
IH
IL
Control & Address Input pulse width for each input
Calibration Timing
tIPW
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
Reset Timing
tZQinitI
tZQoper
tZQCS
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
nCK
nCK
nCK
23
max(5nCK,
max(5nCK,
max(5nCK,
max(5nCK,
Exit Reset from CKE HIGH to a valid command
tXPR
-
-
-
-
tRFC + 10ns)
tRFC + 10ns)
tRFC + 10ns)
tRFC + 10ns)
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL
max(5nCK,t
RFC + 10ns)
max(5nCK,t
RFC + 10ns)
max(5nCK,t
RFC + 10ns)
max(5nCK,tR
FC + 10ns)
tXS
-
-
-
-
-
-
-
-
-
-
-
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tCKESR
tDLLK(min)
tDLLK(min)
tDLLK(min)
tDLLK(min)
nCK
Minimum CKE low width for Self refresh entry to exit
timing
tCKE(min) +
1tCK
tCKE(min) +
1tCK
tCKE(min) +
1tCK
tCKE(min) +
1tCK
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
tCKSRE
tCKSRX
-
-
-
-
-
-
-
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
36 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
Note
Parameter
Power Down Timing
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Exit Power Down with DLL on to any valid com-
mand;Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max
max
max
max
tXP
tXPDLL
tCKE
(3nCK,
7.5ns)
-
-
-
(3nCK,
7.5ns)
-
-
-
-
-
-
-
-
-
(3nCK,6ns)
(3nCK,6ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
max
(10nCK,
24ns)
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
2
max
max
max
max
CKE minimum pulse width
(3nCK,
7.5ns)
(3nCK,
5.625ns)
(3nCK,
5.625ns)
(3nCK,5ns)
Command pass disable delay
tCPDED
tPD
1
-
1
-
1
-
1
-
nCK
tCK
Power Down Entry to Exit Timing
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
15
20
20
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
tACTPDEN
tPRPDEN
tRDPDEN
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
nCK
nCK
RL + 4 +1
RL + 4 +1
RL + 4 +1
RL + 4 +1
WL + 4
+(tWR/
WL + 4
+(tWR/
WL + 4
+(tWR/
WL + 4
+(tWR/
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
tWRPDEN
tWRAPDEN
tWRPDEN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nCK
nCK
nCK
nCK
9
10
9
tCK(avg))
tCK(avg))
tCK(avg))
tCK(avg))
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
WL + 4
WL + 4
WL + 4
WL + 4 +WR
+1
+WR +1
+WR +1
+WR +1
WL + 2
+(tWR/
WL + 2
+(tWR/
WL + 2
+(tWR/
WL + 2
+(tWR/
Timing of WR command to Power Down entry
(BL4MRS)
tCK(avg))
tCK(avg))
tCK(avg))
tCK(avg))
Timing of WRA command to Power Down entry
(BL4MRS)
WL +2 +WR
+1
WL +2 +WR
+1
WL +2 +WR
+1
WL +2 +WR
+1
tWRAPDEN
tREFPDEN
10
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
1
-
-
1
-
-
1
-
-
1
-
-
20,21
tMRSPDEN tMOD(min)
tMOD(min)
tMOD(min)
tMOD(min)
ODT high time without write command or with write
command and BC4
ODTH4
ODTH8
tAONPD
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
nCK
nCK
ns
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with
DLL frozen)
8.5
8.5
8.5
8.5
Asynchronous RTT turn-off delay (Power-Down with
DLL frozen)
tAOFPD
tAON
2
8.5
400
0.7
0.7
2
8.5
300
0.7
0.7
2
8.5
250
0.7
0.7
2
8.5
225
0.7
0.7
ns
ODT turn-on
-400
0.3
0.3
-300
0.3
0.3
-250
0.3
0.3
-225
0.3
0.3
ps
7,f
8,f
f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
tCK(avg)
tCK(avg)
RTT dynamic change skew
tADC
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed
tWLMRD
40
-
40
-
40
-
40
-
tCK
3
3
DQS/DQS delay after tDQS margining mode is pro-
grammed
tWLDQSEN
tWLS
25
-
-
-
25
-
-
-
25
-
-
-
25
-
-
-
tCK
ps
Setup time for tDQSS latch
325
325
245
245
195
195
165
165
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
tWLH
ps
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
0
0
9
2
0
0
9
2
0
0
7.5
2
ns
ns
tWLOE
37 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
18.1 Jitter Notes
Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input
clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another
Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge
to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per),
tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these param-
eters should be met whether clock jitter is present or not.
Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) cross-
ing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe
signal (DQS(L/U), DQS(L/U)#) crossing.
Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},
which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the
device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at
Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.
Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock,
where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps,
then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) =
tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) =
- 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (out-
put deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act =
2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x
tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x
tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!)= 0.38 x 2500 ps - 72 ps = + 878
ps. (Caution on the min/max usage!)
38 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
18.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation"
8. For definition of RTT turn-off time tAOF see "Device Operation".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. Device Operation.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is valid for RON34
14. Single ended signal parameter.
15. tREFI depends on T
OPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
V
(DC) = V DQ(DC). FOr input only pins except RESET, V (DC)=V CA(DC).
REF
REF
REF
REF
See "Address/ Command Setup, Hold and Derating"
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
V
(DC)= V
DQ(DC). For input only pins except RESET, V
(DC)=V
CA(DC).
REF
REF
REF
REF
See "Data Setup, Hold and Slew Rate Derating"
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
0.5
~
~
= 0.133
128ms
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
(DC) and the consecutive crossing of V
(DC)
REF
REF
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
39 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
19.0 Physical Dimensions :
19.1 128Mbx8 based 128Mx72 Module(1 Rank) - M392B2873FH0
Units : Millimeters
Max 4.0
133.35 ± 0.15
128.95
C
9.76
20.92
32.40
20.93
9.74
54.675
A
B
1.0 max
47.00
71.00
1.27 ± 0.10
SPD/TS
18.10
5.00
0.80 ± 0.05
9.9
3.80
0.2 ± 0.15
1.50±0.10
1.00
2.50
Detail A
Detail B
Detail C
19.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs
Address, Command and Control lines
Note : DRAMs indicated with dotted outline are located on the backside of the module.
The used device is 128M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G0846FC-HY**
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
40 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
19.2 128Mbx8 based 256Mx72 Module(2 Ranks) - M392B5673FH0
Units : Millimeters
Max 4.0
133.35 ± 0.15
128.95
C
9.76
20.92
32.40
20.93
9.74
54.675
A
B
1.0 max
47.00
71.00
1.27 ± 0.10
SPD/TS
18.10
5.00
0.80 ± 0.05
9.9
3.80
0.2 ± 0.15
1.50±0.10
1.00
2.50
Detail A
Detail B
Detail C
19.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs
SPD/TS
Address, Command and Control lines
The used device is 128M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G0846F-HY**
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
41 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
19.3 256Mbx4 based 256Mx72 Module(1 Rank) - M392B5670FH0
Units : Millimeters
Max 4.0
133.35 ± 0.15
128.95
C
9.76
20.92
32.40
20.93
9.74
54.675
A
B
1.0 max
47.00
71.00
1.27 ± 0.10
SPD/TS
18.10
5.00
0.80 ± 0.05
9.9
3.80
0.2 ± 0.15
1.50±0.10
1.00
2.50
Detail A
Detail B
Detail C
19.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs
SPD/TS
Address, Command and Control lines
The used device is 256M x4 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G0446F-HY**
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
42 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
19.4 256Mbx4(DDP) based 512Mx72 Module(2 Ranks) - M392B5170FM0
Units : Millimeters
Max 4.0
133.35 ± 0.15
128.95
C
9.76
20.92
32.40
20.93
9.74
54.675
A
B
1.0 max
47.00
71.00
1.27 ± 0.10
SPD/TS
18.10
5.00
0.80 ± 0.05
9.9
3.80
0.2 ± 0.15
1.50±0.10
1.00
2.50
Detail A
Detail B
Detail C
19.4.1 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs
SPD/TS
Address, Command and Control lines
The used device is 256M x4(DDP) DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0446F-MY**
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
43 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
19.5 128Mbx8(DDP) based 512Mx72 Module(4 Ranks) - M392B5173FM0
Units : Millimeters
Max 4.0
133.35 ± 0.15
128.95
C
9.76
20.92
32.40
20.93
9.74
54.675
A
B
1.0 max
47.00
71.00
1.27 ± 0.10
SPD/TS
18.10
5.00
0.80 ± 0.05
9.9
3.80
0.2 ± 0.15
1.50±0.10
1.00
2.50
Detail A
Detail B
Detail C
19.5.1 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs
SPD/TS
Address, Command and Control lines
The used device is 128M x8(DDP) DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B2G0846F-MY**
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
44 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
1. FRONT PART
19.5.2 Heat Spreader Design Guide
Outside
130.45
67
8.69
20.82
17.9
6.4
20.82
8.69
Driver
IC(DP:0.18mm)
DRIVER IC 0.18 -0/+0.1
Inside
Driver
IC(DP:0.18mm)
2. BACK PART
Outside
Driver
IC(DP:0.18mm)
Inside
Driver
IC(DP:0.18mm)
45 of 46
Rev. 0.9 September 2009
DDR3L SDRAM
VLP Registered DIMM
3. CLIP PART
35.82
7.4 ± 0.1
7.4 ± 0.1
Clip open size
3.2~4.5
0.1
SIDE-L
FRONT
SIDE-R
4. ASS’Y VIEW
Reference thickness total (Maximum) : 7.71 (With Clip thickness)
TIM Thickness 0.25
46 of 46
Rev. 0.9 September 2009
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DDR DRAM Module, 512MX72, 20ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
SAMSUNG
M392B5273DH0-CH9
DDR DRAM Module, 512MX72, 20ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
SAMSUNG
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