M393T2953CZ0-CD5 [SAMSUNG]
DDR DRAM Module, 128MX72, 0.5ns, CMOS, PDMA240;
| 型号： | M393T2953CZ0-CD5 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 128MX72, 0.5ns, CMOS, PDMA240 时钟 动态存储器 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总23页 (文件大小：374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 512Mb C-die
72-bit ECC
Revision 1.1
March 2005
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
DDR2 Registered DIMM Ordering Information
Number of
Part Number
Density Organization
Component Composition
Height
Rank
M393T6553CZ0-CD5/CC
M393T2953CZ0-CD5/CC
M393T2950CZ0-CD5/CC
M393T5750CZ0-CD5/CC
512MB
1GB
64Mx72
128Mx72
128Mx72
256Mx72
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*36EA
1
2
1
2
30mm
30mm
30mm
30mm
1GB
2GB
Note: “Z” of Part number stand for Lead-free products.
Features
•
Performance range
D5(DDR2-533)
CC(DDR2-400)
Unit
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
-
400
400
-
4-4-4
3-3-3
•
•
•
JEDEC standard 1.8V ± 0.1V Power Supply
VDDQ = 1.8V ± 0.1V
200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin
•
•
•
•
•
•
•
•
•
•
•
•
4 independent internal banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency: 0, 1 , 2 , 3 and 4
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination with selectable values(50/75/150 ohms or disable)
PASR(Partial Array Self Refresh)
Average Refesh Period 7.8us at lower a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
- support High Temperature Self-Refresh rate enable feature
•
Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA 32Mx16
- RoHS Compliant
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
128Mx4(512Mb) based Module
64Mx8(512Mb) based Module
Row Address
A0-A13
Column Address
A0-A9,A11
Bank Address
BA0-BA1
Auto Precharge
A10
A10
A0-A13
A0-A9
BA0-BA1
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Pin Configurations (Front side/Back side)
Pin
1
Front
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Front
DQ19
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
Back
Pin
61
Front
A4
Pin
181
182
183
184
Back
Pin
91
Front
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
Back
DM5/DQS14
V
V
V
V
V
REF
SS
SS
DDQ
SS
V
V
V
2
DQ4
DQ5
DQ28
DQ29
62
A3
A1
92
DQS5
DQS5
NC/DQS14
SS
SS
DDQ
V
3
DQ0
DQ1
DQ24
DQ25
63
A2
93
SS
V
V
V
V
V
4
64
94
DQ46
DQ47
SS
SS
DD
DD
SS
V
V
5
DM0/DQS9
NC/DQS9
DM3/DQS12
NC/DQS12
KEY
95
DQ42
DQ43
SS
SS
V
V
6
DQS0
DQS0
DQS3
DQS3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
CK0
CK0
96
SS
SS
V
V
V
V
7
97
DQ52
DQ53
SS
SS
SS
SS
V
V
V
V
8
DQ6
DQ7
DQ30
DQ31
98
DQ48
DQ49
SS
SS
DD
DD
V
9
DQ2
DQ3
DQ26
DQ27
NC/Par_In
A0
99
SS
V
V
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
100
101
102
103
104
105
106
107
108
109
110
111
112
113
RFU
RFU
SS
SS
DD
DD
SS
V
V
DQ12
DQ13
CB4
CB5
A10/AP
BA0
BA1
SA2
SS
SS
V
V
DQ8
DQ9
CB0
CB1
NC(TEST)
DDQ
SS
V
V
V
V
RAS
S0
DM6/DQS15
NC/DQS15
SS
SS
DDQ
SS
V
V
DM1/DQS10
NC/DQS10
DM8/DQS17
NC/DQS17
WE
DQS6
DQS6
SS
SS
V
V
DQS1
DQS1
DQS8
DQS8
CAS
DDQ
SS
V
V
V
V
ODT0
A13
DQ54
DQ55
SS
SS
DDQ
SS
4
V
V
RFU
RFU
CB6
CB7
DQ50
DQ51
S1
SS
SS
V
V
RESET
NC
CB2
CB3
ODT1
DD
SS
V
V
V
V
V
DQ60
DQ61
SS
SS
DDQ
SS
SS
V
V
V
V
DQ14
DQ15
DQ36
DQ37
DQ56
DQ57
SS
SS
DDQ
SS
4
V
V
DQ10
DQ11
DQ32
DQ33
DDQ
CKE1
SS
V
V
V
V
CKE0
DM7/DQS16
NC/DQS16
SS
DD
SS
SS
V
V
V
DQ20
DQ21
DM4/DQS13
NC/DQS13
DQS7
DQS7
SS
DD
NC
NC
SS
V
24
25
26
27
28
29
30
DQ16
DQ17
144
145
146
147
148
149
150
54
55
56
57
58
59
60
NC
174
175
176
177
178
179
180
83
84
85
86
87
88
89
90
DQS4
DQS4
203
204
205
206
207
208
209
210
114
115
116
117
118
119
120
234
235
236
237
238
239
240
SS
V
V
V
V
NC/Err_Out
DQ62
DQ63
SS
DDQ
SS
SS
V
V
V
DM2/DQS11
NC/DQS11
A12
A9
DQ38
DQ39
DQ58
DQ59
SS
DDQ
SS
V
DQS2
DQS2
A11
A7
DQ34
DQ35
SS
V
V
V
V
VDDSPD
SA0
SS
DD
SS
SS
V
V
V
DQ22
DQ23
A8
A6
DQ44
DQ45
SDA
SCL
SS
DD
SS
DQ18
A5
DQ40
DQ41
SA1
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin Description
Pin Name
CK0
Description
Clock Inputs, positive line
Pin Name
ODT0~ODT1
DQ0~DQ63
CB0~CB7
Description
On die termination
Data Input/Output
CK0
Clock inputs, negative line
Clock Enables
CKE0, CKE1
RAS
Data check bits Input/Output
Data strobes
Row Address Strobe
Column Address Strobe
Write Enable
DQS0~DQS8
DQS0~DQS8
CAS
Data strobes, negative line
WE
DM(0~8),DQS(9~17) Data Masks / Data strobes (Read)
S0, S1
Chip Selects
DQS9~DQS17
Data strobes (Read), negative line
Reserved for Future Use
No Connect
A0~A9, A11~A13
A10/AP
Address Inputs
RFU
NC
Address Input/Autoprecharge
Memory bus test tool (Not Connect and Not Useable on
DIMMs)
BA0, BA1
DDR2 SDRAM Bank Address
TEST
VDD
VDDQ
VSS
SCL
SDA
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
Core Power
I/O Power
SA0~SA2
Par_In
SPD address
Ground
VREF
Parity bit for the Address and Control bus
Parity error found in the Address and Control bus
Register and PLL control pin
Input/Output Reference
SPD Power
VDDSPD
Err_Out
RESET
*The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Input/Output Functional Description
Symbol
Type
Input
Input
Function
CK0
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
CK0
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating
the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Input
CKE0~CKE1
Enables the associated SDRAM command decoder when low and disables decoder when high. When
decoder is disabled, new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM
when both inputs are high.
Input
S0~S1
Input
Input
ODT0~ODT1
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be
executed by the SDRAM.
RAS, CAS, WE
V
Supply
Reference voltage for SSTL_18 inputs
REF
V
Supply
Input
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of four is activated.
DDQ
BA0~BA1
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP
is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, auto-
precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to
control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of
BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
A0~A9,A10/AP
A11~A13
Input
DQ0~63,
CB0~CB7
In/Out
Input
Data and Check Bit Input/Output pins
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency
of one clock once the write command is registered into the SDRAM.
DM0~DM8
V
, V
SS
Supply
In/Out
In/Out
Power and ground for the DDR SDRAM input buffers and core logic
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
DD
DQS0~DQS17
DQS0~DQS17
These signals are tied at the system planar to either V or V
SS
EEPROM address range.
to configure the serial SPD
DDSPD
SA0~SA2
SDA
Input
In/Out
Input
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be con-
nected from the SDA bus line to V to act as a pullup.
DDSPD
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from
the SCL bus time to V to act as a pullup.
SCL
DDSPD
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports
from 1.7 Volt to 3.6 Volt operation).
V
Supply
DDSPD
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low,
all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low
level (The PLL will remain synchronized with the input clock )
RESET
Input
Par_In
Err_Out
TEST
Input
Input
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
In/Out
Used by memory bus analysis tools (unused on memory DIMMs)
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Functional Block Diagram: 512MB, 64Mx72 Module(populated as 1 rank of x8 DDR2 SDRAMs)
M393T6553CZ0
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 0
I/O 1
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS6
DQS2
DQS6
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
DQS8
DQS8
DM8/DQS17
NC/DQS17
V
Serial PD
D0 - D8
D0 - D8
D0 - D8
DDSPD
Serial PD
SCL
V
/V
SDA
DD DDQ
DM/ NU/ CS DQS DQS
RDQS RDQS
I/O 0
WP A0 A1 A2
SA0 SA1 SA2
VREF
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
V
SS
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK7 -> CK : Register
PCK7 -> CK : Register
OE
RESET
1:1
R
E
G
I
S
T
E
R
S0*
RSO-> CS : DDR2 SDRAMs D0-D8
BA0-BA1
A0-A13
RAS
CAS
WE
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8
RRAS -> RAS : DDR2 SDRAMs D0-D8
RCAS -> CAS : DDR2 SDRAMs D0-D8
RWE -> WE : DDR2 SDRAMs D0-D8
Notes :
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. Unless otherwise noted, resister values are 22 Ohms
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
RST
RESET
* S0 connects to DCS and VDD connects to CSR on the register.
PCK7
PCK7
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Functional Block Diagram: 1GB, 128Mx72 Module(populated as 2 rank of x8 DDR2 SDRAMs)
M393T2953CZ0
RS1
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D9
D4
D13
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS6
DQS2
DQS6
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
DQS8
DQS8
DM8/DQS17
NC/DQS17
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
Serial PD
/V
DD DDQ
SCL
SDA
DM/ NU/ CS DQS DQS
RDQS RDQS
I/O 0
DM/ NU/ CS DQS DQS
RDQS RDQS
I/O 0
WP A0 A1 A2
SA0 SA1 SA2
VREF
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D17
V
SS
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
PCK7 -> CK : Register
PCK7 -> CK : Register
CK0
RESET
S0*
S1*
RSO-> CS : DDR2 SDRAMs D0-D8
RS1-> CS : DDR2 SDRAMs D9-D17
OE
1:2
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RCKE1 -> CKE : DDR2 SDRAMs D9-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
RODT1 -> ODT1 : DDR2 SDRAMs D9-D17
R
E
G
I
S
T
E
R
Notes :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms
3. RS0 and RS1 alternate between the back and front sides of the DIMM
RST
RESET**
* S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register.
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
PCK7**
PCK7**
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Functional Block Diagram: 1GB, 128Mx72 Module(populated as 1 rank of x4 DDR2 SDRAMs)
M393T2950CZ0
VSS
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
DQ1
DQ2
DQ3
D0
D9
DQS1
DQS1
DM1/DQS10
NC/DQS10
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ13
DQ14
DQ15
D1
D10
DQS2
DQS2
DM2/DQS11
NC/DQS11
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
D2
D11
DQS3
DQS3
DM3/DQS12
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D12
DQS4
DQS4
DM4/DQS13
NC/DQS13
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D13
DQS5
DQS5
DM5/DQS14
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D14
Serial PD
DQS6
DQS6
DM6/DQS15
NC/DQS15
SCL
SDA
WP A0 A1 A2
SA0 SA1 SA2
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D15
DQS7
DQS7
DM7DQS16
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DQ56
DQ60
DDSPD
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D16
/V
DD DDQ
DQS8
DQS8
DM8/DQS17
NC/DQS17
VREF
DM
CS DQS DQS
DM
CS DQS DQS
V
SS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D17
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK7 -> CK : Register
PCK7 -> CK : Register
P
L
L
1:2
R
E
G
I
S
T
E
R
S0*
RSO-> CS : DDR2 SDRAMs D0-D17
CK0
BA0-BA1
A0-A13
RAS
CAS
WE
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
OE
RESET
Notes :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RST
RESET**
* S0 connects to DCS of Register1, CSR of Register2. CSR of register 1 and DCS of register 2 connects to VDD
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
PCK7**
PCK7**
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Functional Block Diagram: 2GB, 256Mx72 Module(populated as 2 rank of x4 DDR2 SDRAMs)
M393T5750CZ0
VSS
RS1
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
DM/
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
DQ1
DQ2
DQ3
D0
D18
D9
D27
DQS1
DQS1
DM1/DQS10
NC/DQS10
DM
CS DQS DQS
DM/
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ13
DQ14
DQ15
D1
D19
D10
D28
DQS2
DQS2
DM2/DQS11
NC/DQS11
DM
CS DQS DQS
DM/
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
D2
D20
D11
D29
DQS3
DQS3
DM3/DQS12
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D21
D12
D30
DQS4
DQS4
DM4/DQS13
NC/DQS13
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D22
D13
D31
DQS5
DQS5
DM5/DQS14
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D23
D14
D32
DQS6
DQS6
DM6/DQS15
NC/DQS15
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D24
D15
D33
DQS7
DQS7
DM7DQS16
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS8
DQS8
DM8/DQS17
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D26
D17
D35
Serial PD
V
V
Serial PD
D0 - D35
D0 - D35
D0 - D35
DDSPD
S0*
RSO-> CS : DDR2 SDRAMs D0-D17
RS1-> CS : DDR2 SDRAMs D18-D35
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35
RRAS -> RAS : DDR2 SDRAMs D0-D35
RCAS -> CAS : DDR2 SDRAMs D0-D35
RWE -> WE : DDR2 SDRAMs D0-D35
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RCKE1 -> CKE : DDR2 SDRAMs D18-D35
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
SCL
SDA
S1*
1:2
R
E
G
I
S
T
E
R
/V
DD DDQ
WP A0 A1 A2
SA0 SA1 SA2
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
VREF
V
SS
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
PCK7 -> CK : Register
PCK7 -> CK : Register
OE
RESET
RST
RESET**
PCK7**
* S0 connects to DCS and S0 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register.
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.
PCK7**
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
Units
V
Notes
1
- 1.0 V ~ 2.3 V
VDDQ
VDDL
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
V
V
1
1
VIN VOUT
,
V
1
TSTG
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please
refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
V
V
Supply Voltage
1.7
1.8
1.8
1.9
4
4
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must
be less than or equal to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Operating Temperature Condition
Symbol
TOPER
Parameter
Rating
0 to 95
Units
Notes
1, 2, 3
Operating Temperature
°C
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to
enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
VIH(DC)
Parameter
Min.
Max.
Units
V
Notes
VREF + 0.125
VDDQ + 0.3
DC input logic high
DC input logic low
VIL(DC)
- 0.3
VREF - 0.125
V
Input AC Logic Level
DDR2-400, DDR2-533
Symbol
Parameter
Units
Min.
Max.
-
VIH (ac)
VREF + 0.250
V
V
ac input logic high
ac input logic low
VIL (ac)
-
VREF - 0.250
AC Input Test Conditions
Symbol
Condition
Input reference voltage
Value
Units
Notes
V
V
0.5 * V
1.0
V
V
1
1
REF
DDQ
Input signal maximum peak to peak swing
Input signal minimum slew rate
SWING(MAX)
SLEW
1.0
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
2. The input signal minimum slew rate is to be maintained over the range from V
(AC) level applied to the device under test.
IH/IL
to V (AC) min for rising edges and the range from V
REF
IH
REF
to V (AC) max for falling edges as shown in the below figure.
IL
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the
IL
IH
IH
IL
negative transitions.
VDDQ
VIH(AC) min
VIH(DC) min
VREF
VSWING(MAX)
VIL(DC) max
VIL(AC) max
VSS
delta TF
V
delta TR
REF - VIL(AC) max
delta TF
VIH(AC) min - VREF
delta TR
Falling Slew =
Rising Slew =
< AC Input Test Signal Waveform >
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
Proposed Conditions
Units
Notes
IDD0
Operating one bank active-precharge current;
t
t
t
t
t
t
mA
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid com-
mands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD1
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD
mA
t
= RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING;
Data pattern is same as IDD4W
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
Precharge power-down current;
t
mA
mA
mA
t
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STA-
BLE; Data bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD4W
IDD4R
IDD5B
Operating burst write current;
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
t
t
t
mA
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS
t
t
t
= RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD6
IDD7
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
mA
mA
Low Power
Operating bank interleave read current;
t
t
t
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK =
mA
t
t
t
t
t
t
t
CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R;
Refer to the following page for detailed timing conditions
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)
M393T6553CZ0 : 512MB(64Mx8 *9) Module
Symbol
IDD0
D5(533@CL=4) CC(400@CL=3) Unit
Notes
1,285
1,405
580
1,175
1,240
540
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
805
710
775
715
750
720
348
338
1,000
1,710
1,570
1,960
72
930
1,455
1,385
1,855
72
IDD7
2,705
2,570
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T2953CZ0 : 1GB(64Mx8 *18) Module
Symbol
IDD0
D5(533@CL=4) CC(400@CL=3) Unit Notes
1,700
1,830
820
1,620
1,725
760
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,290
1,180
1,190
546
1,130
1,150
1,130
516
1,345
2,155
2,015
2,395
144
1,325
1,910
1,830
2,260
144
IDD7
3,380
3,095
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)
M393T2950CZ0 : 1GB(128Mx4 *18) Module
Symbol
IDD0
D5(533@CL=4) CC(400@CL=3) Unit Notes
2,150
2,370
820
2,070
2,220
760
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,290
1,180
1,190
546
1,130
1,150
1,130
516
1,480
2,650
2,510
3,520
144
1,460
2,360
2,280
3,340
144
IDD7
5,090
4,760
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T5750CZ0 : 2GB(128Mx4 *36) Module
Symbol
IDD0
D5(533@CL=4) CC(400@CL=3) Unit Notes
3,070
3,340
1,310
2,240
2,030
2,050
922
2,920
3,130
1,210
1,950
1,990
1,950
872
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
2,350
3,630
3,340
4,450
288
2,320
3,240
3,070
4,210
288
IDD7
6,420
5,880
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Units
Part-Number
M393T6553CZ0
M393T2959CZ0
M393T2950CZ0
Input capacitance, CK and CK
Input capacitance, CKE and CS
Input capacitance, Addr,RAS,CAS,WE
CCK
CI1
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
pF
CI2
Input/output capacitance, DQ, DM, DQS, DQS CIO
Part-Number
M393T5750CZ0
Input capacitance, CK and CK
CCK
CI1
-
-
-
-
11
12
12
10
Input capacitance, CKE and CS
Input capacitance, Addr,RAS,CAS,WE
pF
CI2
Input/output capacitance, DQ, DM, DQS, DQS CIO
DM is internally loaded to match DQ and DQS identically.
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Electrical Characteristics & AC Timing for DDR2-533/400
(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command
time
tRFC
tREFI
75
105
127.5
195
327.5
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
CASE
Average periodic refresh interval
85 °C < T
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin(CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-533(D5)
DDR2-400(CC)
Units
4 - 4 - 4
3 - 3 - 3
min
5
max
min
5
max
8
8
ns
ns
ns
ns
ns
ns
ns
3.75
3.75
15
8
5
8
8
-
-
-
15
15
55
40
-
tRP
15
-
-
-
-
tRC
55
70000
70000
tRAS
40
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Symbol
Units
Notes
Parameter
DDR2-533
DDR2-400
min
max
min
max
DQ output access time
from CK/CK
tAC
-500
+500
-600
+600
ps
ps
DQS output access
time from CK/CK
tDQSCK
-450
+450
-500
+500
CK high-level width
CK low-level width
CK half period
tCH
tCL
tHP
0.45
0.45
0.55
0.55
x
0.45
0.45
0.55
0.55
x
tCK
tCK
ps
min(tC
L, tCH)
min(tC
L, tCH)
Clock cycle time, CL=x
tCK
3750
225
8000
x
5000
275
8000
x
ps
ps
DQ and DM input hold
time
tDH(base)
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Symbol
Units
Parameter
DDR2-533
DDR2-400
min
max
min
max
DQ and DM input
setup time
tDS(base)
tIPW
100
x
150
x
ps
Control & Address
input pulse width for
each input
0.6
x
x
0.6
x
x
tCK
DQ and DM input
pulse width for each
input
tDIPW
tHZ
0.35
x
0.35
x
tCK
ps
Data-out high-
impedance time from
CK/CK
tAC
max
tAC
max
DQS low-impedance
time from CK/CK
tLZ(DQS)
tLZ(DQ)
tDQSQ
tAC
min
tAC
max
tAC
min
tAC
max
ps
ps
ps
DQ low-impedance
time from CK/CK
2* tAC
min
tAC
max
2* tAC
min
tAC
max
DQS-DQ skew for
DQS and associated
DQ signals
x
300
x
350
DQ hold skew factor
tQHS
tQH
x
400
x
x
450
x
ps
ps
DQ/DQS output hold
time from DQS
tHP -
tQHS
tHP -
tQHS
First DQS latching
transition to associated
clock edge
tDQSS
tDQSH
tDQSL
tDSS
-0.25
0.35
0.35
0.2
0.25
-0.25
0.35
0.35
0.2
0.25
tCK
tCK
tCK
tCK
tCK
tCK
DQS input high pulse
width
x
x
x
x
x
x
x
x
x
x
DQS input low pulse
width
DQS falling edge to
CK setup time
DQS falling edge hold
time from CK
tDSH
0.2
0.2
Mode register set
tMRD
2
2
command cycle time
Write postamble
Write preamble
tWPST
0.4
0.6
x
0.4
0.6
x
tCK
tCK
ps
tWPRE
tIH(base)
0.35
375
0.35
475
Address and control
input hold time
x
x
Address and control
input setup time
tIS(base)
250
x
350
x
ps
Read preamble
Read postamble
tRPRE
tRPST
tRRD
0.9
0.4
7.5
1.1
0.6
x
0.9
0.4
7.5
1.1
0.6
x
tCK
tCK
ns
Active to active
command period for
1KB page size
products
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Symbol
Units
Parameter
DDR2-533
DDR2-400
min
max
min
max
Active to active
command period for
2KB page size
products
tRRD
10
x
10
x
ns
tFAW
tFAW
Four Activate Window
for 1KB page size
products
37.5
50
37.5
50
ns
ns
Four Activate Window
for 2KB page size
products
CAS to CAS command
delay
tCCD
2
2
tCK
Write recovery time
tWR
15
x
x
15
x
x
ns
Auto precharge write
recovery + precharge
time
tDAL
WR+tR
P
WR+tR
P
tCK
Internal write to read
command delay
tWTR
tRTP
7.5
7.5
x
10
x
ns
ns
Internal read to
precharge command
delay
7.5
Exit self refresh to a
non-read command
tXSNR
tXSRD
tXP
tRFC +
10
tRFC +
10
ns
Exit self refresh to a
read command
200
2
200
2
tCK
tCK
Exit precharge power
down to any non-read
command
x
x
x
x
Exit active power down
to read command
tXARD
2
2
tCK
tCK
Exit active power down
to read command
(slow exit, lower
power)
tXARDS
6 - AL
6 - AL
tCKE
CKE minimum pulse
width
(high and low pulse
width)
tCK
3
2
3
2
tAOND
tAON
ODT turn-on delay
ODT turn-on
2
2
tCK
ns
tAC(mi
n)
tAC(m
ax)+1
tAC(mi
n)
tAC(ma
x)+1
tAONPD
ODT turn-on(Power-
Down mode)
tAC(mi
n)+2
2tCK+t
AC(ma
x)+1
tAC(mi
n)+2
2tCK+t
AC
(max)+
1
ns
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
tCK
ns
tAC(min)
tAC(ma
x)+ 0.6
tAC(max
)+ 0.6
tAC(mi
n)
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Symbol
Units
Parameter
DDR2-533
DDR2-400
min
max
min
max
tAOFPD
ODT turn-off (Power-
Down mode)
tAC(mi
n)+2
2.5tCK
+
tAC(mi
n)+2
2.5tCK
+
ns
tAC(m
ax)+1
tAC(ma
x)+1
ODT to power down
entry latency
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
ODT power down exit
latency
OCD drive mode
output delay
12
12
Minimum time clocks
remains ON after CKE
asynchronously drops
LOW
tDelay
tIS+tCK
+tIH
tIS+tCK
+tIH
ns
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Physical Dimensions: 64Mbx8 based 64Mx72 Module(1 Rank)
M393T6553CZ0
Units : Millimeters
2.70
133.35
30.00
PLL
1.0 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QC
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Physical Dimensions: 64Mbx8/128Mbx4 based 128Mx72 Module(2/1 Ranks)
M393T2953CZ0 / M393T2950CZ0
Units : Millimeters
133.35
4.00
30.00
PLL
1.0 max
1.7 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 128M x4/64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T5104/083QC
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Physical Dimensions: 128Mbx4 based 256Mx72 Module(2 Ranks)
M393T5750CZ0
Units : Millimeters
133.35
4.00
PLL
30.00
1.0 max
1.7 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 128M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51043QC
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
240 Pin DDR2 Registered DIMM Clock Topology
0ns (nominal)
PLL
DDR2 SDRAM
120 ohms
OUT1
CK0
120 ohms
IN
DDR2 SDRAM
Reg.A
CK0
120 ohms
OUTN
120 ohms
C
C
Feedback In
Feedback Out
Reg.B
Note:
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Rev. 1.1 Mar. 2005
DDR2 SDRAM
512MB, 1GB, 2GB Registered DIMMs
Revision History
Revision 1.0 (Feb. 2005)
- Initial Release
Revision 1.1 (Mar. 2005)
- Changed IDD0/IDD3N/IDD3P current values.
Rev. 1.1 Mar. 2005
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