M393T2953EZA-CCC_技术文档

Preliminary

RDIMM

DDR2 SDRAM

DDR2 Registered SDRAM MODULE

240pin Registered Module based on 512Mb E-die

72-bit ECC

60FBGA with Pb-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Revision History

Revision

Month

Year

History

0.1

Apr.

2006

- Initial Release

2 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

DDR2 Registered DIMM Ordering Information

Part Number

Density Organization

Component Composition

64Mx8(K4T51083QE)*9EA

64Mx8(K4T51083QE)*18EA

128Mx4(K4T51043QE)*18EA

128Mx4(K4T51043QE)*36EA

Number of Rank Parity Register

Height

M393T6553EZ3-CD5/CC

512MB

1GB

64Mx72

1

2

1

2

X

O

X

30.00mm

18.30mm

30.00mm

18.30mm

30.00mm

18.30mm

30.00mm

M393T6553EZA-CE7/E6/D5/CC

M392T6553EZA-CE7/E6/D5/CC

M393T2953EZ3-CD5/CC

64Mx72

128Mx72

256Mx72

M393T2953EZA-CE7/E6/D5/CC

M392T2953EZA-CE7/E6/D5/CC

M393T2950EZ3-CD5/CC

1GB

O

X

1GB

M393T2950EZA-CE7/E6/D5/CC

M392T2950EZA-CE7/E6/D5/CC

M393T5750EZ3-CD5/CC

1GB

O

X

1GB

2GB

M393T5750EZA-CE7/E6/D5/CC

2GB

O

Note: “Z” of Part number(11th digit) stand for Lead-free products.

Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.

Note: "A" of Part number(12th digit) stand for Parity Register products.

Note: "92" of Part number(3~4th digit) stand for VLP(Very Low Profile) Register products.

Features

•

Performance range

E7(DDR2-800)

E6(DDR2-667)

D5(DDR2-533)

CC(DDR2-400)

Unit

Mbps

CK

Speed@CL3

Speed@CL4

Speed@CL5

CL-tRCD-tRP

400

533

400

533

400

533

-

400

-

800

667

5-5-5

4-4-4

3-3-3

•

JEDEC standard 1.8V ± 0.1V Power Supply

_DDQ= 1.8V ± 0.1V

V

•

200 MHz f_CKfor 400Mb/sec/pin, 267MHz f_CKfor 533Mb/sec/pin, 333MHz f_CKfor 667Mb/sec/pin, 400MHz f_CKfor 800Mb/sec/pin

•

4 Banks

Posted CAS

Programmable CAS Latency: 3, 4, 5

Programmable Additive Latency: 0, 1 , 2 , 3 and 4

Write Latency(WL) = Read Latency(RL) -1

Burst Length: 4 , 8(Interleave/nibble sequential)

Programmable Sequential / Interleave Burst Mode

Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

Off-Chip Driver(OCD) Impedance Adjustment

On Die Termination with selectable values(50/75/150 ohms or disable)

PASR(Partial Array Self Refresh)

Average Refresh Period 7.8us at lower than a T_CASE85°C, 3.9us at 85°C < T_CASE< 95 °C

- support High Temperature Self-Refresh rate enable feature

Serial presence detect with EEPROM

•

DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8

•

All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

Address Configuration

Organization

Row Address

A0-A13

Column Address

A0-A9,A11

A0-A9

Bank Address

BA0-BA1

Auto Precharge

128Mx4(512Mb) based Module

64Mx8(512Mb) based Module

A10

A0-A13

BA0-BA1

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Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Pin Configurations (Front side/Back side)

1

Front

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

Back

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

Front

DQ19

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

Back

61

Front

A4

181

182

183

184

Back

91

Front

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

Back

DM5/DQS14

V

REF

SS

DDQ

SS

V

2

DQ4

DQ5

DQ28

DQ29

62

A3

A1

92

DQS5

NC/DQS14

SS

DDQ

V

3

DQ0

DQ1

DQ24

DQ25

63

A2

93

SS

V

4

64

94

DQ46

DQ47

SS

DD

SS

V

5

DM0/DQS9

NC/DQS9

DM3/DQS12

NC/DQS12

KEY

95

DQ42

DQ43

SS

V

6

DQS0

DQS3

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

CK0

96

SS

V

7

97

DQ52

DQ53

SS

V

8

DQ6

DQ7

DQ30

DQ31

98

DQ48

DQ49

SS

DD

V

9

DQ2

DQ3

DQ26

DQ27

NC/Par_In

A0

99

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

100

101

102

103

104

105

106

107

108

109

110

111

112

113

RFU

SS

DD

SS

V

DQ12

DQ13

CB4

CB5

A10/AP

BA0

BA1

SA2

SS

V

DQ8

DQ9

CB0

CB1

NC(TEST)

DDQ

SS

V

RAS

S0

DM6/DQS15

NC/DQS15

SS

DDQ

SS

V

DM1/DQS10

NC/DQS10

DM8/DQS17

NC/DQS17

WE

DQS6

SS

V

DQS1

DQS8

CAS

DDQ

SS

V

ODT0

A13

DQ54

DQ55

SS

DDQ

SS

4

V

RFU

CB6

CB7

DQ50

DQ51

SS

S1

V

RESET

NC

CB2

CB3

ODT1

DD

SS

V

DQ60

DQ61

SS

DDQ

SS

V

DQ14

DQ15

DQ36

DQ37

DQ56

DQ57

SS

DDQ

SS

4

V

DQ10

DQ11

DQ32

DQ33

DDQ

CKE1

SS

V

CKE0

DM7/DQS16

NC/DQS16

SS

DD

SS

V

DQ20

DQ21

DM4/DQS13

NC/DQS13

DQS7

NC

SS

DD

SS

V

24

25

26

27

28

29

30

DQ16

DQ17

144

145

146

147

148

149

150

54

55

56

57

58

59

60

NC

174

175

176

177

178

179

180

83

84

85

86

87

88

89

90

DQS4

203

204

205

206

207

208

209

210

114

115

116

117

118

119

120

234

235

236

237

238

239

240

SS

V

NC/Err_Out

DQ62

DQ63

SS

DDQ

SS

V

DM2/DQS11

NC/DQS11

A12

A9

DQ38

DQ39

DQ58

DQ59

SS

DDQ

SS

V

DQS2

A11

A7

DQ34

DQ35

SS

V

VDDSPD

SA0

SS

DD

SS

V

DQ22

DQ23

A8

A6

DQ44

DQ45

SDA

SCL

SS

DD

SS

DQ18

A5

DQ40

DQ41

SA1

V

SS

NC = No Connect, RFU = Reserved for Future Use

1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.

2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)

3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.

4. CKE1,S1 Pin is used for double side Registered DIMM.

Pin Description

Pin Name

CK0

Description

Pin Name

Description

Clock Inputs, positive line

Clock inputs, negative line

Clock Enables

ODT0~ODT1

DQ0~DQ63

CB0~CB7

On die termination

Data Input/Output

CK0

CKE0, CKE1

RAS

Data check bits Input/Output

Data strobes

Row Address Strobe

Column Address Strobe

Write Enable

DQS0~DQS8

CAS

Data strobes, negative line

WE

DM(0~8),DQS(9~17) Data Masks / Data strobes (Read)

S0, S1

Chip Selects

DQS9~DQS17

Data strobes (Read), negative line

Reserved for Future Use

No Connect

A0~A9, A11~A13

A10/AP

Address Inputs

RFU

NC

Address Input/Autoprecharge

Memory bus test tool

(Not Connect and Not Useable on DIMMs)

BA0, BA1

DDR2 SDRAM Bank Address

TEST

SCL

Serial Presence Detect (SPD) Clock Input

SPD Data Input/Output

V_DD

Core Power

I/O Power

SDA

V_DDQ

V_SS

SA0~SA2

Par_In

Err_Out

RESET

SPD address

Ground

Parity bit for the Address and Control bus

V_REF

Input/Output Reference

SPD Power

Parity error found in the Address and Control bus V_DDSPD

Register and PLL control pin

*The VDD and VDDQ pins are tied to the single power-plane on PCB.

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Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Input/Output Functional Description

Symbol

Type

Input

Function

CK0

Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.

Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.

CK0

Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low

initiates the Power Down mode, or the Self Refresh mode.

CKE0~CKE1

Input

Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled,

new commands are ignored but previous operations continue.

These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are

high.

S0~S1

Input

ODT0~ODT1

Input

I/O bus impedance control signals.

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the

SDRAM.

RAS, CAS, WE

V_REF

V_DDQ

Supply

Input

Reference voltage for SSTL_18 inputs

Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity

Selects which SDRAM bank of four is activated.

BA0~BA1

During a Bank Activate command cycle, Address defines the row address.

During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is

used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected

and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command

cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be pre-

charged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.

A0~A9,A10/AP

A11~A13

Input

DQ0~63,

CB0~CB7

In/Out

Input

Data and Check Bit Input/Output pins

Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once

the write command is registered into the SDRAM.

DM0~DM8

V_DD, V_SS

DQS0~DQS17

SA0~SA2

Supply

In/Out

Input

Power and ground for the DDR SDRAM input buffers and core logic

Positive line of the differential data strobe for input and output data.

Negative line of the differential data strobe for input and output data.

These signals are tied at the system planar to either V_SSor V_DDSPDto configure the serial SPD EEPROM address range.

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA

bus line to V_DDSPDto act as a pullup.

SDA

SCL

In/Out

Input

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time

to V_DDSPDto act as a pullup.

Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6

Volt operation).

V_DDSPD

Supply

The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs

will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-

nized with the input clock )

RESET

Input

Par_In

Err_Out

TEST

Input

Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)

Parity error found in the Address and Control bus

In/Out

Used by memory bus analysis tools (unused on memory DIMMs)

5 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Functional Block Diagram

512MB, 64Mx72 Module (M393T6553EZ3 / M393T6553EZA / M392T6553EZA)

(populated as 1 rank of x8 DDR2 SDRAMs)

RS0

DQS0

DQS4

DQS0

DQS4

DM0/DQS9

NC/DQS9

DM4/DQS13

NC/DQS13

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D4

DQS1

DQS5

DQS1

DQS5

DM1/DQS10

NC/DQS10

DM5/DQS14

NC/DQS14

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 0

I/O 1

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS2

DQS6

DQS2

DQS6

DM2/DQS11

NC/DQS11

DM6/DQS15

NC/DQS15

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D6

DQS3

DQS7

DQS3

DQS7

DM3/DQS12

NC/DQS12

DM7/DQS16

NC/DQS16

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D7

V

Serial PD

D0 - D8

DDSPD

DQS8

DM8/DQS17

NC/DQS17

Serial PD

/V

DD DDQ

SCL

SDA

VREF

DM/ NU/ CS DQS DQS

RDQS RDQS

I/O 0

WP A0 A1 A2

SA0 SA1 SA2

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

V

SS

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D8

Signals for Address and Command Parity Function (M393T6553CZA)

Register

V

C0

C1

SS

1:1

PPO

PAR_IN

100K ohms

PAR_IN

S0*

R

E

G

I

S

T

E

R

RSO-> CS : DDR2 SDRAMs D0-D8

QERR

Err_Out

BA0-BA1

A0-A13

RAS

CAS

WE

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8

RRAS -> RAS : DDR2 SDRAMs D0-D8

RCAS -> CAS : DDR2 SDRAMs D0-D8

RWE -> WE : DDR2 SDRAMs D0-D8

The resistors on Par_In, A13, A14, A15, BA2 and the

signal line of Err_Out refer to the section: "Register

Options for Unused Address inputs"

CKE0

ODT0

RCKE0 -> CKE : DDR2 SDRAMs D0-D8

RODT0 -> ODT0 : DDR2 SDRAMs D0-D8

RST

RESET

* S0 connects to DCS and VDD connects to CSR on the register. S1, CKE1 and ODT1 are NC.

PCK7

CK0

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8

PCK7 -> CK : Register

P

L

Notes :

CK0

1. DQ-to-I/O wiring may be changed within a byte.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. Unless otherwise noted, resister values are 22 Ohms

OE

RESET

6 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

1GB, 128Mx72 Module (M393T2953EZ3 / M393T2953EZA / M392T2953EZA)

(populated as 2 rank of x8 DDR2 SDRAMs)

RS1

RS0

DQS0

DQS4

DQS0

DQS4

DM0/DQS9

NC/DQS9

DM4/DQS13

NC/DQS13

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D9

D4

D13

DQS1

DQS5

DQS1

DQS5

DM1/DQS10

NC/DQS10

DM5/DQS14

NC/DQS14

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 0

I/O 1

I/O 0

I/O 1

I/O 0

I/O 1

D1

D10

D5

D14

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS2

DQS6

DQS2

DQS6

DM2/DQS11

NC/DQS11

DM6/DQS15

NC/DQS15

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D11

D6

D15

DQS3

DQS7

DQS3

DQS7

DM3/DQS12

NC/DQS12

DM7/DQS16

NC/DQS16

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D12

D7

D16

DQS8

DM8/DQS17

NC/DQS17

V

Serial PD

D0 - D17

DDSPD

Serial PD

/V

DD DDQ

SCL

SDA

DM/ NU/ CS DQS DQS

RDQS RDQS

I/O 0

DM/ NU/ CS DQS DQS

RDQS RDQS

I/O 0

WP A0 A1 A2

SA0 SA1 SA2

VREF

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D8

D17

V

SS

Signals for Address and Command Parity Function (M393T2953CZA)

Register A

Register B

V

C0

C1

V

C0

C1

SS

DD

S0*

S1*

RSO-> CS : DDR2 SDRAMs D0-D8

RS1-> CS : DDR2 SDRAMs D9-D17

DD

PPO

1:2

PPO

PAR_IN

BA0-BA1

A0-A13

RAS

CAS

WE

CKE0

CKE1

ODT0

ODT1

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17

RRAS -> RAS : DDR2 SDRAMs D0-D17

RCAS -> CAS : DDR2 SDRAMs D0-D17

RWE -> WE : DDR2 SDRAMs D0-D17

RCKE0 -> CKE : DDR2 SDRAMs D0-D8

RCKE1 -> CKE : DDR2 SDRAMs D9-D17

RODT0 -> ODT0 : DDR2 SDRAMs D0-D8

R

E

G

I

S

T

E

R

QERR

Err_Out

QERR

100K ohms

The resistors on Par_In, A13, A14, A15, BA2 and the

signal line of Err_Out refer to the section: "Register

Options for Unused Address inputs"

CK0

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17

RODT1 -> ODT1 : DDR2 SDRAMs D9-D17

P

L

RST

RESET**

PCK7**

CK0

PCK7 -> CK : Register

PCK7**

OE

RESET

* S0 connects to DCS and S1 connects to CSR on a Register,

S1 connects to DCS and S0 connects to CSR on another Register.

Notes :

1. DQ-to-I/O wiring may be changed per nibble.

2. Unless otherwise noted, resister values are 22 Ohms

3. RS0 and RS1 alternate between the back and front sides of the DIMM

** RESET, PCK7 and PCK7 connects to both Registers.

Other signals connect to one of two Registers.

7 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

1GB, 128Mx72 Module (M393T2950EZ3 / M393T2950EZA / M392T2950EZA)

(populated as 1 rank of x4 DDR2 SDRAMs)

VSS

RS0

DQS0

DM0/DQS9

NC/DQS9

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

DQ0

DQ4

DQ5

DQ6

DQ7

DQ1

DQ2

DQ3

D0

D9

DQS1

DM1/DQS10

NC/DQS10

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ13

DQ14

DQ15

D1

D10

DQS2

DM2/DQS11

NC/DQS11

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ17

DQ18

DQ19

D2

D11

DQS3

DM3/DQS12

NC/DQS12

DM

CS DQS DQS

DM

CS DQS DQS

Serial PD

DQ24

DQ28

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ25

DQ26

DQ27

DQ29

DQ30

DQ31

D3

D12

SCL

SDA

WP A0 A1 A2

DQS4

DM4/DQS13

NC/DQS13

SA0 SA1 SA2

DM

CS DQS DQS

DM

CS DQS DQS

DQ32

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ33

DQ34

DQ35

D4

D13

DQS5

DM5/DQS14

NC/DQS14

V

Serial PD

D0 - D17

DDSPD

DM

CS DQS DQS

DM

CS DQS DQS

/V

DD DDQ

DQ40

DQ44

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ41

DQ42

DQ43

DQ45

DQ46

DQ47

D5

D14

VREF

V

DQS6

DM6/DQS15

NC/DQS15

SS

DM

CS DQS DQS

DM

CS DQS DQS

DQ48

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ49

DQ50

DQ51

D6

D15

DQS7

DM7DQS16

NC/DQS16

DM

CS DQS DQS

DM

CS DQS DQS

DQ56

DQ60

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ57

DQ58

DQ59

DQ61

DQ62

DQ63

D7

D16

DQS8

DM8/DQS17

NC/DQS17

DM

CS DQS DQS

DM

CS DQS DQS

CB0

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

CB1

CB2

CB3

D8

D17

1:2

Signals for Address and Command Parity Function (M393T2950CZA)

R

E

G

I

S

T

E

R

S0*

RSO-> CS : DDR2 SDRAMs D0-D17

BA0-BA1

A0-A13

RAS

CAS

WE

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17

RRAS -> RAS : DDR2 SDRAMs D0-D17

RCAS -> CAS : DDR2 SDRAMs D0-D17

RWE -> WE : DDR2 SDRAMs D0-D17

Register A

Register B

V

C0

C1

V

C0

C1

SS

DD

PPO

PAR_IN

100K ohms

PAR_IN

QERR

Err_Out

QERR

CKE0

ODT0

RCKE0 -> CKE : DDR2 SDRAMs D0-D17

RODT0 -> ODT0 : DDR2 SDRAMs D0-D17

The resistors on Par_In, A13, A14, A15, BA2 and the

signal line of Err_Out refer to the section: "Register

Options for Unused Address inputs"

RST

RESET**

PCK7**

Notes :

1. DQ-to-I/O wiring may be changed per nibble.

2. Unless otherwise noted, resister values are 22 Ohms

PCK7**

CK0

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8

* S0 connects to DCS of Register1 and CSR of Register2. CSR of

register 1 and DCS of register 2 connects to VDD.

P

L

CK0

** RESET, PCK7 and PCK7 connects to both Registers. Other sig-

nals connect to one of two Registers. S1, CKE1 and ODT1 are NC.

PCK7 -> CK : Register

OE

RESET

8 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

2GB, 256Mx72 Module (M393T5750EZ3 / M393T5750EZA)

(populated as 2 rank of x4 DDR2 SDRAMs)

VSS

RS1

RS0

DQS0

DM0/DQS9

NC/DQS9

Serial PD

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

DM/ CS DQS DQS

I/O 0

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

DQ0

DQ4

DQ5

DQ6

DQ7

SCL

SDA

DQ1

DQ2

DQ3

I/O 1

I/O 2

I/O 3

D0

D18

D9

D27

WP A0 A1 A2

DQS1

DM1/DQS10

NC/DQS10

SA0 SA1 SA2

Serial PD

V

DDSPD

DM

CS DQS DQS

DM/ CS DQS DQS

I/O 0

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

/V

D0 - D35

DQ13

DQ14

DQ15

I/O 1

I/O 2

I/O 3

D1

D19

D10

D28

DD DDQ

VREF

DQS2

DM2/DQS11

NC/DQS11

V

SS

DM

CS DQS DQS

DM/ CS DQS DQS

I/O 0

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ17

DQ18

DQ19

I/O 1

I/O 2

I/O 3

D2

D20

D11

D29

Signals for Address and Command

Parity Function (M393T5750CZA)

DQS3

DM3/DQS12

NC/DQS12

Register A1

PPO

V

C0

C1

SS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ28

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DD

DQ25

DQ26

DQ27

DQ29

DQ30

DQ31

D3

D21

D12

D30

PAR_IN

QERR

DQS4

DM4/DQS13

NC/DQS13

Register B1

V

C0

C1

DD

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ32

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

PAR_IN

PPO

DQ33

DQ34

DQ35

D4

D22

D13

D31

Err_Out

PAR_IN

QERR

DQS5

DM5/DQS14

NC/DQS14

100K ohms

Register A2

V

C0

C1

SS

DD

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ40

DQ44

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

PPO

PAR_IN

DQ41

DQ42

DQ43

DQ45

DQ46

DQ47

D5

D23

D14

D32

QERR

DQS6

DM6/DQS15

NC/DQS15

Register B2

V

C0

C1

DD

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ48

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

PPO

PAR_IN

DQ49

DQ50

DQ51

D6

D24

D15

D33

QERR

DQS7

DM7DQS16

NC/DQS16

Register A1 and A2 share the a part of Add/

Cmd input signal set.

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ56

DQ60

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

Register B1 and B2 share the rest part of Add/

Cmd input signal set.

DQ57

DQ58

DQ59

DQ61

DQ62

DQ63

D7

D25

D16

D34

DQS8

DM8/DQS17

NC/DQS17

The resistors on Par_In, A13, A14, A15, BA2

and the signal line of Err_Out refer to the sec-

tion: "Register Options for Unused Address

inputs"

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

CB0

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

CB1

CB2

CB3

D8

D26

D17

D35

S0*

RSO-> CS : DDR2 SDRAMs D0-D17

RS1-> CS : DDR2 SDRAMs D18-D35

RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35

RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35

RRAS -> RAS : DDR2 SDRAMs D0-D35

RCAS -> CAS : DDR2 SDRAMs D0-D35

RWE -> WE : DDR2 SDRAMs D0-D35

RCKE0 -> CKE : DDR2 SDRAMs D0-D17

RCKE1 -> CKE : DDR2 SDRAMs D18-D35

RODT0 -> ODT0 : DDR2 SDRAMs D0-D17

RODT1 -> ODT1 : DDR2 SDRAMs D18-D35

S1*

1:2

R

E

G

I

S

T

E

R

CK0

PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35

PCK7 -> CK : Register

BA0-BA1

A0-A13

RAS

CAS

WE

CKE0

CKE1

ODT0

ODT1

P

L

OE

RESET

RST

RESET**

PCK7**

* S0 connects to DCS and S1 connects to CSR on a pair of Registers,

S1 connects to DCS and S0 connects to CSR on another pair of Registers.

** RESET, PCK7 and PCK7 connects to all Registers.

Other signals connect to one pair of four Registers.

9 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Absolute Maximum DC Ratings

Symbol

Parameter

Rating

Units

V

Notes

Voltage on V_DDpin relative to V_SS

V_DD

- 1.0 V ~ 2.3 V

- 0.5 V ~ 2.3 V

-55 to +100

1

Voltage on V_DDQpin relative to V_SS

Voltage on V_DDLpin relative to V_SS

Voltage on any pin relative to V_SS

Storage Temperature

V_DDQ

V_DDL

_IN,V_OUT

T_STG

Note :

V

1

V

1

°C

1, 2

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2

standard.

AC & DC Operating Conditions

Recommended DC Operating Conditions (SSTL - 1.8)

Rating

Symbol

Parameter

Units

Notes

Min.

1.7

Typ.

1.8

Max.

1.9

V_DD

V_DDL

V_DDQ

V_REF

V_TT

Supply Voltage

V

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

1.8

1.9

4

1.7

1.8

1.9

V

0.49*V_DDQ

V_REF-0.04

0.50*V_DDQ

V_REF

0.51*V_DDQ

V_REF+0.04

mV

V

1,2

3

Note : There is no specific device V_DDsupply voltage requirement for SSTL-1.8 compliance. However under all conditions V_DDQmust be less than or equal

to V_DD

1. The value of V_REFmay be selected by the user to provide optimum noise margin in the system. Typically the value of V_REFis expected to be about 0.5

.

x V_DDQof the transmitting device and V_REFis expected to track variations in V_DDQ

2. Peak to peak AC noise on V_REFmay not exceed +/-2% V_REF(DC).

3. V_TTof transmitting device must track V_REFof receiving device.

.

4. AC parameters are measured with V_DD, V_DDQand V_DDLtied together.

10 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Operating Temperature Condition

Symbol

Parameter

Rating

Units

Notes

TOPER

Operating Temperature

0 to 95

°C

1, 2

Note :

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2

standard.

2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self

refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

Input DC Logic Level

Symbol

Parameter

Min.

V_REF+ 0.125

- 0.3

Max.

Units

Notes

V_IH(DC)

DC input logic high

DC input logic low

V_DDQ+ 0.3

V_REF- 0.125

V

V_IL(DC)

Input AC Logic Level

DDR2-400, DDR2-533

DDR2-667, DDR2-800

Symbol

Parameter

Units

Min.

Max.

Min.

V_REF+ 0.200

Max.

V_IH(AC)

AC input logic high

AC input logic low

V_REF+ 0.250

-

V

V_IL(AC)

V_REF- 0.250

V_REF- 0.200

AC Input Test Conditions

Symbol

Condition

Value

Units

Notes

V_REF

V_SWING(MAX)

SLEW

Input reference voltage

0.5 * V_DDQ

1.0

V

1

Input signal maximum peak to peak swing

Input signal minimum slew rate

1.0

V/ns

2, 3

Notes:

1. Input waveform timing is referenced to the input signal crossing through the V_IH/IL(AC) level applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from V_REFto V_IH(AC) min for rising edges and the range from V_REFto V_IL(AC)

max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from V_IL(AC) to V_IH(AC) on the positive transitions and V_IH(AC) to V_IL(AC) on the negative

transitions.

V

DDQ

(AC) min

IH

(DC) min

V

SWING(MAX)

REF

(DC) max

IL

(AC) max

SS

delta TF

V

delta TR

Rising Slew =

- V (AC) max

IL

V

(AC) min - V

delta TR

REF

IH

REF

Falling Slew =

delta TF

< AC Input Test Signal Waveform >

11 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

IDD Specification Parameters Definition

(IDD values are for full operating range of Voltage and Temperature)

Symbol Proposed Conditions

Units

Notes

Operating one bank active-precharge current;

t

IDD0

IDD1

mA

CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating one bank active-read-precharge current;

t

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =

mA

t

RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern

is same as IDD4W

Precharge power-down current;

t

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

t

mA

All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

Precharge quiet standby current;

t

All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

Precharge standby current;

t

All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Active power-down current;

mA

Fast PDN Exit MRS(12) = 0mA

t

All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

Slow PDN Exit MRS(12) = 1mA

Active standby current;

t

mA

All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst write current;

t

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP =

IDD4W

IDD4R

t

RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs

are SWITCHING

Operating burst read current;

t

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-

mA

t

max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-

ING; Data pattern is same as IDD4W

Burst auto refresh current;

t

IDD5B

IDD6

CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current;

CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Normal

mA

Low Power

Operating bank interleave read current;

t

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC =

IDD7

t

mA

RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid

commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow-

ing page for detailed timing conditions

12 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Operating Current Table(1-1) (TA=0^oC, VDD= 1.9V)

M393T6553EZ3 / M393T6553EZA / M392T6553EZA : 512MB(64Mx8 *9) Module

Symbol

IDD0

E7(800@CL=5)

TBD

E6(667@CL=5)

TBD

D5(533@CL=4)

TBD

CC(400@CL=3)

TBD

Unit

mA

Notes

IDD1

TBD

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

IDD6*

TBD

IDD7

TBD

*/IDD6 = DRAM current + standby current of PLL and Register

** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M393T2953EZ3 / M393T2953EZA / M392T2953EZA : 1GB(64Mx8 *18) Module

Symbol

IDD0

E7(800@CL=5)

TBD

E6(667@CL=5)

TBD

D5(533@CL=4)

TBD

CC(400@CL=3)

TBD

Unit

mA

Notes

IDD1

TBD

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

IDD6*

TBD

IDD7

TBD

*/IDD6 = DRAM current + standby current of PLL and Register

** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

13 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Operating Current Table(1-2) (TA=0^oC, VDD= 1.9V)

M393T2950EZ3 / M393T2950EZA / M392T2950EZA : 1GB(128Mx4 *18) Module

Symbol

IDD0

E7(800@CL=5)

TBD

E6(667@CL=5)

TBD

D5(533@CL=4)

TBD

CC(400@CL=3)

TBD

Unit

mA

Notes

IDD1

TBD

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

IDD6*

TBD

IDD7

TBD

*/IDD6 = DRAM current + standby current of PLL and Register

** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M393T5750CZ3 / M393T5750CZA : 2GB(128Mx4 *36) Module

Symbol

IDD0

E7(800@CL=5)

TBD

E6(667@CL=5)

TBD

D5(533@CL=4)

TBD

CC(400@CL=3)

TBD

Unit

mA

Notes

IDD1

TBD

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

IDD6*

TBD

IDD7

TBD

*/IDD6 = DRAM current + standby current of PLL and Register

** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

14 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

o

(VDD=1.8V, VDDQ=1.8V, TA=25 C)

Input/Output Capacitance

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

M393T6553EZ3

M393T6553EZA

M392T6553EZA

M393T2953EZ3

M393T2953EZA

M392T2953EZA

M393T2950EZ3

M393T2950EZA

M392T2950EZA

Symbol

Units

M393T5750EZ3

M393T5750EZA

Part-Number

Input capacitance, CK and CK

CCK

-

11

12

10

-

11

12

10

-

11

12

10

-

11

12

10

Input capacitance, CKE and CS

Input capacitance, Addr,RAS,CAS,WE

CI1

CI2

pF

Input/output capacitance, DQ, DM, DQS, DQS CIO

* DM is internally loaded to match DQ and DQS identically.

15 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Electrical Characteristics & AC Timing for DDR2-800/667/533/400

(0 °C < T

< 95 °C; V

= 1.8V + 0.1V; V = 1.8V + 0.1V)

OPER

DDQ DD

Refresh Parameters by Device Density

Parameter

Symbol

256Mb

512Mb

1Gb

2Gb

4Gb

Units

Refresh to active/Refresh command time

Average periodic refresh interval

tRFC

tREFI

75

105

127.5

195

327.5

ns

0 °C ≤ T_CASE≤ 85°C

85 °C < T_CASE≤ 95°C

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

µs

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed

Bin(CL - tRCD - tRP)

Parameter

tCK, CL=3

tCK, CL=4

tCK, CL=5

tRCD

DDR2-800(E7)

DDR2-667(E6)

DDR2-533(D5)

DDR2-400(CC)

3 - 3 - 3

5 - 5 - 5

4 - 4 - 4

Units

min

max

min

max

min

5

max

min

max

5

8

5

8

5

8

ns

3.75

2.5

8

3.75

3

8

3.75

15

8

5

8

-

8

-

12.5

57.5

45

-

15

60

45

-

15

55

40

-

tRP

-

15

-

tRC

60

-

tRAS

70000

45

70000

Timing Parameters by Speed Grade

DDR2-800

DDR2-667

DDR2-533

DDR2-400

Symbol

tAC

Units

Notes

Parameter

min

max

400

min

-450

-400

0.45

max

min

max

+500

+450

0.55

min

-600

-500

0.45

max

DQ output access time from CK/CK

DQS output access time from CK/CK

CK high-level width

- 400

- 350

0.45

+450

+400

0.55

-500

-450

0.45

+600

+500

0.55

ps

tDQSCK

tCH

350

0.55

tCK

CK low-level width

tCL

0.55

min(tCL,t

CH)

min(tCL,

tCH)

min(tCL,

tCH)

min(tCL,

tCH)

CK half period

tHP

x

ps

Clock cycle time, CL=x

tCK

2500

125

50

8000

3000

175

8000

3750

225

8000

5000

275

8000

ps

DQ and DM input hold time

DQ and DM input setup time

tDH(base)

tDS(base)

x

100

150

Control & Address input pulse width for

each input

tIPW

0.6

x

0.6

x

0.6

x

0.6

x

tCK

DQ and DM input pulse width for each input tDIPW

Data-out high-impedance time from CK/CK tHZ

0.35

x

0.35

x

0.35

x

0.35

x

tCK

ps

tAC max

DQS low-impedance time from CK/CK

DQ low-impedance time from CK/CK

tLZ(DQS)

tAC min tAC max tAC min tAC max

tAC min tAC max

ps

2* tAC

min

2*tAC

min

tLZ(DQ)

tAC max

tAC max 2* tACmin tAC max 2* tACmin tAC max

ps

DQS-DQ skew for DQS and associated DQ

signals

tDQSQ

tQHS

tQH

x

200

300

x

240

340

x

300

400

x

350

450

x

ps

DQ hold skew factor

tHP -

tQHS

tHP -

tQHS

tHP -

tQHS

tHP -

tQHS

DQ/DQS output hold time from DQS

First DQS latching transition to associated

clock edge

tDQSS

- 0.25

0.25

-0.25

0.25

-0.25

0.25

-0.25

0.25

tCK

16 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

DDR2-800

DDR2-667

DDR2-533

DDR2-400

Symbol

Units

Notes

Parameter

min

max

min

max

min

max

min

max

DQS input high pulse width

DQS input low pulse width

DQS falling edge to CK setup time

DQS falling edge hold time from CK

Mode register set command cycle time

Write postamble

tDQSH

tDQSL

tDSS

0.35

0.2

2

x

0.35

0.2

2

x

0.35

0.2

2

x

0.35

0.2

2

x

tCK

ps

x

tDSH

x

tMRD

x

tWPST

tWPRE

tIH(base)

tIS(base)

tRPRE

tRPST

0.4

0.35

250

175

0.9

0.4

0.6

x

0.4

0.35

275

200

0.9

0.4

0.6

x

0.4

0.35

375

250

0.9

0.4

0.6

x

0.4

0.35

475

350

0.9

0.4

0.6

x

Write preamble

Address and control input hold time

Address and control input setup time

Read preamble

x

ps

1.1

0.6

1.1

0.6

1.1

0.6

1.1

0.6

tCK

Read postamble

Active to active command period for 1KB

page size products

tRRD

7.5

10

35

45

x

7.5

10

x

7.5

10

x

7.5

10

x

ns

Active to active command period for 2KB

page size products

tRRD

tFAW

Four Activate Window for 1KB page size

products

37.5

50

37.5

50

37.5

50

Four Activate Window for 2KB page size

products

tFAW

CAS to CAS command delay

Write recovery time

tCCD

tWR

2

x

2

tCK

ns

15

x

15

x

15

x

Auto precharge write recovery + precharge

time

tDAL

WR+tRP

x

WR+tRP

tCK

Internal write to read command delay

tWTR

7.5

10

7.5

ns

Internal read to precharge command delay tRTP

Exit self refresh to a non-read command

Exit self refresh to a read command

tXSNR

tRFC + 10

200

tRFC + 10

200

tRFC + 10

200

tRFC + 10

200

ns

tXSRD

tXP

x

tCK

Exit precharge power down to any non-

read command

2

x

2

x

2

x

tCK

Exit active power down to read command tXARD

Exit active power down to read command

tXARDS

8 - AL

7 - AL

6 - AL

(slow exit, lower power)

CKE minimum pulse width

tCKE

tCK

3

2

3

2

3

2

3

2

(high and low pulse width)

ODT turn-on delay

ODT turn-on

tAOND

tAON

2

tCK

ns

tAC(max)

+ 0.7

tAC(max)

+0.7

tAC(max)

+1

tAC(max)

+1

tAC(min)

2tCK +

tAC(max)

+1

tAC(min)+

2

tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC

ODT turn-on(Power-Down mode)

tAONPD

ns

2

(max)+1

2

(max)+1

2

(max)+1

ODT turn-off delay

ODT turn-off

tAOFD

tAOF

2.5

tCK

ns

tAC(max)

+ 0.6

tAC(max)

+ 0.6

tAC(max)+

0.6

tAC(max)+

0.6

tAC(min)

2.5tCK +

tAC(max)

+1

2.5tCK+

tAC(max)

+1

2.5tCK+

tAC(max)

+1

tAC(min)+

2

tAC(min)+ 2.5tCK+tA tAC(min)+

tAC(min)+

2

ODT turn-off (Power-Down mode)

tAOFPD

ns

2

C(max)+1

2

ODT to power down entry latency

ODT power down exit latency

OCD drive mode output delay

tANPD

tAXPD

tOIT

3

8

0

3

8

0

3

8

0

3

8

0

tCK

ns

12

Minimum time clocks remains ON after

CKE asynchronously drops LOW

tIS+tCK

+tIH

tIS+tCK

+tIH

tIS+tCK

+tIH

tIS+tCK

+tIH

tDelay

ns

17 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

Physical Dimensions

64Mbx8 based 64Mx72 Module (1 Rank) - M393T6553EZ3 / M393T6553EZA

Units : Millimeters

2.70

133.35

30.00

PLL

1.0 max

1.27 ± 0.10

A

B

63.00

55.00

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 64M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QE

18 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

64Mbx8 based 64Mx72 Module (1 Rank) - M392T6553EZA

Units : Millimeters

133.35

128.95

2x 3.00 MIN

2.20

2.70

a

PLL

5.175

63

55

123

1.0 max

A

B

1.27 ± 0.10

133.35

5.00

4.00

0.80±0.05

0.20

4.00

3.80

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 64M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QE

19 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)

M393T2953EZ3 / M393T2953EZA / M393T2950EZ3 / M393T2950EZA

Units : Millimeters

133.35

4.00

30.00

PLL

1.0 max

1.7 max

1.27 ± 0.10

A

B

63.00

55.00

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QE / K4T51043QE

20 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks) - M392T2953EZA / M392T2950EZA

Units : Millimeters

133.35

128.95

2x 3.00 MIN

2.20

4.00

a

PLL

5.175

63

55

123

1.0 max

1.7 max

A

B

1.27 ± 0.10

PLL

133.35

5.00

4.00

0.80±0.05

0.20

4.00

3.80

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QE / K4T51043QE

21 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

128Mbx4 based 256Mx72 Module (2 Ranks) - M393T5750EZ3 / M393T5750EZA

Units : Millimeters

133.35

4.00

PLL

30.00

1.0 max

1.7 max

1.27 ± 0.10

A

B

63.00

55.00

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 128M x4 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51043QE

22 of 23

Rev. 0.1 April 2006

Preliminary

RDIMM

DDR2 SDRAM

240 Pin DDR2 Registered DIMM Clock Topology

0ns (nominal)

PLL

DDR2 SDRAM

120 ohms

OUT1

CK0

120 ohms

IN

DDR2 SDRAM

Reg.A

120 ohms

OUTN

120 ohms

C

Feedback In

Feedback Out

Reg.B

Note:

1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).

2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.

3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.

4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.

23 of 23

Rev. 0.1 April 2006


型号：	M393T2953EZA-CCC
厂家：	SAMSUNG
描述：	DDR DRAM Module, 128MX72, 0.6ns, CMOS, ROHS COMPLIANT, DIMM-240 动态存储器双倍数据速率
文件：	总23页 (文件大小：401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M393T2953EZA-CCC [SAMSUNG]

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