M393T3253GZ3-CCC [SAMSUNG]
DDR DRAM, 32MX72, 0.6ns, CMOS, ROHS COMPLIANT, DIMM-240;
| 型号： | M393T3253GZ3-CCC |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM, 32MX72, 0.6ns, CMOS, ROHS COMPLIANT, DIMM-240 动态存储器 双倍数据速率 |
| 文件： | 总19页 (文件大小：538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR2 SDRAM
RDIMM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 256Mb G-die
72-bit ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 July 2006
1 of 19
DDR2 SDRAM
RDIMM
Table of Contents
1.0 DDR2 Registered DIMM Ordering Information ......................................................................... 4
2.0 Features ....................................................................................................................................... 4
3.0 Address Configuration ............................................................................................................... 4
4.0 Pin Configurations (Front side/Back side) ............................................................................... 5
5.0 Pin Description ........................................................................................................................... 5
6.0 Input/Output Functional Description ........................................................................................ 6
7.0 Functional Block Diagram .......................................................................................................... 7
7.1 256MB, 32Mx72 Module(M393T3253GZ3)........................................................................................ 7
7.2 512MB, 64Mx72 Module( M393T6450GZ3) ...................................................................................... 8
8.0 Absolute Maximum DC Ratings ................................................................................................ 9
9.0 AC & DC Operating Conditions ................................................................................................ 9
9.1 Operating Temperature Condition .............................................................................................. 10
9.2 Input DC Logic Level ................................................................................................................ 10
9.3 Input AC Logic Level ................................................................................................................ 10
9.4 AC Input Test Conditions .......................................................................................................... 10
10.0 IDD Specification Parameters Definition ............................................................................. 11
11.0 Operating Current Table (TA=0oC, VDD= 1.9V) ................................................................... 12
11.1 M393T3253GZ3 : 256MB(32Mx8 *9) Module ............................................................................. 12
11.2 M393T3253GZ3 : 256MB(32Mx8 *9) Module............................................................................. 12
11.3 M393T6450GZ3 : 512MB(64Mx4 *18) Module ........................................................................... 13
11.4 M393T6450GZ3 : 512MB(64Mx4 *18) Module ........................................................................... 13
12.0 Input/Output Capacitance ...................................................................................................... 14
13.0 Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM ................................... 14
13.1 Refresh Parameters by Device Density ................................................................................... 14
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ......................................... 14
13.3 Timing Parameters by Speed Grade ....................................................................................... 15
14.0 Physical Dimensions: ............................................................................................................. 17
14.1 32Mbx8 based 32Mx72 Module(1 Rank) - M393T3253GZ3 .......................................................... 17
14.2 64Mbx4 based 64Mx72 Module(1 Rank) - M393T6450GZ3 .......................................................... 18
15.0 240 Pin DDR2 Registered DIMM Clock Topology ................................................................ 19
Rev. 1.0 July 2006
2 of 19
DDR2 SDRAM
RDIMM
Revision History
Revision
Month
Year
History
1.0
July
2006
- Initial Release
Rev. 1.0 July 2006
3 of 19
DDR2 SDRAM
RDIMM
1.0 DDR2 Registered DIMM Ordering Information
Part Number
Density Organization
Component Composition
32Mx8(K4T56083QG)*9EA
64Mx4(K4T56043QG)*18EA
Number of Rank
Parity Register
Height
30mm
30mm
M393T3253GZ3-CD5/CC
M393T6450GZ3-CD5/CC
256MB
512MB
32Mx72
64Mx72
1
1
X
X
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
2.0 Features
• Performance range
D5 (DDR2-533)
CC (DDR2-400)
Unit
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
-
400
400
-
4-4-4
3-3-3
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95°C
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA - 64Mx4/32Mx8
• All of Lead-free products are compliant for RoHS
Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
3.0 Address Configuration
Organization
64Mx4(256Mb) based Module
32Mx8(256Mb) based Module
Row Address
A0-A12
Column Address
A0-A9,A11
A0-A9
Bank Address
BA0-BA1
Auto Precharge
A10
A10
A0-A12
BA0-BA1
Rev. 1.0 July 2006
4 of 19
DDR2 SDRAM
RDIMM
4.0 Pin Configurations (Front side/Back side)
Pin
1
Front
VREF
VSS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Front
DQ19
VSS
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
Back
Pin
61
62
63
64
Front
A4
VDDQ
Pin
181
182
183
184
Back
Pin
91
92
93
94
95
96
97
98
Front
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
Back
DM5/DQS14
NC/DQS14
VSS
VSS
VSS
VDDQ
VSS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DQ4
DQ5
VSS
DQ28
DQ29
VSS
A3
A1
VDD
DQS5
DQS5
VSS
DQ0
DQ1
VSS
DQ24
DQ25
VSS
A2
VDD
DQ46
DQ47
VSS
DM0/DQS9
NC/DQS9
VSS
DM3/DQS12
NC/DQS12
VSS
KEY
DQ42
DQ43
VSS
VSS
VSS
VDD
DQS0
DQS0
VSS
DQS3
DQS3
VSS
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
CK0
CK0
VDD
DQ52
DQ53
VSS
DQ6
DQ7
VSS
DQ30
DQ31
VSS
DQ48
DQ49
VSS
DQ2
DQ3
VSS
DQ26
DQ27
VSS
NC/Par_In
VDD
A0
VDD
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
RFU
RFU
VSS
DQ12
DQ13
VSS
CB4
CB5
VSS
A10/AP
BA0
VDDQ
BA1
VDDQ
SA2
NC(TEST)
VSS
DQ8
DQ9
VSS
CB0
CB1
VSS
RAS
S0
VDDQ
DM6/DQS15
NC/DQS15
VSS
DM1/DQS10
NC/DQS10
VSS
DM8/DQS17
NC/DQS17
VSS
WE
CAS
VDDQ
S14
ODT1
VDDQ
VSS
DQS6
DQS6
VSS
DQS1
DQS1
VSS
DQS8
DQS8
VSS
ODT0
NC
VDD
DQ54
DQ55
VSS
RFU
RFU
VSS
CB6
CB7
VSS
VDDQ
CKE14
VDD
DQ50
DQ51
VSS
RESET
NC
VSS
CB2
CB3
VSS
VSS
DQ60
DQ61
VSS
DQ14
DQ15
VSS
DQ36
DQ37
VSS
DQ56
DQ57
VSS
VDDQ
DQ10
DQ11
VSS
DQ32
DQ33
VSS
CKE0
VDD
DM7/DQS16
NC/DQS16
VSS
DQ20
DQ21
VSS
DM4/DQS13
NC/DQS13
VSS
DQS7
DQS7
VSS
NC
24
25
26
27
28
29
30
DQ16
DQ17
VSS
144
145
146
147
148
149
150
54
55
56
57
58
59
60
NC
NC/Err_Out
VDDQ
174
175
176
177
178
179
180
83
84
85
86
87
88
89
90
DQS4
DQS4
VSS
203
204
205
206
207
208
209
210
114
115
116
117
118
119
120
234
235
236
237
238
239
240
NC
VDDQ
DQ62
DQ63
VSS
DM2/DQS11
NC/DQS11
VSS
A12
A9
VDD
DQ38
DQ39
VSS
DQ58
DQ59
VSS
DQS2
DQS2
VSS
A11
A7
VDD
A5
DQ34
DQ35
VSS
DQ40
DQ41
VDDSPD
SA0
SA1
DQ22
DQ23
A8
A6
DQ44
DQ45
VSS
SDA
SCL
DQ18
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The TEST pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are optional function to check address and command parity.
4. CKE1, S1 Pin is used for double side Registered DIMM.
5.0 Pin Description
Pin Name
Description
Pin Name
Description
CK0
Clock Input, positive line
Clock input, negative line
Clock Enables
ODT0~ODT1
DQ0~DQ63
CB0~CB7
On die termination Inputs
Data Input/Output
CK0
CKE0, CKE1
RAS
Data check bits Input/Output
Data strobes
Row Address Strobe
Column Address Strobe
DQS0~DQS8
DQS0~DQS8
CAS
Data strobes, negative line
DM(0~8),
DQS(9~17)
WE
Write Enable
Data Masks / Data strobes (Read)
S0, S1
Chip Selects
DQS9~DQS17
Data strobes (Read), negative line
Reserved for Future Use
No Connect
A0~A9, A11~A15
A10/AP
Address Inputs
RFU
NC
Address Input/Autoprecharge
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
BA0, BA1
DDR2 SDRAM Bank Address
TEST
SCL
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
VDD
Core Power
I/O Power
SDA
VDDQ
VSS
SA0~SA2
Par_In
Err_Out
RESET
SPD address Inputs
Ground
Parity bit for the Address and Control bus
VREF
Input/Output Reference
SPD Power
Parity error found on the Address and Control bus VDDSPD
Register and PLL control pin
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.0 July 2006
5 of 19
DDR2 SDRAM
RDIMM
6.0 Input/Output Functional Description
Symbol
Type
Input
Input
Function
CK0
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
CK0
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
Input
CKE0~CKE1
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-
abled, new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
Input
S0~S1
Input
Input
ODT0~ODT1
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
RAS, CAS, WE
VREF
VDDQ
Supply
Reference voltage for SSTL_18 inputs
Supply
Input
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of four is activated.
BA0~BA1
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to pre-
charge.
A0~A9,A10/AP
A11~A12
Input
DQ0~63,
In/Out
Input
Data and Check Bit Input/Output pins
CB0~CB7
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
DM0~DM8
VDD, VSS
Supply
In/Out
In/Out
Power and ground for the DDR SDRAM input buffers and core logic
DQS0~DQS17
DQS0~DQS17
SA0~SA2
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.
Input
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to VDDSPD to act as a pullup.
SDA
In/Out
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDDSPD to act as a pullup.
SCL
Input
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to
3.6 Volt operation).
VDDSPD
Supply
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-
nized with the input clock )
RESET
Input
Par_In
Err_Out
TEST
Input
Output
In/Out
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
Rev. 1.0 July 2006
6 of 19
DDR2 SDRAM
RDIMM
7.0 Functional Block Diagram
7.1 256MB, 32Mx72 Module(M393T3253GZ3) (populated as 1 rank of x8 DDR2 SDRAMs)
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 0
DQ9
I/O 1
I/O 1
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS6
DQS2
DQS6
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
DQS8
Notes :
DQS8
1. DQ-to-I/O wiring may be changed within a byte.
DM8/DQS17
NC/DQS17
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. Unless otherwise noted, resister values are 22 Ohms
DM/ NU/ CS DQS DQS
RDQS RDQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
V
V
Serial PD
DDSPD
Serial PD
/V
D0 - D8
D0 - D8
D0 - D8
DD DDQ
SCL
SDA
VREF
WP A0 A1 A2
SA0 SA1 SA2
V
SS
1:1
R
E
G
I
S0*
RSO-> CS : DDR2 SDRAMs D0-D8
BA0-BA1
A0-A12
RAS
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8
RA0-RA12 -> A0-A12 : DDR2 SDRAMs D0-D8
RRAS -> RAS : DDR2 SDRAMs D0-D8
RCAS -> CAS : DDR2 SDRAMs D0-D8
RWE -> WE : DDR2 SDRAMs D0-D8
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
P
L
L
CAS
S
T
CK0
WE
PCK7 -> CK : Register
CKE0
ODT0
E
R
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
OE
RESET
PCK7 -> CK : Register
RST
RESET
* S0 connects to DCS and VDD connects to CSR on the register.
S1, CKE1 and ODT1 are NC.
PCK7
PCK7
Rev. 1.0 July 2006
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DDR2 SDRAM
RDIMM
7.2 512MB, 64Mx72 Module( M393T6450GZ3) (populated as 1 rank of x4 DDR2 SDRAMs)
VSS
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D9
DQS1
DM1/DQS10
DQS1
NC/DQS10
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
D1
D10
DQ10
DQ11
DQS2
DM2/DQS11
DQS2
NC/DQS11
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
D2
D11
DQS3
DM3/DQS12
DQS3
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D12
DQS4
DM4/DQS13
DQS4
NC/DQS13
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D13
DQS5
DM5/DQS14
DQS5
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D14
DQS6
DM6/DQS15
DQS6
NC/DQS15
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D15
DQS7
DM7DQS16
DQS7
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D16
DQS8
DM8/DQS17
DQS8
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D17
Notes :
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resister values are 22 Ohms.
1:2
R
E
G
I
S0*
RSO-> CS : DDR2 SDRAMs D0-D17
BA0-BA1
A0-A12
RAS
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RA0-RA12 -> A0-A12 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
Serial PD
CAS
S
T
/V
DD DDQ
SCL
WE
CKE0
ODT0
RWE -> WE : DDR2 SDRAMs D0-D17
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
SDA
E
VREF
WP A0 A1 A2
SA0 SA1 SA2
R
V
SS
RST
RESET**
PCK7**
PCK7**
CK0
P
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
* S0 connects to DCS of Register1 and CSR of Register2.
L
CK0
CSR of register 1 and DCS of register 2 connects to VDD. S1, CKE1 and ODT1 are NC.
* RESET, PCK7 and PCK7 connect to both Registers.
L
PCK7 -> CK : Register
OE
RESET
PCK7 -> CK : Register
Other signals connect to one of two Registers.
Rev. 1.0 July 2006
8 of 19
DDR2 SDRAM
RDIMM
8.0 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
V
Notes
Voltage on VDD pin relative to VSS
VDD
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VDDQ
VDDL
V
V
1
V
IN, VOUT
TSTG
Note :
V
1
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC
standard spec.
9.0 AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Typ.
1.8
Symbol
Parameter
Units
Notes
Min.
1.7
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
Supply Voltage
V
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
1.7
1.8
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal
to VDD
.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Rev. 1.0 July 2006
9 of 19
DDR2 SDRAM
RDIMM
9.1 Operating Temperature Condition
Symbol
TOPER
Parameter
Operating Temperature
Rating
0 to 95
Units
°C
Notes
1, 2
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JEDEC standard spec.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to
self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
9.2 Input DC Logic Level
Symbol
VIH(DC)
VIL(DC)
Parameter
DC input logic high
DC input logic low
Min.
VREF + 0.125
- 0.3
Max.
VDDQ + 0.3
VREF - 0.125
Units
V
V
Notes
9.3 Input AC Logic Level
DDR2-400, DDR2-533
Symbol
Parameter
Units
Notes
Min.
Max.
VIH(AC)
VIL(AC)
AC input logic high
AC input logic low
VREF + 0.250
-
-
V
V
VREF - 0.250
9.4 AC Input Test Conditions
Symbol
Condition
Value
0.5 * VDDQ
1.0
Units
V
V
Notes
1
1
VREF
VSWING(MAX)
SLEW
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
V/ns
2, 3
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
(DC) min
IH
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
Rising Slew =
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
delta TF
< AC Input Test Signal Waveform >
Rev. 1.0 July 2006
10 of 19
DDR2 SDRAM
RDIMM
10.0 IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol Proposed Conditions
Units
Notes
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
IDD0
IDD1
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus
Slow PDN Exit MRS(12) = 1mA
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD4W
IDD4R
t
= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC =
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
mA
RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow-
ing page for detailed timing conditions
Rev. 1.0 July 2006
11 of 19
DDR2 SDRAM
RDIMM
11.0 Operating Current Table (TA=0oC, VDD= 1.9V)
11.1 M393T3253GZ3 : 256MB(32Mx8 *9) Module
D5
Symbol
CC
Unit
Notes
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
900
990
72
315
360
360
180
630
1,575
1,440
1,260
45
855
900
72
315
360
360
180
585
1,215
1,170
1,170
45
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
Normal
IDD7
2,250
2,160
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.2 M393T3253GZ3 : 256MB(32Mx8 *9) Module - considering Register and PLL current value
D5
CC
Symbol
Unit
Notes
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
1,310
1,450
472
705
720
1,175
1,270
432
635
660
670
490
915
1,525
1,520
1,480
45
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
750
570
1,030
1,955
1,870
1,690
45
IDD6*
Normal
IDD7
2,720
2,520
* IDD6 : Not count Register and PLL current
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 July 2006
12 of 19
DDR2 SDRAM
RDIMM
11.3 M393T6450GZ3 : 512MB(64Mx4 *18) Module
D5
Symbol
CC
Unit
Notes
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
1,710
1,800
144
630
720
1,800
1,980
144
630
720
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
720
360
720
360
1,170
2,340
2,340
2,340
90
1,260
2,880
2,880
2,520
90
IDD6*
Normal
IDD7
4,320
4,320
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.4 M393T6450GZ3 : 512MB(64Mx4 *18) Module - considering Register and PLL current value
D5
CC
Symbol
Unit
Notes
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
2,100
2,240
604
1,070
1,080
1,150
790
1,520
2,720
2,800
2,720
90
2,290
2,530
664
1,160
1,150
1,250
890
1,680
3,350
3,450
3,050
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
Normal
IDD7
4,870
5,210
* IDD6 : Not count Register and PLL current
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 July 2006
13 of 19
DDR2 SDRAM
RDIMM
(VDD=1.8V, VDDQ=1.8V, TA=25oC)
12.0 Input/Output Capacitance
Parameter
Part-Number
Min
Max
Min
Max
Symbol
Units
M393T3253GZ3
M393T6450GZ3
Input capacitance, CK and CK
CCK
CI1
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
Input capacitance, CKE and CS
pF
Input capacitance, Addr,RAS,CAS,WE
Input/output capacitance, DQ, DM, DQS, DQS
* DM is internally loaded to match DQ and DQS identically.
CI2
CIO
13.0 Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(TOPER ; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
13.1 Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
105
127.5
195
327.5
7.8
ns
0 °C ≤ TCASE ≤ 85°C
85 °C < TCASE ≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
Average periodic refresh interval
3.9
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-533(D5)
4 - 4 - 4
DDR2-400(CC)
3 - 3 - 3
Units
min
5
max
min
5
max
8
8
-
8
8
-
ns
ns
ns
ns
ns
ns
ns
3.75
-
5
-
15
15
60
45
15
15
55
40
tRP
tRC
tRAS
7000
7000
Rev. 1.0 July 2006
14 of 19
DDR2 SDRAM
RDIMM
13.3 Timing Parameters by Speed Grade
DDR2-533
DDR2-400
Parameter
Symbol
Units
Notes
min
-500
-450
0.45
0.45
max
+500
min
-600
-500
0.45
0.45
max
+600
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
tDQSCK
tCH
ps
ps
+450
+500
0.55
0.55
tCK
tCK
ps
CK low-level width
tCL
0.55
0.55
CK half period
tHP
min(tCL, tCH)
x
min(tCL, tCH)
x
Clock cycle time, CL=x
tCK
3750
225
8000
5000
275
8000
ps
DQ and DM input hold time
tDH
x
x
ps
DQ and DM input setup time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDS
100
x
150
x
ps
tIPW
0.6
x
0.6
x
tCK
tCK
ps
tDIPW
tHZ
0.35
x
x
0.35
x
x
tAC max
tAC max
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tAC min
2* tACmin
x
tAC max
tAC min
2* tACmin
x
tAC max
ps
tAC max
tAC max
ps
300
350
ps
x
400
x
450
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
tHP - tQHS
WL-0.25
0.35
0.35
0.2
x
tHP - tQHS
WL-0.25
0.35
0.35
0.2
x
ps
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH
WL+0.25
WL+0.25
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
x
x
x
x
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
x
x
0.2
x
0.2
x
2
x
2
x
0.4
0.6
x
0.4
0.6
x
Write preamble
0.35
375
0.35
475
Address and control input hold time
Address and control input setup time
Read preamble
x
x
tIS
250
x
350
x
ps
tRPRE
tRPST
0.9
1.1
0.6
0.9
1.1
0.6
tCK
tCK
Read postamble
0.4
0.4
Active to active command period for 1KB page size
products
tRRD
tRRD
7.5
10
x
x
7.5
10
x
x
ns
ns
Active to active command period for 2KB page size
products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
tFAW
tFAW
tCCD
tWR
37.5
37.5
ns
ns
50
2
50
2
15
tCK
ns
Write recovery time
15
x
x
x
x
x
x
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
tWR+tRP
7.5
tWR+tRP
10
tCK
ns
tWTR
tRTP
7.5
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
ns
tCK
Exit precharge power down to any non-read com-
mand
tXP
2
2
x
x
2
2
x
x
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
Exit active power down to read command
(Slow exit, Lower power)
6 - AL
6 - AL
CKE minimum pulse width
(high and low pulse width)
tCKE
3
3
tCK
Rev. 1.0 July 2006
15 of 19
DDR2 SDRAM
RDIMM
DDR2-533
DDR2-400
Parameter
Symbol
Units
Notes
min
2
max
2
min
2
max
2
ODT turn-on delay
ODT turn-on
tAOND
tAON
tCK
ns
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
2tCK+tAC(max
)+1
2tCK+tAC
(max)+1
ODT turn-on(Power-Down mode)
tAONPD
tAC(min)+2
tAC(min)+2
ns
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
tCK
ns
tAC(min)
tAC(max)+ 0.6
tAC(min)
tAC(max)+ 0.6
2.5tCK+
tAC(max)+1
2.5tCK+
tAC(max)+1
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
tAC(min)+2
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
tCK
tCK
ns
12
12
Minimum time clocks remains ON after CKE asyn-
chronously drops LOW
tDelay
tIS+tCK +tIH
tIS+tCK +tIH
ns
Rev. 1.0 July 2006
16 of 19
DDR2 SDRAM
RDIMM
14.0 Physical Dimensions:
14.1 32Mbx8 based 32Mx72 Module(1 Rank) - M393T3253GZ3
Units : Millimeters
2.70
133.35
30.00
PLL
1.0 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 32M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T56083QG
Rev. 1.0 July 2006
17 of 19
DDR2 SDRAM
RDIMM
14.2 64Mbx4 based 64Mx72 Module(1 Rank) - M393T6450GZ3
Units : Millimeters
133.35
4.00
30.00
PLL
1.0 max
1.7 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 64M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T56043QG
Rev. 1.0 July 2006
18 of 19
DDR2 SDRAM
RDIMM
15.0 240 Pin DDR2 Registered DIMM Clock Topology
0ns (nominal)
PLL
DDR2 SDRAM
120 ohms
OUT1
CK0
120 ohms
IN
DDR2 SDRAM
Reg.A
CK0
120 ohms
OUTN
120 ohms
C
C
Feedback In
Feedback Out
Reg.B
Note:
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Rev. 1.0 July 2006
19 of 19
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