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M393T5160FBA-CE6 [SAMSUNG]

DDR DRAM Module, 512MX72, 0.45ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240;
M393T5160FBA-CE6
型号： M393T5160FBA-CE6
厂家： SAMSUNG    SAMSUNG
描述：

DDR DRAM Module, 512MX72, 0.45ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240

时钟 动态存储器 双倍数据速率 内存集成电路
文件： 总24页 (文件大小：655K)
中文：  中文翻译
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Rev. 1.0, Jul. 2010  
M393T2863FBA  
M393T5663FBA  
M393T5660FBA  
M393T5160FBA  
240pin Registered DIMM  
based on 1Gb F-die  
60 FBGA with Lead-Free & Halogen-Free  
(RoHS compliant)  
datasheet  
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND  
SPECIFICATIONS WITHOUT NOTICE.  
Products and specifications discussed herein are for reference purposes only. All information discussed  
herein is provided on an "AS IS" basis, without warranties of any kind.  
This document and all information discussed herein remain the sole and exclusive property of Samsung  
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property  
right is granted by one party to the other party under this document, by implication, estoppel or other-  
wise.  
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or  
similar applications where product failure could result in loss of life or personal or physical harm, or any  
military or defense application, or any governmental procurement to which special terms or provisions  
may apply.  
For updates or additional information about Samsung products, contact your nearest Samsung office.  
All brand names, trademarks and registered trademarks belong to their respective owners.  
ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved.  
- 1 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
Revision History  
Revision No.  
History  
Draft Date  
Remark  
Editor  
1.0  
Jul. 2010  
-
S.H.Kim  
-First Release  
- 2 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
Table Of Contents  
240pin Registered DIMM based on 1Gb F-die  
1. DDR2 Unbuffered DIMM Ordering Information.............................................................................................................4  
2. Key Features.................................................................................................................................................................4  
3. Address Configuration ..................................................................................................................................................4  
4. Pin Configurations (Front side/Back side).....................................................................................................................5  
5. Pin Description..............................................................................................................................................................5  
6. Input/Output Function Description ................................................................................................................................6  
7. Functional Block Diagram :...........................................................................................................................................7  
7.1 1GB, 128Mx72 Module - M393T2863FBA .............................................................................................................. 7  
7.2 2GB, 256Mx72 Module - M393T5663FBA .............................................................................................................. 8  
7.3 2GB, 256Mx72 Module - M393T5660FBA .............................................................................................................. 9  
7.4 4GB, 512Mx72 Module - M393T5160FBA .............................................................................................................. 10  
8. Absolute Maximum DC Ratings....................................................................................................................................11  
9. AC & DC Operating Conditions.....................................................................................................................................11  
9.1 Recommended DC Operating Conditions (SSTL - 1.8)........................................................................................... 11  
9.2 Operating Temperature Condition........................................................................................................................... 12  
9.3 Input DC Logic Level ............................................................................................................................................... 12  
9.4 Input AC Logic Level ............................................................................................................................................... 12  
9.5 AC Input Test Conditions......................................................................................................................................... 12  
10. IDD Specification Parameters Definition.....................................................................................................................13  
11. Operating Current Table : ...........................................................................................................................................14  
11.1 M393T2863FBA : 1GB(128Mx8 *9) Module.......................................................................................................... 14  
11.2 M393T2863FBA : 1GB(128Mx8 *9) Module - considering Register and PLL current value.................................. 14  
11.3 M393T5663FBA : 2GB(128Mx8 *18) Module........................................................................................................ 15  
11.4 M393T5663FBA : 2GB(128Mx8 *18) Module - considering Register and PLL current value................................ 15  
11.5 M393T5660FBA : 2GB(256Mx4 *18) Module........................................................................................................ 16  
11.6 M393T5660FBA : 2GB(256Mx4 *18) Module - considering Register and PLL current value................................ 16  
11.7 M393T5160FBA : 4GB(256Mx4 *36) Module........................................................................................................ 17  
11.8 M393T5160FBA : 4GB(256Mx4 *36) Module - considering Register and PLL current value................................ 17  
12. Input/Output Capacitance ...........................................................................................................................................18  
13. Electrical Characteristics & AC Timing for DDR2-800/667 .........................................................................................18  
13.1 Refresh Parameters by Device Density................................................................................................................. 18  
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 18  
13.3 Timing Parameters by Speed Grade.................................................................................................................... 19  
14. Physical Dimensions :.................................................................................................................................................21  
14.1 128Mbx8 based 128Mx72 Module (1 Rank).......................................................................................................... 21  
14.2 128Mbx8/256Mbx4 based 256Mx72 Module (2 Ranks / 1 Rank).......................................................................... 22  
14.3 256Mbx4 based 512Mx72 Module (2 Ranks)........................................................................................................ 23  
15. 240 Pin DDR2 Registered DIMM Clock Topology ......................................................................................................24  
- 3 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
1. DDR2 Unbuffered DIMM Ordering Information  
Number of  
Height  
Part Number  
Density  
Organization  
Component Composition  
Rank  
M393T2863FBA-CE7/F7/E6  
M393T5663FBA-CE7/F7/E6  
M393T5660FBA-CE7/F7/E6  
M393T5160FBA-CE7/F7/E6  
1GB  
2GB  
2GB  
4GB  
128Mx72  
256Mx72  
256Mx72  
512Mx72  
128Mx8(K4T1G084QF)*9  
128Mx8(K4T1G084QF)*18  
256Mx4(K4T1G084QF)*18  
256Mx4(K4T1G084QF)*36  
1
2
1
2
30mm  
30mm  
30mm  
30mm  
NOTE :  
1. “B” of Part number(11th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.  
2. “A” of Part number(12th digit) stands for Parity Register products.  
2. Key Features  
•
Performance range  
E7 (DDR2-800)  
F7 (DDR2-800)  
E6 (DDR2-667)  
Unit  
CAS Latency  
tRCD(min)  
tRP(min)  
5
6
5
tCK  
ns  
12.5  
12.5  
57.5  
15  
15  
60  
15  
15  
60  
ns  
tRC(min)  
ns  
•
•
•
JEDEC standard VDD = 1.8V ± 0.1V Power Supply  
VDDQ = 1.8V ± 0.1V  
267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin  
•
•
•
•
•
•
•
•
•
•
•
8 Banks  
Posted CAS  
Programmable CAS Latency: 3, 4, 5, 6  
Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5  
Write Latency(WL) = Read Latency(RL) -1  
Burst Length: 4 , 8(Interleave/Nibble sequential)  
Programmable Sequential / Interleave Burst Mode  
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)  
Off-Chip Driver(OCD) Impedance Adjustment  
On Die Termination with selectable values(50/75/150 ohms or disable)  
Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C  
- Support High Temperature Self-Refresh rate enable feature  
Serial presence detect with EEPROM  
•
•
•
DDR2 SDRAM Package: 60ball FBGA(Flip-chip) - 256Mx4/128Mx8  
All of products are Lead-Free, Halogen-Free, and RoHS compliant  
NOTE : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.  
3. Address Configuration  
Organization  
Row Address  
A0-A13  
Column Address  
A0-A9, A11  
A0-A9  
Bank Address  
BA0-BA2  
Auto Precharge  
256Mx4(1Gb) based Module  
128Mx8(1Gb) based Module  
A10  
A10  
A0-A13  
BA0-BA2  
- 4 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
4. Pin Configurations (Front side/Back side)  
Pin  
Front  
Pin  
Back  
Pin  
Front  
Pin  
Back  
Pin  
Front  
Pin  
Back  
Pin  
Front  
Pin  
Back  
1
V
121  
V
31  
DQ19  
151  
V
61  
A4  
181  
V
91  
V
SS  
211 DM5/DQS14  
212 NC/DQS14  
REF  
SS  
SS  
DDQ  
2
V
122  
123  
124  
DQ4  
DQ5  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
V
152  
153  
154  
DQ28  
DQ29  
62  
63  
64  
V
DDQ  
182  
183  
184  
A3  
A1  
92  
93  
DQS5  
DQS5  
SS  
SS  
3
DQ0  
DQ1  
DQ24  
DQ25  
A2  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
V
SS  
4
V
V
V
V
94  
V
SS  
DQ46  
DQ47  
SS  
SS  
DD  
DD  
5
V
125 DM0/DQS9  
V
155 DM3/DQS12  
156 NC/DQS12  
KEY  
95  
DQ42  
DQ43  
SS  
SS  
6
DQS0  
DQS0  
126  
127  
128  
129  
130  
131  
132  
133  
NC/DQS9  
DQS3  
DQS3  
65  
66  
67  
68  
69  
70  
71  
72  
V
V
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
CK0  
CK0  
96  
V
SS  
SS  
SS  
DD  
7
V
157  
158  
159  
160  
161  
162  
163  
V
97  
V
SS  
DQ52  
DQ53  
SS  
SS  
8
V
DQ6  
DQ7  
V
DQ30  
DQ31  
V
V
98  
DQ48  
DQ49  
SS  
SS  
DD  
9
DQ2  
DQ3  
DQ26  
DQ27  
NC/Par_In  
A0  
99  
V
SS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
V
V
V
V
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
V
SS  
S2  
S3  
SS  
SS  
DD  
DD  
V
DQ12  
DQ13  
V
CB4  
CB5  
A10/AP  
BA0  
BA1  
SA2  
SS  
SS  
DQ8  
DQ9  
CB0  
CB1  
V
NC(TEST)  
V
SS  
DDQ  
V
V
V
RAS  
V
SS  
223 DM6/DQS15  
224 NC/DQS15  
SS  
SS  
DDQ  
V
134 DM1/DQS10 44  
V
164 DM8/DQS17 73  
165 NC/DQS17  
WE  
S0  
DQS6  
DQS6  
SS  
SS  
DQS1  
DQS1  
135 NC/DQS10  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
DQS8  
DQS8  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
CAS  
V
225  
226  
227  
228  
229  
230  
231  
V
SS  
DDQ  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
V
166  
167  
168  
169  
170  
171  
172  
173  
174  
V
V
ODT0  
V
SS  
DQ54  
DQ55  
SS  
SS  
DDQ  
V
RFU  
RFU  
V
CB6  
CB7  
S1  
A13  
DQ50  
DQ51  
SS  
SS  
RESET  
NC  
CB2  
CB3  
ODT1  
V
V
SS  
DD  
V
V
V
V
V
SS  
DQ60  
DQ61  
SS  
SS  
DDQ  
SS  
V
DQ14  
DQ15  
V
V
V
SS  
DQ36  
DQ37  
DQ56  
DQ57  
SS  
SS  
DDQ  
DQ10  
DQ11  
V
CKE1  
DQ32  
DQ33  
V
SS  
DDQ  
V
CKE0  
V
V
V
SS  
232 DM7/DQS16  
233 NC/DQS16  
SS  
DD  
SS  
V
DQ20  
DQ21  
V
NC  
NC  
V
SS  
202 DM4/DQS13 113  
DQS7  
DQS7  
SS  
DD  
DQ16  
DQ17  
BA2  
DQS4  
DQS4  
203 NC/DQS13  
114  
115  
116  
117  
118  
119  
120  
234  
235  
236  
237  
238  
239  
240  
V
SS  
V
NC/Err_Out 175  
V
204  
205  
206  
207  
208  
V
V
SS  
DQ62  
DQ63  
SS  
DDQ  
SS  
V
146 DM2/DQS11 56  
V
176  
177  
178  
179  
180  
A12  
V
SS  
DQ38  
DQ39  
DQ58  
DQ59  
SS  
DDQ  
DQS2  
DQS2  
147  
148  
149  
150  
NC/DQS11  
57  
58  
59  
60  
A11  
A7  
A9  
DQ34  
DQ35  
V
SS  
V
V
V
V
V
SS  
DD  
SS  
SS  
DDSPD  
V
DQ22  
DQ23  
V
A8  
A6  
V
SS  
DQ44  
DQ45  
SDA  
SCL  
SA0  
SS  
DD  
DQ18  
A5  
89  
90  
DQ40  
DQ41  
209  
210  
SA1  
V
SS  
NOTE : NC = No Connect, RFU = Reserved for Future Use  
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.  
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)  
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.  
5. Pin Description  
Pin Name  
Description  
Pin Name  
Description  
CK0  
Clock Inputs, positive line  
Clock inputs, negative line  
Clock Enables  
ODT0~ODT1  
DQ0~DQ63  
CB0~CB7  
On die termination  
Data Input/Output  
CK0  
CKE0, CKE1  
RAS  
Data check bits Input/Output  
Data strobes  
Row Address Strobe  
Column Address Strobe  
Write Enable  
DQS0~DQS8  
DQS0~DQS8  
CAS  
Data strobes, negative line  
WE  
DM(0~8),DQS(9~17) Data Masks / Data strobes (Read)  
S0~ S3  
A0~A9, A11~A13  
A10/AP  
Chip Selects  
DQS9~DQS17  
Data strobes (Read), negative line  
Reserved for Future Use  
No Connect  
Address Inputs  
RFU  
NC  
Address Input/Autoprecharge  
Memory bus test tool  
(Not Connect and Not Useable on DIMMs)  
BA0~BA2  
DDR2 SDRAM Bank Address  
TEST  
VDD  
SCL  
Serial Presence Detect (SPD) Clock Input  
SPD Data Input/Output  
Core Power  
I/O Power  
VDDQ  
VSS  
SDA  
SA0~SA2  
Par_In  
Err_Out  
RESET  
SPD address  
Ground  
VREF  
VDDSPD  
Parity bit for the Address and Control bus  
Input/Output Reference  
SPD Power  
Parity error found in the Address and Control bus  
Register and PLL control pin  
* The V and V  
pins are tied to the single power-plane on PCB.  
DDQ  
DD  
- 5 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
6. Input/Output Function Description  
Symbol  
Type  
Input  
Input  
Description  
CK0  
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.  
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.  
CK0  
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low  
initiates the Power Down mode, or the Self Refresh mode.  
Input  
CKE0~CKE1  
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-  
abled, new commands are ignored but previous operations continue.  
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are  
high.  
Input  
S0~S3  
Input  
Input  
ODT0~ODT1  
I/O bus impedance control signals.  
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the  
SDRAM.  
RAS, CAS, WE  
VREF  
VDDQ  
Supply  
Reference voltage for SSTL_18 inputs  
Supply  
Input  
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity  
Selects which SDRAM bank of eight is activated.  
BA0~BA2  
During a Bank Activate command cycle, Address defines the row address.  
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is  
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is  
selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Pre-  
charge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is  
high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are  
used to define which bank to precharge.  
A0~A9,A10/AP  
A11~A13  
Input  
DQ0~63,  
CB0~CB7  
In/Out  
Input  
Data and Check Bit Input/Output pins  
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once  
the write command is registered into the SDRAM.  
DM0~DM8  
VDD, VSS  
Supply  
In/Out  
In/Out  
Power and ground for the DDR SDRAM input buffers and core logic  
DQS0~DQS17  
DQS0~DQS17  
SA0~SA2  
Positive line of the differential data strobe for input and output data.  
Negative line of the differential data strobe for input and output data.  
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.  
Input  
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the  
SDA bus line to VDDSPD to act as a pullup.  
SDA  
In/Out  
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time  
to VDDSPD to act as a pullup.  
SCL  
Input  
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to  
3.6 Volt operation).  
VDDSPD  
Supply  
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs  
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-  
nized with the input clock )  
RESET  
Input  
Par_In  
Err_Out  
TEST  
Input  
Output  
In/Out  
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)  
Parity error found in the Address and Control bus  
Used by memory bus analysis tools (unused on memory DIMMs)  
- 6 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
7. Functional Block Diagram :  
7.1 1GB, 128Mx72 Module - M393T2863FBA  
(Populated as 1 rank of x8 DDR2 SDRAMs)  
RS0  
DQS0  
DQS4  
DQS0  
DQS4  
DM0/DQS9  
NC/DQS9  
DM4/DQS13  
NC/DQS13  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D0  
D4  
DQS1  
DQS1  
DM1/DQS10  
NC/DQS10  
DQS5  
DQS5  
DM5/DQS14  
NC/DQS14  
V
V
V
V
Serial PD  
D0 - D8  
D0 - D8  
D0 - D8  
DDSPD  
/V  
DD DDQ  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
I/O 0  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
I/O 0  
REF  
SS  
DQ8  
DQ9  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
I/O 1  
I/O 1  
D1  
D5  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
Serial PD  
SCL  
SDA  
DQS2  
DQS6  
DQS2  
DM2/DQS11  
NC/DQS11  
DQS6  
DM6/DQS15  
NC/DQS15  
WP A0 A1 A2  
SA0 SA1 SA2  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D2  
D6  
Signals for Address and Command Parity Function  
DQS3  
DQS3  
DM3/DQS12  
NC/DQS12  
DQS7  
DQS7  
DM7/DQS16  
NC/DQS16  
Register  
V
V
C0  
C1  
SS  
SS  
PPO  
PAR_IN  
100K ohms  
PAR_IN  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
I/O 0  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
I/O 0  
QERR  
Err_Out  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D3  
D7  
The resistors on Par_In, A14, A15, and the signal  
line of Err_Out refer to the section: "Register Options  
for Unused Address inputs"  
DQS8  
DQS8  
DM8/DQS17  
NC/DQS17  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
I/O 0  
CK0  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
P
L
L
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D8  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8  
PCK7 -> CK : Register  
PCK7 -> CK : Register  
CK0  
OE  
RESET  
1:1  
R
E
G
I
S
T
E
R
S0*  
RSO-> CS : DDR2 SDRAMs D0-D8  
BA0-BA2  
A0-A13  
RAS  
CAS  
WE  
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D8  
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8  
RRAS -> RAS : DDR2 SDRAMs D0-D8  
RCAS -> CAS : DDR2 SDRAMs D0-D8  
RWE -> WE : DDR2 SDRAMs D0-D8  
NOTE :  
1. DQ-to-I/O wiring may be changed within a byte.  
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.  
3. Unless otherwise noted, resister values are 22 Ohms ± 5%  
CKE0  
ODT0  
RCKE0 -> CKE : DDR2 SDRAMs D0-D8  
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8  
RST  
RESET  
PCK7  
* S0 connects to DCS and V connects to CSR on the register. S1, CKE1 and ODT are NC.  
DD  
PCK7  
- 7 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
7.2 2GB, 256Mx72 Module - M393T5663FBA  
(Populated as 2 ranks of x8 DDR2 SDRAMs)  
RS1  
RS0  
DQS0  
DQS4  
DQS0  
DQS4  
DM0/DQS9  
NC/DQS9  
DM4/DQS13  
NC/DQS13  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D0  
D9  
D4  
D13  
DQS1  
DQS5  
DQS1  
DQS5  
DM1/DQS10  
NC/DQS10  
DM5/DQS14  
NC/DQS14  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ8  
DQ9  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
I/O 0  
I/O 1  
I/O 0  
I/O 1  
I/O 0  
I/O 1  
I/O 0  
I/O 1  
D1  
D10  
D5  
D14  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS2  
DQS6  
DQS2  
DQS6  
DM2/DQS11  
NC/DQS11  
DM6/DQS15  
NC/DQS15  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D2  
D11  
D6  
D15  
DQS3  
DQS7  
DQS3  
DQS7  
DM3/DQS12  
NC/DQS12  
DM7/DQS16  
NC/DQS16  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D3  
D12  
D7  
D16  
Serial PD  
DQS8  
DQS8  
DM8/DQS17  
NC/DQS17  
V
V
V
V
Serial PD  
D0 - D17  
D0 - D17  
D0 - D17  
DDSPD  
SCL  
SDA  
/V  
DD DDQ  
WP A0 A1 A2  
SA0 SA1 SA2  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
I/O 0  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
I/O 0  
REF  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D8  
D17  
SS  
Signals for Address and Command Parity Function  
Register A  
Register B  
V
V
C0  
C1  
V
V
C0  
C1  
SS  
DD  
DD  
DD  
PPO  
PPO  
PAR_IN  
100K ohms  
PAR_IN  
PAR_IN  
S0*  
S1*  
BA0-BA2  
A0-A13  
RAS  
CAS  
WE  
CKE0  
CKE1  
ODT0  
ODT1  
RSO-> CS : DDR2 SDRAMs D0-D8  
RS1-> CS : DDR2 SDRAMs D9-D17  
QERR  
Err_Out  
1:2  
R
E
G
I
QERR  
RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D17  
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17  
RRAS -> RAS : DDR2 SDRAMs D0-D17  
RCAS -> CAS : DDR2 SDRAMs D0-D17  
RWE -> WE : DDR2 SDRAMs D0-D17  
RCKE0 -> CKE : DDR2 SDRAMs D0-D8  
RCKE1 -> CKE : DDR2 SDRAMs D9-D17  
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8  
RODT1 -> ODT1 : DDR2 SDRAMs D9-D17  
The resistors on Par_In, A14, A15, and the signal line of Err_Out refer to the sec-  
tion: "Register Options for Unused Address inputs"  
S
T
E
R
CK0  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17  
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17  
PCK7 -> CK : Register  
PCK7 -> CK : Register  
CK0  
OE  
RESET  
RST  
RESET**  
PCK7**  
NOTE : 1. DQ-to-I/O wiring may be changed per nibble.  
2. Unless otherwise noted, resister values are 22 Ohms ± 5%  
PCK7**  
3. RS0 and RS1 alternate between the back and front sides of the DIMM  
* S0 connects to DCS and S1 connects to CSR on a Register, S1 connects to DCS and S0 connects to CSR on another Register.  
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.  
- 8 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
7.3 2GB, 256Mx72 Module - M393T5660FBA  
(Populated as 1 rank of x4 DDR2 SDRAMs)  
V
SS  
RS0  
DQS0  
DQS0  
DM0/DQS9  
NC/DQS9  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ0  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 0  
I/O 0  
DQ1  
DQ2  
DQ3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D0  
D9  
DQS1  
DQS1  
DM1/DQS10  
NC/DQS10  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ13  
DQ14  
DQ15  
D1  
D10  
DQS2  
DQS2  
DM2/DQS11  
NC/DQS11  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ16  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ17  
DQ18  
DQ19  
D2  
D11  
DQS3  
DQS3  
DM3/DQS12  
NC/DQS12  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ24  
DQ28  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ25  
DQ26  
DQ27  
DQ29  
DQ30  
DQ31  
D3  
D12  
DQS4  
DQS4  
DM4/DQS13  
NC/DQS13  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ32  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ33  
DQ34  
DQ35  
D4  
D13  
DQS5  
DQS5  
DM5/DQS14  
NC/DQS14  
Serial PD  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ40  
DQ44  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
SCL  
SDA  
DQ41  
DQ42  
DQ43  
DQ45  
DQ46  
DQ47  
D5  
D14  
WP A0 A1 A2  
SA0 SA1 SA2  
DQS6  
DQS6  
DM6/DQS15  
NC/DQS15  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ48  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ49  
DQ50  
DQ51  
D6  
D15  
V
V
V
V
Serial PD  
D0 - D17  
D0 - D17  
D0 - D17  
DDSPD  
DQS7  
DQS7  
DM7DQS16  
NC/DQS16  
/V  
DD DDQ  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ56  
DQ60  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
REF  
SS  
DQ57  
DQ58  
DQ59  
DQ61  
DQ62  
DQ63  
D7  
D16  
DQS8  
DQS8  
DM8/DQS17  
NC/DQS17  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
Signals for Address and Command Parity Function  
CB0  
CB4  
CB5  
CB6  
CB7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
CB1  
CB2  
CB3  
D8  
D17  
Register A  
Register B  
V
V
C0  
C1  
V
V
C0  
C1  
SS  
DD  
DD  
DD  
PPO  
PPO  
PAR_IN  
100K ohms  
PAR_IN  
PAR_IN  
1:2  
QERR  
Err_Out  
R
E
G
I
S
T
E
R
S0*  
RSO-> CS : DDR2 SDRAMs D0-D17  
QERR  
BA0-BA2  
A0-A13  
RAS  
CAS  
WE  
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17  
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17  
RRAS -> RAS : DDR2 SDRAMs D0-D17  
RCAS -> CAS : DDR2 SDRAMs D0-D17  
RWE -> WE : DDR2 SDRAMs D0-D17  
The resistors on Par_In, A14, A15, and the signal line of Err_Out refer to the  
section: "Register Options for Unused Address inputs"  
CK0  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8  
CKE0  
ODT0  
RCKE0 -> CKE : DDR2 SDRAMs D0-D17  
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17  
P
L
L
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8  
PCK7 -> CK : Register  
PCK7 -> CK : Register  
RST  
CK0  
RESET**  
PCK7**  
OE  
RESET  
PCK7**  
NOTE : 1. DQ-to-I/O wiring may be changed per nibble.  
2. Unless otherwise noted, resister values are 22 Ohms ± 5%  
* S0 connects to DCS of Register1 and CSR of Register2. CSR of register 1 and DCS of register 2 connects to V  
.
DD  
** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers. S1, CKE1 and ODT1 are NC.  
- 9 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
7.4 4GB, 512Mx72 Module - M393T5160FBA  
(Populated as 2 ranks of x4 DDR2 SDRAMs)  
V
SS  
RS1  
RS0  
DQS0  
DQS0  
DM0/DQS9  
NC/DQS9  
DM  
CS DQS DQS  
DM/ CS DQS DQS  
I/O 0  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ0  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 0  
I/O 0  
I/O 0  
DQ1  
DQ2  
DQ3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D0  
D18  
D9  
D27  
DQS1  
DQS1  
DM1/DQS10  
NC/DQS10  
DM  
CS DQS DQS  
DM/ CS DQS DQS  
I/O 0  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ13  
DQ14  
DQ15  
I/O 1  
I/O 2  
I/O 3  
D1  
D19  
D10  
D28  
DQS2  
DQS2  
DM2/DQS11  
NC/DQS11  
DM  
CS DQS DQS  
DM/ CS DQS DQS  
I/O 0  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ16  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ17  
DQ18  
DQ19  
I/O 1  
I/O 2  
I/O 3  
D2  
D20  
D11  
D29  
DQS3  
DQS3  
DM3/DQS12  
NC/DQS12  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ24  
DQ28  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ25  
DQ26  
DQ27  
DQ29  
DQ30  
DQ31  
D3  
D21  
D12  
D30  
DQS4  
DQS4  
DM4/DQS13  
NC/DQS13  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ32  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ33  
DQ34  
DQ35  
D4  
D22  
D13  
D31  
DQS5  
DQS5  
DM5/DQS14  
NC/DQS14  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ40  
DQ44  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ41  
DQ42  
DQ43  
DQ45  
DQ46  
DQ47  
D5  
D23  
D14  
D32  
DQS6  
DQS6  
DM6/DQS15  
NC/DQS15  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ48  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ49  
DQ50  
DQ51  
D6  
D24  
D15  
D33  
Serial PD  
DQS7  
DQS7  
DM7DQS16  
NC/DQS16  
SCL  
SDA  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
WP A0 A1 A2  
DQ56  
DQ60  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ57  
DQ58  
DQ59  
DQ61  
DQ62  
DQ63  
D7  
D25  
D16  
D34  
SA0 SA1 SA2  
Serial PD  
V
V
V
V
DDSPD  
DQS8  
DQS8  
DM8/DQS17  
NC/DQS17  
/V  
D0 - D35  
D0 - D35  
D0 - D35  
DD DDQ  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
CB0  
CB4  
CB5  
CB6  
CB7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
REF  
CB1  
CB2  
CB3  
D8  
D26  
D17  
D35  
SS  
Signals for Address and Command Parity Function  
S0*  
RSO-> CS : DDR2 SDRAMs D0-D17  
RS1-> CS : DDR2 SDRAMs D18-D35  
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35  
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35  
RRAS -> RAS : DDR2 SDRAMs D0-D35  
RCAS -> CAS : DDR2 SDRAMs D0-D35  
RWE -> WE : DDR2 SDRAMs D0-D35  
RCKE0 -> CKE : DDR2 SDRAMs D0-D17  
RCKE1 -> CKE : DDR2 SDRAMs D18-D35  
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17  
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35  
S1*  
1:2  
R
E
G
I
S
T
E
R
Register A  
BA0-BA1  
A0-A13  
RAS  
CAS  
WE  
CKE0  
CKE1  
ODT0  
ODT1  
The resistors on Par_In, A14,  
PPO  
PAR_IN  
A15, and the signal line of  
Err_Out refer to the section:  
"Register Options for Unused  
Address inputs"  
QERR  
PAR_IN  
Err_Out  
100K ohms  
Register B  
PPO  
QERR  
PAR_IN  
RST  
RESET**  
PCK7**  
CK0  
CK0  
PCK7**  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35  
P
L
L
* S0 connects to DCS and S1 connects to CSR on a pair of Registers,  
S1 connects to DCS and S0 connects to CSR on another pair of Registers.  
** RESET, PCK7 and PCK7 connects to all Registers.  
PCK7 -> CK : Register  
PCK7 -> CK : Register  
OE  
RESET  
Other signals connect to one pair of four Registers.  
- 10 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
8. Absolute Maximum DC Ratings  
Symbol  
Parameter  
Rating  
Units  
V
NOTE  
Voltage on VDD pin relative to VSS  
Voltage on VDDQ pin relative to VSS  
Voltage on VDDL pin relative to VSS  
Voltage on any pin relative to VSS  
Storage Temperature  
VDD  
- 1.0 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
-55 to +100  
1
1
VDDQ  
VDDL  
IN, VOUT  
TSTG  
V
V
1
V
V
1
°C  
1, 2  
NOTE :  
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions  
for extended periods may affect reliability.  
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.  
9. AC & DC Operating Conditions  
9.1 Recommended DC Operating Conditions (SSTL - 1.8)  
Rating  
Symbol  
Parameter  
Units  
NOTE  
Min.  
1.7  
Typ.  
1.8  
Max.  
1.9  
VDD  
VDDL  
VDDQ  
VREF  
VTT  
Supply Voltage  
V
Supply Voltage for DLL  
Supply Voltage for Output  
Input Reference Voltage  
Termination Voltage  
1.7  
1.8  
1.9  
V
4
4
1.7  
1.8  
1.9  
V
0.49*VDDQ  
VREF-0.04  
0.50*VDDQ  
VREF  
0.51*VDDQ  
VREF+0.04  
mV  
1,2  
3
V
NOTE : There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V  
must be less than or equal to V  
.
DD  
DDQ  
DD  
1. The value of V  
may be selected by the user to provide optimum noise margin in the system. Typically the value of V  
is expected to be about 0.5 x V  
of the transmitting  
REF  
REF  
DDQ  
device and V  
is expected to track variations in V  
.
REF  
DDQ  
2. Peak to peak AC noise on V  
may not exceed +/-2% V  
(DC).  
REF  
REF  
3. V of transmitting device must track V  
of receiving device.  
TT  
REF  
4. AC parameters are measured with V , V  
and V  
tied together.  
DDL  
DD  
DDQ  
- 11 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
9.2 Operating Temperature Condition  
Symbol  
Parameter  
Rating  
Units  
NOTE  
TOPER  
Operating Temperature  
0 to 95  
°C  
1, 2  
NOTE :  
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard.  
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this  
temperature range, an EMRS command is required to change internal refresh rate.  
9.3 Input DC Logic Level  
Symbol  
Parameter  
Min.  
Max.  
Units  
NOTE  
VIH(DC)  
DC input logic high  
VREF + 0.125  
VDDQ + 0.3  
V
VIL(DC)  
DC input logic low  
- 0.3  
VREF - 0.125  
V
9.4 Input AC Logic Level  
DDR2-667, DDR2-800  
Symbol  
Parameter  
Units  
Min.  
Max.  
VIH(AC)  
VIL(AC)  
AC input logic high  
AC input logic low  
VREF + 0.200  
-
-
V
V
VREF - 0.200  
9.5 AC Input Test Conditions  
Symbol  
Condition  
Value  
Units  
NOTE  
VREF  
VSWING(MAX)  
SLEW  
Input reference voltage  
0.5 * VDDQ  
1.0  
V
1
Input signal maximum peak to peak swing  
Input signal minimum slew rate  
V
1
1.0  
V/ns  
2, 3  
NOTE :  
1. Input waveform timing is referenced to the input signal crossing through the V  
(AC) level applied to the device under test.  
IH/IL  
2. The input signal minimum slew rate is to be maintained over the range from V  
shown in the below figure.  
to V (AC) min for rising edges and the range from V  
to V (AC) max for falling edges as  
REF  
IH  
REF IL  
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative transitions.  
IL  
IH  
IH  
IL  
V
V
V
V
DDQ  
(AC) min  
IH  
(DC) min  
IH  
V
SWING(MAX)  
REF  
V (DC) max  
IL  
V (AC) max  
IL  
V
SS  
delta TF  
delta TR  
V
- V (AC) max  
IL  
V
(AC) min - V  
delta TR  
REF  
IH  
REF  
Falling Slew =  
Rising Slew =  
delta TF  
Figure 1. AC Input Test Signal Waveform  
- 12 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
10. IDD Specification Parameters Definition  
(IDD values are for full operating range of Voltage and Temperature)  
Symbol  
Proposed Conditions  
Operating one bank active-precharge current;  
Units  
NOTE  
IDD0  
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;  
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
mA  
Operating one bank active-read-precharge current;  
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =  
tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern  
is same as IDD4W  
IDD1  
mA  
Precharge power-down current;  
IDD2P  
IDD2Q  
IDD2N  
IDD3P  
IDD3N  
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are  
FLOATING  
mA  
mA  
mA  
Precharge quiet standby current;  
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data  
bus inputs are FLOATING  
Precharge standby current;  
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Active power-down current;  
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address  
bus inputs are STABLE; Data bus inputs are FLOATING  
Fast PDN Exit MRS(12) = 0  
Slow PDN Exit MRS(12) = 1  
mA  
mA  
Active standby current;  
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid  
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
mA  
mA  
Operating burst write current;  
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP  
= tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus  
inputs are SWITCHING  
IDD4W  
IDD4R  
Operating burst read current;  
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-  
max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-  
ING; Data pattern is same as IDD4W  
mA  
mA  
Burst auto refresh current;  
IDD5B  
IDD6  
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands;  
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
Self refresh current;  
Normal  
mA  
mA  
CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are  
FLOATING; Data bus inputs are FLOATING  
Low Power  
Operating bank interleave read current;  
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =  
tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid com-  
mands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following  
page for detailed timing conditions  
IDD7  
mA  
- 13 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
11. Operating Current Table :  
11.1 M393T2863FBA : 1GB(128Mx8 *9) Module  
(TA=0oC, VDD= 1.9V)  
800@CL=5  
CE7  
405  
800@CL6  
667@CL=5  
CE6  
387  
Symbol  
Units  
NOTE  
CF7  
405  
459  
90  
IDD0  
IDD1  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
459  
432  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
90  
90  
180  
180  
225  
207  
180  
333  
648  
720  
945  
90  
180  
225  
216  
207  
198  
180  
180  
333  
315  
648  
585  
720  
630  
945  
900  
IDD61  
IDD7  
90  
90  
1,440  
1,440  
1,305  
mA  
NOTE :  
1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
11.2 M393T2863FBA : 1GB(128Mx8 *9) Module - considering Register and PLL current value  
(TA=0oC, VDD= 1.9V)  
800@CL=5  
CE7  
795  
800@CL=6  
CF7  
667@CL=5  
CE6  
887  
Symbol  
Units  
NOTE  
IDD0  
IDD1  
995  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
899  
1,099  
570  
982  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
550  
530  
620  
710  
640  
585  
705  
636  
637  
757  
668  
610  
730  
650  
683  
873  
785  
1,028  
1,180  
1,325  
90  
1,168  
1,310  
1615  
90  
1,035  
1,140  
1,450  
90  
IDD61  
IDD7  
1,990  
2,130  
1,885  
mA  
NOTE :  
1. IDD6 = DRAM current + standby current of PLL and Register  
2. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
- 14 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
11.3 M393T5663FBA : 2GB(128Mx8 *18) Module  
(TA=0oC, VDD= 1.9V)  
800@CL=5  
CE7  
630  
800@CL6  
667@CL=5  
CE6  
603  
Symbol  
Units  
NOTE  
CF7  
630  
684  
180  
360  
450  
414  
360  
558  
873  
945  
1,170  
180  
IDD0  
IDD1  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
684  
648  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
180  
180  
360  
360  
450  
432  
414  
396  
360  
360  
558  
531  
873  
801  
945  
846  
1,170  
180  
1,116  
180  
IDD61  
IDD7  
1,665  
1,665  
1,521  
mA  
NOTE :  
1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
11.4 M393T5663FBA : 2GB(128Mx8 *18) Module - considering Register and PLL current value  
(TA=0oC, VDD= 1.9V)  
800@CL=5  
CE7  
800@CL=6  
CF7  
667@CL=5  
CE6  
Symbol  
Units  
NOTE  
IDD0  
IDD1  
1,320  
1,454  
820  
1,320  
1,454  
820  
1,193  
1,308  
760  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
1,070  
1,020  
1,144  
1,090  
1,118  
1,523  
1,735  
2,000  
180  
1,070  
1,020  
1,144  
1,090  
1,118  
1,523  
1,735  
2,000  
180  
980  
932  
1,026  
990  
1,021  
1,361  
1,526  
1,796  
180  
IDD61  
IDD7  
2,695  
2,695  
2,391  
mA  
NOTE :  
1. IDD6 = DRAM current + standby current of PLL and Register  
2. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
- 15 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
11.5 M393T5660FBA : 2GB(256Mx4 *18) Module  
(TA=0oC, VDD= 1.9V)  
800@CL=5  
CE7  
810  
800@CL6  
667@CL=5  
CE6  
774  
Symbol  
Units  
NOTE  
CF7  
810  
IDD0  
IDD1  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
918  
918  
864  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
180  
180  
180  
360  
360  
360  
450  
450  
432  
414  
414  
396  
360  
360  
360  
666  
666  
630  
1,206  
1,368  
1,890  
180  
1,206  
1,368  
1,890  
180  
1,080  
1,188  
1,800  
180  
IDD61  
IDD7  
2,808  
2,808  
2,538  
mA  
NOTE :  
1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
11.6 M393T5660FBA : 2GB(256Mx4 *18) Module - considering Register and PLL current value  
(TA=0oC, VDD= 1.9V)  
800@CL=5  
CE7  
800@CL=6  
CF7  
667@CL=5  
CE6  
Symbol  
Units  
NOTE  
IDD0  
IDD1  
1,500  
1,688  
820  
1,500  
1,688  
820  
1,364  
1,524  
760  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
1,070  
1,020  
1,144  
1,090  
1,226  
1,856  
2,158  
2,720  
180  
1,070  
1,020  
1,144  
1,090  
1,226  
1,856  
2,158  
2,720  
180  
980  
932  
1,026  
990  
1,120  
1,640  
1,868  
2,480  
180  
IDD61  
IDD7  
3,838  
3,838  
3,408  
mA  
NOTE :  
1. IDD6 = DRAM current + standby current of PLL and Register  
2. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
- 16 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
11.7 M393T5160FBA : 4GB(256Mx4 *36) Module  
(TA=0oC, VDD= 1.9V)  
800@CL=5  
CE7  
800@CL6  
667@CL=5  
CE6  
Symbol  
Units  
NOTE  
CF7  
1,260  
1,368  
360  
IDD0  
IDD1  
1,260  
1,368  
360  
1,206  
1,296  
360  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
720  
720  
720  
900  
900  
864  
828  
828  
792  
720  
720  
720  
1,116  
1,656  
1,818  
2,340  
360  
1,116  
1,656  
1,818  
2,340  
360  
1,062  
1,512  
1,620  
2,232  
360  
IDD61  
IDD7  
3,258  
3,258  
2,970  
mA  
NOTE :  
1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
11.8 M393T5160FBA : 4GB(256Mx4 *36) Module - considering Register and PLL current value  
(TA=0oC, VDD= 1.9V)  
800@CL=5  
CE7  
800@CL=6  
CF7  
667@CL=5  
CE6  
Symbol  
Units  
NOTE  
IDD0  
IDD1  
2,280  
2,528  
1,310  
1,780  
1,700  
1,918  
1,810  
1,906  
2,646  
2,908  
3,560  
360  
2,280  
2,528  
1,310  
1,780  
1,700  
1,918  
1,810  
1,906  
2,646  
2,908  
3,560  
360  
2,076  
2,296  
1,220  
1,640  
1,564  
1,732  
1,660  
1,752  
2,362  
2,560  
3,232  
360  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD61  
IDD7  
4,968  
4,968  
4,420  
mA  
NOTE :  
1. IDD6 = DRAM current + standby current of PLL and Register  
2. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
- 17 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
12. Input/Output Capacitance  
o
(VDD=1.8V, VDDQ=1.8V, TA=25 C)  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Sym.  
Units  
Part-Number  
M393T2863FBA  
M393T5663FBA  
M393T5660FBA  
M393T5160FBA  
Input capacitance, CK and CK  
Input capacitance, CKE and CS  
CCK  
CI1  
-
-
11  
12  
-
-
11  
12  
-
-
11  
12  
-
-
11  
12  
Input capacitance, Address,  
RAS,CAS,WE  
pF  
CI2  
-
-
12  
10  
-
-
12  
10  
-
-
12  
10  
-
-
12  
10  
Input/output capacitance,  
DQ, DM, DQS, DQS  
CIO  
NOTE : DM is internally loaded to match DQ and DQS identically.  
13. Electrical Characteristics & AC Timing for DDR2-800/667  
(0°C < TOPER < 95°C, VDDQ = 1.8V + 0.1V, VDD = 1.8V + 0.1V)  
13.1 Refresh Parameters by Device Density  
Parameter  
Symbol  
256Mb  
75  
512Mb  
105  
1Gb  
127.5  
7.8  
2Gb  
195  
7.8  
4Gb  
327.5  
7.8  
Units  
ns  
Refresh to active/Refresh command time  
tRFC  
tREFI  
0 °C ≤ TCASE ≤ 85°C  
85 °C < TCASE ≤ 95°C  
7.8  
7.8  
μs  
Average periodic refresh interval  
3.9  
3.9  
3.9  
3.9  
3.9  
μs  
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin  
Speed  
DDR2-800(E7)  
DDR2-800(F7)  
DDR2-667(E6)  
5 - 5 - 5  
Bin(CL - tRCD - tRP)  
Parameter  
5 - 5 - 5  
6 - 6- 6  
Units  
min  
max  
min  
max  
min  
max  
tCK, CL=3  
5
8
-
3.75  
3
-
5
3.75  
3
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCK, CL=4  
tCK, CL=5  
tCK, CL=6  
tRCD  
3.75  
2.5  
-
8
8
8
8
8
8
-
2.5  
15  
15  
60  
45  
8
-
-
12.5  
12.5  
57.5  
45  
-
-
15  
15  
60  
45  
-
tRP  
-
-
-
-
-
-
tRC  
70000  
70000  
70000  
tRAS  
- 18 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
13.3 Timing Parameters by Speed Grade  
(Refer to notes for informations related to this table at the component datasheet)  
DDR2-800  
DDR2-667  
NOTE  
Parameter  
Symbol  
Units  
min  
-400  
-350  
0.48  
0.48  
max  
400  
min  
max  
450  
DQ output access time from CK/CK  
DQS output access time from CK/CK  
Average clock HIGH pulse width  
Average clock LOW pulse width  
tAC  
- 450  
- 400  
0.48  
0.48  
ps  
40  
40  
tDQSCK  
tCH(avg)  
tCL(avg)  
350  
400  
ps  
0.52  
0.52  
0.52  
0.52  
tCK(avg)  
tCK(avg)  
35,36  
35,36  
Min(tCL(abs),  
tCH(abs))  
Min(tCL(abs),  
tCH(abs))  
CK half pulse period  
tHP  
x
x
ps  
37  
Average clock period  
tCK(avg)  
tDH(base)  
tDS(base)  
tIPW  
2500  
8000  
3000  
8000  
ps  
ps  
35,36  
DQ and DM input hold time  
125  
x
175  
x
6,7,8,21,28,31  
6,7,8,20,28,31  
DQ and DM input setup time  
50  
x
100  
x
ps  
Control & Address input pulse width for each input  
DQ and DM input pulse width for each input  
Data-out high-impedance time from CK/CK  
DQS/DQS low-impedance time from CK/CK  
DQ low-impedance time from CK/CK  
DQS-DQ skew for DQS and associated DQ signals  
DQ hold skew factor  
0.6  
x
0.6  
x
tCK(avg)  
tCK(avg)  
ps  
tDIPW  
tHZ  
0.35  
x
0.35  
x
x
tAC(max)  
x
tAC(max)  
18,40  
18,40  
18,40  
13  
tLZ(DQS)  
tLZ(DQ)  
tDQSQ  
tQHS  
tAC(min)  
tAC(max)  
tAC(min)  
tAC(max)  
ps  
2* tAC(min)  
tAC(max)  
2* tAC(min)  
tAC(max)  
ps  
x
x
200  
300  
x
x
x
240  
340  
x
ps  
ps  
38  
DQ/DQS output hold time from DQS  
DQS latching rising transitions to associated clock edges  
DQS input HIGH pulse width  
tQH  
tHP - tQHS  
- 0.25  
0.35  
0.35  
0.2  
tHP - tQHS  
-0.25  
0.35  
0.35  
0.2  
ps  
39  
tDQSS  
tDQSH  
tDQSL  
tDSS  
0.25  
x
0.25  
x
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
nCK  
30  
DQS input LOW pulse width  
x
x
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
MRS command to ODT update delay  
Write postamble  
x
x
30  
30  
tDSH  
0.2  
x
0.2  
x
tMRD  
2
x
2
x
tMOD  
0
12  
0.6  
x
0
12  
0.6  
x
ns  
32  
10  
tWPST  
tWPRE  
tIH(base)  
tIS(base)  
tRPRE  
tRPST  
0.4  
0.4  
tCK(avg)  
tCK(avg)  
ps  
Write preamble  
0.35  
250  
175  
0.9  
0.35  
275  
200  
0.9  
Address and control input hold time  
Address and control input setup time  
Read preamble  
x
x
5,7,9,23,29  
5,7,9,22,29  
19,41  
x
x
ps  
1.1  
0.6  
x
1.1  
0.6  
x
tCK(avg)  
tCK(avg)  
ns  
Read postamble  
0.4  
0.4  
19,42  
Activate to activate command period for 1KB page size products tRRD  
Activate to activate command period for 2KB page size products tRRD  
7.5  
7.5  
4,32  
10  
x
10  
x
ns  
4,32  
- 19 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
DDR2-800  
Symbol  
DDR2-667  
Parameter  
Units  
NOTE  
min  
max  
min  
max  
Four Activate Window for 1KB page size products  
Four Activate Window for 2KB page size products  
CAS to CAS command delay  
tFAW  
tFAW  
tCCD  
tWR  
35  
x
x
x
x
x
x
x
x
x
x
x
37.5  
x
x
x
x
x
x
x
x
x
x
x
ns  
ns  
32  
32  
45  
50  
2
2
nCK  
ns  
Write recovery time  
15  
15  
32  
33  
Auto precharge write recovery + precharge time  
Internal write to read command delay  
Internal read to precharge command delay  
Exit self refresh to a non-read command  
Exit self refresh to a read command  
tDAL  
WR + tnRP  
WR + tnRP  
nCK  
ns  
tWTR  
tRTP  
tXSNR  
tXSRD  
tXP  
7.5  
7.5  
24,32  
3,32  
32  
7.5  
7.5  
ns  
tRFC + 10  
tRFC + 10  
ns  
200  
2
200  
2
nCK  
nCK  
nCK  
Exit precharge power down to any command  
Exit active power down to read command  
tXARD  
2
2
1
Exit active power down to read command  
(slow exit, lower power)  
tXARDS  
8 - AL  
x
7 - AL  
x
nCK  
1,2  
CKE minimum pulse width (HIGH and LOW pulse width)  
tCKE  
3
2
x
3
2
x
nCK  
nCK  
ns  
27  
16  
ODT turn-on delay  
ODT turn-on  
tAOND  
tAON  
2
2
tAC(min)  
tAC(max)+0.7  
tAC(min)  
tAC(max)+0.7  
6,16,40  
2*tCK(avg)  
+tAC(max)+1  
2*tCK(avg)  
+tAC(max)+1  
ODT turn-on (Power-Down mode)  
tAONPD  
tAC(min)+2  
tAC(min)+2  
ns  
ODT turn-off delay  
ODT turn-off  
tAOFD  
tAOF  
2.5  
2.5  
2.5  
2.5  
nCK  
ns  
17,45  
tAC(min)  
tAC(max)+0.6  
tAC(min)  
tAC(max)+0.6  
17,43,45  
2.5*tCK(avg)+  
tAC(max)+1  
2.5*tCK(avg)+  
tAC(max)+1  
ODT turn-off (Power-Down mode)  
tAOFPD  
tAC(min)+2  
tAC(min)+2  
ns  
ODT to power down entry latency  
ODT power down exit latency  
OCD drive mode output delay  
tANPD  
tAXPD  
tOIT  
3
8
0
x
x
3
8
0
x
x
nCK  
nCK  
ns  
12  
12  
32  
15  
Minimum time clocks remains ON after CKE asynchronously  
drops LOW  
tIS+tCK(avg)  
+tIH  
tIS+tCK(avg)  
+tIH  
tDelay  
x
x
ns  
- 20 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
14. Physical Dimensions :  
14.1 128Mbx8 based 128Mx72 Module (1 Rank)  
- M393T2863FBA  
Units : Millimeters  
2.70 max  
30.00  
PLL  
1.0 max  
1.27 ± 0.10  
A
B
63.00  
55.00  
3.00  
5.00  
4.00  
0.80±0.05  
0.20  
4.00  
3.80  
4.00  
2.50  
1.00  
1.50±0.10  
Detail A  
Detail B  
The used device is 128M x8 DDR2 SDRAM, Flip-chip.  
DDR2 SDRAM Part NO : K4T1G084QF  
- 21 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
14.2 128Mbx8/256Mbx4 based 256Mx72 Module (2 Ranks / 1 Rank)  
- M393T5663FBA/M393T5660FBA  
Units : Millimeters  
133.35  
4.00 max  
30.00  
PLL  
1.0 max  
1.27 ± 0.10  
A
B
63.00  
55.00  
3.00  
5.00  
4.00  
0.80±0.05  
0.20  
4.00  
3.80  
4.00  
2.50  
1.00  
1.50±0.10  
Detail A  
Detail B  
The used device is 128M x8 / 256M x4 DDR2 SDRAM, Flip-chip.  
DDR2 SDRAM Part NO : K4T1G084QF / K4T1G044QF  
- 22 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
14.3 256Mbx4 based 512Mx72 Module (2 Ranks)  
- M393T5160FBA  
Units : Millimeters  
133.35  
4.00 max  
PLL  
30.00  
1.0 max  
1.27 ± 0.10  
A
B
63.00  
55.00  
3.00  
5.00  
4.00  
0.80±0.05  
0.20  
4.00  
3.80  
4.00  
2.50  
1.00  
1.50±0.10  
Detail A  
Detail B  
The used device is 256M x4 DDR2 SDRAM, Flip-chip.  
DDR2 SDRAM Part NO : K4T1G044QF  
- 23 -  
Rev. 1.0  
Registered DIMM  
datasheet  
DDR2 SDRAM  
15. 240 Pin DDR2 Registered DIMM Clock Topology  
0ns (nominal)  
PLL  
DDR2 SDRAM  
120 ohms  
OUT1  
CK0  
120 ohms  
IN  
DDR2 SDRAM  
Reg.A  
CK0  
120 ohms  
OUTN  
120 ohms  
C
C
Feedback In  
Feedback Out  
Reg.B  
NOTE :  
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).  
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.  
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.  
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.  
- 24 -  

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