M393T5160QZA-CE7 [SAMSUNG]
DDR DRAM Module, 512MX72, 0.45ns, CMOS, ROHS COMPLIANT, RDIMM-240;
| 型号： | M393T5160QZA-CE7 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 512MX72, 0.45ns, CMOS, ROHS COMPLIANT, RDIMM-240 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总29页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RDIMM
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 1Gb Q-die
72-bit ECC
60FBGA and 63FBGA with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
Table of Contents
1.0 DDR2 Registered DIMM Ordering Information ...........................................................................4
2.0 Features .........................................................................................................................................4
3.0 Address Configuration .................................................................................................................4
4.0 Pin Configurations (Front side/Back side) .................................................................................5
5.0Pin Description ...............................................................................................................................5
6.0 Input/Output Function Description ..............................................................................................6
7.0 Functional Block Diagram ............................................................................................................7
7.1 1GB, 128Mx72 Module - M393T2863QZA / M393T2863QZ3 .................................................................7
7.2 2GB, 256Mx72 Module - M393T5663QZA / M393T5663QZ3 .................................................................8
7.3 2GB, 256Mx72 Module - M393T5660QZA / M393T5660QZ3 .................................................................9
7.4 4GB, 512Mx72 Module - M393T5160QZA / M393T5160QZ3 ...............................................................10
7.5 8GB, 1Gx72 Module - M393T1G60QJA ...........................................................................................11
8.0 Absolute Maximum DC Ratings .................................................................................................12
9.0 AC & DC Operating Conditions .................................................................................................12
9.1 Recommended DC Operating Conditions (SSTL - 1.8) .....................................................................12
9.2 Operating Temperature Condition ................................................................................................13
9.3 Input DC Logic Level ...................................................................................................................13
9.4 Input AC Logic Level ...................................................................................................................13
9.5 AC Input Test Conditions ............................................................................................................13
10.0 IDD Specification Parameters Definition ................................................................................14
11.0 Operating Current Table ...........................................................................................................15
11.1 M393T2863QZA / M393T2863QZ3 : 1GB(128Mx8 *9) Module ........................................................15
11.2 M393T2863QZA : 1GB(128Mx8 *9) Module ................................................................................15
11.3 M393T5663QZA / M393T5663QZ3 : 2GB(128Mx8 *18) Module ......................................................16
11.4 M393T5663QZA : 2GB(128Mx8 *18) Module ..............................................................................16
11.5 M393T5660QZA / M393T5660QZ3 : 2GB(256Mx4 *18) Module .......................................................17
11.6 M393T5660QZA : 2GB(256Mx4 *18) Module ...............................................................................17
11.7 M393T5160QZA / M393T5160QZ3 : 4GB(256Mx4 *36) Module .......................................................18
11.8 M393T5160QZA : 4GB(256Mx4 *36 ) Module .............................................................................18
11.9 M393T1G60QJA : 8GB(DDP512Mx4 *36) Module .......................................................................19
11.10 M393T1G60QJA : 8GB(DDP512Mx4 *36 ) Module .....................................................................19
12.0 Input/Output Capacitance ........................................................................................................20
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ......................................20
13.1 Refresh Parameters by Device Density ......................................................................................20
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ...........................................20
13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667) .....................................................21
13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400) .....................................................23
14.0 Physical Dimensions : ............................................................................................................. 25
14.1 128Mbx8 based 128Mx72 Module (1 Rank) .................................................................................25
14.2 128Mbx8/256Mbx4 based 256Mx72 Module (2/1 Ranks) ...............................................................26
14.3 256Mbx4 based 512Mx72 Module (2 Ranks) ...............................................................................27
14.4 DDP 512Mbx4 based 1Gx72 Module (4 Ranks) ...........................................................................28
15.0 240 Pin DDR2 Registered DIMM Clock Topology ...................................................................29
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Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
Revision History
Revision
Month
April
May
Year
2008
2008
2008
History
1.0
1.01
- Initial Release
- Corrected typo
1.1
July
- Applied JEDEC update(JESD79-2E) on AC timing table
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Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
1.0 DDR2 Registered DIMM Ordering Information
Part Number
Density Organization
Component Composition
128Mx8(K4T1G084QQ)*9EA
128Mx8(K4T1G084QQ)*18EA
256Mx4(K4T1G044QQ)*18EA
256Mx4(K4T1G044QQ)*36EA
DDP 512Mx4(K4T2G0404QQ)*36EA
128Mx8(K4T1G084QQ)*9EA
128Mx8(K4T1G084QQ)*18EA
256Mx4(K4T1G044QQ)*18EA
256Mx4(K4T1G044QQ)*36EA
Number of Rank Parity Register
Height
M393T2863QZA-CE7/F7/E6
M393T5663QZA-CE7/F7/E6
M393T5660QZA-CE7/F7/E6
M393T5160QZA-CE7/F7/E6
M393T1G60QJA-CE6/D5
M393T2863QZ3-CD5/CC
M393T5663QZ3-CD5/CC
M393T5660QZ3-CD5/CC
M393T5160QZ3-CD5/CC
Note :
1GB
2GB
2GB
4GB
8GB
1GB
2GB
2GB
4GB
128Mx72
256Mx72
256Mx72
512Mx72
1Gx72
1
2
1
2
4
1
2
1
2
O
O
O
O
O
X
X
X
X
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
30.00mm
128Mx72
256Mx72
256Mx72
512Mx72
1. “Z” of Part number(11th digit) stands for Lead-Free and RoHS compliant products.
2. "J" of Part number(11th digit) stands for Lead-Free and RoHS compliant dual-die package products.
3. “3” of Part number(12th digit) stands for Non-parity Register products
4. "A" of Part number(12th digit) stands for Parity Register products.
2.0 Features
•
Performance range
Speed
DDR2-800 5-5-5
DDR2-800 6-6-6
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
Units
tCK
ns
CAS Latency
tRCD(min)
tRP(min)
5
6
5
4
3
12.5
12.5
57.5
15
15
60
15
15
60
15
15
60
15
15
55
ns
tRC(min)
ns
•
•
•
JEDEC standard VDD = 1.8V ± 0.1V Power Supply
DDQ = 1.8V ± 0.1V
V
200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
•
•
•
•
•
•
•
•
•
•
•
8 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5, 6
Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/Nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination with selectable values(50/75/150 ohms or disable)
Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
- Support High Temperature Self-Refresh rate enable feature
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA - 256Mx4/128Mx8, 63ball FBGA - DDP 512Mx4
All of base components are Lead-Free, Halogen-Free, and RoHS compliant
•
•
•
Note : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
3.0 Address Configuration
Organization
Row Address
A0-A13
Column Address
A0-A9, A11
A0-A9
Bank Address
BA0-BA2
Auto Precharge
256Mx4(1Gb) based Module
128Mx8(1Gb) based Module
A10
A10
A0-A13
BA0-BA2
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Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
4.0 Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
61
Front
A4
Pin
181
Back
DDQ
Pin
91
Front
SS
Pin
Back
1
V
121
V
31
DQ19
151
V
V
V
211 DM5/DQS14
REF
SS
SS
2
3
4
5
6
7
8
9
V
DQ0
DQ1
122
123
124
DQ4
DQ5
32
33
34
35
36
37
38
39
40
41
42
43
V
DQ24
DQ25
152
153
154
DQ28
DQ29
62
63
64
V
DDQ
A2
182
183
184
A3
A1
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC(TEST)
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7
DQS7
212 NC/DQS14
SS
SS
213
214
215
216
217
218
219
220
221
222
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
S2
S3
V
V
V
V
SS
SS
DD
DD
V
125 DM0/DQS9
V
155 DM3/DQS12
156 NC/DQS12
KEY
SS
SS
DQS0
DQS0
126
127
128
129
130
131
132
133
NC/DQS9
DQS3
DQS3
V
DQ26
DQ27
V
CB0
CB1
V
DQS8
DQS8
V
65
66
67
68
69
70
71
72
V
V
V
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
CK0
CK0
SS
SS
DD
V
157
158
159
160
161
162
163
V
SS
SS
V
DQ6
DQ7
DQ30
DQ31
V
SS
SS
DD
DQ2
DQ3
NC/Par_In
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
V
V
SS
SS
DD
DD
V
DQ12
DQ13
CB4
CB5
A10/AP
BA0
BA1
SS
SS
DQ8
DQ9
V
V
SS
DDQ
V
V
V
RAS
S0
223 DM6/DQS15
224 NC/DQS15
SS
SS
DDQ
V
134 DM1/DQS10 44
135 NC/DQS10
164 DM8/DQS17 73
165 NC/DQS17
WE
CAS
SS
SS
DQS1
DQS1
45
46
47
48
49
50
51
52
53
54
55
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
V
225
226
227
228
229
230
231
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
DDQ
136
137
138
139
140
141
142
143
144
145
V
166
167
168
169
170
171
172
173
174
V
V
ODT0
A13
SS
SS
DDQ
S1
V
RFU
RFU
CB6
CB7
SS
SS
RESET
NC
CB2
CB3
V
ODT1
V
DD
V
V
V
V
SS
SS
DDQ
SS
V
DQ14
DQ15
V
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
DQ36
DQ37
SS
SS
DDQ
DQ10
DQ11
V
CKE1
V
SS
DDQ
V
CKE0
V
V
232 DM7/DQS16
233 NC/DQS16
SS
DD
SS
V
DQ20
DQ21
V
NC
NC
202 DM4/DQS13 113
203 NC/DQS13
SS
DD
DQ16
DQ17
BA2
114
115
116
117
118
119
120
234
235
236
237
238
239
240
V
SS
DQ62
DQ63
V
NC/Err_Out 175
V
204
205
206
207
208
V
V
SS
DQ58
DQ59
SS
DDQ
A12
SS
V
146 DM2/DQS11 56
V
176
177
178
179
180
DQ38
DQ39
SS
DDQ
DQS2
DQS2
147
148
149
150
NC/DQS11
57
58
59
60
A11
A7
A9
V
SS
V
V
V
V
V
SS
DD
SS
SS
DDSPD
SA0
SA1
V
DQ22
DQ23
V
A8
A6
DQ44
DQ45
SDA
SCL
SS
DD
DQ18
A5
89
90
209
210
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
5.0Pin Description
Pin Name
CK0
Description
Pin Name
Description
Clock Inputs, positive line
Clock inputs, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
ODT0~ODT1
DQ0~DQ63
CB0~CB7
DQS0~DQS8
DQS0~DQS8
On die termination
Data Input/Output
Data check bits Input/Output
Data strobes
CK0
CKE0, CKE1
RAS
CAS
WE
Data strobes, negative line
DM(0~8), DQS(9~17) Data Masks / Data strobes (Read)
S0~ S3
Chip Selects
DQS9~DQS17
RFU
NC
Data strobes (Read), negative line
Reserved for Future Use
No Connect
A0~A9, A11~A13 Address Inputs
A10/AP
Address Input/Autoprecharge
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
BA0~BA2
DDR2 SDRAM Bank Address
TEST
VDD
SCL
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
Core Power
I/O Power
VDDQ
VSS
SDA
SA0~SA2
Par_In
Err_Out
RESET
SPD address
Ground
VREF
VDDSPD
Parity bit for the Address and Control bus
Parity error found in the Address and Control bus
Register and PLL control pin
Input/Output Reference
SPD Power
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
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Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
6.0 Input/Output Function Description
Symbol
CK0
Type
Input
Input
Description
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
CK0
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
Input
CKE0~CKE1
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-
abled, new commands are ignored but previous operations continue.
Input
S0~S3
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
Input
Input
ODT0~ODT1
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
RAS, CAS, WE
VREF
VDDQ
Supply
Reference voltage for SSTL_18 inputs
Supply
Input
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of eight is activated.
BA0~BA2
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected
and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge com-
mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define
which bank to precharge.
A0~A9,A10/AP
A11~A13
Input
DQ0~63,
In/Out
Input
Data and Check Bit Input/Output pins
CB0~CB7
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
DM0~DM8
VDD, VSS
Supply
In/Out
In/Out
Power and ground for the DDR SDRAM input buffers and core logic
DQS0~DQS17
DQS0~DQS17
SA0~SA2
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.
Input
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to VDDSPD to act as a pullup.
SDA
In/Out
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDDSPD to act as a pullup.
SCL
Input
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6
Volt operation).
VDDSPD
Supply
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-
nized with the input clock )
RESET
Input
Par_In
Err_Out
TEST
Input
Output
In/Out
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
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Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
7.0 Functional Block Diagram
7.1 1GB, 128Mx72 Module - M393T2863QZA / M393T2863QZ3
(populated as 1 rank of x8 DDR2 SDRAMs)
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 0
DQ9
I/O 1
I/O 1
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS6
DQS2
DQS6
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
V
V
V
V
Serial PD
D0 - D8
D0 - D8
D0 - D8
DDSPD
/V
DD DDQ
REF
SS
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
Serial PD
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
SCL
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
SDA
WP A0 A1 A2
SA0 SA1 SA2
Note :
DQS8
DQS8
1. DQ-to-I/O wiring may be changed within a byte.
DM8/DQS17
NC/DQS17
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. Unless otherwise noted, resister values are 22 Ohms ± 5%
DM/ NU/ CS DQS DQS
RDQS RDQS
Signals for Address and Command Parity Function
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
Register
V
V
C0
C1
SS
SS
PPO
PAR_IN
100K ohms
PAR_IN
QERR
Err_Out
The resistors on Par_In, A14, A15, and the signal
line of Err_Out refer to the section: "Register Options
for Unused Address inputs"
1:1
R
E
G
I
S0*
RSO-> CS : DDR2 SDRAMs D0-D8
BA0-BA2
A0-A13
RAS
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D8
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8
RRAS -> RAS : DDR2 SDRAMs D0-D8
RCAS -> CAS : DDR2 SDRAMs D0-D8
RWE -> WE : DDR2 SDRAMs D0-D8
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
P
L
L
CAS
S
T
E
R
WE
PCK7 -> CK : Register
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
OE
RESET
PCK7 -> CK : Register
RST
RESET
PCK7
* S0 connects to DCS and V connects to CSR on the register. S1, CKE1 and ODT are NC.
DD
PCK7
7 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
7.2 2GB, 256Mx72 Module - M393T5663QZA / M393T5663QZ3
(populated as 2 rank of x8 DDR2 SDRAMs)
RS1
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
I/O 0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
D0
D9
D4
D13
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 0
I/O 0
I/O 0
DQ9
I/O 1
I/O 1
I/O 1
I/O 1
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS6
DQS2
DQS6
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
Serial PD
DQS8
V
V
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
DQS8
SCL
SDA
DM8/DQS17
NC/DQS17
/V
DD DDQ
WP A0 A1 A2
SA0 SA1 SA2
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
REF
SS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D17
Note :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms ± 5%
3. RS0 and RS1 alternate between the back and front sides of the DIMM
S0*
RSO-> CS : DDR2 SDRAMs D0-D8
RS1-> CS : DDR2 SDRAMs D9-D17
RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RCKE1 -> CKE : DDR2 SDRAMs D9-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
RODT1 -> ODT1 : DDR2 SDRAMs D9-D17
Signals for Address and Command Parity Function
S1*
1:2
R
E
G
I
BA0-BA2
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
Register A
Register B
V
C0
C1
V
V
C0
C1
SS
DD
DD
DD
V
PPO
PPO
PAR_IN
100K ohms
PAR_IN
PAR_IN
QERR
Err_Out
S
T
QERR
E
R
The resistors on Par_In, A14, A15, and the signal line
of Err_Out refer to the section: "Register Options for
Unused Address inputs"
RST
RESET**
PCK7**
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
PCK7**
P
L
L
* S0 connects to DCS and S1 connects to CSR on a Register,
S1 connects to DCS and S0 connects to CSR on another Register.
CK0
PCK7 -> CK : Register
OE
RESET
PCK7 -> CK : Register
** RESET, PCK7 and PCK7 connects to both Registers.
Other signals connect to one of two Registers.
8 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
7.3 2GB, 256Mx72 Module - M393T5660QZA / M393T5660QZ3
(populated as 1 rank of x4 DDR2 SDRAMs)
V
SS
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D9
DQS1
DM1/DQS10
DQS1
NC/DQS10
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
D1
D10
DQ10
DQ11
DQS2
DM2/DQS11
DQS2
NC/DQS11
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
D2
D11
DQS3
DM3/DQS12
DQS3
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D12
DQS4
DM4/DQS13
DQS4
NC/DQS13
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D13
DQS5
DM5/DQS14
DQS5
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D14
Serial PD
SCL
SDA
DQS6
DM6/DQS15
WP A0 A1 A2
SA0 SA1 SA2
DQS6
NC/DQS15
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D15
DQS7
DM7DQS16
DQS7
NC/DQS16
V
V
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
/V
D7
D16
DD DDQ
REF
SS
DQS8
DM8/DQS17
DQS8
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D17
Signals for Address and Command Parity Function
Register A
Register B
V
C0
C1
V
V
C0
C1
SS
DD
DD
DD
1:2
V
R
E
G
I
S0*
RSO-> CS : DDR2 SDRAMs D0-D17
PPO
PPO
BA0-BA2
A0-A13
RAS
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
PAR_IN
PAR_IN
PAR_IN
QERR
Err_Out
QERR
100K ohms
CAS
S
T
E
R
The resistors on Par_In, A14, A15, and the signal line
of Err_Out refer to the section: "Register Options for
Unused Address inputs"
WE
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RST
RESET**
PCK7**
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
P
L
L
PCK7**
PCK7 -> CK : Register
OE
RESET
PCK7 -> CK : Register
* S0 connects to DCS of Register1 and CSR of Register2. CSR of reg-
ister 1 and DCS of register 2 connects to V
.
DD
Note :
1. DQ-to-I/O wiring may be changed per nibble.
** RESET, PCK7 and PCK7 connects to both Registers. Other signals
connect to one of two Registers. S1, CKE1 and ODT1 are NC.
2. Unless otherwise noted, resister values are 22 Ohms ± 5%
9 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
7.4 4GB, 512Mx72 Module - M393T5160QZA / M393T5160QZ3
(populated as 2 rank of x4 DDR2 SDRAMs)
V
SS
RS1
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D18
D9
D27
DQS1
DM1/DQS10
DQS1
NC/DQS10
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
I/O 1
I/O 2
I/O 3
D1
D19
D10
D28
DQ10
DQ11
DQS2
DQS2
DM2/DQS11
NC/DQS11
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
I/O 1
I/O 2
I/O 3
D2
D20
D11
D29
DQS3
DM3/DQS12
DQS3
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D21
D12
D30
DQS4
DM4/DQS13
DQS4
NC/DQS13
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D22
D13
D31
DQS5
DM5/DQS14
DQS5
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D23
D14
D32
DQS6
DM6/DQS15
DQS6
NC/DQS15
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D24
D15
D33
Serial PD
DQS7
DM7DQS16
SCL
DQS7
NC/DQS16
SDA
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
WP A0 A1 A2
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D25
D16
D34
SA0 SA1 SA2
Serial PD
V
V
V
V
DDSPD
DQS8
DM8/DQS17
DQS8
NC/DQS17
/V
D0 - D35
D0 - D35
D0 - D35
DD DDQ
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
REF
SS
CB1
CB2
CB3
D8
D26
D17
D35
S0*
S1*
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RSO-> CS : DDR2 SDRAMs D0-D17
RS1-> CS : DDR2 SDRAMs D18-D35
Signals for Address and Command Parity Function
Register A
1:2
R
E
G
I
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35
RRAS -> RAS : DDR2 SDRAMs D0-D35
The resistors on Par_In, A14,
PPO
PAR_IN
A15, and the signal line of
Err_Out refer to the section:
"Register Options for Unused
Address inputs"
QERR
RCAS -> CAS : DDR2 SDRAMs D0-D35
PAR_IN
RWE -> WE : DDR2 SDRAMs D0-D35
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RCKE1 -> CKE : DDR2 SDRAMs D18-D35
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
S
T
Err_Out
Register B
PPO
QERR
100K ohms
E
R
PAR_IN
RST
RESET**
PCK7**
PCK7**
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
* S0 connects to DCS and S1 connects to CSR on a pair of Registers,
S1 connects to DCS and S0 connects to CSR on another pair of Registers.
P
L
L
** RESET, PCK7 and PCK7 connects to all Registers.
Other signals connect to one pair of four Registers.
PCK7 -> CK : Register
OE
RESET
PCK7 -> CK : Register
10 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
7.5 8GB, 1Gx72 Module - M393T1G60QJA
(populated as 4 rank of x4 DDR2 SDRAMs)
RODT0
RCKE0
RS1
RODT1
RCKE1
RS3
RODT0
RCKE0
RS1
RODT1
RCKE1
RS3
RS0
RS2
RS0
RS2
22 Ω
DQS0
DQS0
DQ3~0
DQS
DQS
DQ3~0
DM
DQS
DQS9
DQS9
DQ7~4
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS
DQ3~0
DM
D0
D1
D2
D3
D8
D18
D19
D20
D21
D26
D9
D27
D28
D29
D30
D35
DQS1
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS10
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS1
DQS10
DQ11~8
DQ15~12
D10
D11
D12
D17
DQS2
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS11
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS2
DQS11
DQ19~16
DQ23~20
DQS3
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS12
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS3
DQS12
DQ27~24
DQ31~28
DQS8
DQS8
CB3~0
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS17
DQS17
CB7~4
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
RODT0
RCKE0
RS1
RODT1
RCKE1
RS3
RODT0
RCKE0
RS1
RODT1
RCKE1
RS3
RS0
RS2
RS0
RS2
DQS4
DQS
DQS
DQ3~0
DM
DQS
DQS13
DQS
DQS
DQ3~0
DM
DQS
DQS4
DQS
DQ3~0
DM
DQS13
DQS
DQ3~0
DM
DQ35~32
DQ39~36
D4
D5
D6
D7
D22
D23
D24
D25
D13
D14
D15
D16
D31
D32
D33
D34
DQS5
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS14
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS5
DQS14
DQ43~40
DQ47~44
DQS6
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS15
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS6
DQS15
DQ51~48
DQ55~52
DQS7
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS16
DQS
DQS
DQ3~0
DM
DQS
DQS
DQ3~0
DM
DQS7
DQS16
DQ59~56
DQ63~60
Register
PARIN
PTYERR
Register
0 Ω
0 Ω
100 KΩ
PAR_IN
ERR_OUT
S0,2*
RS0-> CS0 : DDR2 SDRAMs D0-D17, RS2-> CS0 : DDR2 SDRAMs D18-D35
PARIN
PTYERR
S1,3**
BA0-BA2
A0-A15
RAS
RS1-> CS1 : DDR2 SDRAMs D0-D17, RS3-> CS1 : DDR2 SDRAMs D18-D35
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35
RRAS -> RAS : DDR2 SDRAMs D0-D35
1:2
R
E
G
I
Serial PD
SCL
SDA
CAS
RCAS -> CAS : DDR2 SDRAMs D0-D35
WP A0 A1 A2
SA0 SA1 SA2
WE
RWE -> WE : DDR2 SDRAMs D0-D35
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
S
T
E
R
CKE0
CKE1
ODT0
ODT1
RCKE1 -> CKE : DDR2 SDRAMs D18-D35
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
P
L
CK0
CK0
PCK7-> CK : Register
PCK7-> CK : Register
PCK0-PCK6, PCK8, PCK9-> CK : DDR2 SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9-> CK : DDR2 SDRAMs D0-D35
RST
RESET**
L
PCK7**
OE
RESET
PCK7**
* S0 connects to DCS0, S1 to DCS1 on the first register, S2 connects DCS0, S3 connects DCS1, on the secon register
S2 and S3 have required pull up resistors (100K ohms), not indicated here.
**A14-15 have optional pull down resistors (100K ohms), not indicated here.
11 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
8.0 Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Rating
Units
V
Notes
Voltage on VDD pin relative to VSS
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VDDQ
VDDL
V
V
1
V
IN, VOUT
TSTG
Note :
V
1
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
9.0 AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Typ.
1.8
Symbol
Parameter
Units
Notes
Min.
1.7
Max.
1.9
VDD
VDDL
VDDQ
VREF
VTT
Supply Voltage
V
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
1.7
1.8
1.9
V
0.49*VDDQ
VREF-0.04
0.50*VDDQ
VREF
0.51*VDDQ
VREF+0.04
mV
V
1,2
3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal
to VDD
.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
12 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
9.2 Operating Temperature Condition
Symbol
TOPER
Parameter
Operating Temperature
Rating
0 to 95
Units
°C
Notes
1, 2
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
9.3 Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
VIH(DC)
DC input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL(DC)
DC input logic low
- 0.3
VREF - 0.125
V
9.4 Input AC Logic Level
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Min. Max.
Symbol
Parameter
Units
Min.
Max.
VIH(AC)
VIL(AC)
AC input logic high
AC input logic low
VREF + 0.250
-
-
VREF + 0.200
-
-
V
V
VREF - 0.250
VREF - 0.200
9.5 AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
VSWING(MAX)
SLEW
Input reference voltage
0.5 * VDDQ
V
1
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
1
V/ns
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
(DC) max
IL
(AC) max
IL
SS
delta TF
V
delta TR
Rising Slew =
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
delta TF
< AC Input Test Signal Waveform >
13 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
10.0 IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
Proposed Conditions
Units
Note
Operating one bank active-precharge current;
IDD0
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
IDD1
mA
Precharge power-down current;
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
mA
mA
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0
mA
mA
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD4W
IDD4R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-
max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
mA
mA
Burst auto refresh current;
IDD5B
IDD6
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
Normal
mA
mA
CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid com-
mands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following
page for detailed timing conditions
IDD7
mA
14 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
11.0 Operating Current Table
11.1 M393T2863QZA / M393T2863QZ3 : 1GB(128Mx8 *9) Module
(TA=0oC, VDD= 1.9V)
Symbol
IDD0
IDD1
E7(800@CL=5) F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Units
Notes
675
765
675
765
630
720
585
675
135
270
315
315
162
405
855
900
1,215
135
2,070
585
675
135
270
315
315
162
405
810
855
1,170
135
2,025
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
135
135
135
270
270
270
315
315
315
315
315
315
162
162
162
495
495
450
1,035
1,215
1,305
135
1,035
1,215
1,305
135
945
1,080
1,260
135
IDD7
2,250
2,250
2,070
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.2 M393T2863QZA : 1GB(128Mx8 *9) Module
- considering Register and PLL current value
(TA=0oC, VDD= 1.9V)
E7(800@CL=5) F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Units Notes
Symbol
IDD0
IDD1
1,265
1,405
615
800
795
1,265
1,405
615
800
795
1,130
1,270
575
730
735
785
632
920
1,395
1,590
1,810
135
995
1,135
535
660
675
705
552
805
1,235
1,330
1,645
135
905
1,045
495
590
615
625
472
735
1,120
1,205
1,480
135
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
865
712
865
712
1,035
1,555
1,805
1,975
135
1,035
1,555
1,805
1,975
135
IDD7
2,940
2,940
2,650
2,540
2,385
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
15 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
(TA=0oC, VDD= 1.9V)
11.3 M393T5663QZA / M393T5663QZ3 : 2GB(128Mx8 *18) Module
Symbol
IDD0
IDD1
E7(800@CL=5)
990
F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Units
Notes
990
1,080
270
945
1,035
270
900
990
270
900
990
270
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1,080
270
540
630
630
324
810
1,350
1,530
1,620
270
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
540
540
540
540
630
630
630
630
630
630
630
630
324
324
324
324
810
765
720
720
1,350
1,530
1,620
270
1,260
1,395
1,575
270
1,170
1,215
1,530
270
1,125
1,170
1,485
270
IDD7
2,565
2,565
2,385
2,385
2,340
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.4 M393T5663QZA : 2GB(128Mx8 *18) Module
- considering Register and PLL current value
(TA=0oC, VDD= 1.9V)
F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3) Units Notes
Symbol
IDD0
IDD1
E7(800@CL=5)
1,680
1,850
910
1,680
1,850
910
1,535
1,695
850
1,390
1,540
790
1,290
1,430
730
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,250
1,200
1,360
1,054
1,370
2,000
2,320
2,450
270
1,250
1,200
1,360
1,054
1,370
2,000
2,320
2,450
270
1,160
1,130
1,260
954
1,255
1,820
2,075
2,255
270
1,070
1,060
1,160
854
1,140
1,640
1,785
2,060
270
980
990
1,060
754
1,070
1,505
1,630
1,865
270
IDD7
3,595
3,595
3,255
3,095
2,890
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
16 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
11.5 M393T5660QZA / M393T5660QZ3 : 2GB(256Mx4 *18) Module
(TA=0oC, VDD= 1.9V)
Symbol
IDD0
IDD1
E7(800@CL=5) F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3)
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1,350
1,530
270
1,350
1,530
270
1,260
1,440
270
1,170
1,350
270
1,170
1,350
270
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
540
540
540
540
540
630
630
630
630
630
630
630
630
630
630
324
324
324
324
324
990
990
900
810
810
1,980
2,340
2,520
270
1,980
2,340
2,520
270
1,800
2,070
2,430
270
1,620
1,620
2,340
270
1,530
1,530
2,250
270
IDD7
4,410
4,410
4,050
4,050
3,960
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.6 M393T5660QZA : 2GB(256Mx4 *18) Module
- considering Register and PLL current value
(TA=0oC, VDD= 1.9V)
Symbol
IDD0
IDD1
E7(800@CL=5) F7(800@CL=6) E6(667@CL=5) D5(533@CL=4) CC(400@CL=3)
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
2,040
2,300
910
2,040
2,300
910
1,850
2,100
850
1,660
1,900
790
1,560
1,790
730
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,250
1,200
1,360
1,054
1,550
2,630
3,130
3,350
270
1,250
1,200
1,360
1,054
1,550
2,630
3,130
3,350
270
1,160
1,130
1,260
954
1,390
2,360
2,750
3,110
270
1,070
1,060
1,160
854
1,230
2,090
2,190
2,870
270
980
990
1,060
754
1,160
1,910
1,990
2,630
270
IDD7
5,440
5,440
4,920
4,760
4,510
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
17 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
(TA=0oC, VDD= 1.9V)
11.7 M393T5160QZA / M393T5160QZ3 : 4GB(256Mx4 *36) Module
Symbol
IDD0
IDD1
E7(800@CL=5)
1,980
2,160
540
F7(800@CL=6)
1,980
2,160
540
E6(667@CL=5)
1,890
2,070
540
D5(533@CL=4)
1,800
1,980
540
CC(400@CL=3)
1,800
1,980
540
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,080
1,260
1,260
648
1,620
2,610
2,970
3,150
540
1,080
1,260
1,260
648
1,620
2,610
2,970
3,150
540
1,080
1,260
1,260
648
1,530
2,430
2,700
3,060
540
1,080
1,260
1,260
648
1,440
2,250
2,250
2,970
540
1,080
1,260
1,260
648
1,440
2,160
2,160
2,880
540
IDD7
5,040
5,040
4,680
4,680
4,590
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.8 M393T5160QZA : 4GB(256Mx4 *36 ) Module
- considering Register and PLL current value
(TA=0oC, VDD= 1.9V)
Symbol
E7(800@CL=5)
F7(800@CL=6)
E6(667@CL=5)
D5(533@CL=4)
CC(400@CL=3)
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD0
3,000
3,000
2,760
2,520
2,370
IDD1
3,320
3,320
3,070
2,820
2,660
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,490
2,140
2,060
2,350
1,738
2,410
3,600
4,060
1,490
2,140
2,060
2,350
1,738
2,410
3,600
4,060
1,400
2,000
1,960
2,200
1,588
2,220
3,280
3,640
1,310
1,860
1,860
2,050
1,438
2,030
2,960
3,040
1,220
1,720
1,760
1,900
1,288
1,930
2,730
2,800
4,370
540
4,370
540
4,060
540
3,750
540
3,440
540
IDD7
6,750
6,750
6,130
5,870
5,520
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
18 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
11.9 M393T1G60QJA : 8GB(DDP512Mx4 *36 ) Module
(TA=0oC, VDD= 1.9V)
Symbol
IDD0
IDD1
E6(667@CL=5)
3,150
D5(533@CL=4)
3,060
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
3,330
1,080
2,160
2,520
2,520
1,296
2,790
3,690
3,960
4,320
1,080
5,940
3,240
1,080
2,160
2,520
2,520
1,296
2,700
3,420
3,420
4,140
1,080
5,850
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
IDD7
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.10 M393T1G60QJA : 8GB(DDP512Mx4 *36 ) Module
- considering Register and PLL current value (TA=0oC, VDD= 1.9V)
Symbol
IDD0
IDD1
E6(667@CL=5)
4,020
D5(533@CL=4)
3,780
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
4,330
1,940
3,080
3,220
3,460
2,236
3,480
4,540
4,900
5,320
1,080
7,390
4,080
1,850
2,940
3,120
3,310
2,086
3,290
4,220
4,300
5,010
1,080
7,130
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
IDD7
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
19 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
12.0 Input/Output Capacitance
(VDD=1.8V, VDDQ=1.8V, TA=25°C)
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Sym.
Units
M393T2863QZA M393T5663QZA M393T5660QZA M393T5160QZA
M393T2863QZ3 M393T5663QZ3 M393T5660QZ3 M393T5160QZ3
Part-Number
M393T1G60QJA
Input capacitance, CK and CK
Input capacitance, CKE and CS
CCK
CI1
-
-
11
12
-
-
11
12
-
-
11
12
-
-
11
12
-
-
11
12
Input capacitance, Address,
RAS,CAS,WE
pF
CI2
-
-
12
10
-
-
12
10
-
-
12
10
-
-
12
10
-
-
12
10
Input/output capacitance,
DQ, DM, DQS, DQS
CIO
* DM is internally loaded to match DQ and DQS identically.
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
13.1 Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
75
105
127.5
7.8
195
7.8
327.5
7.8
ns
0 °C ≤ TCASE ≤ 85°C
7.8
3.9
7.8
3.9
µs
µs
Average periodic refresh interval
tREFI
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin(CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tCK, CL=6
tRCD
DDR2-800(E7)
5-5-5
DDR2-800(F7)
6 - 6 - 6
DDR2-667(E6)
5 - 5 - 5
DDR2-533(D5)
4 - 4 - 4
DDR2-400(CC)
3 - 3 - 3
Units
min
5
max
8
min
-
max
-
min
5
max
8
min
5
max
8
min
5
max
8
ns
ns
ns
ns
ns
ns
ns
ns
3.75
2.5
-
8
3.75
3
8
3.75
3
8
3.75
3.75
-
8
5
8
8
8
8
8
-
-
-
2.5
15
15
60
45
8
-
-
-
-
-
12.5
12.5
57.5
45
-
-
15
15
60
45
-
15
-
15
15
55
40
-
tRP
-
-
-
-
-
-
15
-
-
-
-
tRC
60
tRAS
70000
70000
70000
45
70000
70000
20 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)
(Refer to notes for informations related to this table at the component datasheet)
DDR2-800
DDR2-667
Parameter
Symbol
Units
Notes
min
-400
-350
0.48
0.48
max
400
min
max
450
DQ output access time from CK/CK
DQS output access time from CK/CK
Average clock HIGH pulse width
Average clock LOW pulse width
tAC
-450
-400
0.48
0.48
ps
40
40
tDQSCK
tCH(avg)
tCL(avg)
350
400
ps
0.52
0.52
0.52
0.52
tCK(avg)
tCK(avg)
35,36
35,36
Min(tCL(abs),
tCH(abs))
Min(tCL(abs),
tCH(abs))
CK half pulse period
tHP
x
x
ps
37
Average clock period
tCK(avg)
tDH(base)
tDS(base)
tIPW
2500
8000
3000
8000
ps
ps
35,36
DQ and DM input hold time
125
x
175
x
6,7,8,21,28,31
6,7,8,20,28,31
DQ and DM input setup time
50
x
100
x
ps
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS/DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
0.6
x
0.6
x
tCK(avg)
tCK(avg)
ps
tDIPW
tHZ
0.35
x
0.35
x
x
tAC(max)
x
tAC(max)
18,40
18,40
18,40
13
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC(min)
tAC(max)
tAC(min)
tAC(max)
ps
2* tAC(min)
tAC(max)
2* tAC(min)
tAC(max)
ps
x
x
200
300
x
x
x
240
340
x
ps
ps
38
DQ/DQS output hold time from DQS
DQS latching rising transitions to associated clock edges
DQS input HIGH pulse width
tQH
tHP - tQHS
- 0.25
0.35
0.35
0.2
tHP - tQHS
-0.25
0.35
0.35
0.2
ps
39
tDQSS
tDQSH
tDQSL
tDSS
0.25
x
0.25
x
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
nCK
30
DQS input LOW pulse width
x
x
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
MRS command to ODT update delay
Write postamble
x
x
30
30
tDSH
0.2
x
0.2
x
tMRD
2
x
2
x
tMOD
0
12
0.6
x
0
12
0.6
x
ns
32
10
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
0.4
0.4
tCK(avg)
tCK(avg)
ps
Write preamble
0.35
250
175
0.9
0.35
275
200
0.9
Address and control input hold time
Address and control input setup time
Read preamble
x
x
5,7,9,23,29
5,7,9,22,29
19,41
x
x
ps
1.1
0.6
x
1.1
0.6
x
tCK(avg)
tCK(avg)
ns
Read postamble
0.4
0.4
19,42
Activate to activate command period for 1KB page size products tRRD
Activate to activate command period for 2KB page size products tRRD
7.5
7.5
4,32
10
x
10
x
ns
4,32
21 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
DDR2-800
DDR2-667
Notes
Parameter
Symbol
Units
min
max
min
max
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
tFAW
tFAW
tCCD
tWR
35
x
x
x
x
x
x
x
x
x
x
x
37.5
x
x
x
x
x
x
x
x
x
x
x
ns
ns
32
32
45
50
2
2
nCK
ns
Write recovery time
15
15
32
33
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
WR + tnRP
WR + tnRP
nCK
ns
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
7.5
24,32
3,32
32
7.5
7.5
ns
tRFC + 10
tRFC + 10
ns
200
2
200
2
nCK
nCK
nCK
Exit precharge power down to any command
Exit active power down to read command
tXARD
2
2
1
Exit active power down to read command
(slow exit, lower power)
tXARDS
8 - AL
x
7 - AL
x
nCK
1,2
CKE minimum pulse width (HIGH and LOW pulse width)
tCKE
3
2
x
3
2
x
nCK
nCK
ns
27
16
ODT turn-on delay
ODT turn-on
tAOND
tAON
2
2
tAC(min)
tAC(max)+0.7
tAC(min)
tAC(max)+0.7
6,16,40
2*tCK(avg)
2*tCK(avg)
ODT turn-on (Power-Down mode)
tAONPD
tAC(min)+2
tAC(min)+2
ns
+tAC(max)+1
+tAC(max)+1
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
nCK
ns
17,45
tAC(min)
tAC(max)+0.6
tAC(min)
tAC(max)+0.6
17,43,45
2.5*tCK(avg)
+tAC(max)+1
2.5*tCK(avg)
+tAC(max)+1
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
tAC(min)+2
ns
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
x
x
3
8
0
x
x
nCK
nCK
ns
12
12
32
15
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tIS+tCK(avg)
+tIH
tIS+tCK(avg)
+tIH
tDelay
x
x
ns
22 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)
(Refer to notes for informations related to this table at the component datasheet)
DDR2-533
DDR2-400
Parameter
Symbol
Units
Notes
min
max
min
-600
-500
0.45
0.45
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK HIGH pulse width
tAC
-500
500
600
ps
ps
tDQSCK
tCH
-450
450
500
0.45
0.55
0.55
tCK
tCK
ps
CK LOW pulse width
tCL
0.45
0.55
0.55
CK half pulse period
tHP
Min(tCL, tCH)
x
Min(tCL, tCH)
x
11,12
15
Clock cycle time, CL=x
tCK
3750
8000
5000
275
8000
ps
DQ and DM input hold time (differential strobe)
DQ and DM input setup time (differential strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input setup time (single-ended strobe)
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS(/DQS) low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tDH(base)
tDS(base)
tDH1(base)
tDS1(base)
tIPW
225
x
x
ps
6,7,8,21,28
6,7,8,20,28
6,7,8,26
6,7,8,25
100
x
150
x
ps
-25
x
25
x
ps
-25
x
25
x
ps
0.6
x
0.6
x
tCK
tCK
ps
tDIPW
tHZ
0.35
x
0.35
x14
x
x
tAC(max)
tAC(max)
18
18
18
13
12
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tAC(min)
tAC(max)
tAC(min)
2* tAC(min)
x
tAC(max)
ps
2* tAC(min)
tAC(max)
tAC(max)
ps
x
x
300
400
x
350
450
x
ps
x
ps
DQ/DQS output hold time from DQS
DQS latching rising transitions to associated clock edges
DQS input HIGH pulse width
tQH
tHP - tQHS
-0.25
0.35
0.35
0.2
tHP - tQHS
-0.25
0.35
0.35
0.2
ps
tDQSS
tDQSH
tDQSL
tDSS
0.25
x
0.25
x
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS input LOW pulse width
x
x
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
MRS command to ODT update delay
Write postamble
x
x
tDSH
0.2
x
0.2
x
tMRD
2
x
2
x
tMOD
0
12
0.6
x
0
12
0.6
x
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
tRRD
0.4
0.4
tCK
tCK
ps
10
Write preamble
0.35
375
250
0.9
0.35
475
Address and control input hold time
Address and control input setup time
Read preamble
x
x
5,7,9,23
x
350
x
ps
5,7,9,22
1.1
0.6
x
0.9
1.1
0.6
x
tCK
tCK
ns
19
19
4
Read postamble
0.4
0.4
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
7.5
7.5
tRRD
10
x
10
x
ns
4
23 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
DDR2-533
DDR2-400
Parameter
Symbol
tFAW
Units
Notes
min
37.5
50
max
min
37.5
50
max
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ns
ns
tFAW
tCCD
tWR
2
2
tCK
ns
Write recovery time
15
15
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
WR+tRP
WR+tRP
tCK
ns
14
24
3
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
10
7.5
7.5
ns
tRFC + 10
tRFC + 10
ns
200
2
200
2
tCK
tCK
tCK
Exit precharge power down to any non-read command
Exit active power down to read command
tXARD
2
2
1
Exit active power down to read command
(slow exit, lower power)
tXARDS
6 - AL
x
6 - AL
x
tCK
1,2
CKE minimum pulse width (HIGH and LOW pulse width)
tCKE
3
2
x
3
2
x
tCK
tCK
ns
27
16
16
ODT turn-on delay
ODT turn-on
tAOND
tAON
2
2
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
2tCK+
2tCK+
ODT turn-on (Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
tAC(min)+2
2.5
tAC(min)+2
2.5
ns
tCK
ns
tAC(max)+1
tAC(max)+1
2.5
2.5
17,44
17,44
tAC(max)
+ 0.6
tAC(max)
+ 0.6
ODT turn-off
tAC(min)
tAC(min)
2.5tCK+
2.5tCK+
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
tAC(min)+2
ns
tAC(max)+1
tAC(max)+1
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
x
x
3
8
0
x
x
tCK
tCK
ns
12
12
32
15
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tDelay
tIS+tCK+tIH
x
tIS+tCK+tIH
x
ns
24 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
14.0 Physical Dimensions :
14.1 128Mbx8 based 128Mx72 Module (1 Rank)
Units : Millimeters
2.70 max
- M393T2863QZA / M393T2863QZ3
30.00
PLL
1.0 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 128M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QQ
25 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
14.2 128Mbx8/256Mbx4 based 256Mx72 Module (2/1 Ranks)
Units : Millimeters
- M393T5663QZA/M393T5660QZA
/M393T5663QZ3/M393T5660QZ3
133.35
4.00 max
30.00
PLL
1.0 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 128M x8 / 256M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QQ / K4T1G044QQ
26 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
14.3 256Mbx4 based 512Mx72 Module (2 Ranks)
Units : Millimeters
- M393T5160QZA/M393T5160QZ3
133.35
4.00 max
PLL
30.00
1.0 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 256M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G044QQ
27 of 29
Rev. 1.1 July 2008
RDIMM
DDR2 SDRAM
14.4 DDP 512Mbx4 based 1Gx72 Module (4 Ranks)
- M393T1G60QJA
Units : Millimeters
133.35
7.55 max
30.00
1.0 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is DDP 512M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T2G044QQ
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RDIMM
DDR2 SDRAM
15.0 240 Pin DDR2 Registered DIMM Clock Topology
0ns (nominal)
PLL
DDR2 SDRAM
120 ohms
OUT1
CK0
120 ohms
IN
DDR2 SDRAM
Reg.A
CK0
120 ohms
OUTN
120 ohms
C
C
Feedback In
Feedback Out
Reg.B
Note:
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
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