M395T2953EZ4-CE660_技术文档

FBDIMM

DDR2 SDRAM

DDR2 Fully Buffered DIMM

240pin FBDIMMs based on 512Mb E-die

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure couldresult in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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FBDIMM

DDR2 SDRAM

Table of Contents

1. FEATURES .......................................................................................................................................4

2.0 FBDIMM GENERALS .....................................................................................................................5

2.1 FB-DIMM Operation Overview ..........................................................................................................5

2.2 FB-DIMM Channel Frequency Scaling ...............................................................................................6

2.3 FB-DIMM Clocking Scheme .............................................................................................................7

2.4 FB-DIMM Protocol ..........................................................................................................................7

2.5 Southbound Command Delivery ......................................................................................................8

2.6 Basic Timing Diagram .....................................................................................................................9

2.7 Advanced Memory Buffer Block Diagram ........................................................................................11

2.8 Interfaces.................................................................................................................................... 12

3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE ...............12

3.1 DDR2 Channel .............................................................................................................................12

3.2 SMBus Slave Interface ..................................................................................................................12

3.3 FBD Channel Latency ...................................................................................................................13

3.4 Peak Theoretical Throughput .........................................................................................................13

3.5 Hot-add .......................................................................................................................................13

3.6 Hot remove ..................................................................................................................................13

3.7 Hot replace ..................................................................................................................................13

4.0 PIN CONFIGUREATION ..............................................................................................................14

5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM ...............................................................................16

5.1 512MB, 64Mx72 Module - M395T6553EZ4 ........................................................................................16

5.2 1GB, 128Mx72 Module - M395T2953EZ4 ..........................................................................................17

5.3 2GB, 256Mx72 Module - M395T5750EZ4 ..........................................................................................18

6.0 ELECTRICAL CHARACTERISTICS ............................................................................................19

7.0 CHANNEL INITIALIZATION ........................................................................................................25

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FBDIMM

DDR2 SDRAM

Revision History

Revision

Month

November

January

February

April

Year

2006

2007

History

1.0

1.1

- First Released.

- Added AMB revision

1.2

1.3

- Added IDTA1.5 FBD, Corrected DIMM Thickness(8.0mm to 8.2mm)

- Changed AMB device operation temperature symbol(Tj to Tcase)

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FBDIMM

DDR2 SDRAM

1. FEATURES

- 240pin fully buffered dual in-line memory module (FB-

- Channel fail over mode support

DIMM)

- Serial presence detect with EEPROM

- 4 Banks

- 3.2Gb/s, 4.0Gb/s link transfer rate

- 1.8V +/- 0.1V Power Supply for DRAM VDD/VDDQ

- 1.5V +0.075/-0.045V Power Supply for AMB VCC

- 3.3V +/- 0.3V Power Supply for VDDSPD

- Buffer Interface with high-speed differential point-to-

point Link at 1.5 volt

- Posted CAS

- Programmable CAS Latency: 3, 4, 5

- Automatic DDR2 DRAM bus and channel calibration

- MBIST and IBIST Test functions

- Hot add-on and Hot Remove Capability

- Transparent mode for DRAM test support

- Channel error detection & reporting

Table 1 : Ordering Information

Number of

Rank

Type of Heat

Spreader

Part Number

Density Organization

Component Composition

AMB

Height

M395T6553EZ4-CD55/E65

M395T6553EZ4-CD56/E66

M395T6553EZ4-CD52/E62

M395T6553EZ4-CD51/E61

M395T2953EZ4-CD55/E65

M395T2953EZ4-CD56/E66

M395T2953EZ4-CD52/E62

M395T2953EZ4-CD51/E61

M395T5750EZ4-CD55/E65

M395T5750EZ4-CD56/E66

M395T5750EZ4-CD52/E62

M395T5750EZ4-CD51/E61

Intel D1

IDT C1

64Mx8(K4T51083QE)

* 9EA

512MB

1GB

64M x 72

128M x 72

256M x 72

1

2

NEC B5+

IDT A1.5

Intel D1

IDT C1

64Mx8(K4T51083QE)

* 18EA

Full Module

30.35mm

NEC B5+

IDT A1.5

Intel D1

IDT C1

128Mx4(K4T51043QE)

* 36EA

2GB

NEC B5+

IDT A1.5

Note :

1. “Z” of Part number(11th digit) stands for Lead-free products.

2. The last digit stands for AMB.

Table 2 : Performance range

E6(DDR2-667)

D5(DDR2-533)

533

Unit

Mbps

CK

DDR2 DRAM Speed

CL-tRCD-tRP

667

5-5-5

4-4-4

Table 3 : Address Configuration

Organization

64Mx8(512Mb) based Module

128Mx4(512Mb) based Module

Row Address

Column Address

A0-A9

Bank Address

Auto Precharge

A0-A13

BA0-BA1

A10

A0-A9, A11

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FBDIMM

DDR2 SDRAM

2.0 FBDIMM GENERALS

2.1 FB-DIMM Operation Overview

FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth and

scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited

density build-up as channel speeds increase with memory system having the stub-bus architecture. FB-DIMM solution is intended to

eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be connected serially to

a given channel.

Memory system architecture perspective, FB-DIMM is fully differentiated from Registered DIMM and Unbuffered DIMM. A lot of new

technologies are integrated into this solution in order to achieve this scalable higher speed memory solution. Serial link interface with

packet data format and dedicated read/write paths are key attribute in FB-DIMM protocol. Point to Point interconnect with fully differential

signaling and de-emphasis scheme are key attribute in FBD channel link. Clock recovery by using data stream is key attribute in FBD

clocking. FB-DIMM supports both clock resync and resampling mode options. CRC (Cyclic Redundancy Check) bits are transferred with

data stream for reliability at high speed data transaction. Failover mechanism supports system running with dynamic IO failure. Finally all

FB-DIMM is connected in daisy chain manner. Thus, every interconnection between AMB (advanced memory buffer) to AMB, AMB to

Host and AMB to DRAM, is point to point interconnection which allows higher data transfer bandwidth.

Figure 1 shows a lot of new technologies integrated with FBD solution.

Figure 1 : FB-DIMM Memory System Overview

DRAM

Two unidirectional links

Protocol Packet

DRAM

- Northbound

- Southbound

ADDR.CMD, DATA

DQs ADDR CLK

CMD

Daisy Chain

Connection

Upto 8 AMB

SB (ADDR, CMD, Wdata)

NB(Rdata)

Rx

Tx

Clk_Ref

Tx

Rx

Tx

AMB

Rx

Host

ADDR

CMD

DQs

CLK

DRAM

DIMM Topology

P2P Interconnect

- LVDS

Reliability

Fly-by CLK, CMD

Clock Recovery

- CRC fail-over

- De-Emphasis

FIFO

Buffer

Clock

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DDR2 SDRAM

2.2 FB-DIMM Channel Frequency Scaling

There are many frequency parameters including reference clock frequency, DRAM clock frequency, DRAM data transfer rate, channel

transfer rate and channel unit interval. All of frequency parameters are scaled with a certain gear ratio. External clock source provides

reference clock input to AMB and Host. External clock source is relatively slower than channel and DRAM frequency. Thus, AMB dou-

bles external clock input and generates clock inputs to DRAMs. DRAM use clock input from AMB which is two times faster than refer-

ence clock for DRAM operation. DRAM data transfer rate is two times faster than DRAM clock input with nature of double data rate

operation and four times faster than external clock source. Channel speed is represented by unit interval - average time interval between

voltage transitions of a signal in the FBD channel. It is six times faster than DRAM data transfer rate. For example, external clock source

gives 6ns clock (166MHz), AMB doubles it and gives 3ns clock (333MHz) to DRAM and FBD channel communicate with unit interval -

250ps (4.0Gbps transfer rate).

Figure 2 shows frequency scale ratio over frequency parameters in FBD memory system.

Figure 2 : FB-DIMM Speed Scaling

DDR667 Ex.

6ns

3ns

CLK_REF

DRAM

CLK_DRAM

250ps Packet T/F

12 UIs in one CLK_DRAM

SB (ADDR, CMD, Wdata)

DQs ADDR CLK

CMD

Rx

Tx

Clk_Ref

Tx

Rx

AMB

Host

NB(Rdata)

DRAM

Reference CLK

Clock

UI

312.5ps

250ps

CLK_DRAM

266MHz

CLK_REF

133MHz

166MHz

200MHz

Frequency

3.2Gb/s

DDR2-533

DDR2-667

DDR2-800

333MHz

4.0Gb/s

208.33ps

400MHz

4.8Gb/s

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FBDIMM

DDR2 SDRAM

2.3 FB-DIMM Clocking Scheme

In FB-DIMM platform design, phase adjustment among reference clock inputs to each individual AMB and host is not taken account.

Thus, clock synchronization is made by using both external reference clock and channel data stream in FB-DIMM memory system. Host

and each individual AMB has a each individual IO basis clock recovery circuitry for channel data communication. It runs with inputs from

PLL inside chip and data stream from the other AMB or Host. Because data stream itself involves data communication process, no sig-

naling switching or data communication may loss clock synchronization between transmitter and receiver. Thus, min transition density is

defined for this purpose. In FBD channel, a density of 6 transitions within 512 transfers or unit intervals (UI) on the channel is required for

interpolator training.

Figure 3 : FB-DIMM Clocking

Min. Transition Density

6 Transitions

Using Reference CLK (Not in Phase)

Adjust edge/phase by; Min. Transition Density

DRAM

512 Transfers

DQs ADDR CLK

CMD

Rx

Tx

Rx

SB (ADDR, CMD, Wdata)

AMB

Tx

Clk_Ref

Host

NB(Rdata)

DRAM

Clock

Reference CLK

Recovery

Clock

2.4 FB-DIMM Protocol

FB-DIMM channel has two unidirectional communication paths - south bound and north bound. South bound and north bound use phys-

ically different signal path. South and north mean direction of signal transaction. Southbound means direction of signals running from the

host controller toward the DIMMs. North is the opposite of south. Due to nature of memory operation, southbound carries information

including command to DRAM, address to DRAM and write data to DRAM, while north bound carries read data from DRAM. In channel

protocol point of view, southbound and northbound have different data frame formats and frame format size is optimized to ratio of read

and write. Data transfer perspective, read data transfer rate of north bound is twice faster than write data transfer. Higher channel utiliza-

tion achieves with asymmetric read and write data transfer rate.

Figure 4 : Southbound / Northbound Frame format

Sout bound

Northbound

Command (with Address)

A CMD

B CMD

C CMD

R_Data(x72bits)

Command (with Address)

or Write Data in

R_Data(x72bits)

Command (with Address)

or Write Data in

Southbound consists of 10 differential signal pairs (lane), physically 20 signaling line. Southbound Format has 10x12 (10 IO (or Lane) x

12 IO switching) frame format, which deliver 10x12 bit information per one DRAM clock. One south bound frame is divided into three

command slot. See figure 5. Command slot A delivers command (with address). Command slot B and C delivers command (with

address) or write data into DRAM.

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FBDIMM

DDR2 SDRAM

Figure 5 : FBDIMM Command Encoding & SB Frame

Southbound Command Frame Format*

Bit

9

8

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

8

9

aE0 aE7 aE8 F0=0 aC20 aC16 aC12 aC8 aC4 aC0

aE1 aE6 aE9 F1=0 aC21 aC17 aC13 aC9 aC5 aC1

aE2 aE5 aE10 aE13 aC22 aC18 aC14 aC10 aC6 aC2

aE3 aE4 aE11 aE12 aC23 aC19 aC15 aC11 aC7 aC3

CLK_REF

CLK_DRAM

Packet T/F

A CMD

B CMD

C CMD

FE21

FE20

FE19

FE18

FE17

FE16

0

bC20 bC16 bC12 bC8 bC4 bC0

bC21 bC17 bC13 bC9 bC5 bC1

bC22 bC18 bC14 bC10 bC6 bC2

bC23 bC19 bC15 bC11 bC7 bC3

cC20 cC16 cC12 cC8 cC4 cC0

cC21 cC17 cC13 cC9 cC5 cC1

cC22 cC18 cC14 cC10 cC6 cC2

cC23 cC19 cC15 cC11 cC7 cC3

x10 bits

10 FE15

11 FE14

FE0 FE7 FE11

FE1 FE6 FE10

FE2 FE5 FE9 FE13

FE3 FE4 FE8 FE12

12 transfers

Note :

1. aE[0~12] : CRC Checksum of the A Command

2. F[0~1] : Frame Type

3. FE[0~21] : CRC Checksum of 72bit data

4. CRC : Cyclic Redundancy Check

DRAM Cmnds

23

22

21

20

1

0

19

18

17

16

X

15

X

14

X

13

X

12

11

10

9

8

7

6

5

4

3

2

1

0

Activate

Write

Read

DS2 DS1 DS0

DRAM Addr RS

DRAM Bank & Address

1

0

1

0

1

RS

Precharge All

1

0

1

0

1

0

X

Precharge Single

Auto (CBR) Refresh

Enter Self Refresh

DRAM Bank

X

Exit Self Refresh/

DS2 DS1 DS0

0

1

RS

X

0

1

X

Exit Power Down

Enter Power Down

reserved

DS2 DS1 DS0

0

1

RS

X

0

1

0

X

Note : The values in “ X” fields in non-reserved commands above may be driven onto the DRAM device pins.

2.5 Southbound Command Delivery

A DRAM command located in the "A" command may be delivered to the DRAM devices as soon as the 14-bit (10-bits in fail-over) CRC

is checked. This minimizes DRAM access latency by allowing the command to be delivered after the first 4 transfers of the frame have

been received. The "A" command is transferred immediately to the DRAM pins with minimum delay whereas the "B" and "C" command

are delivered one DRAM clock later. To minimize memory access latency the read related Activate, Read (if the page is open) and

explicit Precharge commands to a rank of DRAM devices should be placed in the "A" command, if possible. Figure 6 illustrates the deliv-

ery of the three potential commands in a frame to three separate DRAM channels.

Command "A" is delivered in this case to the DRAM devices on DIMM 3 as soon as the command can traverse the AMB buffer. The "B"

and "C" commands are delayed and presented to two other DRAM channels on the following clock. See below figure7~10 for Basic

Read & Write Operations

Northbound consists of 14 differential signal pairs (lane), physically 28 signaling line. Southbound Format has 14x12 (14 IO (or Lane) x

12 IO switching) frame format, which deliver 14x12 bit information per one DRAM clock. One north bound frame is divided into two. Both

frame deliver read data from DRAM

Figure 6 : FBDIMM Command Delivery Rules

1

2

3

4

5

“A”

“B”

“C”

FBD southbound

cmd/data

1. CMD A transferred immediately

2. CMD A, B, C cannot target the same DIMM

3. Host is responsible for scheduling CMD

DIMM 1 cmd

DIMM 2 cmd

“C”

“B”

DIMM 3 cmd

DIMM 4 cmd

“A”

FBD northbound

cmd/data

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FBDIMM

DDR2 SDRAM

2.6 Basic Timing Diagram

Figure 7 : Basic DRAM Read Data Transfers on FBD

1

2

3

4

5

6

7

8

9

10

11

12

13

ACT1

NOP

RD1

NOP

FBD southbound

cmd/data

DIMM 1 cmd

DIMM 1 data

DIMM 2 cmd

DIMM 2 data

ACT1

RD1

FBD northbound

data

Figure 8 : Back to Back DRAM Read Data Transfers

1

2

3

4

5

6

7

8

9

10

11

12

13

ACT1

NOP

ACT2 RD1

NOP NOP

RD2

NOP

FBD southbound

cmd/data

DIMM 1 cmd

DIMM 1 data

DIMM 2 cmd

DIMM 2 data

ACT1

RD1

ACT2

RD2

FBD northbound

data

No Bubble

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FBDIMM

DDR2 SDRAM

Figure 9 : Basic DRAM Write Data Transfers on FBD

1

2

3

4

5

6

7

8

9

10

11

12

13

ACT1

NOP

NOP WR1 NOP NOP SYNC

Wdata Wdata Wdata Wdata 1010

Wdata Wdata Wdata Wdata 0101

FBD southbound

cmd/data

DIMM 1 cmd

DIMM 1 data

DIMM 2 cmd

DIMM 2 data

ACT1

WR1

Fixed fall through time

FBD northbound

data

Status

Figure 10 : Simultaneous RD / WR Data Transfers

1

2

3

4

5

6

7

8

9

10

11

12

13

ACT1 ACT2 ACT3 RD1 WR2

RD3

SYNC

1010

0101

FBD southbound

cmd/data

Wdata Wdata Wdata Wdata NOP NOP

DIMM 1 cmd

DIMM 1 data

DIMM 2 cmd

DIMM 2 data

ACT1

ACT3 RD1

RD3

ACT2

WR2

FBD northbound

data

Status

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FBDIMM

DDR2 SDRAM

2.7 Advanced Memory Buffer Block Diagram

Figure 11 : Advanced Memory Buffer Block Diagram

Advance Memory Buffer

Block Dlagram

10x2

Southbound

Data Out

NORTH

Southbound

Data In

Data Merge

Re-Time

Re-synch

1x2

PLL

demux

PISO

mux

Ref Clock

10*2

Link Init SM

and Control

and CSRs

Reset#

Reset

Control

lnit

patterns

4

DRAM Clock

IBIST - RX

IBIST - TX

4

DRAM Clock #

Command

Decoder &

CRC Check

failover

LAI Logic

29

DRAM Address /

Cmd Out

Command Copy 1

DRAM Cmd

29

Thermal

Sensor

DRAM Address /

Command Copy 2

DDR State

Controller

and CSRs

Data Out

Data In

Core Control

and CSRs

36

deep

Write

Data

FIFO

72 + 18x2

DRAM

External MEMBIST

DDR calibration &

DDR IOBIST/DFX

Data / strobe

LAI

Controller

Data CRC Gen

& Read FIFO

Sync & ldie

NB LAI Buffer

Pattern

Generator

IBIST -TX

IBIST - RX

SMbus

Controller

mux

Link lnit SM

and Control

and CSRs

failover

14*6*2

14*12

PISO

demux

Re-synch

Re-Time

Data Merge

Northbound

Data Out

Northbound

Data In

14x2

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FBDIMM

DDR2 SDRAM

2.8 Interfaces

Figure12 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FBD links, one DDR2 channel and an SM-

Bus interface. Each FBD link connects the Advanced Memory Buffer to a host memory controller or an adjacent FBD. The DDR2 channel

supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM

Figure 12 : Advanced Memory Buffer Interface Block Diagram

MEMORY INTERFACE

NB FBD

Out Link

NB FBD

In Link

AMB

SB FBD

Out Link

SB FBD

In Link

SMB

The FBDIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel.

The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound

data path each DIMM receives the data and again redrives the data to the next DIMM until the last DIMM receives the data. The last DIMM

in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). On the northbound data path each DIMM

receives the data and re-drives the data to the next DIMM until the host is reached.

3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE

The Advanced Memory Buffer supports one FBD Channel consisting of two bidirectional link interfaces using high-speed differential point-

to-point electrical signaling.

The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM

in the host direction. The southbound output link forwards this same data to the next FBD.

The northbound input link is 14 lanes wide and carries read return data or status information from the next FBDIMM in the chain back

towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or

status information that is generated internally.

3.1 DDR2 Channel

The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two

ranks of eight banks with 16 row/column request, 64 data signals, and eight check-bit signals. There are two copies of address and com-

mand signals to support DIMM routing and electrical requirements. Four-transfer bursts are driven on the data and check-bit lines at 800

MHz.

Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware

state machines using write/read trial and error (or equivalent implementation). Hardware aligns the read data and check-bits to a single

core clock.

The Advanced Memory Buffer provides four copies of the command clock phase references (CLK[3:0]) and write data/check-bit.

3.2 SMBus Slave Interface

The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration registers independent of the FBD

link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100

kHz. SMBus access to the Advanced Memory Buffer may be a requirement to boot a system. This provides a mechanism to set link

strength, frequency and other parameters needed to insure robust operation given platform specific configurations. It is also required for

diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the Advanced Memory

Buffer to get its unique ID.

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FBDIMM

DDR2 SDRAM

3.3 FBD Channel Latency

FBD channel latency is measured from the time a read request is driven on the FBD channel pins to the time when the first 16 bytes (2nd

chunk) of read completion data is sampled by the memory controller.

When not using the Variable Read Latency capability, the latency for a specific FBDIMM on an FBD channel is always equal to the latency

for any other FBDIMM on that channel. However, the latency for each FBDIMM in a specific configuration with some number of FBDIMMs

installed may not be equal to the latency for each FBDIMM in a configuration with some different number of FBDIMMs installed.

As more DIMMs are added to the FBD channel, additional latency is required to read from each DIMM on the channel. Because the FBD

channel is based on the point-to-point interconnection of buffer components between DIMMs, memory requests are required to travel

through N-1 buffers before reaching the Nth buffer. The result is that a four DIMM channel configuration will have greater idle read latency

compared to a one DIMM channel configuration.

The Variable Read Latency capability can be used to reduce latency for DIMMs closer to the host.

The idle latencies listed in this section are representative of what might be achieved in typical AMB designs. Actual implementations with

latencies less than the values listed will have higher application performance and vice versa.

3.4 Peak Theoretical Throughput

An FBD channel transfers read completion data on the FBD Northbound data connection. 144 bits of data are transferred for every FBD

Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst

of 8 from a single channel or a DRAM burst of four from two lock-stepped channels provides a total of 72 bytes of data (64 bytes plus 8

bytes ECC).

The FBD frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FBD channel clock to the DRAM command

clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput as a single DRAM channel. For ex-

ample, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data connection is 4.267 GB/sec.

Write data is transferred on the FBD Southbound command and data connection, via Command+Wdata frames. 72 bits of data are trans-

ferred for every FBD Command+Wdata frame. Two Command+Wdata frames match the 18-byte data transfer of an ECC DDR DRAM in

a single DRAM command clock. A DRAM burst of 8 transfers from a single channel, or a burst of 4 from two lock-step channels provides

a total of 72 bytes of data (64 bytes plus 8 bytes ECC).

When the FBD frame rate matches the DRAM command clock, the Southbound command and data connection will exhibit one half the

peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of

the Southbound command and data connection is 2.133 GB/sec.

The total peak theoretical throughput for a single FBD channel is defined as the sum of the peak theoretical throughput of the Northbound

data connection and the Southbound command and data connection. When the FBD frame rate matches the DRAM command clock, this

is equal to 1.5 times the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak

theoretical throughput of a DDR2 533 channel would be 4.267 GB/sec, while the peak theoretical throughput of an FBD-533 channel would

be 6.4 GB/sec

3.5 Hot-add

The FBDIMM channel does not provide a mechanism to automatically detect and report the addition of a new FBDIMM south of the cur-

rently active last FBDIMM. It is assumed the system will be notified through some means of the addition of one or more new FBDIMMs

so that specific commands can be sent to the host controller to initialize the newly added FBDIMM(s) and perform a hot-add reset to bring

them into the channel timing domain. It should be noted that the power to the FBDIMM socket must be removed before a hot-add FBDIMM

is inserted or removed. Applying or removing the power to a FBDIMM socket is a system platform function.

3.6 Hot remove

In order to accomplish removal of FBDIMMs, the host must perform a fast reset sequence targeted at the last FBDIMM that will be retained

on the channel. The fast reset re-establishes the appropriate last FBDIMM so that the southbound transmission outputs of the last active

FBDIMM and the southbound and northbound outputs of the FBDIMMs beyond the last active FBDIMM are disabled. Once the appropriate

outputs are disabled, the system can coordinate the procedure to remove power in preparation for physical removal of the FBDIMM if

needed. Note that the power to the FBDIMM socket must be removed before a hot-add FBDIMM is inserted or removed. Applying or re-

moving the power to a FBDIMM socket is a system platform function.

3.7 Hot replace

Hot replace of FBDIMM is accomplished through combining the hot-remove and hotadd processes.

Rev. 1.3 April 2007

13 of 31

FBDIMM

DDR2 SDRAM

4.0 PIN CONFIGUREATION

Table 4 : DDR2 240 Pin FBDIMM Configurations (Front side/Back side)

1

Front

V_DD

V_SS

V_DD

V_SS

V_CC

V_SS

V_CC

V_SS

V_TT

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Back

V_DD

V_SS

V_DD

V_SS

V_CC

V_SS

V_CC

V_SS

V_TT

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

Front

PN3

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Back

SN3

61

62

63

64

65

66

67

68

Front

PN9

181

182

183

184

185

186

187

188

Back

SN9

91

Front

PS9

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

SS9

V_SS

2

PN3

SN3

92

V_SS

3

PN10

V_SS

SN10

V_SS

93

PS5

V_SS

SS5

V_SS

4

PN4

V_SS

SN4

V_SS

94

5

95

6

PN11

V_SS

SN11

V_SS

96

PS6

V_SS

SS6

V_SS

7

PN5

V_SS

SN5

V_SS

97

8

98

9

KEY

99

PS7

V_SS

SS7

V_SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

PN13

V_SS

SN13

V_SS

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

PS0

V_SS

SS0

V_SS

PS8

V_SS

SS8

V_SS

RFU*

V_SS

RFU*

V_SS

PS1

V_SS

SS1

V_SS

RFU**

V_SS

RFU**

V_SS

VID1

RESET

V_SS

VID0

DNU/M_Test

V_SS

PS2

V_SS

SS2

V_SS

V_DD

V_SS

PN12

V_SS

SN12

V_SS

SCK

V_SS

RFU**

V_SS

RFU**

V_SS

PS3

V_SS

SS3

V_SS

V_DD

V_SS

V_DD

PN6

V_SS

SN6

V_SS

V_DD

PN0

V_SS

SN0

V_SS

V_DD

PS4

V_SS

SS4

V_SS

PN7

V_SS

SN7

V_SS

V_DD

V_TT

V_DD

PN1

V_SS

PN2

V_SS

SN1

V_SS

SN2

V_SS

V_DD

V_TT

PN8

V_SS

SN8

V_SS

RFU*

V_SS

RFU*

V_SS

SA2

SDA

SCL

VDDSPD

SA0

V_SS

PS9

V_SS

SS9

PN9

SN9

SA1

RFU = Reserved Future Use.

* These pin positions are reserved for forwarded clocks to be used in future module implementations

** These pin positions are reserved for future architecture flexibility

1. The following signals are CRC bits and thus appear out of the normal sequence : PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN12, PS9/PS9,

SS9/SS9.

Rev. 1.3 April 2007

14 of 31

FBDIMM

DDR2 SDRAM

Table 5 : Pin Description

Pin Name

SCK

Type

Input

Pin Description

System Clock Input, positive line

Pin Numbers

228

229

SCK

Input

System Clock Input, negative line

PN[13:0]

PS[9:0]

Output

Input

Primary northbound Data, positive lines

Primary northbound Data, negative lines

Primary Southbound Data, positive lines

Primary Southbound Data, negative lines

22, 25, 28, 31, 34, 37, 40, 48, 51, 54, 57, 60, 63, 66

23, 26, 29, 32, 35, 38, 41, 49, 52, 55, 58, 61, 64, 67

70, 73, 76, 79, 82, 90, 93, 96, 99, 102

Input

71, 74, 77, 80, 83, 91, 94, 97, 100, 103

142, 145, 148, 151, 154, 157, 160, 168, 171, 174, 177,

180, 183, 186

SN[13:0]

Output

Secondary Northbound Data, positive lines

Secondary Northbound Data, negative lines

143, 146, 149, 152, 155, 158, 161, 16, 172, 175, 178,

181, 184, 187

SS[9:0]

SCL

Input

Secondary Southbound Data, positive lines

Secondary Southbound Data, negative lines

Serial Presence Detect (SPD) Clock Input

SPD Data Input / Output

190, 193, 196, 199, 202, 210, 213, 216, 219, 222

191, 194, 197, 200, 203, 211, 214, 217, 220, 223

120

119

SDA

SPD Address Inputs, also used to slelect the DIMM number in

the AMB

SA[2:0]

Input

118, 239, 240

Voltage ID : These pins must be unconnected for DDR2 -

based Fully Buffered DIMMs

VID[1:0]

NC

16, 136

17

VID[0] is V_DDvalue : OPEN = 1.8 V, GND = 1.5 V ; VID[1] is

V

_CCvalue : OPEN = 1.5V, GND = 1.2V

RESET

RFU

Input

RFU

AMB reset signal

19, 20, 44, 45, 86, 87, 105, 106, 139, 140, 164, 165,

206, 207, 225, 226

Reserved for Future Use

AMB Core Power and AMB Channel Interface Power (1.5

Volt)

V_CC

V_DD

PWR

9, 10, 12, 13, 129, 130, 132, 133

1, 2, 3, 5, 6, 7, 108, 109, 111, 112, 113, 115, 116, 121,

122, 123, 125, 126, 127, 231, 232, 233, 235, 236

DRAM Power and AMB DRAM I/O Power (1.8Volt)

V_TT

PWR

DRAM Address/Command/Clcok Termination Power(V_DD/2) 15, 117, 135, 237

V_DDSPD

SPD Power

238

4, 8, 11, 14, 18, 21, 24, 27, 30, 33, 36, 39, 42, 43, 46,

47, 50, 53, 56, 59, 62, 65, 68, 69, 72, 75, 78, 81, 84, 85,

88, 89, 92, 95, 98, 101, 104, 107, 110, 114, 124, 128,

131, 134, 138, 141, 144, 147, 150, 153, 156, 159, 162,

163, 166, 167, 170, 173, 176, 179, 182, 185, 188, 189,

192, 195, 198, 201, 204, 205, 208, 209, 212, 215, 218,

221, 224, 227, 230, 234

V_SS

GND

DNU

Ground

The DNU/M_Test pin provides an external connection R/Cs A-

D for testing the margin of Vref which is produced by a voltage

divider on the module. It is not intended to be used in normal

DNU/M_Test

system operation and must not be connected (DNU) in a sys- 137

tem. This test pin may have other features on future card de-

signs and if it does, will be included in this specification at that

time.

Rev. 1.3 April 2007

15 of 31

FBDIMM

DDR2 SDRAM

5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM

5.1 512MB, 64Mx72 Module - M395T6553EZ4

(populated as 1 rank of x8 DDR2 SDRAMs)

S0

DQS0

DQS9

DQS4

DQS13

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

I/O 0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D4

DQS1

DQS5

DQS10

DQS14

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

DQ9

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS6

DQS11

DQS15

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D6

DQS7

DQS3

DQS16

DQS12

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

D7

D3

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

PN0-PN13

PS0-PS9

SN0-SN13

SS0-SS9

DQS17

DM/ NU/ CS DQS DQS

RDQS RDQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

S0->CS(all SDRAMs)

I/O 1

DQ0-DQ63

CB0-CB7

D8

CKE0->CKE(all SDRAMs)

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A

M

B

DQS0-DQS17

DQS0-DQS8

ODT->ODT(all SDRAMs)

BA0-BA2(all SDRAMs)

A0-A15(all SDRAMs)

RAS(all SDRAMs)

SCL

SDA

SA1-SA2

SA0

CAS(all SDRAMs)

RESET

Serial PD

WE(all SDRAMs)

CK/CK(all SDRAMs)

SCK/SCK

V

Terminators

AMB

TT

SCL

SDA

All address/command/control/clock

V

WP A0 A1 A2

SA0 SA1 SA2

TT

V

CC

V

SPD, AMB

D0-D8, AMB

D0-D8

DDSPD

V

DD

V

REF

Note :

1.DQ-to I/O wiring may be changed within a byte.

2.There are two physical copies of each address/command/control/clock

V

D0-D8,SPD,AMB

SS

Rev. 1.3 April 2007

16 of 31

FBDIMM

DDR2 SDRAM

5.2 1GB, 128Mx72 Module - M395T2953EZ4

(populated as 2 rank of x8 DDR2 SDRAMs)

S1

S0

DQS0

DQS9

DQS4

DQS13

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

I/O 0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D9

D4

D13

DQS1

DQS5

DQS10

DQS14

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

DQ9

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D10

D5

D14

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS6

DQS11

DQS15

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D11

D6

D15

DQS7

DQS3

DQS16

DQS12

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

D7

D16

D3

D12

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

PN0-PN13

PS0-PS9

SN0-SN13

SS0-SS9

DQS17

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

S0->CS(D0-D8)

DQ0-DQ63

CB0-CB7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

CKE0->CKE(D0-D8)

S1->CS(D9-D17)

A

M

B

I/O 1

DQS0-DQS17

DQS0-DQS8

D8

D17

CKE1->CKE(D9-D17)

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

ODT->ODT(all SDRAMs)

BA0-BA2(all SDRAMs)

A0-A15(all SDRAMs)

RAS(all SDRAMs)

SCL

SDA

SA1-SA2

SA0

CAS(all SDRAMs)

RESET

WE(all SDRAMs)

CK/CK(all SDRAMs)

SCK/SCK

V

All address/command/control/clock

TT

V

Terminators

TT

Serial PD

V

AMB

CC

SCL

SDA

WP A0 A1 A2

V

SPD, AMB

D0-D17, AMB

D0-D17

DDSPD

V

DD

SA0 SA1 SA2

V

REF

Note :

1.DQ-to I/O wiring may be changed within a byte.

2.There are two physical copies of each address/command/control/clock

V

D0-D17,SPD,AMB

SS

Rev. 1.3 April 2007

17 of 31

FBDIMM

DDR2 SDRAM

5.3 2GB, 256Mx72 Module - M395T5750EZ4

(populated as 2 rank of x4 DDR2 SDRAMs)

VSS

S1

S0

DQS0

DQS9

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ0

DQ4

I/O 0

DQ1

DQ2

DQ3

DQ5

DQ6

DQ7

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

D0

D18

D9

D27

DQS1

DQS10

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ12

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ9

DQ13

DQ14

DQ15

D1

D19

D10

D28

DQ10

DQ11

DQS2

DQS11

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ20

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ17

DQ18

DQ19

DQ21

DQ22

DQ23

D2

D20

D11

D29

DQS3

DQS12

DQS3

DQS12

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ28

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ25

DQ26

DQ27

DQ29

DQ30

DQ31

D3

D21

D12

D30

DQS4

DQS13

DQS4

DQS13

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ32

DQ36

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ33

DQ34

DQ35

DQ37

DQ38

DQ39

D4

D22

D13

D31

DQS5

DQS14

DQS5

DQS14

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ40

DQ44

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ41

DQ42

DQ43

DQ45

DQ46

DQ47

D5

D23

D14

D32

DQS6

DQS15

DQS6

DQS15

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ48

DQ52

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ49

DQ50

DQ51

DQ53

DQ54

DQ55

D6

D24

D15

D33

DQS7

DQS16

DQS7

DQS16

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ56

DQ60

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ57

DQ58

DQ59

DQ61

DQ62

DQ63

D7

D25

D16

D34

DQS8

DQS17

DQS8

DQS17

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

CB0

CB4

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

CB1

CB2

CB3

CB5

CB6

CB7

D8

D26

D17

D35

SN0-SN13

SS0-SS9

PN0-PN13

V

All address/command/control/clock

PN0-PN13

PS0-PS9

TT

S0->CS(D0-D17)

DQ0-DQ63

CB0-CB7

CKE0->CKE(D0-D17)

S1->CS(D18-D35)

Serial PD

A

DQS0-DQS17

DQS0-DQS8

M

B

CKE1->CKE(D18-D35)

SCL

SDA

ODT->ODT(all SDRAMs)

BA0-BA2(all SDRAMs)

A0-A15(all SDRAMs)

RAS(all SDRAMs)

SCL

V

Terminators

AMB

TT

WP A0 A1 A2

SDA

SA1-SA2

SA0

V

CC

CAS(all SDRAMs)

RESET

SA0 SA1 SA2

WE(all SDRAMs)

CK/CK(all SDRAMs)

V

SPD, AMB

D0-D35, AMB

D0-D35

SCK/SCK

DDSPD

V

DD

V

REF

Note :

V

D0-D35,SPD,AMB

SS

1.DQ-to I/O wiring may be changed within a byte.

2.There are two physical copies of each address/command/control/clock.

3. There are four physical copies of each clock.

Rev. 1.3 April 2007

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FBDIMM

DDR2 SDRAM

6.0 ELECTRICAL CHARACTERISTICS

Table 6 : AbsoIute Maximum Ratings

Parameter

Voltage on any pin relative to VSS

Voltage on VCC pin relative to VSS

Voltage VDD pin relative to VSS

Voltage on VTT pin relative to VSS

Storage temperature

Symbol

V_IN, V_OUT

V_CC

MIN

-0.3

-0.5

-55

0

MAX

1.75

2.3

Units

V

Note

1

V

V_DD

V

V_TT

2.3

V

T_STG

100

85

°C

DDR2 SDRAM device operating temperature(Ambient)

AMB device operating temperature (Ambient)

T_CASE

°C

1,2

85

95

0

110

°C

1,2

Note : 1. Stresses greater than those Iisted may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may adversely affect reliability.

2. DDR2 SDRAMs of FBDIMM should require this specification.

Parameter

Symbol

0 °C ≤ T_CASE≤ 85°C

85 °C < T_CASE≤ 95°C

DRAM

7.8

Units

µs

Average periodic refresh interval

tREFI

3.9

µs

Table 7 : Input DC Operating Conditions

Parameter

AMB supply voltage

Symbol

V_CC

MIN

1.455

1.7

Nom

1.50

1.8

MAX

1.575

1.9

Units

V

Notes

DDR2 SDRAM supply voltage

Termination voltage

V_DD

V

V_TT

V_DDSPD

V_IH(DC)

V_IL(DC)

V_IH(DC)

V_IL(DC)

I_L

0.48 x V_DD

3.0

0.50 x V_DD

3.3

0.52 x V_DD

3.6

V

EEPROM supply voltage

V

SPD Input HIGH (Iogic 1) voltage

SPD Input LOW (logic 0) voltage

RESET Input HIGH (logic 1) voltage

RESET Input LOW (logic 0) voltage

Leakage Current (RESET)

Leakage Current (link)

V_DDSPD

0.8

V

1

2

1

2

3

1.0

V

0.5

90

5

V

-90

-5

uA

I_L

Note : 1. Applies for SMB and SPD bus signals.

2. Applies for AMB CMOS signal RESET#.

3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specification.

Table 8 : Timing Parameters

Parameter

EI Assertion Pass-Thru Timing

EI Deassertion Pass-Thru Timing

EI Assertion Duration

Symbol

MIN

Typ.

Max.

4

Units

clks

ns

Notes

-

2

t_{EI Propagate}

t

t_EID

t_EI

Bitlock

100

1,2

3

FBD Cmd to DDR Clk out that latches Cmd

FBD Cmd to DDR Write

8.1

TBD

5.0

ns

DDR Read to FBD (last DIMM)

Resample Pass-Thru time

ResynchPass-Thru time

ns

4

1.075

2.075

ns

Bit Lock Interval

t_BitLock

119

154

frames

1

Frame Lock Interval

t_FrameLock

Note : 1. Defined in FB-DIMM Architecture and Protocol Spec

2. Clocks defined as core clocks = 2x SCK input

3. @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to the DRAMs

4. @ DDR2-667 - measured from latest DQS input AMB TO start of matching data frame at northbound FB-DIMM outputs.

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FBDIMM

DDR2 SDRAM

Table 9 : Power specification parameter and test condition

Power

Units

Symbol

Conditions

Supply

Icc_Idle_0

Idle Current, single or last DIMM

L0 state, idle (0 BW)

Primary channel enabled, Secondary Channel Disabled

CKE high. Command and address lines stable.

DRAM clock active.

@1.5V

mA

Idd_Idle_0

@1.8V

mA

Idd_Idle_0 Total Power

W

Icc_Idle_1

Idd_Idle_1

Idle Current, first DIMM

@1.5V

@1.8V

mA

L0 state, idle (0 BW)

Primary and Secondary channels enabled

CKE high. Command and address lines stable.

DRAM clock active.

mA

Idd_Idle_1 Total Power

W

Icc_Active_1

Idd_Active_1

Active Power

@1.5V

@1.8V

mA

L0 state.

50% DRAM BW, 67% read, 33% write.

Primary and Secondary channels enabled.

DRAM clock active, CKE high.

mA

Idd_Active_1 Total Power

W

Icc_Active_2

Idd_Active_2

Active Power, data pass through

L0 state.

50% DRAM BW to downstream DIMM, 67% read, 33% write.

Primary and Secondary channels enabled

CKE high. Command and address lines stable.

DRAM clock active.

@1.5V

@1.8V

mA

Idd_Active_2 Total Power

W

Idd_Training

(for AMB spec, Not in

SPD)

Training

@1.5V

@1.8V

mA

Primary and Secondary channels enabled.

100% toggle on all channel lanes

DRAMs idle. 0 BW.

Idd_Training

(for AMB spec, Not in

SPD)

CKE high, Command and address lines stable.

DRAM clock active.

mA

W

Idd_Training Total Power

Table 10 : Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V)

512MB (M395T6553EZ4)

1GB (M395T2953EZ4)

2GB (M395T5750EZ4)

D56/

D51

E66/

E61

D56/

D51

E66/

E61

D56/

D51

E66/

E61

Symbol

D55

D52

E65

E62

D55

D52

E65

E62

D55

D52

E65

E62

Notes Unit

(PC2-4200)

2200

(PC2-5300)

2600

(PC2-4200)

2200

(PC2-5300)

2600

(PC2-4200)

2200

(PC2-5300)

2600

Icc_Idle_0

Idd_Idle_0

P_idle_0

2200

970

2090

396

2600

1015

2350

451

2200

1240

2090

666

2600

1330

2350

766

2200

1980

2090

1206

5.583

2930

1206

6.906

2930

2600

2160

2350

1396

6.354

3220

1396

7.724

3220

@1.5V

@1.8V

mA

W

970

1015

1240

1330

1980

2160

5.308

3000

970

5.308

3000

970

4.044

2930

396

6.024

3400

1015

7.284

3900

6.024

3400

1015

7.284

3900

4.558

3220

451

5.821

3000

1240

7.081

3400

5.821

3000

1240

7.081

3400

4.557

2930

666

6.622

3400

1330

7.882

3900

6.622

3400

1330

7.882

3900

5.157

3220

766

7.227

3000

1980

8.487

3400

7.227

3000

1980

8.487

3400

8.199

3400

2160

9.459

3900

8.199

3400

2160

9.459

3900

Icc_Idle_1

Idd_Idle_1

P_idle_1

@1.5V

@1.8V

mA

W

6.568

3400

6.568

3400

5.367

2930

5.928

3220

5.880

2930

6.527

3220

Icc_active_1

Idd_active_1

P_active_1

Icc_active_2

Idd_active_2

P_active_2

Icc_training

Idd_training

P_training

@1.5V

@1.8V

mA

W

2230.6 2230.6 1809.6 2425.9 2425.9 2031.9 2500.6 2500.6 2079.6 2740.9 2740.9 2346.9 3980.6 3980.6 3159.6 4340.6 4340.6 3546.6

9.593

3200

970

9.593

3200

970

8.053 10.752 10.752 8.932 10.106 10.106 8.566 11.350 11.350 9.531 12.918 12.918 10.618 14.390 14.390 11.810

2930

396

3700

1015

7.756

4000

1015

8.229

3700

1015

7.756

4000

1015

8.229

3220

451

3200

1240

7.396

3500

1240

7.869

3200

1240

7.396

3500

1240

7.869

2930

666

3700

1330

8.355

4000

1330

8.827

3700

1330

8.355

4000

1330

8.827

3220

766

3200

1980

8.802

3500

1980

9.275

3200

1980

8.802

3500

1980

9.275

2930

1206

6.906

3050

1959

3700

2160

9.932

4000

2160

3700

2160

9.932

4000

2160

3220

1396

7.724

3380

2166

@1.5V

@1.8V

mA

W

6.883

3500

970

6.883

3500

970

5.367

3050

1149

6.987

5.928

3380

1221

7.643

5.880

3050

1419

7.500

6.527

3380

1536

8.242

@1.5V

@1.8V

mA

W

7.356

8.526 10.404 10.404 9.439

Note :

1. FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet.

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FBDIMM

DDR2 SDRAM

Table 11 : VTT Currents

Description

Idle current, DDR2 SDRAM device power down

Active power, 50% DDR2 SDRAM BW

Symbol

ITT1

Typ

500

MAX

700

Units

mA

ITT2

700

mA

Table 12 : Reference Clock Input Specifications

Values

Parameter

Symbol

Units

Note

MIN

MAX

Reference clock frequency @3.2 Gb/s

(nominal 133.33 MHz)

fRefclk-3.2

fRefclk-4.0

126.67

133.40

MHz

1.2

Reference clock frequency @4.0 Gb/s

(nominal 166.67 MHz)

158.33

166.75

1.2

3

Rise time, fall time

Voltage high

T

_SCK-RISE, T_SCK-FALL

V_SCK-HIGH

175

660

700

850

ps

mV

Voltage low

V_SCK-LOW

-150

Absolute crossing point

Relative crossing

V_CROSS-ABS

V_CROSS-REL

250

550

calculated

10

4

calculated

-

4,5

Percent mismatch between rise and fall

times

T_{SCK-RISE-FALL-MATCH}

%

Duty cycle of reference clock

Clock leakage current

Clock input capacitance

Clock input capacitance delta

Transport delay

T_{SCK-DUTYCYCLE}

I_I-CK

40

-10

60

10

2

%

uA

6,7

7

C_I-CK

0.5

pF

C_{I_CK(D)}

T1

-0.25

0.25

5

pF

8

ns

9, 10

11

Phase jitter sample size

Reference clock jitter, filtered

Reference clock deterministic jitter

Note :

NSAMPLE

T_REF-JITTER

T_REF-DJ

10¹⁶

Periods

ps

40

12,13

TBD

ps

1.133MHz for PC2-4200 and 166MHz for PC2-5300.

2. Measured with SSC disabled.

3. Measured differentially through the range of 0.175V to 0.525V.

4. The crossing point must meet the absolute and relative crossing point specification simultaneously.

5. V_{CROSS_REL_(MIN)}and V_{CROSS_REL(MAX)}are derived using the following calculation : Min = 0.5(V_havg-0.710)+0.250;and Max=0.5(V_havg-0.710)+0.550,

where Vhavg is the average of V_SCK-HIGHM.

6. Measured with a single-ended input voltage of 1V.

7. Applies to reference clocks SCK and SCK.

8. Difference between SCK and SCK input.

9. T1 = [Tdatapath-Tclockpath](excluding PLL loop delays). This parameter is not a direct clock output parameter but in indirectly determines the clock

output parameter T_REF-JITTER.

10. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined from the reference clock

source, through the TX, to data arrival at the data dampling point in the RX. The clock path is defined from the reference clock source to clock arrival

at the same sampling point. The path delays are caused by copper trace routes. on-chip routing, on-chip buffering, etc. They include the time-of flight

of interpolators or other clock adjustment mechanisms. They do not include the phase delays caused by finite PLL loop bandwidth because these de-

lays are modeled by the PLL transfer functions.

11. Direct measurement of phase jitter records over 1016 periods is impractical. It is expected that the jitter will be measured over a smaller, yet statistically

significant, sample size and the total jitter at 10¹⁶samples extrapolated from an estimate of the sigma of the random jitter components.

12. Measured with SSC enabled on reference clock generator.

13. As measured after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRXTotal - MIN parameters.

Rev. 1.3 April 2007

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FBDIMM

DDR2 SDRAM

Table 13 : Differential Transmitter Output Specifications

Values

Parameter

Symbol

Units

Comments

MIN

MAX

Differential peak-to-peak output voltage for large

voltage swing

V_{TX-DIFFp-p_L}

V_{TX-DIFFPp-p_R}

V_{TX-DIFFp-p_S}

V_{TX-CM_L}

900

1,300

mV

dB

EQ1, Note1

EQ2, Note1

EQ2, Note1,2

1,3,4

Differential peak-to -peak output voltage for requ-

lar voltage swing

800

520

Differential peak-to-peak output voltage for small

votage swing

DC common code output voltage for large voltage

swing

375

280

-4.0

-7.0

90

DC common code output voltage for small volt-

age swing

V_{TX-CM_S}

135

-3.0

-5.0

De-emphasized differential output voltage ratio

for -3.5 dB de-emphasis

V_{TX-DE-3.5-Ratio}

V_{TX-DE-6.0-Ratio}

V_{TX-CM-ACp-p-L}

V_{TX-CM-ACp-p-R}

V_{TX-CM-ACp-p-S}

V_TX-IDLE-SE

De-emphasized differential output voltage ratio

for -6.0 dB de-emphasis

dB

1,2,3

AC peak-to-peak common mode output voltage

for large swing

mV

EQ7, Note1,5

6

AC peak-to-peak common mode output voltage

for regular swing

80

AC peak-to-peak common mode output voltage

for small swing

70

Maximum single-ended voltage in EI condition

DC+AC

50

Maximum single-ended voltage in EI condition

DC+AC

V_{TX-IDLE-SE-DC}

V_{TX-IDLE-DIFFp-p}

20

6

Maximum peak-to-peak differential voltage in EI

condition

40

Single-ended voltage (w.r.t. VSS) on D+/D-

Mimimum TX eye width, 3.2 and 4.0 Gb/s

Mimimum TX eye width 4.8 Gb/s

Maximum TX deterministic jitter, 3.2 and 4.8Gb/s

Maximum TX deterministic jitter, 4.8 Gb/s

Insantaneous pulse width

V_TX-SE

T_TX-Eye-MIN

T_{TX-EYE-MIN4.8}

T_TX-DJ-DD

-75

750

mV

UI

1,7

1,8

UI

1,8

02

UI

1,8,9

T_TX-DJ-DD-4.8

T_TX-PULSE

TBD

UI

1,8,9

10

0.85

30

UI

Differential TX output rise/fall time

Mismatch between rise and fall times

Differential return loss

T

_TX-RISET_TX-FALL

T_{TX-RF-MISMATCH}

RL_TTX-DIFF

RL_TX-CM

90

20

ps

dB

20-80% voltage, Note1

8

6

1 GHz-2.4 GHz, Note 11

12

Common mode return loss

Transmitter termination impender

R_TX

41

55

4

EQ 4, Boundaries are applied sepa-

rately to high and low output voltage

states

D+/D-TX Impedance difference

R_TX-MATCH-DC

%

Lane-to lane skew at TX

L_TX-SKEW1

L_TX-SKEW2

100+3UI

100=2UI

ps

13, 15

14, 15

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FBDIMM

DDR2 SDRAM

Table 14 : Differential Receiver Input Specifications

Values

Parameter

Symbol

Units

Comments

MIN

MAX

TBD

75

Differential peak-to-peak input voltage for large volt-

age swing

V_RX-DIFFp-p

V_RX-IDLE-SE

170

mV

EQ 5, Note1

Maximum single-ended voltage in El condition

2,3

Maximum single-ended voltage in Ei condition (DC

only)

V_{RX-IDLE-SE-DC}

50

Maximum peak-to-peak differential voltage in El

condition

V_{RX-IDLE-DIFFp-p}

65

mV

3

Single-ended voltage (w.r.t. V_SS) on D+/D-

Single-pulse peak differential input voltage

Amplitude ratio between adjacent symbols

V_RX-SE

-300

85

900

mV

4

V_{RX-DIFF-PULSE}

V_{RX-DIFF-ADJ-RATIO}

4,5

4,6

TBD

0.4

Maximum RX inherent timing error, 3.2 and 4.0 Gb/

x

T_RX-TJ-MAX

UI

4,7,8

Maximum RX inherent deterministic timing eror, 3.2

and 4.8 Gb/s

T_RX-TJ-MAX4.8

TBD

Single-pulse width as zero-voltage crossing

Skingle-pulse width at minimum-level crossing

Differential RX input rise/fall time

common mode fo the input voltage

Differential RX output rise/fall time

Common mode of input voltage

V_RX-DJ-DD

V_RX-DJ-DD-4.8

T_RX-PW-ZC

0.3

UI

4,7,8,9

TBD

4,7,8,9

0.55

0.2

50

UI

4,5

T_RX-PW-ML

UI

4.5

20~80% voltage

EQ 6, Note1, 10

EQ 7, Note 1

11

T_RX-RISET_RX-FALL

V_RX-CM

ps

mV

%

120

400

270

45

AC peak-to-peak common mode of input voltage

Ratio of V_RX-CM-ACp-pto minimum V_RX-DIFFp-p

Differential return loss

V_RX-CM-ACp-p

V_{RX-CM-EH-RATOP}

RL_RX-DIFF

9

6

dB

Ω

1GHz-2.4 GHz, Note 12

13

Common mode return loss

RL_RX-CM

RX termination impedance

R_RX

41

55

4

D+/D- RX Impedance difference

R_RX-MATCH-DC

%

EQ 8

Lane-to-lane skew at the receiver that

must be tolerated. Note 14

Lane-to lane PCB skew at RX

L_RX-PCB-SKEW

6

UI

Minimum RX drift tolerance

Minim data tracking 3dB bandwidth

Electrical idle entry detect time

Electrical idle exit detect time

Bit Error Ratio

T_RX-DRIFT

F_TRK

400

0.2

ps

MHz

ns

15

16

17

T_{EI-ENTRY-DETECT}

T_{EI-EXIT-DETECT}

BER

60

30

10^-12

ns

18

Note :

1. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower than at the pin.

2. Single-ended voltages below that value that are simultaneously detected on D+ and D-are interpreted as the Electrical Idle condition. Worst-case mar-

gins are determined for the case with transmitter using small voltage swing.

3. Multiple lanes need to detect the El condition before the device can act upon the El detection.

4. Specified at the package pins into a timing and voltage compliance test setup.

5. The single-pulse mask provides suffcient symbol energy for reliable RX reception. Each symbol must comply with both the single-pulse mask and the

cumulative eyemask.

6. The relative amplitude ratio limit between adjacent symbols prevents excessive intersymbol interference in the RX. Each symbol must comply with the

peak amplitude ratio with regard to both the preceding and subsequent symbols.

7. This number does not include the effects of SSC or reference clock jitter.

8. This number includes setup and hold of the RX sampling flop.

9. Defined as the dual-dirac deterministic timing error.

10. Allows for 15 mV DC offset between transmit and receive devices.

Rev. 1.3 April 2007

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FBDIMM

DDR2 SDRAM

11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peaktopeak common mode specification. For example,

if VRX-DIFFp-p is 200 mV, the maximum AC peak-to peak common mode is the lesser of (200 mV*0.45=90 mV)and VRX-CM-AC-p-p.

12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed.

13. The termination small signal resistance; tolerance across voltage from 100 mV to 400 mV shall not exceed +/-5 W with regard to the average of the

values measured at 100 mV and at 400 mV for that pin.

14. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output skew from the component of the

end-to-end channel skew in the AMB specification.

15. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage and temperature ranges

for a single component. Drift rate of change is significantly below the tracking capability of the receiver.

16. This bandwidth number assume the specified minimum data transition density. Maximum jitter at 0.2 MHz is 0.05 UI,

17. The specified time includes the time required to forward the El entry condition.

18. BER per differential lane.

V

_RX-DIFFp-p= 2x[V_RX-D+-V_RX-D-] (EQ5)

(V_RX-CM= DC(avg) of [V_RX-D++ V_RX-D-] /2) (EQ 6)

V_RX-CM-AC=((Max[V_RX-D++ V_RX-D)/2)((Min [V_RX-D++ V_RX-D-)/2) (EQ 7)

R_RX-MATCH-DC= 2x((R_RX-D+-R_RX-D-)/(R_RX-D++ R_RX-D-) (EQ 8)

Rev. 1.3 April 2007

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FBDIMM

DDR2 SDRAM

7.0 CHANNEL INITIALIZATION

This chapter defines the process of initializing the FBD channel. The FBD initialzation process generally follows the top to bottom se-

quence of state transitions shown in the high level AMB Initialization Flow diagram in Figure The host must sequence the AMB devices

through the Disable, (back to Disable), Training, Testing, and Polling states in order to transition the AMBs into the active channel L0

state. The value in parenthesis in each state bubble indicates the condition/activity of the links during these states.

Figure16 : AMB Initialization Flow Diagram

Power-up

Disable

Calibrate

(EI)

(1’s)

Tranining

(TS0)

Testing

(TS1)

Polling

(TS2)

Config

(TS3)

L0

L0s

(EI)

Recalibrate

(NOP2)

The states in the AMB Initialization Flow diagram are :

Disable - The channel is inactive and the interface signals are in a low power Electrical Idle condition.

Training - The initial bit alignment and frame alignment training is done in this state.

Testing - Each bit lane is individually tested in this state.

Polling - The channel capabilities of the individual AMB devices are communicated in this state.

Config - The channel width configuration is communicated to the AMB devices in this state.

L0 - The channel is active and frames of information are flowing between the host and the AMB devices.

Recalibrate - The channel is momentarily idled to allow TX and Rx circuits to be recalibrated.

L0s - The channel is in a low-latency power saving condition. (Optional)

Each bit lane is initialized (mosly) independently to support fault tolerance. The transitions in the figure represent the transitions of the

AMB core logic state machine and are taken when the transition event is detected on the minimum required number of southound bit

lanes. The chain of FBD links connecting the host the AMBs must each be initialized to esabish the timing for broadcasting data frames

in the southbound direction and for merging data frame in the northbound direction. The AMBs on the channel are generally initialized

as a group but because each AMB is individually addressable many altemate may altemate initialization sequences may be employed.

Rev. 1.3 April 2007

25 of 31

FBDIMM

DDR2 SDRAM

Figure 17 : FBDIMM Physical Dimension -1 (For PCB) : 64Mbx8 based 64Mx72 Module (1Rank)

M395T6553EZ4

133.35

126.85

2x 3.25

2x 2.50 MIN

d

AMB

e

c

b

2x DIA. 2.0 +0.1/-0

a

67

51

5.175

123

R0.595

6.0

1.19

R0.75

5.0

2.50

0.8 +/- 0.05

2.50

1.19

120°

2.25

3.80

1.25

1.00

MAX 0.178

DETAIL b

R0.595

1.50

DETAIL a

DETAIL c

DETAIL d

DETAIL e

Rev. 1.3 April 2007

26 of 31

FBDIMM

DDR2 SDRAM

Figure 18 : FBDIMM Physical Dimension -2 (For Heat Spreader): 64Mbx8 based 64Mx72 Module (1Rank)

M395T6553EZ4

Units : Millimeters

8.2 max

133.35

67

51

1.27 ± 0.10

Back

3.0 max

123

Rev. 1.3 April 2007

27 of 31

FBDIMM

DDR2 SDRAM

Figure 19 : FBDIMM Physical Dimension -1 (For PCB) : 64Mbx8 based 128Mx72 Module (2Rank)

M395T2953EZ4

133.35

126.85

2x 3.25

2x 2.50 MIN

d

AMB

e

c

b

2x DIA. 2.0 +0.1/-0

a

67

51

5.175

123

R0.595

6.0

1.19

R0.75

5.0

2.50

0.8 +/- 0.05

2.50

1.19

120°

2.25

3.80

1.25

1.00

MAX 0.178

DETAIL b

R0.595

1.50

DETAIL a

DETAIL c

DETAIL d

DETAIL e

Rev. 1.3 April 2007

28 of 31

FBDIMM

DDR2 SDRAM

Figure 20 : FBDIMM Physical Dimension -2 (For Heat Spreader) : 64Mbx8 based 128Mx72 Module (2Rank)

M395T2953EZ4

Units : Millimeters

8.2 max

133.35

67

51

1.27 ± 0.10

Back

3.0 max

123

Rev. 1.3 April 2007

29 of 31

FBDIMM

DDR2 SDRAM

Figure 21 : FBDIMM Physical Dimension -1 (For PCB) : 128Mbx4 based 256Mx72 Module (2Rank)

M395T5750EZ4

133.35

126.85

2x 3.25

2x 2.50 MIN

d

AMB

e

c

b

2x DIA. 2.0 +0.1/-0

a

67

51

5.175

123

R0.595

6.0

1.19

R0.75

5.0

2.50

0.8 +/- 0.05

2.50

1.19

120°

2.25

3.80

1.25

1.00

MAX 0.178

DETAIL b

R0.595

1.50

DETAIL a

DETAIL c

DETAIL d

DETAIL e

Rev. 1.3 April 2007

30 of 31

FBDIMM

DDR2 SDRAM

Figure 22 : FBDIMM Physical Dimension -2 (For Heat Spreader) : 128Mbx4 based 256Mx72 Module (2Rank)

M395T5750EZ4

Units : Millimeters

8.2 max

133.35

67

51

1.27 ± 0.10

Back

3.0 max

123

Rev. 1.3 April 2007

31 of 31


型号：	M395T2953EZ4-CE660
厂家：	SAMSUNG
描述：	DDR DRAM Module, 128MX72, CMOS, ROHS COMPLIANT, DIMM-240 动态存储器双倍数据速率
文件：	总31页 (文件大小：642K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M395T2953EZ4-CE660 [SAMSUNG]

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