M395T5160QZ4-CE76_技术文档

FBDIMM

DDR2 SDRAM

DDR2 Fully Buffered DIMM

240pin FBDIMMs based on 1Gb Q-die

60FBGA with Lead-Free and Halogen-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

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FBDIMM

DDR2 SDRAM

Table of Contents

1.0 FEATURES .....................................................................................................................................4

2.0 FBDIMM GENERALS .....................................................................................................................5

2.1 FB-DIMM Operation Overview ........................................................................................................5

2.2 FB-DIMM Channel Frequency Scaling .............................................................................................6

2.3 FB-DIMM Clocking Scheme ............................................................................................................7

2.4 FB-DIMM Protocol ........................................................................................................................7

2.5 Southbound Command Delivery .....................................................................................................8

2.6 Basic Timing Diagram ...................................................................................................................9

2.7 Advanced Memory Buffer Block Diagram ......................................................................................11

2.8 Interfaces ..................................................................................................................................12

3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE ...............12

3.1 DDR2 Channel ............................................................................................................................12

3.2 SMBus Slave Interface ................................................................................................................12

3.3 FBD Channel Latency .................................................................................................................13

3.4 Peak Theoretical Throughput .......................................................................................................13

3.5 Hot-add .....................................................................................................................................13

3.6 Hot remove ................................................................................................................................13

3.7 Hot replace ................................................................................................................................13

4.0 PIN CONFIGUREATION ..............................................................................................................14

5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM ...............................................................................16

5.1 1GB, 128Mx72 Module - M395T2863QZ4 ........................................................................................16

5.2 2GB, 256Mx72 Module - M395T5663QZ4 ........................................................................................17

5.3 4GB, 512Mx72 Module - M395T5160QZ4 .......................................................................................18

5.4 4GB, 512Mx72 Module - M395T5163QZ4 .......................................................................................19

5.5 8GB, 1Gx72 Module - M395T1G60QJ4 .......................................................................................21

6.0 ELECTRICAL CHARACTERISTICS ............................................................................................23

7.0 CHANNEL INITIALIZATION ........................................................................................................32

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FBDIMM

DDR2 SDRAM

Revision History

Revision

Month

Year

2008

History

1.0

1.1

March

- Initial Spec. Release

- Added 4Rank Products based on Low Power AMB

- Corrected Typo

1.11

1.12

1.2

March

April

August

December

- Corrected mechanical Dimension

- Changed the ordering information

- Updated the IDD current specification

1.3

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FBDIMM

DDR2 SDRAM

1.0 FEATURES

-

240pin fully buffered dual in-line memory module (FB-

-

Serial presence detect with EEPROM

DIMM)

8 Banks

-

3.2Gb/s, 4.0Gb/s link transfer rate

Posted CAS

1.8V +/- 0.1V Power Supply for DRAM V /V

Programmable CAS Latency: 3, 4, 5, 6

Programmable Additive Latency: 0, 1, 2, 3, 4, 5

Automatic DDR2 DRAM bus and channel calibration

MBIST and IBIST Test functions

Hot add-on and Hot Remove Capability

Transparent mode for DRAM test support

DD DDQ

1.5V +0.075/-0.045V Power Supply for AMB V

CC

3.3V +/- 0.3V Power Supply for V

DDSPD

Buffer Interface with high-speed differential point-to-

point Link at 1.5 volt

Channel error detection & reporting

Channel fail over mode support

-

Table 1 : Ordering Information

Type of

Number

Part Number

Density Organization

Component Composition

AMB

Heat

Height

of Rank

Spreader

M395T2863QZ4-CE66/F76/E76

M395T2863QZ4-CE65

IDT C1

Intel D1

1GB

2GB

128M x 72

128Mx8(K4T1G084QQ) *9EA

1

M395T2863QZ4-CE68/F78

M395T2863QZ4-CE69

IDT L4

Montage D1

IDT C1

M395T5663QZ4-CE66/F76/E76

M395T5663QZ4-CE65

Intel D1

256M x 72 128Mx8(K4T1G084QQ) *18EA

2

M395T5663QZ4-CE68/F78

M395T5663QZ4-CE69

IDT L4

Full Module 30.35mm

Montage D1

IDT C1

M395T5160QZ4-CE66/F76/E76

M395T5160QZ4-CE65

Intel D1

256Mx4(K4T1G044QQ) *36EA

512M x 72

M395T5160QZ4-CE68

IDT L4

4GB

8GB

M395T5160QZ4-CE69

Montage D1

IDT L4

M395T5163QZ4-CE68/F78/E78

128Mx8(K4T1G084QQ) *36EA

4

DDP 512Mx4(K4T2G044QQ)

M395T1G60QJ4-CE68/F78

Note :

1G x 72

*36EA

IDT L4

1. “Z” of Part number(11th digit) stands for Lead-Free and RoHS compliant products.

2. “J” of Part number(11th digit) stands for Dual-Die Package based, Lead-Free and RoHS compliant products.

3. The last digit stands for AMB.

Table 2 : Performance range

F7(DDR2-800)

800

E7(DDR2-800)

800

E6(DDR2-667)

667

Unit

Mbps

CK

DDR2 DRAM Speed

CL-tRCD-tRP

6-6-6

5-5-5

Table 3 : Address Configuration

Organization

128Mx8(1Gb) based Module

256Mx4(1Gb) based Module

Row Address

A0-A13

Column Address

A0-A9

Bank Address

BA0-BA2

Auto Precharge

A10

A0-A13

A0-A9, A11

BA0-BA2

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FBDIMM

DDR2 SDRAM

2.0 FBDIMM GENERALS

2.1 FB-DIMM Operation Overview

FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth

and scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in

limited density build-up as channel speeds increase with memory system having the stub-bus architecture. FB-DIMM solution is

intended to eliminate this stub-bus channel bottleneck by using point-to-point links that enable multiple memory modules to be con-

nected serially to a given channel.

Memory system architecture perspective, FB-DIMM is fully differentiated from Registered DIMM and Unbuffered DIMM. A lot of new

technologies are integrated into this solution in order to achieve this scalable higher speed memory solution. Serial link interface with

packet data format and dedicated read/write paths are key attribute in FB-DIMM protocol. Point to Point interconnect with fully differen-

tial signaling and de-emphasis scheme are key attribute in FBD channel link. Clock recovery by using data stream is key attribute in FBD

clocking. FB-DIMM supports both clock resync and resampling mode options. CRC (Cyclic Redundancy Check) bits are transferred with

data stream for reliability at high speed data transaction. Failover mechanism supports system running with dynamic IO failure. Finally

all FB-DIMM is connected in daisy chain manner. Thus, every interconnection between AMB (advanced memory buffer) to AMB, AMB to

Host and AMB to DRAM, is point to point interconnection which allows higher data transfer bandwidth.

Figure 1 shows a lot of new technologies integrated with FBD solution.

Figure 1 : FB-DIMM Memory System Overview

DRAM

Two unidirectional links

Protocol Packet

DRAM

- Northbound

- Southbound

ADDR.CMD, DATA

DQs ADDR CLK

CMD

Daisy Chain

Connection

Upto 8 AMB

Rx

Tx

Clk_Ref

Tx

Rx

Tx

SB (ADDR, CMD, Wdata)

NB(Rdata)

AMB

Rx

Host

ADDR

CMD

DQs

CLK

DRAM

DIMM Topology

P2P Interconnect

- LVDS

Reliability

Fly-by CLK, CMD

Clock Recovery

- CRC fail-over

- De-Emphasis

FIFO

Buffer

Clock

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FBDIMM

DDR2 SDRAM

2.2 FB-DIMM Channel Frequency Scaling

There are many frequency parameters including reference clock frequency, DRAM clock frequency, DRAM data transfer rate, channel

transfer rate and channel unit interval. All of frequency parameters are scaled with a certain gear ratio. External clock source provides

reference clock input to AMB and Host. External clock source is relatively slower than channel and DRAM frequency. Thus, AMB dou-

bles external clock input and generates clock inputs to DRAMs. DRAM use clock input from AMB which is two times faster than refer-

ence clock for DRAM operation. DRAM data transfer rate is two times faster than DRAM clock input with nature of double data rate

operation and four times faster than external clock source. Channel speed is represented by unit interval - average time interval between

voltage transitions of a signal in the FBD channel. It is six times faster than DRAM data transfer rate. For example, external clock source

gives 6ns clock (166MHz), AMB doubles it and gives 3ns clock (333MHz) to DRAM and FBD channel communicate with unit interval -

250ps (4.0Gbps transfer rate).

Figure 2 shows frequency scale ratio over frequency parameters in FBD memory system.

Figure 2 : FB-DIMM Speed Scaling

DDR667 Ex.

6ns

3ns

CLK_REF

DRAM

CLK_DRAM

250ps Packet T/F

12 UIs in one CLK_DRAM

SB (ADDR, CMD, Wdata)

DQs ADDR CLK

CMD

Rx

Tx

Clk_Ref

Tx

Rx

AMB

Host

NB(Rdata)

DRAM

Reference CLK

Clock

UI

312.5ps

250ps

CLK_DRAM

266MHz

CLK_REF

133MHz

166MHz

200MHz

Frequency

3.2Gb/s

DDR2-533

DDR2-667

DDR2-800

333MHz

4.0Gb/s

208.33ps

400MHz

4.8Gb/s

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FBDIMM

DDR2 SDRAM

2.3 FB-DIMM Clocking Scheme

In FB-DIMM platform design, phase adjustment among reference clock inputs to each individual AMB and host is not taken account.

Thus, clock synchronization is made by using both external reference clock and channel data stream in FB-DIMM memory system. Host

and each individual AMB has a each individual IO basis clock recovery circuitry for channel data communication. It runs with inputs from

PLL inside chip and data stream from the other AMB or Host. Because data stream itself involves data communication process, no sig-

naling switching or data communication may loss clock synchronization between transmitter and receiver. Thus, min transition density is

defined for this purpose. In FBD channel, a density of 6 transitions within 512 transfers or unit intervals (UI) on the channel is required for

interpolator training.

Figure 3 : FB-DIMM Clocking

Min. Transition Density

6 Transitions

Using Reference CLK (Not in Phase)

Adjust edge/phase by; Min. Transition Density

DRAM

512 Transfers

DQs ADDR CLK

CMD

Rx

Tx

Rx

SB (ADDR, CMD, Wdata)

AMB

Tx

Clk_Ref

Host

NB(Rdata)

DRAM

Clock

Reference CLK

Recovery

Clock

2.4 FB-DIMM Protocol

FB-DIMM channel has two unidirectional communication paths - south bound and north bound. South bound and north bound use phys-

ically different signal path. South and north mean direction of signal transaction. Southbound means direction of signals running from the

host controller toward the DIMMs. North is the opposite of south. Due to nature of memory operation, southbound carries information

including command to DRAM, address to DRAM and write data to DRAM, while north bound carries read data from DRAM. In channel

protocol point of view, southbound and northbound have different data frame formats and frame format size is optimized to ratio of read

and write. Data transfer perspective, read data transfer rate of north bound is twice faster than write data transfer. Higher channel utiliza-

tion achieves with asymmetric read and write data transfer rate.

Figure 4 : Southbound / Northbound Frame format

Sout bound

Northbound

Command (with Address)

A CMD

B CMD

C CMD

R_Data(x72bits)

Command (with Address)

or Write Data in

R_Data(x72bits)

Command (with Address)

or Write Data in

Southbound consists of 10 differential signal pairs (lane), physically 20 signaling line. Southbound Format has 10x12 (10 IO (or Lane) x

12 IO switching) frame format, which deliver 10x12 bit information per one DRAM clock. One south bound frame is divided into three

command slot. See figure 5. Command slot A delivers command (with address). Command slot B and C delivers command (with

address) or write data into DRAM.

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FBDIMM

DDR2 SDRAM

Figure 5 : FBDIMM Command Encoding & SB Frame

Southbound Command Frame Format*

Bit

9

8

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

8

9

aE0 aE7 aE8 F0=0 aC20 aC16 aC12 aC8 aC4 aC0

aE1 aE6 aE9 F1=0 aC21 aC17 aC13 aC9 aC5 aC1

aE2 aE5 aE10 aE13 aC22 aC18 aC14 aC10 aC6 aC2

aE3 aE4 aE11 aE12 aC23 aC19 aC15 aC11 aC7 aC3

CLK_REF

CLK_DRAM

Packet T/F

A CMD

B CMD

C CMD

FE21

FE20

FE19

FE18

FE17

FE16

0

bC20 bC16 bC12 bC8 bC4 bC0

bC21 bC17 bC13 bC9 bC5 bC1

bC22 bC18 bC14 bC10 bC6 bC2

bC23 bC19 bC15 bC11 bC7 bC3

cC20 cC16 cC12 cC8 cC4 cC0

cC21 cC17 cC13 cC9 cC5 cC1

cC22 cC18 cC14 cC10 cC6 cC2

cC23 cC19 cC15 cC11 cC7 cC3

x10 bits

10 FE15

11 FE14

FE0 FE7 FE11

FE1 FE6 FE10

FE2 FE5 FE9 FE13

FE3 FE4 FE8 FE12

12 transfers

Note :

1. aE[0~12] : CRC Checksum of the A Command

2. F[0~1] : Frame Type

3. FE[0~21] : CRC Checksum of 72bit data

4. CRC : Cyclic Redundancy Check

DRAM Cmnds

23

22

21

20

1

0

19

18

17

16

X

15

X

14

X

13

X

12

11

10

9

8

7

6

5

4

3

2

1

0

Activate

Write

Read

DS2 DS1 DS0

DRAM Addr RS

DRAM Bank & Address

1

0

1

0

1

RS

Precharge All

1

0

1

0

1

0

X

Precharge Single

Auto (CBR) Refresh

Enter Self Refresh

DRAM Bank

X

Exit Self Refresh/

DS2 DS1 DS0

0

1

RS

X

0

1

X

Exit Power Down

Enter Power Down

reserved

0

1

RS

X

0

1

0

X

Note : The values in “ X” fields in non-reserved commands above may be driven onto the DRAM device pins.

2.5 Southbound Command Delivery

A DRAM command located in the "A" command may be delivered to the DRAM devices as soon as the 14-bit (10-bits in fail-over) CRC

is checked. This minimizes DRAM access latency by allowing the command to be delivered after the first 4 transfers of the frame have

been received. The "A" command is transferred immediately to the DRAM pins with minimum delay whereas the "B" and "C" command

are delivered one DRAM clock later. To minimize memory access latency the read related Activate, Read (if the page is open) and

explicit Precharge commands to a rank of DRAM devices should be placed in the "A" command, if possible. Figure 6 illustrates the deliv-

ery of the three potential commands in a frame to three separate DRAM channels.

Command "A" is delivered in this case to the DRAM devices on DIMM 3 as soon as the command can traverse the AMB buffer. The "B"

and "C" commands are delayed and presented to two other DRAM channels on the following clock. See below figure7~10 for Basic

Read & Write Operations

Northbound consists of 14 differential signal pairs (lane), physically 28 signaling line. Southbound Format has 14x12 (14 IO (or Lane) x

12 IO switching) frame format, which deliver 14x12 bit information per one DRAM clock. One north bound frame is divided into two. Both

frame deliver read data from DRAM

Figure 6 : FBDIMM Command Delivery Rules

1

2

3

4

5

“A”

“B”

“C”

FBD southbound

cmd/data

1. CMD A transferred immediately

2. CMD A, B, C cannot target the same DIMM

3. Host is responsible for scheduling CMD

DIMM 1 cmd

DIMM 2 cmd

“C”

“B”

DIMM 3 cmd

“A”

DIMM 4 cmd

FBD northbound

cmd/data

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FBDIMM

DDR2 SDRAM

2.6 Basic Timing Diagram

Figure 7 : Basic DRAM Read Data Transfers on FBD

1

2

3

4

5

6

7

8

9

10

11

12

13

ACT1

NOP

RD1

NOP

FBD southbound

cmd/data

DIMM 1 cmd

DIMM 1 data

DIMM 2 cmd

DIMM 2 data

ACT1

RD1

FBD northbound

data

Figure 8 : Back to Back DRAM Read Data Transfers

1

2

3

4

5

6

7

8

9

10

11

12

13

ACT1

NOP

ACT2 RD1

NOP NOP

RD2

NOP

FBD southbound

cmd/data

DIMM 1 cmd

DIMM 1 data

DIMM 2 cmd

DIMM 2 data

ACT1

RD1

ACT2

RD2

FBD northbound

data

No Bubble

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FBDIMM

DDR2 SDRAM

Figure 9 : Basic DRAM Write Data Transfers on FBD

1

2

3

4

5

6

7

8

9

10

11

12

13

ACT1

NOP

NOP WR1 NOP NOP SYNC

Wdata Wdata Wdata Wdata 1010

Wdata Wdata Wdata Wdata 0101

FBD southbound

cmd/data

DIMM 1 cmd

DIMM 1 data

DIMM 2 cmd

DIMM 2 data

ACT1

WR1

Fixed fall through time

FBD northbound

data

Status

Figure 10 : Simultaneous RD / WR Data Transfers

1

2

3

4

5

6

7

8

9

10

11

12

13

ACT1 ACT2 ACT3 RD1 WR2

RD3

SYNC

1010

0101

FBD southbound

cmd/data

Wdata Wdata Wdata Wdata NOP NOP

DIMM 1 cmd

DIMM 1 data

DIMM 2 cmd

DIMM 2 data

ACT1

ACT3 RD1

RD3

ACT2

WR2

FBD northbound

data

Status

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FBDIMM

DDR2 SDRAM

2.7 Advanced Memory Buffer Block Diagram

Figure 11 : Advanced Memory Buffer Block Diagram

Advance Memory Buffer

Block Dlagram

10x2

Southbound

Data In

10x2

Southbound

Data Out

NORTH

Data Merge

Re-Time

Re-synch

1x2

PLL

demux

PISO

mux

Ref Clock

10*2

Link Init SM

and Control

and CSRs

Reset#

Reset

Control

lnit

patterns

4

DRAM Clock

IBIST - RX

IBIST - TX

4

DRAM Clock #

Command

Decoder &

CRC Check

failover

LAI Logic

29

DRAM Address /

Cmd Out

Command Copy 1

DRAM Cmd

29

Thermal

Sensor

DRAM Address /

Command Copy 2

DDR State

Controller

and CSRs

Data Out

Data In

Core Control

and CSRs

36

deep

Write

Data

FIFO

72 + 18x2

DRAM

External MEMBIST

DDR calibration &

DDR IOBIST/DFX

Data / strobe

LAI

Controller

Data CRC Gen

& Read FIFO

Sync & ldie

NB LAI Buffer

Pattern

Generator

IBIST -TX

IBIST - RX

SMbus

Controller

mux

Link lnit SM

and Control

and CSRs

failover

14*6*2

14*12

PISO

demux

Re-synch

Re-Time

Data Merge

Northbound

Data Out

Northbound

Data In

14x2

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FBDIMM

DDR2 SDRAM

2.8 Interfaces

Figure12 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FBD links, one DDR2 channel and an SM-

Bus interface. Each FBD link connects the Advanced Memory Buffer to a host memory controller or an adjacent FBD. The DDR2 channel

supports direct connection to the DDR2 SDRAMs on a Fully Buffered DIMM

Figure 12 : Advanced Memory Buffer Interface Block Diagram

MEMORY INTERFACE

NB FBD

Out Link

NB FBD

In Link

AMB

SB FBD

Out Link

SB FBD

In Link

SMB

The FBDIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8 DIMMs per channel.

The host sends data on the southbound link to the first DIMM where it is received and redriven to the second DIMM. On the southbound

data path each DIMM receives the data and again redrives the data to the next DIMM until the last DIMM receives the data. The last DIMM

in the chain initiates the transmission of data in the direction of the host (a.k.a. northbound). On the northbound data path each DIMM

receives the data and re-drives the data to the next DIMM until the host is reached.

3.0 FBD HIGH-SPEED DIFFERENTIAL POINT TO POINT LINK (at 1.5 V) INTERFACE

The Advanced Memory Buffer supports one FBD Channel consisting of two bidirectional link interfaces using high-speed differential point-

to-point electrical signaling.

The southbound input link is 10 lanes wide and carries commands and write data from the host memory controller or the adjacent DIMM

in the host direction. The southbound output link forwards this same data to the next FBD.

The northbound input link is 14 lanes wide and carries read return data or status information from the next FBDIMM in the chain back

towards the host. The northbound output link forwards this information back towards the host and multiplexes in any read return data or

status information that is generated internally.

3.1 DDR2 Channel

The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The DDR2 channel supports two

ranks of eight banks with 16 row/column request, 64 data signals, and eight check-bit signals. There are two copies of address and com-

mand signals to support DIMM routing and electrical requirements. Four-transfer bursts are driven on the data and check-bit lines at 800

MHz.

Propagation delays between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by hardware

state machines using write/read trial and error (or equivalent implementation). Hardware aligns the read data and check-bits to a single

core clock.

The Advanced Memory Buffer provides four copies of the command clock phase references (CLK[3:0]) and write data/check-bit .

3.2 SMBus Slave Interface

The Advanced Memory Buffer supports an SMBus interface to allow system access to configuration registers independent of the FBD

link. The Advanced Memory Buffer will never be a master on the SMBus, only a slave. Serial SMBus data transfer is supported at 100

kHz. SMBus access to the Advanced Memory Buffer may be a requirement to boot a system. This provides a mechanism to set link

strength, frequency and other parameters needed to insure robust operation given platform specific configurations. It is also required for

diagnostic support when the link is down. The SMBus address straps located on the DIMM connector are used by the Advanced Memory

Buffer to get its unique ID.

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FBDIMM

DDR2 SDRAM

3.3 FBD Channel Latency

FBD channel latency is measured from the time a read request is driven on the FBD channel pins to the time when the first 16 bytes (2nd

chunk) of read completion data is sampled by the memory controller.

When not using the Variable Read Latency capability, the latency for a specific FBDIMM on an FBD channel is always equal to the latency

for any other FBDIMM on that channel. However, the latency for each FBDIMM in a specific configuration with some number of FBDIMMs

installed may not be equal to the latency for each FBDIMM in a configuration with some different number of FBDIMMs installed.

As more DIMMs are added to the FBD channel, additional latency is required to read from each DIMM on the channel. Because the FBD

channel is based on the point-to-point interconnection of buffer components between DIMMs, memory requests are required to travel

through N-1 buffers before reaching the Nth buffer. The result is that a four DIMM channel configuration will have greater idle read latency

compared to a one DIMM channel configuration.

The Variable Read Latency capability can be used to reduce latency for DIMMs closer to the host.

The idle latencies listed in this section are representative of what might be achieved in typical AMB designs. Actual implementations with

latencies less than the values listed will have higher application performance and vice versa.

3.4 Peak Theoretical Throughput

An FBD channel transfers read completion data on the FBD Northbound data connection. 144 bits of data are transferred for every FBD

Northbound data frame. This matches the 18-byte data transfer of an ECC DDR DRAM in a single DRAM command clock. A DRAM burst

of 8 from a single channel or a DRAM burst of four from two lock-stepped channels provides a total of 72 bytes of data (64 bytes plus 8

bytes ECC).

The FBD frame rate matches the DRAM command clock because of the fixed 6:1 ratio of the FBD channel clock to the DRAM command

clock. Therefore, the Northbound data connection will exhibit the same peak theoretical throughput as a single DRAM channel. For exam-

ple, when using DDR2 533 DRAMs, the peak theoretical bandwidth of the Northbound data connection is 4.267 GB/sec.

Write data is transferred on the FBD Southbound command and data connection, via Command+Wdata frames. 72 bits of data are trans-

ferred for every FBD Command+Wdata frame. Two Command+Wdata frames match the 18-byte data transfer of an ECC DDR DRAM in

a single DRAM command clock. A DRAM burst of 8 transfers from a single channel, or a burst of 4 from two lock-step channels provides

a total of 72 bytes of data (64 bytes plus 8 bytes ECC).

When the FBD frame rate matches the DRAM command clock, the Southbound command and data connection will exhibit one half the

peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak theoretical bandwidth of

the Southbound command and data connection is 2.133 GB/sec.

The total peak theoretical throughput for a single FBD channel is defined as the sum of the peak theoretical throughput of the Northbound

data connection and the Southbound command and data connection. When the FBD frame rate matches the DRAM command clock, this

is equal to 1.5 times the peak theoretical throughput of a single DRAM channel. For example, when using DDR2 533 DRAMs, the peak

theoretical throughput of a DDR2 533 channel would be 4.267 GB/sec, while the peak theoretical throughput of an FBD-533 channel would

be 6.4 GB/sec

3.5 Hot-add

The FBDIMM channel does not provide a mechanism to automatically detect and report the addition of a new FBDIMM south of the cur-

rently active last FBDIMM. It is assumed the system will be notified through some means of the addition of one or more new FBDIMMs so

that specific commands can be sent to the host controller to initialize the newly added FBDIMM(s) and perform a hot-add reset to bring

them into the channel timing domain. It should be noted that the power to the FBDIMM socket must be removed before a hot-add FBDIMM

is inserted or removed. Applying or removing the power to a FBDIMM socket is a system platform function.

3.6 Hot remove

In order to accomplish removal of FBDIMMs, the host must perform a fast reset sequence targeted at the last FBDIMM that will be retained

on the channel. The fast reset re-establishes the appropriate last FBDIMM so that the southbound transmission outputs of the last active

FBDIMM and the southbound and northbound outputs of the FBDIMMs beyond the last active FBDIMM are disabled. Once the appropriate

outputs are disabled, the system can coordinate the procedure to remove power in preparation for physical removal of the FBDIMM if need-

ed. Note that the power to the FBDIMM socket must be removed before a hot-add FBDIMM is inserted or removed. Applying or removing

the power to a FBDIMM socket is a system platform function.

3.7 Hot replace

Hot replace of FBDIMM is accomplished through combining the hot-remove and hotadd processes

Rev. 1.3 December 2008

13 of 42

FBDIMM

DDR2 SDRAM

4.0 PIN CONFIGUREATION

Table 4 : DDR2 240 Pin FBDIMM Configurations (Front side/Back side)

1

Front

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Back

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

Front

PN3

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Back

SN3

61

62

63

64

65

66

67

68

Front

PN9

181

182

183

184

185

186

187

188

Back

SN9

91

Front

PS9

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

SS9

V

DD

V

2

PN3

SN3

92

DD

SS

V

3

PN10

SN10

93

PS5

SS5

DD

SS

V

4

PN4

SN4

94

SS

V

5

95

DD

SS

V

6

PN11

SN11

96

PS6

SS6

DD

SS

V

7

PN5

SN5

97

DD

V

8

98

SS

V

9

KEY

99

PS7

SS7

CC

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

PN13

SN13

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

CC

SS

V

PS0

SS0

SS

V

PS8

SS8

CC

SS

V

CC

SS

V

RFU*

PS1

SS1

SS

V

RFU**

TT

V

VID1

VID0

SS

V

RESET

DNU/M_Test

PS2

SS2

SS

V

PN12

SN12

SCK

SS

DD

V

RFU**

SS

DD

V

PS3

SS3

SS

V

PN6

SN6

SS

DD

V

PN0

SN0

SS

DD

V

PS4

SS4

SS

DD

V

PN7

SN7

SS

V

PN1

SN1

SS

DD

V

SS

DD

V

PN8

SN8

RFU*

SS

TT

V

PN2

SN2

SA2

SDA

SCL

DDSPD

V

SA0

SS

V

PN9

SN9

SA1

SS

PS9

SS9

RFU = Reserved Future Use.

* These pin positions are reserved for forwarded clocks to be used in future module implementations

** These pin positions are reserved for future architecture flexibility

1. The following signals are CRC bits and thus appear out of the normal sequence : PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN12,

PS9/PS9, SS9/SS9.

Rev. 1.3 December 2008

14 of 42

FBDIMM

DDR2 SDRAM

Table 5 : Pin Description

Pin Name

SCK

Type

Input

Pin Description

System Clock Input, positive line

Pin Numbers

228

229

SCK

Input

System Clock Input, negative line

PN[13:0]

PS[9:0]

Output

Input

Primary northbound Data, positive lines

Primary northbound Data, negative lines

Primary Southbound Data, positive lines

Primary Southbound Data, negative lines

22, 25, 28, 31, 34, 37, 40, 48, 51, 54, 57, 60, 63, 66

23, 26, 29, 32, 35, 38, 41, 49, 52, 55, 58, 61, 64, 67

70, 73, 76, 79, 82, 90, 93, 96, 99, 102

Input

71, 74, 77, 80, 83, 91, 94, 97, 100, 103

142, 145, 148, 151, 154, 157, 160, 168, 171, 174, 177,

180, 183, 186

SN[13:0]

Output

Secondary Northbound Data, positive lines

Secondary Northbound Data, negative lines

143, 146, 149, 152, 155, 158, 161, 16, 172, 175, 178,

181, 184, 187

SS[9:0]

SCL

Input

Secondary Southbound Data, positive lines

Secondary Southbound Data, negative lines

Serial Presence Detect (SPD) Clock Input

SPD Data Input / Output

190, 193, 196, 199, 202, 210, 213, 216, 219, 222

191, 194, 197, 200, 203, 211, 214, 217, 220, 223

120

119

SDA

SPD Address Inputs, also used to slelect the DIMM number in

the AMB

SA[2:0]

Input

118, 239, 240

Voltage ID : These pins must be unconnected for DDR2 -

based Fully Buffered DIMMs

V

[1:0]

NC

16, 136

17

ID

V

[0] is V value : OPEN = 1.8 V, GND = 1.5 V ; V [1] is

ID

CC

DD ID

value : OPEN = 1.5V, GND = 1.2V

RESET

RFU

Input

RFU

AMB reset signal

19, 20, 44, 45, 86, 87, 105, 106, 139, 140, 164, 165,

206, 207, 225, 226

Reserved for Future Use

AMB Core Power and AMB Channel Interface Power (1.5

Volt)

V

PWR

9, 10, 12, 13, 129, 130, 132, 133

CC

DD

1, 2, 3, 5, 6, 7, 108, 109, 111, 112, 113, 115, 116, 121,

122, 123, 125, 126, 127, 231, 232, 233, 235, 236

DRAM Power and AMB DRAM I/O Power (1.8Volt)

V

PWR

DRAM Address/Command/Clcok Termination Power(V /2) 15, 117, 135, 237

DD

TT

V

SPD Power

238

DDSPD

4, 8, 11, 14, 18, 21, 24, 27, 30, 33, 36, 39, 42, 43, 46,

47, 50, 53, 56, 59, 62, 65, 68, 69, 72, 75, 78, 81, 84, 85,

88, 89, 92, 95, 98, 101, 104, 107, 110, 114, 124, 128,

131, 134, 138, 141, 144, 147, 150, 153, 156, 159, 162,

163, 166, 167, 170, 173, 176, 179, 182, 185, 188, 189,

192, 195, 198, 201, 204, 205, 208, 209, 212, 215, 218,

221, 224, 227, 230, 234

V

GND

DNU

Ground

SS

The DNU/M_Test pin provides an external connection R/Cs A-

D for testing the margin of Vref which is produced by a voltage

divider on the module. It is not intended to be used in normal

DNU/M_Test

system operation and must not be connected (DNU) in a sys- 137

tem. This test pin may have other features on future card de-

signs and if it does, will be included in this specification at that

time.

Rev. 1.3 December 2008

15 of 42

FBDIMM

DDR2 SDRAM

5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM

5.1 1GB, 128Mx72 Module - M395T2863QZ4

(populated as 1 rank of x8 DDR2 SDRAMs)

S0

DQS0

DQS9

DQS4

DQS13

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

I/O 0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D4

DQS1

DQS5

DQS10

DQS14

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

DQ9

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS6

DQS11

DQS15

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D6

DQS7

DQS3

DQS16

DQS12

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

D7

D3

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

PN0-PN13

PS0-PS9

SN0-SN13

SS0-SS9

DQS17

DM/ NU/ CS DQS DQS

RDQS RDQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

S0->CS(all SDRAMs)

I/O 1

DQ0-DQ63

CB0-CB7

D8

CKE0->CKE(all SDRAMs)

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A

M

B

DQS0-DQS17

DQS0-DQS8

ODT->ODT(all SDRAMs)

BA0-BA2(all SDRAMs)

A0-A15(all SDRAMs)

RAS(all SDRAMs)

SCL

SDA

SA1-SA2

SA0

CAS(all SDRAMs)

RESET

Serial PD

WE(all SDRAMs)

CK/CK(all SDRAMs)

SCK/SCK

V

Terminators

AMB

TT

SCL

SDA

All address/command/control/clock

V

WP A0 A1 A2

SA0 SA1 SA2

TT

V

CC

V

SPD, AMB

D0-D8, AMB

D0-D8

DDSPD

V

DD

V

REF

Note :

1.DQ-to I/O wiring may be changed within a byte.

2.There are two physical copies of each address/command/control/clock

V

D0-D8,SPD,AMB

SS

Rev. 1.3 December 2008

16 of 42

FBDIMM

DDR2 SDRAM

5.2 2GB, 256Mx72 Module - M395T5663QZ4

(populated as 2 rank of x8 DDR2 SDRAMs)

S1

S0

DQS0

DQS9

DQS4

DQS13

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

I/O 0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D9

D4

D13

DQS1

DQS5

DQS10

DQS14

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

DQ9

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D10

D5

D14

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS6

DQS11

DQS15

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D11

D6

D15

DQS7

DQS3

DQS16

DQS12

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

D7

D16

D3

D12

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS8

PN0-PN13

PS0-PS9

SN0-SN13

SS0-SS9

DQS17

DM/ NU/ CS DQS DQS

RDQS RDQS

DM/ NU/ CS DQS DQS

RDQS RDQS

S0->CS(D0-D8)

DQ0-DQ63

CB0-CB7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

CKE0->CKE(D0-D8)

S1->CS(D9-D17)

A

M

B

I/O 1

DQS0-DQS17

DQS0-DQS8

D8

D17

CKE1->CKE(D9-D17)

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

ODT->ODT(all SDRAMs)

BA0-BA2(all SDRAMs)

A0-A15(all SDRAMs)

RAS(all SDRAMs)

SCL

SDA

SA1-SA2

SA0

CAS(all SDRAMs)

RESET

WE(all SDRAMs)

CK/CK(all SDRAMs)

SCK/SCK

V

All address/command/control/clock

TT

V

Terminators

TT

Serial PD

V

AMB

CC

SCL

SDA

WP A0 A1 A2

V

SPD, AMB

D0-D17, AMB

D0-D17

DDSPD

V

DD

SA0 SA1 SA2

V

REF

Note :

1.DQ-to I/O wiring may be changed within a byte.

2.There are two physical copies of each address/command/control/clock

V

D0-D17,SPD,AMB

SS

Rev. 1.3 December 2008

17 of 42

FBDIMM

DDR2 SDRAM

5.3 4GB, 512Mx72 Module - M395T5160QZ4

(populated as 2 rank of x4 DDR2 SDRAMs)

V_SS

S1

S0

DQS0

DQS9

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ0

DQ4

DQ5

DQ6

DQ7

I/O 0

DQ1

DQ2

DQ3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

D0

D18

D9

D27

DQS1

DQS10

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ12

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ9

DQ13

DQ14

DQ15

D1

D19

D10

D28

DQ10

DQ11

DQS2

DQS11

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ20

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ17

DQ18

DQ19

DQ21

DQ22

DQ23

D2

D20

D11

D29

DQS3

DQS12

DQS3

DQS12

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ28

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ25

DQ26

DQ27

DQ29

DQ30

DQ31

D3

D21

D12

D30

DQS4

DQS13

DQS4

DQS13

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ32

DQ36

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ33

DQ34

DQ35

DQ37

DQ38

DQ39

D4

D22

D13

D31

DQS5

DQS14

DQS5

DQS14

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ40

DQ44

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ41

DQ42

DQ43

DQ45

DQ46

DQ47

D5

D23

D14

D32

DQS6

DQS15

DQS6

DQS15

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ48

DQ52

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ49

DQ50

DQ51

DQ53

DQ54

DQ55

D6

D24

D15

D33

DQS7

DQS16

DQS7

DQS16

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ56

DQ60

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ57

DQ58

DQ59

DQ61

DQ62

DQ63

D7

D25

D16

D34

DQS8

DQS17

DQS8

DQS17

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

CB0

CB4

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

CB1

CB2

CB3

CB5

CB6

CB7

D8

D26

D17

D35

PN0-PN13

SN0-SN13

SS0-SS9

V

All address/command/control/clock

TT

PN0-PN13

PS0-PS9

Serial PD

S0->CS(D0-D17)

DQ0-DQ63

CB0-CB7

CKE0->CKE(D0-D17)

S1->CS(D18-D35)

A

DQS0-DQS17

DQS0-DQS8

SCL

SDA

M

B

CKE1->CKE(D18-D35)

WP A0 A1 A2

ODT->ODT(all SDRAMs)

BA0-BA2(all SDRAMs)

A0-A15(all SDRAMs)

RAS(all SDRAMs)

SCL

V

Terminators

AMB

TT

SDA

SA1-SA2

SA0

V

SA0 SA1 SA2

CC

CAS(all SDRAMs)

RESET

WE(all SDRAMs)

CK/CK(all SDRAMs)

V

SPD, AMB

D0-D35, AMB

D0-D35

SCK/SCK

DDSPD

V

DD

V

REF

V

D0-D35,SPD,AMB

SS

Note :

1. DQ-to I/O wiring may be changed within a byte.

2. There are two physical copies of each address/command/control/clock.

3. There are four physical copies of each clock.

Rev. 1.3 December 2008

18 of 42

FBDIMM

DDR2 SDRAM

5.4 4GB, 512Mx72 Module - M395T5163QZ4

(populated as 4 rank of x8 DDR2 SDRAMs)

DQS0

DQS9

S0

S1

S2

S3

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

I/O 0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D9

D18

D0

DQS1

DQS10

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DQ8

I/O 0

DQ9

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D10

D19

D28

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS11

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D11

D20

D29

DQS3

DQS12

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D12

D21

D30

DQS4

DQS13

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D4

D13

D22

D31

Rev. 1.3 December 2008

19 of 42

FBDIMM

DDR2 SDRAM

DQS5

DQS14

S0

S1

S2

S3

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

I/O 0

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

D5

D14

D23

D32

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS6

DQS15

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D6

D15

D24

D33

DQS7

DQS16

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D7

D16

D25

D34

DQS3

DQS12

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

DM/ NU/ DQS DQS CS

RDQS RDQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D8

D17

D26

D35

Serial PD

SN0-SN13

PN0-PN13

SN0-SN13

PN0-PN13

PS0-PS9

SS0-SS9

SCL

SDA

WP A0 A1 A2

SA0 SA1 SA2

CK0 -> CKE (D0 - D17)

CK1 -> CKE (D18 - D35)

ODT0 -> ODT (D0 - D17)

ODT1 -> ODT (D18 - D26)

ODT2 -> ODT (D27 - D35)

BA0-BA2 (all SDRAMs)

DQ0-DQ63

CB0-CB7

A

M

B

DQS0-DQS17

DQS0-DQS8

SCL

SDA

A0,A1-A3-A5, A7-A15 (all SDRAMs)

A2_ECC, A6_ECC(D8,D17,D26,D35)

RAS (all SDRAMs)

SA1-SA2

SA0

CAS (all SDRAMs)

V

RESET

All address/command/control/clock

TT

WE (all SDRAMs)

CK/CK (all SDRAMs)

SCK/SCK

V

Terminators

AMB

TT

V

CC

V

SPD, AMB

D0-D17, AMB

D0-D17

DDSPD

V

DD

V

REF

Note :

1. DQ-to I/O wiring may be changed within a byte.

2. There are two physical copies of each address/command/control/clock.

V

D0-D17,SPD,AMB

SS

Rev. 1.3 December 2008

20 of 42

FBDIMM

DDR2 SDRAM

5.5 8GB, 1Gx72 Module - M395T1G60QJ4

(populated as 4 rank of x4 DDR2 SDRAMs)

V_SS

S1

S3

S0

S2

DQS0

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ0

I/O 0

DQ1

DQ2

DQ3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

D0

D36

D18

D54

DQS9

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ4

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ5

DQ6

DQ7

D1

D37

D19

D55

DQS1

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ9

D2

D38

D20

D56

DQ10

DQ11

DQS10

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ12

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ13

DQ14

DQ15

D3

D39

D21

D57

DQS2

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ17

DQ18

DQ19

D4

D40

D22

D58

DQS11

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ20

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ21

DQ22

DQ23

D5

D41

D23

D59

DQS3

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ25

DQ26

DQ27

D6

D42

D24

D60

DQS12

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ28

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ29

DQ30

DQ31

D7

D43

D25

D61

DQS8

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

CB0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

CB1

CB2

CB3

D8

D44

D26

D62

Rev. 1.3 December 2008

21 of 42

FBDIMM

DDR2 SDRAM

V_SS

S1

S3

S0

S2

DQS4

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

I/O 1

I/O 2

I/O 3

D9

D45

D27

D63

DQS13

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D10

D46

D28

D64

DQS5

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ40

DQ41

DQ42

DQ43

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D11

D47

D29

D65

DQS10

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D12

D48

D30

D66

DQS6

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D13

D49

D31

D67

DQS11

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D14

D50

D32

D68

DQS7

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D15

D51

D33

D69

DQS16

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D16

D52

D34

D70

DQS17

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D17

D53

D35

D71

V

All address/command/control/clock

TT

Serial PD

PN0-PN13

PS0-PS9

SN0-SN13

SS0-SS9

SCL

SDA

WP A0 A1 A2

SA0 SA1 SA2

S0->CS(D36-D53)

DQ0-DQ63

CB0-CB7

DQS0-DQS17

S1->CS(D54-D71)

S2->CS(D0-D17)

S3->CS(D18-D35)

CKE0 -> CKE (D0-D17,D36-D53)

CKE1 -> CKE (D18-D35,D53-D71)

ODT->ODT0 (D36-D71)

BA0-BA2 (all SDRAMs)

A0,A1-A3-A5,A7-A13 (all SDRAMs)

A

M

B

V

Terminators

AMB

TT

SCL

SDA

SA1-SA2

SA0

V

CC

A2,A6 (D0-D7, D9-D16, D18-D25, D27-D34, D36-D43, D45-D52, D54-D61, D63-D70)

ECCA2,ECCA6 (D8, D17, D26, D35, D44, D53, D62, D71)

RAS(all SDRAMs)

V

SPD, AMB

D0-D71, AMB

D0-D71

RESET

DDSPD

CAS(all SDRAMs)

SCK/SCK

WE(all SDRAMs)

V

DD

CK/CK(all SDRAMs)

V

REF

Note :

1. DQ-to I/O wiring may be changed within a nibble

V

D0-D71,SPD,AMB

SS

2. There are two physical copies of each address/command/control excluding CS

3. There are four physical copies of each clock.

4. ODT pin(D0-D35) is connected to V

SS

Rev. 1.3 December 2008

22 of 42

FBDIMM

DDR2 SDRAM

6.0 ELECTRICAL CHARACTERISTICS

Table 6 : AbsoIute Maximum Ratings

Parameter

Symbol

, V

OUT

MIN

-0.3

-0.5

-55

0

MAX

1.75

2.3

Units

V

Note

Voltage on any pin relative to V

V

1

SS

IN

Voltage on V pin relative to V

V

CC

V

CC

SS

Voltage V pin relative to V

V

DD

V

DD

SS

Voltage on V pin relative to V

TT

V

2.3

V

SS

TT

Storage temperature

T

100

85

°C

STG

DDR2 SDRAM device operating temperature(Ambient)

T

°C

1,2

CASE

85

95

AMB device operating temperature (Ambient)

T

0

110

°C

1,2

CASE

Note : 1. Stresses greater than those Iisted may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may adversely affect reliability.

2. DDR2 SDRAMs of FBDIMM should require this specification.

Parameter

Symbol

DRAM

Units

µs

0 °C ≤ T

≤ 85°C

≤ 95°C

7.8

CASE

Average periodic refresh interval

tREFI

85 °C < T

3.9

µs

CASE

Table 7 : Input DC Operating Conditions

Parameter

AMB supply voltage

Symbol

MIN

1.455

1.7

Nom

1.50

MAX

1.575

1.9

Units

Notes

V

CC

DD

DDR2 SDRAM supply voltage

Termination voltage

1.8

V

0.48 x V

3.0

0.50 x V

3.3

0.52 x V

3.6

V

TT

DDSPD

DD

EEPROM supply voltage

V

SPD Input HIGH (Iogic 1) voltage

SPD Input LOW (logic 0) voltage

RESET Input HIGH (logic 1) voltage

RESET Input LOW (logic 0) voltage

Leakage Current (RESET)

Leakage Current (link)

V

(DC)

2.1

V

1

2

1

2

3

IH

DDSPD

V (DC)

0.8

V

IL

V

(DC)

V

IH

V (DC)

0.5

90

5

V

IL

I

-90

-5

uA

L

Note : 1. Applies for SMB and SPD bus signals.

2. Applies for AMB CMOS signal RESET.

3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specification.

Table 8 : Timing Parameters

Parameter

EI Assertion Pass-Thru Timing

EI Deassertion Pass-Thru Timing

EI Assertion Duration

Symbol

tEI Propagatet

tEID

MIN

Typ.

Max.

4

Units

Notes

clks

ns

-

2

Bitlock

tEI

100

1,2

3

FBD Cmd to DDR Clk out that latches Cmd

FBD Cmd to DDR Write

8.1

TBD

5.0

ns

DDR Read to FBD (last DIMM)

Resample Pass-Thru time

ResynchPass-Thru time

ns

4

1.075

2.075

ns

Bit Lock Interval

tBitLock

119

154

frames

1

Frame Lock Interval

tFrameLock

Note : 1. Defined in FB-DIMM Architecture and Protocol Spec

2. Clocks defined as core clocks = 2x SCK input

3. @DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to the DRAMs

4. @ DDR2-667 - measured from latest DQS input AMB TO start of matching data frame at northbound FB-DIMM outputs.

Rev. 1.3 December 2008

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FBDIMM

DDR2 SDRAM

Table 9 : Power specification parameter and test condition

Power

Units

Symbol

Conditions

Supply

Icc_Idle_0

Idle Current, single or last DIMM

L0 state, idle (0 BW)

Primary channel enabled, Secondary Channel Disabled

CKE high. Command and address lines stable.

DRAM clock active.

@1.5V

mA

Idd_Idle_0

@1.8V

mA

Idd_Idle_0 Total Power

W

Icc_Idle_1

Idd_Idle_1

Idle Current, first DIMM

@1.5V

@1.8V

mA

L0 state, idle (0 BW)

Primary and Secondary channels enabled

CKE high. Command and address lines stable.

DRAM clock active.

mA

Idd_Idle_1 Total Power

W

Icc_Active_1

Idd_Active_1

Active Power

@1.5V

@1.8V

mA

L0 state.

50% DRAM BW, 67% read, 33% write.

Primary and Secondary channels enabled.

DRAM clock active, CKE high.

mA

Idd_Active_1 Total Power

W

Icc_Active_2

Idd_Active_2

Active Power, data pass through

L0 state.

50% DRAM BW to downstream DIMM, 67% read, 33% write.

Primary and Secondary channels enabled

CKE high. Command and address lines stable.

DRAM clock active.

@1.5V

@1.8V

mA

Idd_Active_2 Total Power

W

Idd_Training

(for AMB spec, Not in

SPD)

Training

@1.5V

@1.8V

mA

Primary and Secondary channels enabled.

100% toggle on all channel lanes

DRAMs idle. 0 BW.

Idd_Training

(for AMB spec, Not in

SPD)

CKE high, Command and address lines stable.

DRAM clock active.

mA

W

Idd_Training Total Power

Rev. 1.3 December 2008

24 of 42

FBDIMM

DDR2 SDRAM

Table 10.1 : Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V)

1GB(M395T2863QZ4)

Symbol

E66

E65

E68

E69

F76

F78

(PC2-6400)

1700

770

E76

Notes

Unit

(PC2-5300)

Icc_Idle_0

2600

970

2600

970

1600

770

1480

770

3200

1070

7.07

3200

1070

7.07

@1.5V

@1.8V

mA

W

Idd_Idle_0

P_idle_0

5.94

3400

970

5.94

3400

970

3.98

2300

770

3.79

1930

790

4.14

Icc_Idle_1

Idd_Idle_1

P_idle_1

4200

1070

8.65

2500

770

4200

1070

8.65

@1.5V

@1.8V

mA

W

7.20

3900

2335

10.58

3700

970

7.20

3900

2335

10.58

3700

970

5.09

2900

2235

8.81

2400

770

4.54

1990

1765

6.49

1920

790

5.40

Icc_active_1

Idd_active_1

P_active_1

Icc_active_2

Idd_active_2

P_active_2

Icc_training

Idd_training

P_training

4700

2556

12.26

4500

1070

9.12

3300

2456

9.86

4700

2556

12.26

4500

1070

9.12

@1.5V

@1.8V

mA

W

2600

770

@1.5V

@1.8V

mA

W

7.67

4000

970

7.67

4000

970

5.24

2300

670

4.53

1960

810

5.56

4600

1070

9.28

2400

670

4600

1070

9.28

@1.5V

@1.8V

mA

W

8.14

4.90

4.63

5.05

Table 10.2 : Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V)

2GB(M395T5663QZ4)

Symbol

E66

E65

E68

E69

F76

F78

(PC2-6400)

1700

1040

4.65

E76

Notes

Unit

(PC2-5300)

Icc_Idle_0

2600

1240

6.45

2600

1980

7.86

1600

1040

4.50

2300

1040

5.60

2900

2505

9.33

2400

1040

5.76

2300

940

1480

1040

4.31

3200

1340

7.59

3200

1340

7.59

@1.5V

@1.8V

mA

W

Idd_Idle_0

P_idle_0

Icc_Idle_1

Idd_Idle_1

P_idle_1

3400

1240

7.71

4000

1980

9.12

1930

1060

5.05

4200

1340

9.16

2500

1040

5.91

4200

1340

9.16

@1.5V

@1.8V

mA

W

Icc_active_1

Idd_active_1

P_active_1

Icc_active_2

Idd_active_2

P_active_2

Icc_training

Idd_training

P_training

3900

2605

11.09

3700

1240

8.18

3900

4221

14.16

3700

1980

9.59

1990

2035

7.00

4700

2826

12.77

4500

1340

9.63

3300

2726

10.38

2600

1040

6.07

4700

2826

12.77

4500

1340

9.63

@1.5V

@1.8V

mA

W

1920

1060

5.04

@1.5V

@1.8V

mA

W

4000

1240

8.66

4000

1980

10.06

1960

1080

5.14

4600

1340

9.79

2400

940

4600

1340

9.79

@1.5V

@1.8V

mA

W

5.41

5.57

Note :

1. FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet.

Rev. 1.3 December 2008

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FBDIMM

DDR2 SDRAM

Table 10.3 : Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V)

4GB(M395T5160QZ4)

Symbol

Notes

Unit

E66

E65

E68

E69

F76

E76

(PC2-5300)

(PC2-6400)

Icc_Idle_0

2600

1980

7.86

2600

1980

7.86

1700

1580

5.68

1480

1650

5.47

1930

1680

6.23

1990

3361

9.52

1920

1680

6.22

1960

1700

6.32

3200

2080

8.99

3200

2080

8.99

@1.5V

@1.8V

mA

W

Idd_Idle_0

P_idle_0

Icc_Idle_1

Idd_Idle_1

P_idle_1

3400

1980

9.12

3400

1980

9.12

2600

1580

7.10

4200

2080

10.57

4700

4661

16.26

4500

2080

11.04

4600

2080

11.20

4200

2080

10.57

4700

4661

16.26

4500

2080

11.04

4600

2080

11.20

@1.5V

@1.8V

mA

W

Icc_active_1

Idd_active_1

P_active_1

Icc_active_2

Idd_active_2

P_active_2

Icc_training

Idd_training

P_training

3900

4221

14.16

3700

1980

9.59

3900

4221

14.16

3700

1980

9.59

3200

3921

12.49

2600

1580

7.10

@1.5V

@1.8V

mA

W

@1.5V

@1.8V

mA

W

4000

1980

10.06

4000

1980

10.06

2500

1580

6.94

@1.5V

@1.8V

mA

W

Note :

1. FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet.

Table 10.4 : Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V)

4GB(M395T5163QZ4)

Symbol

E68

(PC2-5300)

1600

1580

5.52

F78

(PC2-6400)

1700

1580

5.68

E78

(PC2-6400)

1700

1580

5.68

Notes

Unit

Icc_Idle_0

@1.5V

@1.8V

mA

W

Idd_Idle_0

P_idle_0

Icc_Idle_1

Idd_Idle_1

P_idle_1

2300

1580

6.62

2500

1580

6.94

2500

1580

6.94

@1.5V

@1.8V

mA

W

Icc_active_1

Idd_active_1

P_active_1

Icc_active_2

Idd_active_2

P_active_2

Icc_training

Idd_training

P_training

2900

3045

10.35

2400

1580

6.78

3300

3266

11.40

2600

1580

7.10

3300

3266

11.40

2600

1580

7.10

@1.5V

@1.8V

mA

W

@1.5V

@1.8V

mA

W

2300

1480

6.43

2400

1480

6.59

2400

1480

6.59

@1.5V

@1.8V

mA

W

Note :

1. FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet.

Rev. 1.3 December 2008

26 of 42

FBDIMM

DDR2 SDRAM

Table 10.5 : Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V)

8GB(M395T1G60QJ4)

Symbol

E68

(PC2-5300)

1700

2660

7.73

F78

(PC2-6400)

1900

2660

8.05

Notes

Unit

Icc_Idle_0

Idd_Idle_0

P_idle_0

@1.5V

@1.8V

mA

W

Icc_Idle_1

Idd_Idle_1

P_idle_1

2600

2660

9.15

2800

2660

9.46

@1.5V

@1.8V

mA

W

Icc_active_1

Idd_active_1

P_active_1

Icc_active_2

Idd_active_2

P_active_2

Icc_training

Idd_training

P_training

3200

5001

14.54

2600

2660

9.15

3600

5241

15.63

2800

2660

9.46

@1.5V

@1.8V

mA

W

@1.5V

@1.8V

mA

W

2500

2660

8.99

2700

2660

9.31

@1.5V

@1.8V

mA

W

Note :

1. FBDIMM Power was calculated on the basis of DRAM and AMB Values in datasheet.

Rev. 1.3 December 2008

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FBDIMM

DDR2 SDRAM

Table 11 : V_TTCurrents

Description

Symbol

ITT1

Typ

500

MAX

700

Units

mA

Idle current, DDR2 SDRAM device power down

Active power, 50% DDR2 SDRAM BW

ITT2

700

mA

Table 12 : Reference Clock Input Specifications

Values

Parameter

Symbol

Units

Note

MIN

MAX

Reference clock frequency @3.2 Gb/s

(nominal 133.33 MHz)

Reference clock frequency @4.0 Gb/s

(nominal 166.67 MHz)

Rise time, fall time

Voltage high

Voltage low

fRefclk-3.2

fRefclk-4.0

126.67

133.40

MHz

1.2

158.33

166.75

1.2

3

T

, T

175

660

-150

700

850

ps

SCK-RISE SCK-FALL

V

mV

SCK-HIGH

V

SCK-LOW

Absolute crossing point

Relative crossing

V

250

calculated

550

calculated

4

4,5

CROSS-ABS

CROSS-REL

Percent mismatch between rise and

fall times

T

-

10

%

SCK-RISE-FALL-MATCH

Duty cycle of reference clock

Clock leakage current

Clock input capacitance

Clock input capacitance delta

Transport delay

Phase jitter sample size

Reference clock jitter, filtered

Reference clock deterministic jitter

Note :

T

40

-10

0.5

60

10

2

0.25

5

%

uA

pF

ns

SCK-DUTYCYCLE

I

6,7

7

8

9, 10

11

12,13

I-CK

C

I-CK

C

-0.25

I_CK(D)

T1

16

NSAMPLE

10

Periods

ps

T

40

TBD

REF-JITTER

T

ps

REF-DJ

1.133MHz for PC2-4200 and 166MHz for PC2-5300.

2. Measured with SSC disabled.

3. Measured differentially through the range of 0.175V to 0.525V.

4. The crossing point must meet the absolute and relative crossing point specification simultaneously.

5. V and V are derived using the following calculation : Min = 0.5(V

-0.710)+0.250;and Max=0.5(V -0.710)+0.550,

havg

CROSS_REL_(MIN)

CROSS_REL(MAX)

havg

where Vhavg is the average of V

SCK-HIGHM.

6. Measured with a single-ended input voltage of 1V.

7. Applies to reference clocks SCK and SCK.

8. Difference between SCK and SCK input.

9. T1 = [Tdatapath-Tclockpath](excluding PLL loop delays). This parameter is not a direct clock output parameter but in indirectly determines the clock

output parameter T

REF-JITTER.

10. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined from the reference clock

source, through the TX, to data arrival at the data dampling point in the RX. The clock path is defined from the reference clock source to clock arrival

at the same sampling point. The path delays are caused by copper trace routes. on-chip routing, on-chip buffering, etc. They include the time-of flight

of interpolators or other clock adjustment mechanisms. They do not include the phase delays caused by finite PLL loop bandwidth because these de-

lays are modeled by the PLL transfer functions.

11. Direct measurement of phase jitter records over 1016 periods is impractical. It is expected that the jitter will be measured over a smaller, yet statistically

16

significant, sample size and the total jitter at 10 samples extrapolated from an estimate of the sigma of the random jitter components.

12. Measured with SSC enabled on reference clock generator.

13. As measured after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRXTotal - MIN parameters.

Rev. 1.3 December 2008

28 of 42

FBDIMM

DDR2 SDRAM

Table 13 : Differential Transmitter Output Specifications

Values

Parameter

Symbol

Units

Comments

MIN

MAX

Differential peak-to-peak output voltage for large

voltage swing

V

900

1,300

mV

dB

EQ1, Note1

EQ2, Note1

EQ2, Note1,2

1,3,4

TX-DIFFp-p_L

Differential peak-to -peak output voltage for requ-

lar voltage swing

V

800

520

TX-DIFFPp-p_R

Differential peak-to-peak output voltage for small

votage swing

V

TX-DIFFp-p_S

DC common code output voltage for large voltage

swing

V

375

280

-4.0

-7.0

90

TX-CM_L

DC common code output voltage for small volt-

age swing

V

135

-3.0

-5.0

TX-CM_S

De-emphasized differential output voltage ratio

for -3.5 dB de-emphasis

V

TX-DE-3.5-Ratio

TX-DE-6.0-Ratio

De-emphasized differential output voltage ratio

for -6.0 dB de-emphasis

dB

1,2,3

AC peak-to-peak common mode output voltage

for large swing

V

mV

EQ7, Note1,5

6

TX-CM-ACp-p-L

TX-CM-ACp-p-R

TX-CM-ACp-p-S

AC peak-to-peak common mode output voltage

for regular swing

V

80

AC peak-to-peak common mode output voltage

for small swing

70

Maximum single-ended voltage in EI condition

DC+AC

V

50

TX-IDLE-SE

Maximum single-ended voltage in EI condition

DC+AC

V

20

6

TX-IDLE-SE-DC

Maximum peak-to-peak differential voltage in EI

condition

V

40

TX-IDLE-DIFFp-p

Single-ended voltage (w.r.t. VSS) on D+/D-

Mimimum TX eye width, 3.2 and 4.0 Gb/s

Mimimum TX eye width 4.8 Gb/s

Maximum TX deterministic jitter, 3.2 and 4.8Gb/s

Maximum TX deterministic jitter, 4.8 Gb/s

Insantaneous pulse width

V

-75

750

mV

UI

1,7

TX-SE

T

1,8

TX-Eye-MIN

T

UI

1,8

TX-EYE-MIN4.8

T

02

UI

1,8,9

TX-DJ-DD

T

TBD

UI

1,8,9

10

TX-DJ-DD-4.8

T

0.85

30

UI

TX-PULSE

Differential TX output rise/fall time

Mismatch between rise and fall times

Differential return loss

T

90

20

ps

dB

20-80% voltage, Note1

TX-RISE TX-FALL

T

TX-RF-MISMATCH

RL

8

6

1 GHz-2.4 GHz, Note 11

12

TTX-DIFF

Common mode return loss

RL

TX-CM

Transmitter termination impender

R

41

55

4

TX

EQ 4, Boundaries are applied sepa-

rately to high and low output voltage

states

D+/D-TX Impedance difference

R

%

TX-MATCH-DC

Lane-to lane skew at TX

L

100+3UI

100=2UI

ps

13, 15

14, 15

TX-SKEW1

TX-SKEW2

Rev. 1.3 December 2008

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FBDIMM

DDR2 SDRAM

Table 14 : Differential Receiver Input Specifications

Values

Parameter

Symbol

Units

Comments

MIN

MAX

TBD

75

Differential peak-to-peak input voltage for large voltage swing

Maximum single-ended voltage in El condition

V

170

mV

EQ 5, Note1

RX-DIFFp-p

V

2,3

RX-IDLE-SE

Maximum single-ended voltage in Ei condition (DC only)

Maximum peak-to-peak differential voltage in El condition

V

50

2,3

RX-IDLE-SE-DC

V

65

3

RX-IDLE-DIFFp-p

Single-ended voltage (w.r.t. V ) on D+/D-

SS

V

-300

85

900

4

RX-SE

Single-pulse peak differential input voltage

Amplitude ratio between adjacent symbols

Maximum RX inherent timing error, 3.2 and 4.0 Gb/x

Maximum RX inherent deterministic timing eror, 3.2 and 4.8 Gb/s

Single-pulse width as zero-voltage crossing

Single-pulse width at minimum-level crossing

Differential RX input rise/fall time

V

4,5

RX-DIFF-PULSE

V

TBD

0.4

4,6

RX-DIFF-ADJ-RATIO

T

UI

ps

mV

%

4,7,8

RX-TJ-MAX

T

TBD

0.3

4,7,8

RX-TJ-MAX4.8

V

4,7,8,9

RX-DJ-DD

V

TBD

4,7,8,9

RX-DJ-DD-4.8

T

0.55

0.2

50

4,5

RX-PW-ZC

Common mode fo the input voltage

4.5

20~80% voltage

EQ 6, Note1, 10

EQ 7, Note 1

11

RX-PW-ML

Differential RX output rise/fall time

T

RX-RISE RX-FALL

Common mode of input voltage

V

120

400

270

45

RX-CM

RX-CM-ACp-p

V

RX-CM-EH-RATOP

AC peak-to-peak common mode of input voltage

V

Ratio of V

to minimum V

RX-CM-ACp-p

RX-DIFFp-p

Differential return loss

RL

9

6

dB

Ω

1GHz-2.4 GHz, Note 12

13

RX-DIFF

Common mode return loss

RX termination impedance

D+/D- RX Impedance difference

RL

RX-CM

R

41

55

4

RX

R

%

EQ 8

RX-MATCH-DC

Lane-to-lane skew at the receiver

that must be tolerated. Note 14

Lane-to lane PCB skew at RX

L

6

UI

RX-PCB-SKEW

Minimum RX drift tolerance

Minim data tracking 3dB bandwidth

Electrical idle entry detect time

Electrical idle exit detect time

Bit Error Ratio

T

400

0.2

ps

MHz

ns

15

16

17

RX-DRIFT

F

TRK

EI-ENTRY-DETECT

T

60

30

T

ns

EI-EXIT-DETECT

-12

BER

10

18

Notes :

1. Specified at the package pins into a timing and voltage compliant test setup. Note that signal levels at the pad will be lower than at the pin.

2. Single-ended voltages below that value that are simultaneously detected on D+ and D-are interpreted as the Electrical Idle condition. Worst-case mar-

gins are determined for the case with transmitter using small voltage swing.

3. Multiple lanes need to detect the El condition before the device can act upon the El detection.

4. Specified at the package pins into a timing and voltage compliance test setup.

5. The single-pulse mask provides suffcient symbol energy for reliable RX reception. Each symbol must comply with both the single-pulse mask and the

cumulative eyemask.

6. The relative amplitude ratio limit between adjacent symbols prevents excessive intersymbol interference in the RX. Each symbol must comply with the

peak amplitude ratio with regard to both the preceding and subsequent symbols.

7. This number does not include the effects of SSC or reference clock jitter.

8. This number includes setup and hold of the RX sampling flop.

9. Defined as the dual-dirac deterministic timing error.

10. Allows for 15 mV DC offset between transmit and receive devices.

Rev. 1.3 December 2008

30 of 42

FBDIMM

DDR2 SDRAM

11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peaktopeak common mode specification. For example,

if V p-p is 200 mV, the maximum AC peak-to peak common mode is the lesser of (200 mV*0.45=90 mV)and V

.

RX-CM-AC-p-p

RX-DIFF

12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs to be carefully designed.

13. The termination small signal resistance; tolerance across voltage from 100 mV to 400 mV shall not exceed +/-5 W with regard to the average of the

values measured at 100 mV and at 400 mV for that pin.

14. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter output skew from the component of the

end-to-end channel skew in the AMB specification.

15. Measured from the reference clock edge to the center of the input eye. This specification must be met across specified voltage and temperature ranges

for a single component. Drift rate of change is significantly below the tracking capability of the receiver.

16. This bandwidth number assume the specified minimum data transition density. Maximum jitter at 0.2 MHz is 0.05 UI,

17. The specified time includes the time required to forward the El entry condition.

18. BER per differential lane.

V

= 2x[V

+-V

] (EQ5)

RX-DIFFp-p

RX-D

RX-D-

(V

= DC(avg) of [V

+ V

] /2) (EQ 6)

RX-D-

RX-CM

RX-D+

V

=((Max[V

+ V

)/2)((Min [V

+ V

)/2) (EQ 7)

RX-D-

RX-CM-AC

RX-D+

RX-D

RX-D+

R

= 2x((R

-R

)/(R

+ R

) (EQ 8)

RX-D-

RX-MATCH-DC

RX-D+ RX-D-

RX-D+

Rev. 1.3 December 2008

31 of 42

FBDIMM

DDR2 SDRAM

7.0 CHANNEL INITIALIZATION

This chapter defines the process of initializing the FBD channel. The FBD initialzation process generally follows the top to bottom se-

quence of state transitions shown in the high level AMB Initialization Flow diagram in Figure The host must sequence the AMB devices

through the Disable, (back to Disable), Training, Testing, and Polling states in order to transition the AMBs into the active channel L0

state. The value in parenthesis in each state bubble indicates the condition/activity of the links during these states.

Figure15 : AMB Initialization Flow Diagram

Power-up

Disable

Calibrate

(EI)

(1’s)

Tranining

(TS0)

Testing

(TS1)

Polling

(TS2)

Config

(TS3)

L0

L0s

(EI)

Recalibrate

(NOP2)

The states in the AMB Initialization Flow diagram are :

Disable - The channel is inactive and the interface signals are in a low power Electrical Idle condition.

Training - The initial bit alignment and frame alignment training is done in this state.

Testing - Each bit lane is individually tested in this state.

Polling - The channel capabilities of the individual AMB devices are communicated in this state.

Config - The channel width configuration is communicated to the AMB devices in this state.

L0 - The channel is active and frames of information are flowing between the host and the AMB devices.

Recalibrate - The channel is momentarily idled to allow TX and Rx circuits to be recalibrated.

L0s - The channel is in a low-latency power saving condition. (Optional)

Each bit lane is initialized (mosly) independently to support fault tolerance. The transitions in the figure represent the transitions of the

AMB core logic state machine and are taken when the transition event is detected on the minimum required number of southound bit

lanes. The chain of FBD links connecting the host the AMBs must each be initialized to esabish the timing for broadcasting data frames

in the southbound direction and for merging data frame in the northbound direction. The AMBs on the channel are generally initialized

as a group but because each AMB is individually addressable many altemate may altemate initialization sequences may be employed.

Rev. 1.3 December 2008

32 of 42

FBDIMM

DDR2 SDRAM

Figure 16 : FBDIMM Physical Dimension -1 (For PCB) : 128Mbx8 based 128Mx72 Module (1Rank)

M395T2863QZ4

133.35

126.85

2x 3.25

2x 2.50 MIN

d

AMB

e

c

b

2x DIA. 2.0 +0.1/-0

a

67

51

5.175

123

R0.595

6.0

1.19

R0.75

5.0

2.50

0.8 +/- 0.05

2.50

1.19

120°

2.25

3.80

1.25

1.00

MAX 0.178

DETAIL b

R0.595

1.50

DETAIL a

DETAIL c

DETAIL d

DETAIL e

Rev. 1.3 December 2008

33 of 42

FBDIMM

DDR2 SDRAM

Figure 17 : FBDIMM Physical Dimension -2 (For Heat Spreader): 128Mbx8 based 128Mx72 Module (1Rank)

M395T2863QZ4

Units : Millimeters

8.2 max

133.35

67

51

1.27 ± 0.10

Back

3.0 max

123

Rev. 1.3 December 2008

34 of 42

FBDIMM

DDR2 SDRAM

Figure 18 : FBDIMM Physical Dimension -1 (For PCB) : 128Mbx8 based 256Mx72 Module (2Rank)

M395T5663QZ4

133.35

126.85

2x 3.25

2x 2.50 MIN

d

AMB

e

c

b

2x DIA. 2.0 +0.1/-0

a

67

51

5.175

123

R0.595

6.0

1.19

R0.75

5.0

2.50

0.8 +/- 0.05

2.50

1.19

120°

2.25

3.80

1.25

1.00

MAX 0.178

DETAIL b

R0.595

1.50

DETAIL a

DETAIL c

DETAIL d

DETAIL e

Rev. 1.3 December 2008

35 of 42

FBDIMM

DDR2 SDRAM

Figure 19 : FBDIMM Physical Dimension -2 (For Heat Spreader) : 128Mbx8 based 256Mx72 Module (2Rank)

M395T5663QZ4

Units : Millimeters

8.2 max

133.35

67

51

1.27 ± 0.10

Back

3.0 max

123

Rev. 1.3 December 2008

36 of 42

FBDIMM

DDR2 SDRAM

Figure 20 : FBDIMM Physical Dimension -1 (For PCB) : 256Mbx4 based 512Mx72 Module (2Rank)

M395T5160QZ4

133.35

126.85

2x 3.25

2x 2.50 MIN

d

AMB

e

c

b

2x DIA. 2.0 +0.1/-0

a

67

51

5.175

123

R0.595

6.0

1.19

R0.75

5.0

2.50

0.8 +/- 0.05

2.50

1.19

120°

2.25

3.80

1.25

1.00

MAX 0.178

DETAIL b

R0.595

1.50

DETAIL a

DETAIL c

DETAIL d

DETAIL e

Rev. 1.3 December 2008

37 of 42

FBDIMM

DDR2 SDRAM

Figure 21 : FBDIMM Physical Dimension -2 (For Heat Spreader): 256Mbx4 based 512Mx72 Module (2Rank)

M395T5160QZ4

Units : Millimeters

8.2 max

133.35

67

51

1.27 ± 0.10

Back

3.0 max

123

Rev. 1.3 December 2008

38 of 42

FBDIMM

DDR2 SDRAM

Figure 22 : FBDIMM Physical Dimension -1 (For PCB) : 128Mbx8 based 512Mx72 Module (4Rank)

M395T5163QZ4

133.35

126.85

2x 3.25

2x 2.50 MIN

d

AMB

e

c

b

2x DIA. 2.0 +0.1/-0

a

67

51

5.175

123

R0.595

6.0

1.19

R0.75

5.0

2.50

0.8 +/- 0.05

2.50

1.19

120°

2.25

3.80

1.25

1.00

MAX 0.178

DETAIL b

R0.595

1.50

DETAIL a

DETAIL c

DETAIL d

DETAIL e

Rev. 1.3 December 2008

39 of 42

FBDIMM

DDR2 SDRAM

Figure 23 : FBDIMM Physical Dimension -2 (For Heat Spreader): 128Mbx8 based 512Mx72 Module (4Rank)

M395T5163QZ4

Units : Millimeters

8.2 max

133.35

67

51

1.27 ± 0.10

Back

3.0 max

123

Rev. 1.3 December 2008

40 of 42

FBDIMM

DDR2 SDRAM

Figure 24 : FBDIMM Physical Dimension -1 (For PCB) : 256Mbx4 based 1Gx72 Module (4Rank)

M395T1G60QJ4

133.35

126.85

2x 3.25

2x 2.50 MIN

d

AMB

e

c

b

2x DIA. 2.0 +0.1/-0

a

67

51

5.175

123

R0.595

6.0

1.19

R0.75

5.0

2.50

0.8 +/- 0.05

2.50

1.19

120°

2.25

3.80

1.25

1.00

MAX 0.178

DETAIL b

R0.595

1.50

DETAIL a

DETAIL c

DETAIL d

DETAIL e

Rev. 1.3 December 2008

41 of 42

FBDIMM

DDR2 SDRAM

Figure 25 : FBDIMM Physical Dimension -2 (For Heat Spreader): 256Mbx4 based 1Gx72 Module (4Rank)

M395T1G60QJ4

Units : Millimeters

8.2 max

133.35

67

51

1.27 ± 0.10

Back

3.0 max

123

Rev. 1.3 December 2008

42 of 42


型号：	M395T5160QZ4-CE76
厂家：	SAMSUNG
描述：	DDR DRAM Module, 512MX72, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240 动态存储器双倍数据速率内存集成电路
文件：	总42页 (文件大小：915K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M395T5160QZ4-CE76 [SAMSUNG]

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