M464S3354BTS-L7A [SAMSUNG]
SDRAM Unbuffered SODIMM; 无缓冲SDRAM SODIMM
| 型号： | M464S3354BTS-L7A |
| 厂家： | 
SAMSUNG |
| 描述： | SDRAM Unbuffered SODIMM |
| 文件： | 总15页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256MB, 512MB Unbuffered SODIMM
SDRAM
SDRAM Unbuffered SODIMM
144pin Unbuffered SODIMM based on 512Mb B-die
64-bit Non ECC
Revision 1.2
March 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
Revision History
Revision 1.0 (January, 2004)
- First release
Revision 1.1 (February, 2004)
- Corrected typo.
Revision 1.2 (March. 2004)
- Corrected package dimension.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
144Pin Unbuffered SODIMM based on 512Mb B-die(x8, x16)
SDRAM
Ordering Information
Component
Package
Part Number
Density
Organization
Component Composition
Height
M464S3354BTS-C(L)7A
M464S6554BTS-C(L)7A
256MB
512MB
32M x 64
64M x 64
32Mx16(K4S511632B) * 4EA
32Mx16(K4S511632B) * 8EA
1,000mil
1,250mil
54-TSOP(II)
Operating Frequencies
7A
@CL3
133MHz(7.5ns)
3 - 3 - 3
@CL2
100MHz(10ns)
2 - 2 - 2
Maximum Clock Frequency
CL-tRCD-tRP(clock)
Feature
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address)
Burst length (1, 2, 4, 8)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VDD
A0
2
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
51
53
55
57
59
DQ14
DQ15
VSS
NC
52
54
56
58
60
DQ46
DQ47
VSS
NC
95
97
DQ21
DQ22
DQ23
VDD
A6
96
DQ53
DQ54
DQ55
VDD
A7
3
4
98
5
6
8
99
100
102
104
106
108
110
7
101
103
105
107
109
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
NC
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
A8
BA0
VSS
BA1
A11
Voltage Key
VSS
A9
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
**CLK0
VDD
RAS
WE
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
**CKE0 111 A10/AP 112
VDD
CAS
113
115
VDD
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
SDA
VDD
114
116 DQM6
118 DQM7
VDD
DQM4
DQM5
VDD
**CKE1 117
**CS0
**CS1
DU
A12
*A13
119
121
120
122
124
126
128
130
132
134
136
138
140
142
144
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
SCL
VDD
A3
**CLK1 123
A1
A4
VSS
VSS
NC
NC
125
127
129
131
133
135
137
139
141
143
A2
A5
NC
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
VSS
NC
DQ40
DQ41
DQ42
DQ43
VDD
VDD
DQ16
DQ17
DQ18
DQ19
VSS
VDD
DQ48
DQ49
DQ50
DQ51
VSS
DQ44
DQ45
DQ20
DQ52
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Pin Description
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CLK0 ~ CLK1
CKE0 ~ CKE1
CS0 ~ CS1
RAS
Function
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Pin Name
Function
WE
Write enable
DQM
DQM0 ~ 7
VDD
Power supply (3.3V)
Ground
VSS
SDA
SCL
DU
Serial data I/O
Serial clock
Don′t use
CAS
NC
No connection
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
CS
System clock
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
Column address : (x16 : CA0 ~ CA9)
A0 ~ A12
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data input/output mask
DQ0 ~ 63
VDD/VSS
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power supply/ground
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
256MB, 32Mx64 Module (M464S3354BTS) (Populated as 1 bank of x16 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
CS0
DQM0
DQM4
LDQM CS
DQ0
LDQM CS
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ1
DQ1
DQ2
DQ2
U0
U2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQM2
UDQM
DQM5
DQM6
UDQM
DQ8
DQ9
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM CS
LDQM CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
U1
U3
DQM3
DQM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
A0 ~ A12, BA0 & 1
Serial PD
SCL
RAS
CAS
WE
SDA
WP
SA0 SA1 SA2
47KΩ
CKE0
U0
U1
U2
10Ω
DQn
Every DQ pin of SDRAM
CLK0
VDD
U3
10Ω
Three 0.1uF X7R 0603Capacitors
per each SDRAM
To all SDRAMs
Vss
CLK1
10pF
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
512MB, 64Mx64 Module (M366S6554BTS) (Populated as 2 bank of x16 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
DQM0
DQM4
LDQM CS
LDQM CS
LDQM CS
LDQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ1
DQ1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
U4
U2
U6
DQM1
UDQM
UDQM
DQM5
UDQM
UDQM
DQ8
DQ8
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ8
DQ9
DQ9
DQ9
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM2
DQM6
LDQM CS
LDQM CS
LDQM CS
LDQM CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ0
DQ1
DQ1
DQ1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
U5
U3
U7
DQM3
UDQM
UDQM
DQM7
UDQM
UDQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ8
DQ8
DQ9
DQ9
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U3
SDRAM U4 ~ U7
A0 ~ A12, BA0 & 1
RAS
CAS
Serial PD
SCL
SDA
WP
SA0 SA1 SA2
47KΩ
WE
CKE0
CKE1
10Ω
DQn
Every DQ pin of SDRAM
U0/U4
U1/U5
U2/U6
U3/U7
VDD
CLK0/1
Three 0.1 uF X7R 0603 Capacitors
per each SDRAM
To all SDRAMs
Vss
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
Unit
V
-1.0 ~ 4.6
V
-55 ~ +150
1.0 * # of component
50
°C
W
Power dissipation
PD
Short circuit current
IOS
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input high voltage
Input low voltage
3.0
VDDQ+0.3
V
1
VIL
0
-
0.8
-
V
2
Output high voltage
Output low voltage
Input leakage current
VOH
VOL
ILI
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
M464S3354BTS
M464S6454BTS
Unit
Parameter
Symbol
Min
Max
Min
Max
Input capacitance (A0 ~ A12, BA0 ~ BA1)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0 ~ CKE1)
Input capacitance (CLK0 ~ CLK1)
Input capacitance (CS0 ~ CS1)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
15
15
15
15
15
10
10
25
25
25
21
25
12
12
25
25
15
15
15
10
10
45
45
25
21
25
12
12
pF
pF
pF
pF
pF
pF
pF
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
DC CHARACTERISTICS
M464S3354BTS (32M x 64, 256MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
400
mA
mA
1
ICC2P
CKE ≤ VIL(max), tCC = 10ns
8
8
Precharge standby current
in power-down mode
ICC2PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
80
40
Input signals are changed one time during 20ns
Precharge standby current
in non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC2NS
ICC3P
CKE ≤ VIL(max), tCC = 10ns
25
25
Active standby current in
power-down mode
ICC3PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC3N
120
100
mA
mA
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
520
mA
1
2
4Banks activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
800
12
6
mA
mA
mA
C
Self refresh current
CKE ≤ 0.2V
L
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
DC CHARACTERISTICS
M464S6554BTS (64M x 64, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
520
mA
mA
1
ICC2P
CKE ≤ VIL(max), tCC = 10ns
16
16
Precharge standby current
in power-down mode
ICC2PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC2N
160
80
Input signals are changed one time during 20ns
Precharge standby current
in non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC2NS
ICC3P
CKE ≤ VIL(max), tCC = 10ns
50
50
Active standby current in
power-down mode
ICC3PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
ICC3N
240
200
mA
mA
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
ICC4
640
mA
1
2
4Banks activated
tCCD = 2CLKs
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
920
24
mA
mA
mA
C
Self refresh current
CKE ≤ 0.2V
L
12
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
7A
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
15
ns
ns
1
1
1
1
20
Row precharge time
20
ns
tRAS(min)
tRAS(max)
tRC(min)
45
ns
Row active time
100
us
Row cycle time
65
ns
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + tRP
1
1
1
2
1
CLK
CLK
CLK
2
2
3
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
7A
Parameter
Symbol
Unit
ns
Note
1
Min
7.5
10
Max
CAS latency=3
CLK cycle
time
tCC
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5.4
6
CLK to valid
output delay
tSAC
ns
1,2
2
3
Output data
hold time
tOH
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
A0 ~ A9,
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
A11, A12
Register
Refresh
Mode register set
H
X
H
L
L
L
L
L
X
OP code
1,2
3
Auto refresh
H
L
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
Column
address
L
L
H
H
L
L
H
L
Write &
column address
Column
address
H
X
X
V
H
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
PACKAGE DIMENSIONS : 32Mx64 (M464S3354BTS)
Units : Inches (Millimeters)
2.66
(67.56)
2.50
(63.60)
2-R 0.078 Min
(2.00 Min)
0.16 ± 0.039
(4.00 ± 0.10)
1
59
61
143
0.13
(3.30)
0.91
(23.20)
1.29
(32.80)
2-φ 0.07
(1.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
Z
Y
0.15
(3.70)
2
60
62
144
0.150 Max
(3.80 Max)
0.024 ± 0.001
(0.600 ± 0.050)
0.16 ± 0.0039
(4.00 ± 0.10)
0.008 ±0.006
(0.200 ±0.150)
0.06 ± 0.0039
(1.50 ± 0.1)
0.03 TYP
0.04 ± 0.0039
(1.00 ± 0.10)
(0.80 TYP)
Detail Z
Detail Y
Tolerances : ± 0.006(.15) unless otherwise specified
The used device is 32Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S511632B
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SDRAM
PACKAGE DIMENSIONS : 64Mx64 (M464S6554BTS)
Units : Inches (Millimeters)
2.66
(67.56)
2.50
(63.60)
2-R 0.078 Min
(2.00 Min)
0.16 ± 0.039
(4.00 ± 0.10)
1
59
61
143
0.13
(3.30)
0.91
(23.20)
1.29
(32.80)
2-φ 0.07
(1.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
Z
Y
0.15
(3.70)
2
60
62
144
0.150 Max
(3.80 Max)
0.024 ± 0.001
(0.600 ± 0.050)
0.16 ± 0.0039
(4.00 ± 0.10)
0.008 ±0.006
(0.200 ±0.150)
0.06 ± 0.0039
(1.50 ± 0.1)
0.03 TYP
0.04 ± 0.0039
(1.00 ± 0.10)
(0.80 TYP)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 32Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S511632B
Rev. 1.2 March 2004
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