M466F0804DT1-L60 [SAMSUNG]
EDO DRAM Module, 8MX64, 60ns, CMOS, SODIMM-144;
| 型号： | M466F0804DT1-L60 |
| 厂家： | 
SAMSUNG |
| 描述： | EDO DRAM Module, 8MX64, 60ns, CMOS, SODIMM-144 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRAM MODULE
M466F0804DT1-L
M466F0804DT1-L EDO Mode
8M x 64 DRAM SODIMM Using 4Mx16, 4K Refresh 3.3V, Low power/Self-Refresh
GENERAL DESCRIPTION
FEATURES
The Samsung M466F0804DT1-L is a 8Mx64bits Dynamic
RAM high density memory module. The Samsung
M466F0804DT1-L consists of eight CMOS 4Mx16bits DRAMs
in TSOP 400mil packages and a 2K EEPROM in 8-pin
TSSOP package mounted on a 144-pin glass-epoxy sub-
strate. A 0.1uF decoupling capacitor is mounted on the
printed circuit board for each DRAM. The M466F0804DT1-L
is a Small Out-line Dual in-line Memory Module and is
intended for mounting into 144 pin edge connector sockets.
• Part Identification
- M466F0804DT1-L(4096 cycles/128ms, TSOP, L-ver)
• Extended Data Out Mode Operation
• New JEDEC standard proposal with EEPROM
• Serial Presense Detect with EEPROM
• CAS-before-RAS Refresh capability
• Self -refresh capability
• RAS-only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single +3.3V±0.3V power supply
PERFORMANCE RANGE
• PCB : Height(1000mil), double sided component
Speed
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
tHPC
20ns
25ns
-L50
84ns
104ns
-L60
PIN CONFIGURATIONS
PIN NAMES
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
Pin Name
Function
1
3
VSS
DQ0
DQ1
DQ2
2
4
6
8
VSS
49 DQ13 50 DQ45 97 DQ22 98 DQ54
A0 to
Address Inputs
Data In/Out
DQ32 51 DQ14 52 DQ46 99 DQ23 100 DQ55
DQ33 53 DQ15 54 DQ47 101 VCC 102 VCC
DQ34 55
DQ0 - DQ63
W
5
7
Read/Write Enable
Output Enable
VSS
56
VSS
103
A6
A8
104
A7
OE
9
DQ3 10 DQ35 57 RSVD 58 RSVD 105
12
106 A11
RAS0, RAS1
CAS0 - CAS7
VCC
Row Address Strobe
Column Address Strobe
Power(+3.3V)
11
VCC
VCC
59 RSVD 60 RSVD 107 VSS 108
RFU 62 RFU 109 A9 110
64 111 A10 112
RFU 66
68
69 RAS0 70
23 CAS0 24 CAS4 71 RAS1 72
VSS
NC
NC
13 DQ4 14 DQ36 61
15 DQ5 16 DQ37 63
17 DQ6 18 DQ38 65
19 DQ7 20 DQ39 67
VCC
VCC
RFU 113 VCC 114 VCC
RFU 115 CAS2 116 CAS6
RFU 117 CAS3 118 CAS7
RFU 119 VSS 120 Vss
RFU 121 DQ24 122 DQ56
VSS
Ground
W
NC
No Connection
Serial Address / Data I/O
Serial Clock
21
VSS
22
VSS
SDA
SCL
25 CAS1 26 CAS5 73
OE
VSS
74
76
27
29
31
33
35
VCC
A0
A1
28
30
32
34
36
VCC
A3
A4
75
VSS
123 DQ25 124 DQ57
RSVD
RFU
Reserved Use
77 RSVD 78 RSVD 125 DQ26 126 DQ58
79 RSVD 80 RSVD 127 DQ27 128 DQ59
Reserved for Future Use
A2
VSS
A5
VSS
81
VCC
82
VCC
129 VCC 130 VCC
83 DQ16 84 DQ48 131 DQ28 132 DQ60
37 DQ8 38 DQ40 85 DQ17 86 DQ49 133 DQ29 134 DQ61
39 DQ9 40 DQ41 87 DQ18 88 DQ50 135 DQ30 136 DQ62
41 DQ10 42 DQ42 89 DQ19 90 DQ51 137 DQ31 138 DQ63
43 DQ11 44 DQ43 91
45 46 93 DQ20 94 DQ52 141 SDA 142 SCL
47 DQ12 48 DQ44 95 DQ21 96 DQ53 143 VCC 144 VCC
VSS
92
VSS
139 VSS 140 Vss
VCC
VCC
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
FUNCTIONAL BLOCK DIAGRAM
RAS0
RAS1
W
OE
A0-A11
DQ0~15
DQ32~47
LCAS
CAS4
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LCAS
CAS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
U0
U4
U2
UCAS
DQ8
DQ9
UCAS
DQ8
DQ9
CAS5
CAS1
UCAS
UCAS
DQ8
DQ9
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16~31
DQ48~63
CAS2
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CAS6
LCAS
LCAS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
U1
U5
U3
UCAS
DQ8
DQ9
UCAS
DQ8
DQ9
CAS7
UCAS
CAS3
UCAS
DQ8
DQ9
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Serial PD
VCC
Vss
0.1uF Capacitor
for each DRAM
SCL
SDA
To all DRAMs
A0 A1 A2
Vss
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Symbol
VIN, VOUT
VCC
Rating
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
8
Unit
V
V
°C
W
Tstg
PD
Power Dissipation
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
3.0
0
Typ
Max
3.6
0
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
3.3
0
-
V
V
V
V
*1
2.0
VCC+0.3
0.8
*2
-
-0.3
*1 : VCC+1.3V at pulse width£15ns, which is measured at VCC.
*2 : -1.3V at pulse width£15ns, which is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
M466F0804DT1-L
Symbol
Speed
Unit
Min
Max
-50
-60
484
444
mA
mA
-
-
ICC1
ICC2
ICC3
Don¢t care
-
8
mA
-50
-60
-
-
484
444
mA
mA
-50
-60
-
-
364
324
mA
mA
ICC4
ICC5
ICC6
Don¢t care
-
1.6
mA
-50
-60
-
-
484
444
mA
mA
ICC7
ICCS
-
-
2.8
2.8
mA
mA
Don¢t care
Don¢t care
Don¢t care
II(L)
IO(L)
-10
-10
10
10
uA
uA
VOH
VOL
2.4
-
-
V
V
0.4
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min)
: Standby Current (RAS=CAS=W=VCC-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Battery back-up current. Average power supply, Battery back-up mode.
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS,LCAS=0.2V,
DQ=Don¢t care, tRC=31.25us, tRAS=tRASmin~300ns
ICCS
I(IL)
I(OL)
VOH
VOL
: Self Refresh Current, RAS=UCAS=LCAS=VIL, W=OE=A0~A11=VCC-0.2V or 0.2V, DQ~DQ63=VCC-0.2V or Open
: Input Leakage Current (Any input 0£VIN£Vcc+0.3V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V£VOUT£VCC)
: Output High Voltage Level (IOH = -2mA)
: Output Low Voltage Level (IOL = 2mA)
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
CAPACITANCE (TA = 25°C, VCC=3.3V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A11]
Input capacitance[W, OE]
CIN1
CIN2
CIN3
CIN4
CDQ
50
66
38
24
24
pF
pF
pF
pF
pF
-
-
-
-
-
Input capacitance[RAS0, RAS1]
Input capacitance[CAS0 - CAS7]
Input/Output capacitance[DQ0 - 63]
AC CHARACTERISTICS (0°C£TA£70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-50
-60
Parameter
Symbol
Unit
Note
Min
84
Max
Min
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
104
153
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
tRC
128
tRWC
tRAC
tCAC
tAA
50
13
25
60
15
30
3,4,9
3,4,5
3,9
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
tCLZ
tOLZ
tCEZ
tT
OE to output in Low-Z
3
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
3
13
50
3
13
50
3,11
2
1
1
30
50
8
40
60
10
40
10
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCS
tWCH
tWP
RAS hold time
CAS hold time
38
8
CAS pulse width
10K
37
10K
45
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
17
12
5
4
9
25
30
0
0
7
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command set-up time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
12
12
7
10
30
0
25
0
0
0
7
7
6
6
0
0
0
0
7
10
10
10
10
0
7
8
tRWL
tCWL
tDS
7
15
0
8,18
8,18
Data hold time
7
10
tDH
Refresh period
128
128
tREF
tCWD
tRWD
CAS to W dealy time
33
70
38
84
6,14
6
RAS to W dealy time
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
AC CHARACTERISTICS (0°C£TA£70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-50
-60
Parameter
Symbol
Unit
Note
Min
45
47
5
Max
Min
53
58
5
Max
Column address to W delay time
CAS precharge to W delay time
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
6
6
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
16
17
10
5
10
5
Access time from CAS precharge
Hyper page mode cycle time
28
35
3
20
67
7
25
73
10
60
35
10
10
10
10
13
tHPC
tHPRWC
tCP
Hyper page mode read-modify write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
OE access time
50
30
10
10
200K
200K
tRASP
tRHCP
tWRP
tWRH
tOEA
tOED
tOEZ
13
13
15
13
3
OE to data delay
10
3
13
3
Output buffer turn off delay time from OE
OE command hold time
5
5
tOEH
tDOH
tREZ
Output data hold time
5
5
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
13
13
3
15
15
11
3
3
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
15
5
15
5
OE to CAS hold time
CAS hold time to OE
5
5
OE precharge time
5
5
W pulse width(Hyper page cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)
5
5
100
90
-50
100
110
-50
19,20,21
19,20,21
19,20,21
tCHS
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
NOTES
10. tASC³ 6ns, Assume tT=2.0ns
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
11. If RAS goes high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes high before RAS high going , the open circuit condition
of the output is achieved by RAS going.
2.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
12.
13.
14.
15.
16.
tASC is referenced to the earlier CAS falling edge and tCAH is
referenced to the later CAS falling edge.
3.
4.
Measured with a load equivalent to 1 TTL loads and 100pF.
tCP is specified from the last CAS rising edge in the previous
cycle to the first CAS falling edge in the next cycle.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
tCWD is referenced to the later CAS falling edge at word read-
modify-write cycle.
tCWL is specified from W falling edge to the earlier CAS rising
edge.
5.
Assumes that tRCD³ tRCD(max).
6. tWCS, tRWD, tCWD, tAWD and tCPWD are non-restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If tWCS³ tWCS(min), the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If tRWD³ tRWD(min),
tCWD³ tCWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
tCSR is referenced to earlier CAS falling edge to the RAS fall-
ing edge.
17. tCHR is referenced to the later CAS rising from RAS falling
edge.
18.
19.
tDS, tDH is specified by the earlier CAS falling edge.
If tRASS³ 100us, then RAS precharge time must use tRPS
instead of tRP.
Either tRCH or tRRH must be satisfied for a read cycle.
7.
8.
20. For RAS-only refresh and burst CAS-before-RAS refresh
mode, 4096 cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh
specification.
These parameters are referenced to the CAS leading edge in
early write cycles.
9.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit access time
is controlled by tAA.
For distributed CAS-before-RAS with 15.6us interval CAS-
before-RAS should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specifi-
cation.
21.
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
COLUMN
ADDRESS
ROW
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tWEZ
tCEZ
tAA
tOEZ
VIH -
tOEA
tOLZ
OE
VIL -
tCAC
tCLZ
tREZ
DATA-OUT
tRAC
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCH
tWCS
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
DQ
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tASC
tRAL
tASR
tRAH
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
DQ
tOEH
tOED
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
VIL -
RAS
CAS
tCRP
tASR
tRCD
tRSH
VIH -
VIL -
tCAS
tCSH
tRAD
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tCWD
tRWL
tCWL
VIH -
VIL -
W
tWP
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tDS
tDH
tOEZ
tRAC
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
DQ
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ó
tCSH
tRCD
tRHCP
tCAS
tHPC
tHPC
tCAS
tHPC
tCRP
tASR
tCP
tCP
tCP
tCAS
tCAS
VIH -
VIL -
CAS
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
ROW
A
ADDR
tRRH
tRCS
tRCH
VIH -
VIL -
tCPA
tCAC
tAA
tCHO
tOEP
W
tCAC
tCAC
tAA
tCPA
tOCH
tOEA
tAA
tCPA
tAA
tCAC
VIH -
VIL -
tOEA
OE
DQ
tOEP
tOEZ
tOEA
tCAC
tDOH
tOEZ
tOEZ
tRAC
VOH -
VOL -
VALID
DATA-OUT
VALID
VALID
DATA-OUT
DATA-OUT
tOLZ
tCLZ
VALID
DATA-OUT
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
¡ó
VIH -
tRHCP
RAS
VIL -
tHPC
tHPC
tRSH
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
¡ó
CAS
tRAD
tRAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
COLUMN
tASC
tCAH
¡ó
¡ó
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWCH
tWP
tWCS
tWP
tWCH
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
W
tCWL
tCWL
tCWL
tRWL
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
tRSH
RAS
CAS
tHPRWC
tCAS
tCRP
tCRP
tRCD
VIH -
VIL -
tCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
COL.
ADDR
A
W
ADDR
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tDH
tAA
tAA
tOEZ
tOEZ
tDS
tDS
tRAC
VI/OH -
VI/OL -
DQ
tCLZ
tCLZ
VALID
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
VIH -
VIL -
READ(tCAC)
READ(tCPA)
WRITE
READ(tAA)
RAS
tHPC
tHPC
tHPC
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
tCAH
tCAS
tCAH
CAS
A
tRAD
tRAH
tASR
tASC tCAH
tASC
tASC
tCAH
tASC
VIH -
VIL -
COLUMN
COL.
ADDR
COL.
ADDR
ROW
ADDR
COLUMN
ADDRESS
ADDRESS
tRCS
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tDH
tDS
tOEA
tCAC
tAA
tRAC
tWEZ
tREZ
tAA
tWEZ
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
VALID
VALID
DATA-OUT
DQ
DATA-IN
DATA-OUT
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
tRAS
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
tCSR
VIH -
tCHR
CAS
VIL -
tWRP
tWRH
VIH -
W
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRAS
tRP
tRP
tRAS
VIH -
VIL -
RAS
CAS
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
tRAD
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tWRH
tWRP
tRRH
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
OE
tCEZ
tOLZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
tOEZ
DATA-OUT
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRP
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
W
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
DQ
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tRCH
tAA
tWRP
tWRH
tRCS
READ CYCLE
tCAC
VIH -
W
VIL -
VIH -
OE
VIL -
tWEZ
tCEZ
tREZ
tOEA
tOEZ
tCLZ
VOH -
DQ
DATA-OUT
VOL -
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
READ-MODIFY-WRITE
tAWD
tCWL
tRWL
tWRP
tWRH
tRCS
tCWD
VIH -
tWP
W
tCAC
tOEA
VIL -
tAA
VIH -
OE
tOED
tOEZ
VIL -
tDH
tCLZ
tDS
VI/OH -
DQ
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
tRPC
VIH -
RAS
VIL -
tRPC
tCP
tCHS
tCSR
VIH -
CAS
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
VIH -
W
VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tCEZ
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
REV. 0.1 Oct. 2000
DRAM MODULE
M466F0804DT1-L
PACKAGE DIMENSIONS
Units : Inches (millimeters)
2.66(67.60)
2.50(63.60)
2-R 0.078 Min
(2.00 Min)
0.16±0.039
(4.00±0.1)
0.13(3.30)
0.91(23.20)
1.29(32.80)
0.18
2-f 0.07
(1.80)
(4.60)
0.083
(2.10)
0.10
(2.50)
( Front view )
Z
Y
1.15
(3.70)
0.150Max
(3.81Max)
0.04±0.0039
(1.00±0.10)
0.162 Min
(4.11 Min)
( Back view )
0.06±0.0039
(1.50±0.1)
0.008±0.006
(0.200±0.150)
0.160±0.0039
(4.00±0.1)
0.024±0.001
(0.60±0.05)
0.03 TYP
(0.80 TYP)
Detail Z
Detail Y
Tolerances : ±.005(.13) unless otherwise specified
The used device is 4Mx16 DRAM with EDO mode, TSOP II
DRAM Part No. : K4E641612D-T
REV. 0.1 Oct. 2000
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