M471B2874DZ1-CF8 [SAMSUNG]
DDR DRAM Module, 128MX64, CMOS, ROHS COMPLIANT, SO-DIMM-204;
| 型号： | M471B2874DZ1-CF8 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 128MX64, CMOS, ROHS COMPLIANT, SO-DIMM-204 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总45页 (文件大小：805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Unbuffered SoDIMM
DDR3 SDRAM
DDR3 SDRAM Specification
204pin Unbuffered SODIMM based on 1Gb D-die
64-bit Non-ECC
82FBGA with Lead-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Table Contents
1.0 DDR3 Unbuffered SoDIMM Ordering Information ......................................................................................................4
2.0 Key Features .................................................................................................................................................................4
3.0 Address Configuration ................................................................................................................................................. 4
4.0 x64 DIMM Pin Configurations (Front side/Back side) ................................................................................................5
5.0 Pin Description ..............................................................................................................................................................6
6.0 Input/Output Functional Description ..........................................................................................................................7
7.0 Functional Block Diagram: ..........................................................................................................................................8
7.1 512MB, 64Mx64 Module(Populated as 1 rank of x16 DDR3 SDRAMs) ...............................................................8
7.2 1GB, 128Mx64 Module(Populated as 2 ranks of x16 DDR3 SDRAMs) ...............................................................9
7.3 2GB, 256Mx64 Module(Populated as 2 ranks of x8 DDR3 SDRAMs) ...............................................................10
8.0 Absolute Maximum Ratings .......................................................................................................................................11
8.1 Absolute Maximum DC Ratings ...........................................................................................................................11
8.2 DRAM Component Operating Temperature Range ............................................................................................11
9.0 AC & DC Operating Conditions .................................................................................................................................11
9.1 Recommended DC Operating Conditions (SSTL - 15) .......................................................................................11
10.0 AC & DC Input Measurement Levels .......................................................................................................................12
10.1 AC and DC Logic Input Levels for Single-ended Signals ................................................................................12
10.2 VREF Tolerances. ...............................................................................................................................................13
10.3 AC and DC Logic Input Levels for Differential Signals ...................................................................................14
10.3.1 Differential Signals Definition .................................................................................................................14
10.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ..................................14
10.3.3 Single-ended Requirements for Differential Signals ............................................................................15
10.3.4 Differential Input Cross Point Voltage ...................................................................................................16
10.4 Slew Rate Definition for Single Ended Input Signals ......................................................................................16
10.5 Slew rate definition for Differential Input Signals ............................................................................................16
11.0 AC and DC Output Measurement Levels ................................................................................................................17
11.1 Single Ended AC and DC Output Levels ..........................................................................................................17
11.2 Differential AC and DC Output Levels ..............................................................................................................17
11.3 Single Ended Output Slew Rate ........................................................................................................................17
11.4 Differential Output Slew Rate ............................................................................................................................18
12.0 IDD specification definition ......................................................................................................................................19
12.1 IDD SPEC Table ...................................................................................................................................................21
13.0 Input/Output Capacitance ........................................................................................................................................23
14.0 Electrical Characteristics and AC timing ................................................................................................................24
14.1 Refresh Parameters by Device Density .............................................................................................................24
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .........................................................24
14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ..........................................................25
14.3.1 Speed Bin Table Notes ............................................................................................................................26
15.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333 ............................................................................27
15.1 Jitter Notes ..........................................................................................................................................................30
15.2 Timing Parameter Notes .....................................................................................................................................31
15.3 Address / Command Setup, Hold and Derating: ..............................................................................................32
15.4 Data Setup, Hold and Slew Rate Derating: .......................................................................................................38
16.0 Physical Dimensions : .............................................................................................................................................43
16.1 64Mbx16 based 64Mx64 Module(1 Rank) .........................................................................................................43
16.2 64Mbx16 based 128Mx64 Module(2 Ranks) .....................................................................................................44
16.3 128Mbx8 based 256Mx64 Module(2 Ranks) .....................................................................................................45
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Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Revision History
Revision
1.0
Month
March
July
Year
2008
2008
History
- First release
- Typo corrected
1.1
- Change Current SPEC
- Correct Typo.
1.2
August
2008
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Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
1.0 DDR3 Unbuffered SoDIMM Ordering Information
Number of
Height
Part Number
Density
Organization
Component Composition
Rank
M471B6474DZ1-CF7/F8/H9
M471B2874DZ1-CF7/F8/H9
M471B5673DZ1-CF7/F8/H9
512MB
1GB
2GB
64Mx64
128Mx64
256Mx64
64Mx16(K4B1G1646D-HC##)*4
64Mx16(K4B1G1646D-HC##)*8
128Mx8(K4B1G0846D-HC##)*16
1
2
2
30mm
30mm
30mm
* ## : F7 / F8 / H9
** F7 : 800Mbps 6-6-6, F8 : 1066Mbps 7-7-7, H9 : 1333Mbps 9-9-9
2.0 Key Features
DDR3-800
6-6-6
2.5
DDR3-1066
DDR3-1333
9-9-9
1.5
Speed
Unit
7-7-7
1.875
7
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
ns
tCK
ns
6
9
15
13.125
13.125
37.5
13.5
13.5
36
15
ns
tRAS(min)
tRC(min)
37.5
52.5
ns
50.625
49.5
ns
•
•
•
JEDEC standard 1.5V ± 0.075V Power Supply
DDQ = 1.5V ± 0.075V
400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin
V
•
•
•
•
•
•
8 independent internal bank
Programmable CAS Latency: 6,7,8,9
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
•
•
•
•
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C
•
Asynchronous Reset
3.0 Address Configuration
Organization
Row Address
A0-A12
Column Address
A0-A9
Bank Address
BA0-BA2
Auto Precharge
A10/AP
64x16(1Gb) based Module
128x8(1Gb) based Module
A0-A13
A0-A9
BA0-BA2
A10/AP
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Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
4.0 x64 DIMM Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
139
141
143
145
147
149
Front
Pin
140
142
144
146
148
Back
DQ38
DQ39
V
V
V
V
V
1
2
71
72
REFDQ
SS
SS
SS
SS
V
3
4
DQ4
DQ5
KEY
DQ34
DQ35
SS
V
5
DQ0
DQ1
6
73
75
77
CKE0
74
76
78
CKE1
SS
V
V
V
V
7
8
DQ44
DQ45
SS
DD
DD
SS
3
V
9
10
DQS0
DQS0
NC
DQ40
DQ41
A15
SS
3
V
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
50
53
55
57
59
61
63
65
67
69
DM0
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
79
81
BA2
80
82
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
A14
SS
V
V
V
V
V
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DQS5
DQS5
SS
SS
DD
DD
SS
DQ2
DQ3
DQ6
DQ7
83
A12/BC
A9
84
A11
A7
DM5
V
V
85
86
SS
SS
V
V
V
V
87
88
DQ42
DQ43
DQ46
DQ47
SS
SS
DD
DD
DQ8
DQ9
DQ12
DQ13
89
A8
A5
90
A6
A4
V
V
91
92
SS
SS
V
V
V
V
93
94
DQ48
DQ49
DQ52
DQ53
SS
SS
DD
DD
DQS1
DQS1
DM1
95
A3
A1
96
A2
A0
V
V
RESET
97
98
SS
SS
V
V
V
V
DQS6
DQS6
DM6
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
SS
SS
DD
DD
V
DQ10
DQ11
DQ14
DQ15
101
103
105
107
109
111
113
115
117
119
CK0
CK0
CK1
CK1
SS
V
DQ54
DQ55
SS
V
V
V
V
DQ50
DQ51
SS
SS
DD
DD
V
DQ16
DQ17
DQ20
DQ21
A10/AP
BA0
BA1
RAS
SS
V
DQ60
DQ61
SS
V
V
V
V
DQ56
DQ57
SS
SS
DD
DD
V
DQS2
DQS2
DM2
WE
S0
SS
V
V
CAS
ODT0
DQS7
DQS7
SS
SS
V
V
V
DQ22
DQ23
DM7
SS
DD
DD
3
V
V
DQ18
DQ19
ODT1
NC
A13
SS
SS
V
121
123
125
127
129
131
133
135
137
S1
DQ58
DQ59
DQ62
DQ63
SS
V
V
V
DQ28
DQ29
SS
DD
DD
V
V
V
DQ24
DQ25
TEST
REFCA
SS
SS
V
V
V
SA0
NC
SDA
SCL
SS
SS
SS
V
V
DQS3
DQS3
DQ32
DQ33
DQ36
DQ37
SS
DDSPD
SA1
DM3
V
V
V
V
V
V
SS
SS
SS
SS
TT
TT
DQ26
DQ27
DQ30
DQ31
DQS4
DQS4
DM4
V
SS
Note :
1. NC = No Connect, NU = Not Useable, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
5 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
5.0 Pin Description
Pin Name
Description
Number Pin Name
Description
Number
CK0, CK1
Clock Inputs, positive line
2
DQ0-DQ63
Data Input/Output
64
Data Masks/ Data strobes,
Termination data strobes
CK0, CK1
Clock Inputs, negative line
2
DM0-DM7
8
CKE0, CKE1 Clock Enables
2
1
1
DQS0-DQS7 Data strobes
8
8
1
RAS
CAS
Row Address Strobe
DQS0-DQS7 Data strobes complement
Column Address Strobe
RESET
TEST
VDD
Reset Pin
Logic Analyzer specific test pin (No connect
on SODIMM)
WE
Write Enable
1
2
1
S0, S1
Chip Selects
Core and I/O Power
18
52
A0-A9, A11,
A13-A15
VSS
Address Inputs
14
Ground
VREFDQ
VREFCA
A10/AP
Address Input/Autoprecharge
1
1
Input/Output Reference
2
1
VDDSPD
VTT
A12/BC
Address Input/Burst chop
SDRAM Bank Addresses
SPD and Temp sensor Power
BA0-BA2
3
2
1
1
2
Termination Voltage
Reserved for future use
Total
2
3
ODT0, ODT1 On-die termination control
NC
SCL
SDA
Serial Presence Detect (SPD) Clock Input
204
SPD Data Input/Output
SPD Address
SA0-SA1
*The V and V
pins are tied common to a single power-plane on these desigus.
DDQ
DD
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Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
6.0 Input/Output Functional Description
Symbol
Type
Function
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera-
tions is synchronized to the input clock.
CK0-CK1
CK0-CK1
Input
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refresh mode.
CKE0-CKE1
S0-S1
Input
Input
Input
Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is
selected by S0; Rank 1 is selected by S1.
When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define
the operation to be executed by the SDRAM.
RAS, CAS, WE
BA0-BA2
Input
Input
Selects which DDR3 SDRAM internal bank of eight is activated.
ODT0-ODT1
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of
CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-
BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-
charge.A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-thefly) will be
performed (HIGH, no burst chop; LOW, burst chopped)
A0-A9,
A10/AP,
A11
A12/BC
A13-A15
Input
DQ0-DQ63
DM0-DM7
I/O
Data Input/Output pins.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input
data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.
Input
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3
SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS.
DQS0-DQS7
DQS0-DQS7
I/O
VDD,VDDSPD,
VSS
Supply
Supply
I/O
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs.
VREFDQ,
VREFCA
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be
connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SDA
SCL
SA0-SA1
TEST
Input
Input
I/O
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules
RESET In Active Low This signal resets the DDR3 SDRAM
RESET
Input
7 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
7.0 Functional Block Diagram:
7.1 512MB, 64Mx64 Module(Populated as 1 rank of x16 DDR3 SDRAMs)
SCL
SA0
SA1
SCL
A0
A1
A2
(SPD)
WP
SDA
240Ω
DQS0
DQS0
DM0
LDQS
LDQS
LDM
± 1%
ZQ
DQ[0:7]
DQS1
DQS1
DM1
DQ[0:7]
UDQS
UDQS
UDM
D0
DQ[8:15]
DQ[8:15]
V
V
tt
tt
V
SPD
DDSPD
V
V
D0 - D3
D0 - D3
D0 - D3
D0 - D3, SPD
D0 - D3
D0 - D3
REFCA
REFDQ
240Ω
DQS2
DQS2
LDQS
LDQS
LDM
± 1%
V
DD
ZQ
DM2
V
SS
DQ[16:23]
DQS3
DQ[0:7]
UDQS
UDQS
UDM
D1
CK0
CK0
DQS3
DM3
DQ[8:15]
DQ[24:31]
Terminated near
card edge
CK1
CK1
NC
ODT1
S1
NC
240Ω
DQS4
DQS4
LDQS
LDQS
LDM
D0 - D3
± 1%
RESET
ZQ
DM4
DQ[32:39]
DQS5
DQ[0:7]
UDQS
UDQS
UDM
D2
DQS5
DM5
DQ[8:15]
DQ[40:47]
D0
D1
D2
D3
240Ω
DQS6
DQS6
LDQS
LDQS
LDM
± 1%
ZQ
DM6
DQ[48:55]
DQS7
DQ[0:7]
UDQS
UDQS
UDM
D3
Address and Controllines
DQS7
DM7
DQ[8:15]
DQ[56:63]
Note :
1. DQ wiring may differ from that shown
however ,DQ, DM, DQS and DQS
relationships are maintained as shown
Vtt
Vtt
Rank0
V
DD
8 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
7.2 1GB, 128Mx64 Module(Populated as 2 ranks of x16 DDR3 SDRAMs)
SCL
SA0
SA1
SCL
A0
A1
A2
(SPD)
WP
SDA
240Ω
240Ω
DQS0
DQS0
DM0
LDQS
LDQS
LDM
LDQS
LDQS
LDM
± 1%
± 1%
ZQ
ZQ
DQ[0:7]
DQS1
DQS1
DM1
DQ[0:7]
UDQS
UDQS
UDM
DQ[0:7]
UDQS
UDQS
UDM
D0
D4
DQ[8:15]
DQ[8:15]
DQ[8:15]
V
V
tt
tt
V
SPD
DDSPD
V
V
D0 - D7
D0 - D7
D0 - D7
D0 - D7, SPD
D0 - D3
D4 - D7
D0 - D3
D4 - D7
D0 - D7
REFCA
240Ω
240Ω
DQS2
DQS2
LDQS
LDQS
LDM
LDQS
LDQS
LDM
REFDQ
± 1%
± 1%
ZQ
ZQ
DM2
V
DD
DQ[16:23]
DQS3
DQ[0:7]
DQ[0:7]
UDQS
UDQS
UDM
V
UDQS
UDQS
UDM
SS
D1
D5
DQS3
CK0
CK1
DM3
DQ[8:15]
DQ[8:15]
DQ[24:31]
CK0
CK1
RESET
240Ω
240Ω
DQS4
DQS4
LDQS
LDQS
LDM
LDQS
LDQS
LDM
± 1%
± 1%
ZQ
ZQ
DM4
DQ[32:39]
DQS5
DQ[0:7]
DQ[0:7]
UDQS
UDQS
UDM
UDQS
UDQS
UDM
D2
D6
DQS5
DM5
DQ[8:15]
DQ[8:15]
DQ[40:47]
240Ω
240Ω
DQS6
DQS6
LDQS
LDQS
LDM
LDQS
LDQS
LDM
D4
V1
D5
D6
D2
D7
D3
± 1%
± 1%
V2
V2
V3
V4
V4
ZQ
ZQ
DM6
DQ[48:55]
DQS7
DQ[0:7]
DQ[0:7]
UDQS
UDQS
UDM
UDQS
UDQS
UDM
D3
D7
DQS7
DM7
DQ[8:15]
DQ[8:15]
DQ[56:63]
V1
D0
V3
D1
Rank0
Rank1
Address and Controllines
Vtt
Note :
Vtt
Vtt
1. DQ wiring may differ from that shown
however ,DQ, DM, DQS and DQS
relationships are maintained as shown
V
V
DD
DD
9 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
7.3 2GB, 256Mx64 Module(Populated as 2 ranks of x8 DDR3 SDRAMs)
V
V
DD
DD
Vtt
Vtt
Vtt
240Ω
240Ω
240Ω
240Ω
DQS3
DQS3
DQS4
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
± 1%
± 1%
± 1%
± 1%
DQS4
ZQ
ZQ
ZQ
ZQ
DM3
DM4
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[24:31]
DQ[32:39]
D11
D3
D11
D3
240Ω
240Ω
240Ω
240Ω
DQS1
DQS1
DQS6
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
± 1%
± 1%
± 1%
± 1%
DQS6
ZQ
ZQ
ZQ
ZQ
DM1
DM6
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[8:15]
DQ[48:55]
D1
D9
D1
D9
240Ω
240Ω
240Ω
240Ω
DQS0
DQS0
DM0
DQS7
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
± 1%
± 1%
± 1%
± 1%
DQS7
ZQ
ZQ
Rank0
Rank1
ZQ
ZQ
DM7
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[56:63]
D0
D8
D0
D8
240Ω
240Ω
240Ω
240Ω
DQS2
DQS2
DQS5
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
DQS
DQS
DM
± 1%
± 1%
± 1%
± 1%
DQS5
ZQ
ZQ
ZQ
ZQ
D10
DM2
DM5
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[0:7]
DQ[16:23]
DQ[40:47]
D2
D10
D2
V2
V1
V1
V8
D9
V3
D3
D12
D5
D6
V7
V9
V5
V
V
tt
tt
V
SPD
D8
D10
D7
DDSPD
V4
V4
V6
V6
V
D0 - D15
D0 - D15
D0 - D15
REFCA
REFDQ
V
SCL
SA0
SA1
SCL
A0
(SPD)
WP
SDA
V
D0
D2
D13
D4
D15
DD
A1
V5
tt
V
D0 - D15, SPD
D0 - D7
SS
A2
V3
D1
V7
D14
V
V1
CK0
CK1
CK0
CK1
D11
V2
V9
V8
D8 - D15
D0 - D7
D8 - D15
D0 - D7
Address and Controllines
Note :
RESET
1. DQ wiring may differ from that shown
however ,DQ, DM, DQS and DQS
relationships are maintained as shown
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8.0 Absolute Maximum Ratings
8.1 Absolute Maximum DC Ratings
DDR3 SDRAM
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to VSS
-0.4 V ~ 1.975 V
V
1,3
VDDQ
VIN, VOUT
TSTG
Voltage on VDDQ pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-55 to +100
V
V
1,3
1
°C
1, 2
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than
500mV; VREF may be equal to or less than 300mV.
8.2 DRAM Component Operating Temperature Range
Symbol
Parameter
rating
Unit
Notes
TOPER
Operating Temperature Range
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the
JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case tem-
perature must be maintained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaran-
teed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component
with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with
Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7
= 0b)
9.0 AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions (SSTL - 15)
Rating
Typ.
1.5
Symbol
Parameter
Units
Notes
Min.
1.425
1.425
Max.
1.575
1.575
VDD
Supply Voltage
Supply Voltage for Output
V
V
1,2
1,2
VDDQ
1.5
Note :
1. Under all conditions VDDQ must be less than or equal to VDD
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
.
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10.0 AC & DC Input Measurement Levels
10.1 AC and DC Logic Input Levels for Single-ended Signals
Single Ended AC and DC input levels for Command and Address
DDR3-800/1066
DDR3-1333
Symbol
Parameter
Unit Notes
Max.
Min.
Max.
Min.
VIH.CA(DC)
VREF + 100
VDD
VREF + 100
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic lowM
mV
mV
mV
mV
mV
mV
1
V
IL.CA(DC)
IH.CA(AC)
IL.CA(AC)
IH.CA(AC150)
IL.CA(AC150)
VSS
VREF - 100
VSS
VREF - 100
1
V
VREF + 175
VREF + 175
-
-
1,2
1,2
1,2
1,2
V
VREF - 175
VREF - 175
-
-
-
-
V
VREF+150
-
-
-
V
VREF-150
-
Reference Voltage for ADD,
CMD inuts
V
REFCA(DC)
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
Note :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
Single Ended AC and DC input levels for DQ and DM
DDR3-800/1066
DDR3-1333
Symbol
Parameter
Unit Notes
Min.
Max.
Min.
Max.
VIH.DQ(DC)
VREF + 100
VDD
VREF + 100
VDD
DC input logic high
DC input logic low
mV
mV
mV
mV
V
1
V
IL.DQ(DC)
IH.DQ(AC)
IL.DQ(AC)
VREFDQ(DC)
Note :
VSS
VREF - 100
VSS
VREF - 100
1
V
VREF + 175
VREF + 150
AC input logic high
AC input logic low
-
-
1,2,5
1,2,5
3,4
V
VREF - 175
0.51*VDD
VREF - 150
0.51*VDD
-
-
0.49*VDD
0.49*VDD
I/O Reference Voltage(DQ)
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. Single ended swing requirement for DQS - DQS is 350mV (peak to peak). Differential swing for DQS - DQS is 700mV (peak to peak).
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10.2 V
Tolerances.
REF
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 2. It shows a valid reference voltage
V
REF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts of VREF. Fur-
thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD
.
voltage
VDD
VSS
time
Figure 2. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF
.
"VREF" shall be understood as VREF(DC), as defined in Figure 2.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
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10.3 AC and DC Logic Input Levels for Differential Signals
10.3.1 Differential Signals Definition
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 3 : Definition of differential ac-swing and "time above ac level" tDVAC
10.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
DDR3-800/1066/1333
Symbol
Parameter
unit
Note
min
+0.2
max
note 3
VIHdiff
VILdiff
differential input high
differential input low
V
V
V
V
1
1
2
2
note 3
-0.2
V
IHdiff(AC)
ILdiff(AC)
2 x (VIH(AC)-VREF
note 3
)
differential input high ac
differential input low ac
note 3
V
2 x (VREF - VIL(AC))
Notes:
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a
reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Reter to "overshoot and Undersheet
Specification"
Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS.
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
Slew Rate [V/ns]
min
75
57
50
38
34
29
22
13
0
max
min
175
170
167
163
162
161
159
155
150
150
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
0
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10.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle
preceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig-
nals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSEL max
VSEL
VSS or VSSQ
time
Figure 4 : Single-ended requirement for differential signals.
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode charateristics of these signals.
Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3-800/1066/1333
Symbol
Parameter
Unit
Notes
Min
Max
Note3
Note3
(VDD/2)+0.175
(VDD/2)+0.175
Note3
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
V
V
V
V
1, 2
1, 2
1, 2
1, 2
VSEH
(VDD/2)-0.175
(VDD/2)-0.175
VSEL
Note3
Notes:
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a
signal group, then the reduced level applies also here
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
Specification"
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10.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS
.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
Figure 5. VIX Definition
Cross point voltage for differential input signals (CK, DQS)
DDR3-800/1066/1333
Symbol
Parameter
Unit
Notes
Min
Max
150
175
150
-150
-175
-150
mV
mV
mV
VIX
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
1
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
Note :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing VSEL
VSEH of at least VDD/2 =/-250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.
/
10.4 Slew Rate Definition for Single Ended Input Signals
See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.tDH nominal slew rate for a falling signal is defined
as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF
10.5 Slew rate definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
Differential input slew rate definition
Measured
Description
Defined by
From
To
VIHdiffmin - VILdiffmax
Delta TRdiff
VIHdiffmin - VILdiffmax
VILdiffmax
VIHdiffmin
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
Differential input slew rate for falling edge (CK-CK and DQS-DQS)
VIHdiffmin
VILdiffmax
Delta TFdiff
Note : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds
V
IHdiffmin
0
V
ILdiffmax
delta TFdiff
delta TRdiff
Figure 6. Differential Input Slew Rate definition for DQS, DQS and CK, CK
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11.0 AC and DC Output Measurement Levels
11.1 Single Ended AC and DC Output Levels
Single Ended AC and DC output levels
Symbol Parameter
DDR3-800/1066/1333
Units
Notes
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
V
OM(DC) DC output mid measurement level (for IV curve linearity)
OL(DC) DC output low measurement level (for IV curve linearity)
OH(AC) AC output high measurement level (for output SR)
OL(AC) AC output low measurement level (for output SR)
0.5 x VDDQ
0.2 x VDDQ
V
V
V
V
V
V
VTT + 0.1 x VDDQ
VTT - 0.1 x VDDQ
1
1
V
Note : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2.
11.2 Differential AC and DC Output Levels
Differential AC and DC output levels
Symbol
Parameter
DDR3-800/1066/1333
Units
Notes
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
VOLdiff(DC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
Note : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static singel ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.
11.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
Single Ended Output slew rate definition
Measured
Description
Defined by
From
To
VOH(AC)-VOL(AC)
Delta TRse
VOL(AC)
VOH(AC)
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
VOH(AC)-VOL(AC)
Delta TFse
V
OH(AC)
VOL(AC)
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
Single Ended Output slew rate
DDR3-800
DDR3-1066
DDR3-1333
Parameter
Symbol
Units
Min
2.5
Max
Min
Max
Min
2.5
Max
Single ended output slew rate
Description : SR : Slew Rate
SRQse
5
2.5
5
5
V/ns
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
se : Singe-ended Signals
For Ron = RZQ/7 setting
V
OH(AC)
V
V
TT
OL(AC)
delta TFse
delta TRse
Figure 7. Single Ended Output Slew Rate definition
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11.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
VOHdiff(AC) for differential signals as shown in below.
Differential Output slew rate definition
Measured
Description
Defined by
From
To
VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
VOLdiff(AC)
VOHdiff(AC)
Differential output slew rate for rising edge
Differential output slew rate for falling edge
VOHdiff(AC)-VOLdiff(AC)
Delta TFdiff
VOHdiff(AC)
VOLdiff(AC)
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output slew rate
DDR3-800
DDR3-1066
DDR3-1333
Parameter
Symbol
Units
Min
Max
Min
Max
Min
Max
Differential output slew rate
Description : SR : Slew Rate
SRQse
5
10
5
10
5
10
V/ns
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
diff : Singe-ended Signals
V
(AC)
(AC)
OHdiff
V
V
TT
OLdiff
delta TFdiff
delta TRdiff
Figure 8. Differential Output Slew Rate definition
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12.0 IDD specification definition
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: AC Timing Table ; BL: 8a); AL: 0; CS: High between ACT and PRE; Command, Address, Bank
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
IDD0
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: AC Timing Table ; BL: 8a); AL: 0; CS: High between ACT, RD and PRE; Command, Address,
Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0;
IDD1
Precharge Standby Current
IDD2N
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling ;
Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Precharge Standby ODT Current
DD2NT
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling ;
Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling
DDQ2NT
(optional)
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pecharge
Power Down Mode: Slow Exitc)
IDD2P0
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data
IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pecharge
Power Down Mode: Fast Exitc)
IDD2P1
IDD2Q
IDD3N
IDD3P
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data
IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling
according to Table 34 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Sig-
nal: stable at 0
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially tog-
gling ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank Activity: all
banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 10); Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: stable at 0
IDD4R
IDDQ4R
(optional)
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially
toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank Activity: all banks open, WR
commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH
IDD4W
IDD5B
IDD6
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: AC Timing Table ; BL: 8a); AL: 0; CS: High between REF; Command, Address, Bank Address Inputs:
partially toggling according to Table 38 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK:
LOW; CL: AC Timing Table ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-Refresh oper-
ation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
19 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Symbol
Description
Self-Refresh Current: Extended Temperature Range (optional) )
f
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Extendede); CKE: Low; External clock: Off; CK and CK:
LOW; CL: AC Timing Table ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Extended Temper-
ature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
IDD6ET
f
Auto Self-Refresh Current (optional) )
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK:
LOW; CL: AC Timing Table ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0; Bank Activity: Auto
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
IDD6TC
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: AC Timing Table; BL: 8a); AL: CL-1; CS: High between ACT and RDA; Com-
mand, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0;
Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Reg-
istersb); ODT Signal: stable at 0
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
g) IDD current measure method and detail patterns are described on DDR3 component datasheet
20 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
12.1 IDD SPEC Table
M471B6474DZ1 : 512MB (64Mx64) Module
F7
F8
H9
Symbol
Unit
Notes
(DDR3-800@CL=6)
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
340
480
40
360
500
44
400
540
48
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
140
200
180
160
200
720
740
820
40
180
220
220
180
240
920
940
840
40
200
240
240
200
260
1160
1160
880
40
IDD4R
IDD4W
IDD5B
IDD6
IDD7
1120
1240
1480
M471B2874DZ1 : 1GB (128Mx64) Module
F7
F8
H9
Symbol
Unit
Notes
(DDR3-800@CL=6)
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
540
680
80
580
720
88
640
780
96
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
280
400
360
320
400
920
940
1020
80
360
440
440
360
460
1140
1160
1060
80
400
480
480
400
500
1400
1400
1120
80
IDD4R
IDD4W
IDD5B
IDD6
IDD7
1320
1460
1720
21 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
M471B5673DZ1 : 2GB (256Mx64) Module
F7
F8
H9
Symbol
Unit
Notes
(DDR3-800@CL=6)
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
1000
1160
160
560
800
720
640
800
1480
1560
2040
160
1120
1280
176
720
880
880
720
920
1800
1960
2120
160
1200
1360
192
800
960
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
960
800
1000
2120
2320
2240
160
IDD4R
IDD4W
IDD5B
IDD6
IDD7
2360
2640
3400
22 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
13.0 Input/Output Capacitance
M471B6474DZ1
DDR3-1066
DDR3-800
Min Max
DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Input/output capacitance
CIO
-
-
TBD
TBD
-
TBD
-
TBD
pF
pF
(DQ, DM, DQS, DQS, TDQS, TDQS)
Input capacitance
(CK and CK)
CCK
-
TBD
-
TBD
Input capacitance
CI
-
-
TBD
TBD
-
-
TBD
TBD
-
-
TBD
TBD
pF
pF
(All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M471B2874DZ1
DDR3-1066
DDR3-800
Min Max
DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
-
TBD
TBD
-
TBD
-
TBD
pF
pF
Input capacitance
(CK and CK)
CCK
-
TBD
-
TBD
Input capacitance
CI
-
-
TBD
TBD
-
-
TBD
TBD
-
-
TBD
TBD
pF
pF
(All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M471B5673DZ1
DDR3-1066
DDR3-800
Min Max
DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
-
TBD
TBD
-
TBD
-
TBD
pF
pF
Input capacitance
(CK and CK)
CCK
-
TBD
-
TBD
Input capacitance
CI
-
-
TBD
TBD
-
-
TBD
TBD
-
-
TBD
TBD
pF
pF
(All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
23 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
14.0 Electrical Characteristics and AC timing
(0 °C<TCASE ≤95 °C, VDDQ = 1.5V ± 0.075V; VDD = 1.5V ± 0.075V)
14.1 Refresh Parameters by Device Density
Parameter
All Bank Refresh to active/refresh cmd time
Symbol
tRFC
1Gb
110
7.8
2Gb
160
7.8
4Gb
300
7.8
8Gb
350
7.8
Units
ns
Note
0 °C ≤ TCASE ≤ 85°C
µs
Average periodic refresh interval
tREFI
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
3.9
µs
1
Note :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or
requirements referred to in this material.
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR3-800
6-6-6
min
6
DDR3-1066
7-7-7
min
DDR3-1333
9-9-9
min
9
Units
Note
Bin (CL - tRCD - tRP)
Parameter
CL
7
tCK
ns
ns
ns
ns
ns
ns
tRCD
tRP
15
13.13
13.13
37.5
13.5
13.5
36
15
tRAS
tRC
37.5
52.5
10
50.63
7.5
49.5
6.0
tRRD
tFAW
40
37.5
30
24 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
Speed
CL-nRCD-nRP
DDR3-800
6 - 6 - 6
Units
Note
Parameter
Symbol
tAA
min
15
max
20
Intermal read command to first data
ACT to internal read or write delay time
PRE command period
ns
ns
tRCD
tRP
15
-
15
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
CL = 6 / CWL = 5
tRC
52.5
37.5
2.5
ns
tRAS
9*tREFI
3.3
ns
8
tCK(AVG)
ns
1,2,3
Supported CL Settings
6
5
nCK
nCK
Supported CWL Settings
DDR3-1066 Speed Bins
Speed
DDR3-1066
7 - 7 - 7
CL-nRCD-nRP
Units
Note
Parameter
Symbol
tAA
min
13.125
13.125
13.125
50.625
37.5
max
20
Intermal read command to first data
ACT to internal read or write delay time
PRE command period
ns
ns
tRCD
-
tRP
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
ns
tRAS
9*tREFI
3.3
ns
8
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
ns
1,2,3,6
1,2,3,4
4
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
Reserved
Reserved
ns
ns
1.875
1.875
<2.5
<2.5
ns
1,2,3,4
4
Reserved
ns
ns
1,2,3
Supported CL Settings
Supported CWL Settings
6,7,8
5,6
nCK
nCK
25 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
DDR3-1333 Speed Bins
Speed
DDR3-1333
9 -9 - 9
CL-nRCD-nRP
Units
Note
Parameter
Symbol
tAA
min
13.5
13.5
13.5
49.5
36
max
20
Intermal read command to first data
ACT to internal read or write delay time
PRE command period
ns
ns
tRCD
-
tRP
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
ns
tRAS
9*tREFI
3.3
ns
8
1,2,3,7
1,2,3,4,7
4
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
ns
CL = 6
CL = 7
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5,6
CWL = 7
CWL = 5,6
Reserved
Reserved
Reserved
ns
ns
ns
4
1.875
1.875
<2.5
<2.5
ns
1,2,3,4,7
1,2,3,4,
4
Reserved
Reserved
ns
ns
CL = 8
CL = 9
CL = 10
ns
1,2,3,7
1,2,3,4,
4
Reserved
Reserved
ns
ns
1.5
1.5
<1.875
<1.875
ns
1,2,3,4
4
Reserved
ns
ns
1,2,3
5
CWL = 7
tCK(AVG)
(Optional)
6,7,8,9
5,6,7
ns
Supported CL Settings
Supported CWL Settings
nCK
nCK
14.3.1 Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Note :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be ful-
filled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequen-
cies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns
or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data sheet and/
or the DIMM SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
26 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
15.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333
Timing Parameters by Speed Bin
Speed
DDR3-800
DDR3-1066
DDR3-1333
Units
Note
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
Clock Timing
tCK(DLL_OF
F)
Minimum Clock Cycle Time (DLL off mode)
8
-
8
-
8
-
ns
6
Average Clock Period
Clock Period
tCK(avg)
tCK(abs)
See Speed Bins Table
ps
ps
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
tCK(avg)min +
tCK(avg)max +
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
tJIT(per)min
tJIT(per)max
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.47
-100
-90
0.53
0.53
100
90
0.47
0.53
0.47
0.47
-80
0.53
0.53
80
tCK(avg)
Average low pulse width
0.47
0.53
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
-90
90
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-80
80
-70
70
ps
200
180
180
160
160
140
ps
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
147
175
194
209
222
232
241
249
257
263
269
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
132
157
175
188
200
209
217
224
231
237
242
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
118
140
155
168
177
186
193
200
205
210
215
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
ps
24
Absolute clock HIGH pulse width
Absolute clock Low pulse width
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
25
26
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to
tDQSQ
tQH
-
200
-
-
150
-
-
125
-
ps
tCK(avg)
ps
13
0.38
-800
-
0.38
-600
-
0.38
-500
-
13, g
tLZ(DQ)
tHZ(DQ)
400
400
300
300
250
250
13,14, f
13,14, f
ps
tDS(base)
75
-
25
-
30
-
ps
d, 17
V
(AC)V (AC) levels
IL
IH
Data hold time to DQS, DQS referenced to
(AC)V (AC) levels
tDH(base)
tDIPW
150
600
100
490
65
-
ps
ps
d, 17
28
-
-
-
-
V
IH
IL
DQ and DM Input pulse width for each input
Data Strobe Timing
400
-
DQS, DQS READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS output high time
tRPRE
tRPST
tQSH
0.9
0.3
Note 19
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
tCK
tCK
13, 19, g
11, 13, b
13, g
Note 11
Note 11
Note 11
0.38
0.38
0.9
-
-
-
-
0.38
0.38
0.9
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK
DQS, DQS output low time
tQSL
13, g
DQS, DQS WRITE Preamble
DQS, DQS WRITE Postamble
tWPRE
tWPST
0.3
0.3
tCK
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
-400
-800
-
400
400
400
-300
-600
-
300
300
300
-255
-500
-
255
250
250
ps
ps
ps
13,f
DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS)
13,14,f
12,13,14
DQS, DQS high-impedance time (Referenced from
tHZ(DQS)
RL+BL/2)
DQS, DQS differential input low pulse width
tDQSL
tDQSH
tDQSS
tDSS
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
tCK
29, 31
30, 31
c
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS faling edge setup time to CK, CK rising edge
DQS,DQS faling edge hold time to CK, CK rising edge
tCK
tCK(avg)
tCK(avg)
tCK(avg)
c, 32
c, 32
tDSH
0.2
-
0.2
-
0.2
-
27 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
Units
Note
Parameter
Command and Address Timing
DLL locking time
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
tDLLK
tRTP
512
-
-
512
-
-
512
-
-
nCK
internal READ Command to PRECHARGE Command
delay
max
max
max
e
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
Delay from start of internal write transaction to internal
read command
max
max
max
tWTR
-
-
-
e,18
e
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
WRITE recovery time
tWR
15
4
-
-
15
4
-
-
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
nCK
max
max
max
Mode Register Set command update delay
tMOD
-
-
-
-
-
-
(12nCK,15ns)
(12nCK,15ns)
(12nCK,15ns)
CAS# to CAS# command delay
tCCD
tDAL(min)
tMPRR
tRAS
4
4
4
nCK
nCK
nCK
ns
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
WR + roundup (tRP / tCK(AVG))
1
-
1
-
1
-
22
e
See 13.3 " Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin" on page 37
max
max
max
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRD
-
-
-
-
-
-
e
e
(4nCK,10ns)
(4nCK,7.5ns)
(4nCK,6ns)
max
max
max
(4nCK,10ns)
(4nCK,10ns)
(4nCK,7.5ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK refer-
tFAW
tFAW
40
50
-
-
37.5
50
-
-
30
45
-
-
ns
ns
e
e
tIS(base)
tIH(base)
200
275
125
200
65
-
-
ps
ps
b,16
b,16
-
-
-
-
enced to V (AC) / V (AC) levels
IH
IL
Command and Address hold time from CK, CK refer-
enced to V (AC) / V (AC) levels
140
IH
IL
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
tIS(base)
AC150
200 + 150
900
125 + 150
780
65+125
620
-
-
ps
ps
b,16,27
28
-
-
-
-
IH
IL
Control & Address Input pulse width for each input
Calibration Timing
tIPW
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
Reset Timing
tZQinitI
tZQoper
tZQCS
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
nCK
nCK
nCK
23
max(5nCK, tRFC
+ 10ns)
max(5nCK, tRFC
+ 10ns)
max(5nCK, tRFC
+ 10ns)
Exit Reset from CKE HIGH to a valid command
tXPR
-
-
-
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL
max(5nCK,tRFC
+ 10ns)
max(5nCK,tRFC
+ 10ns)
max(5nCK,tRFC
+ 10ns)
tXS
-
-
-
-
-
-
-
-
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tCKESR
tDLLK(min)
tDLLK(min)
tDLLK(min)
nCK
Minimum CKE low width for Self refresh entry to exit
timing
tCKE(min) +
1tCK
tCKE(min) +
1tCK
tCKE(min) +
1tCK
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
tCKSRE
tCKSRX
-
-
-
-
-
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
max(5nCK,
10ns)
max(5nCK,
10ns)
max(5nCK,
10ns)
28 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
Units
Note
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Percharge Power Down with DLL
frozen to commands not requiring a locked DLL
max
max
max
tXP
tXPDLL
tCKE
(3nCK,
7.5ns)
-
-
-
(3nCK,
7.5ns)
-
-
-
-
-
-
(3nCK,6ns)
max
max
(10nCK,
24ns)
max
(10nCK,
24ns)
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
(10nCK,
24ns)
2
max
max
max
CKE minimum pulse width
(3nCK,
7.5ns)
(3nCK,
5.625ns)
(3nCK,
5.625ns)
Command pass disable delay
tCPDED
tPD
1
-
1
-
1
-
nCK
tCK
Power Down Entry to Exit Timing
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
15
20
20
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
tACTPDEN
tPRPDEN
tRDPDEN
1
1
-
-
-
1
1
-
-
-
1
1
-
-
-
nCK
nCK
RL + 4 +1
RL + 4 +1
RL + 4 +1
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
WL + 4 +(tWR/
tCK(avg))
WL + 4 +(tWR/
tCK(avg))
WL + 4 +(tWR/
tCK(avg))
tWRPDEN
-
-
-
-
-
-
-
-
-
-
-
-
nCK
nCK
nCK
nCK
9
10
9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
tWRAPDEN WL + 4 +WR +1
WL + 4 +WR +1
WL + 4 +WR +1
Timing of WR command to Power Down entry
(BL4MRS)
WL + 2 +(tWR/
tWRPDEN
WL + 2 +(tWR/
tCK(avg))
WL + 2 +(tWR/
tCK(avg))
tCK(avg))
Timing of WRA command to Power Down entry
(BL4MRS)
tWRAPDEN WL +2 +WR +1
WL +2 +WR +1
WL +2 +WR +1
10
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
tREFPDEN
tMRSPDEN
1
-
-
1
-
-
1
-
-
20,21
tMOD(min)
tMOD(min)
tMOD(min)
ODT high time without write command or with wirte
command and BC4
ODTH4
ODTH8
tAONPD
4
6
2
-
-
4
6
2
-
-
4
6
2
-
-
nCK
nCK
ns
ODT high time with Write command and BL8
Asynchronous RTT tum-on delay (Power-Down with
DLL frozen)
8.5
8.5
8.5
Asynchronous RTT tum-off delay (Power-Down with
DLL frozen)
tAOFPD
tAON
2
8.5
400
0.7
0.7
2
8.5
300
0.7
0.7
2
8.5
250
0.7
0.7
ns
ODT turn-on
-400
0.3
0.3
-300
0.3
0.3
-250
0.3
0.3
ps
7,f
8,f
f
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
tCK(avg)
tCK(avg)
RTT dynamic change skew
tADC
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed
tWLMRD
40
-
40
-
40
-
tCK
3
3
DQS/DQS delay after tDQS margining mode is pro-
grammed
tWLDQSEN
tWLS
25
-
-
-
25
-
-
-
25
-
-
-
tCK
ps
Setup time for tDQSS latch
325
325
245
245
195
195
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
tWLH
ps
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
0
0
9
2
0
0
9
2
ns
ns
tWLOE
29 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
15.1 Jitter Notes
Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input
clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another
Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge
to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per),
tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these param-
eters should be met whether clock jitter is present or not.
Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK)
crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe
signal (DQS(L/U), DQS(L/U)) crossing. Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] =
RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the
device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For
DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifi-
cations are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to
input clock jitter.
Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock,
where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps,
then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) =
tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) =
- 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (out-
put deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act =
2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x
tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x
tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!)
30 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
15.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation"
8. For definition of RTT turn-off time tAOF see "Device Operation".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. Device Operation.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is valid for RON34
14. Single ended signal parameter.
15. tREFI depends on T
OPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
V
(DC) = V DQ(DC). FOr input only pins except RESET, V (DC)=V CA(DC).
REF
REF
REF
REF
See "Address/ Command Setup, Hold and Derating"
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
V
(DC)= V
DQ(DC). For input only pins except RESET, V
(DC)=V
CA(DC).
REF
REF
REF
REF
See "Data Setup, Hold and Slew Rate Derating"
18. Start of internal write transaction is definited as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Altough CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
0.5
~
~
= 0.133
128ms
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
(DC) and the consecutive crossing of V
(DC)
REF
REF
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
31 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
15.3 Address / Command Setup, Hold and Derating:
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS
and ∆tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
REF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate
line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line any-
where between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value. If the
actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual sig-
nal from the dc level to VREF(DC) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in Table below, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
ADD/CMD Setup and Hold Base-Values for 1V/ns
[ps]
tIS(base)
DDR3-800
200
DDR3-1066
125
DDR3-1333
65
reference
VIH/L(AC)
VIH/L(DC)
VIH/L(AC)
tIH(base)
275
200
140
tIS(base)-AC150
200 + 150
125 + 150
65+125
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
Note : The tIS(base)-AC150 specifications are further adjusted to add an addi-tional 100ps of derating to accommodate for the lower alternate thresh-old
of 150mV and another 25ps to acccount for the earlier reference point [(175mv-150mV)/1 V/ns].
Derating values DDR3-800/1066 tIS/tIH-ac/dc based
∆tIS, ∆tIH Derating [ps] AC/DC based
AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV
CLK,CLK Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
∆tIS
1.0V/ns
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
58
42
8
∆tIS
∆tIH
66
50
16
12
6
∆tIS
∆tIH
74
58
24
20
14
8
∆tIH
84
68
34
30
24
18
8
∆tIS
∆tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
88
59
0
88
59
0
96
67
8
104
75
16
14
10
5
112
83
24
20
13
13
7
120
91
32
30
26
21
15
-2
128
99
40
38
34
29
23
5
34
34
34
0
0
0
50
CMD/
ADD
Slew
rate
-2
-4
-2
-4
-2
-4
6
4
46
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
2
-2
40
-11
-17
-35
-62
-11
-17
-35
-62
-11
-17
-35
-62
-3
-9
-27
-54
-8
0
34
V/ns
-18
-32
-52
-1
-10
-24
-44
-2
24
-19
-46
-11
-38
-16
-36
-6
10
-30
-26
-22
-10
32 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Derating values DDR3-1333/1600 tIS/tIH-ac/dc based - Alternate AC150 Threshold
∆tIS, ∆tIH Derating [ps] AC/DC based
Alternate AC150 Threshold -> VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV
CLK,CLK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
1.2V/ns
∆tIS
1.0V/ns
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
58
42
8
∆tIS
∆tIH
66
50
16
12
6
∆tIS
∆tIH
74
58
24
20
14
8
∆tIH
84
68
34
30
24
18
8
∆tIS
∆tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
75
50
0
75
50
0
75
50
0
83
58
8
91
66
16
16
16
16
15
6
99
74
24
24
24
24
23
14
-1
107
82
32
32
32
32
31
22
7
115
90
40
40
40
40
39
30
15
34
34
34
0
0
0
50
CMD/
ADD
Slew
rate
0
-4
0
-4
0
-4
8
4
46
0
-10
-16
-26
-40
-60
0
-10
-16
-26
-40
-60
0
-10
-16
-26
-40
-60
8
-2
40
0
0
0
8
-8
0
34
V/ns
-1
-10
-25
-1
-10
-25
-1
-10
-25
7
-18
-32
-52
-10
-24
-44
-2
24
-2
-17
-16
-36
-6
10
-9
-26
-10
Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition
tVAC @175mV [ps]
Slew Rate[V/ns]
tVAC @150mV [ps]
min
max
min
175
170
167
163
162
161
159
155
150
150
max
>2.0
2.0
75
57
50
38
34
29
22
13
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
1.0
0.9
0.8
0.7
0.6
0.5
< 0.5
0
33 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
VIH(AC) min
VREF to ac
region
V
IH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
VSS
tVAC
Delta TF
Delta TR
Setup Slew Rate VIH(AC)min - VREF(DC)
=
V
REF(DC) - VIL(AC)max
Setup Slew Rate
=
Rising Signal
Delta TR
Falling Signal
Delta TF
Figure 9 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
34 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
V
IH(DC) min
dc to VREF
region
nominal
slew rate
VREF(DC)
nominal
dc to VREF
region
dc to VREF
region
slew rate
VIL(DC) max
VIL(AC) max
VSS
Delta TF
Delta TR
Hold Slew Rate
Hold Slew Rate
Rising Signal
VREF(DC) - VIL(DC)max
Delta TR
V
IH(DC)min - VREF(DC)
Delta TF
=
=
Falling Signal
Figure 10 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
35 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
nominal
line
VIH(AC) min
V
REF to ac
region
V
IH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VIL(AC) max
VREF to ac
region
nominal
line
Delta TR
VSS
tangent line[VIH(AC)min - VREF(DC)]
Delta TR
Setup Slew Rate
=
Rising Signal
Delta TF
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]
=
Falling Signal
Delta TF
Figure 11. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
36 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
nominal
line
V
IH(DC) min
dc to VREF
region
tangent
line
VREF(DC)
tangent
line
dc to VREF
region
nominal
line
VIL(DC) max
VIL(AC) max
VSS
Delta TF
Delta TR
tangent line [ VREF(DC) - VIL(DC)max ]
Delta TR
Hold Slew Rate
=
Rising Signal
tangent line [ VIH(DC)min - VREF(DC) ]
Delta TF
Hold Slew Rate
=
Falling Signal
Figure 12 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
37 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
15.4 Data Setup, Hold and Slew Rate Derating:
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the ∆
tDS and ∆tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max.
If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value. If
the actual signal is later than the nominal slew rate line anywhere
between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(DC) region’, use nominal slew rate for derating value. If
the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual
signal from the dc level to VREF(DC) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization
Data Setup and Hold Base-Value
[ps]
tDS(base)
tDH(base)
DDR3-800
75
DDR3-1066
DDR3-1333
reference
VIH/L(AC)
VIH/L(DC)
25
30
65
150
100
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
Derating values DDR3-1066/1333 tIS/tIH-ac/dc based
∆tDS, ∆tDH Derating [ps] AC/DC baseda
DQS,DQS Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
-
50
34
0
-
88
59
0
-2
-
50
34
0
-4
-
88
59
0
50
34
0
-
67
8
6
2
-3
-
-
42
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
14
10
5
16
12
6
-
-
-
-
DDR3 DQ
-2
-6
-
-4
-10
-
4
22
18
13
7
20
14
8
-
-
-
-
-
-
-
Slew
-
-
-2
-8
-
26
21
15
-2
-30
-
24
18
8
800/ rate
1066 V/ns
-
-
-
-
0
29
23
6
34
24
10
-10
-
-
-
-
-
-
-
-1
-
-10
-
-2
-16
-
-
-
-
-
-
-
-
-
-11
-
-6
-26
-
-
-
-
-
-
-
-
-
-
-
-
-22
-
75
50
0
-
50
34
0
-
75
50
0
0
-
50
34
0
-4
-
75
50
0
50
34
0
-
-
-
-
-
58
8
8
8
8
-
42
8
-
-
-
-
-
-
-
-
16
16
16
16
15
-
16
12
6
-
-
-
-
-
-
-
DDR3 DQ
0
-4
-10
-
4
24
24
24
23
14
-
20
14
8
-2
-16
-
-
-
-
-
Slew
-
-
0
-2
-8
-
32
32
31
22
7
24
18
8
-6
-26
-
-
1333/ rate
1600 V/ns
-
-
-
-
-
0
40
39
30
15
34
24
10
-10
-
-
-
-
-
-
-10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note : a. Cell contents shaded in red are defined as ’not supported’.
Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition
tVAC[ps] DDR3-800/1066
min max
tVAC[ps] DDR3-1333
Slew Rate[V/ns]
min
max
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
75
57
50
38
34
29
22
13
0
-
-
-
-
-
-
-
-
-
-
175
170
167
163
162
161
159
155
155
150
-
-
-
-
-
-
-
-
-
-
0
38 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
VIH(AC) min
VREF to ac
region
V
IH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
VSS
tVAC
Delta TF
Delta TR
Setup Slew Rate
Rising Signal
V
IH(AC)min - VREF(DC)
V
REF(DC) - VIL(AC)max
Setup Slew Rate
=
=
Falling Signal
Delta TF
Delta TR
Figure 13 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
39 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
V
IH(DC) min
dc to VREF
region
nominal
slew rate
VREF(DC)
nominal
dc to VREF
region
dc to VREF
region
slew rate
VIL(DC) max
VIL(AC) max
VSS
Delta TF
Delta TR
V
REF(DC) - VIL(DC)max
VIH(DC)min - VREF(DC)
Delta TF
Hold Slew Rate
Rising Signal
Hold Slew Rate
Falling Signal
=
=
Delta TR
Figure 14 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
40 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
nominal
line
VIH(AC) min
V
REF to ac
region
V
IH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VIL(AC) max
VREF to ac
region
nominal
line
Delta TR
VSS
tangent line[VIH(AC)min - VREF(DC)]
Delta TR
Setup Slew Rate
=
Rising Signal
Delta TF
tangent line[VREF(DC) - VIL(AC)max]
Delta TF
Setup Slew Rate
=
Falling Signal
Figure 15 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
41 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
Note :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
nominal
line
V
IH(DC) min
dc to VREF
region
tangent
line
VREF(DC)
tangent
line
dc to VREF
region
nominal
line
VIL(DC) max
VIL(AC) max
VSS
Delta TF
Delta TR
tangent line [ VREF(DC) - VIL(DC)max ]
Delta TR
Hold Slew Rate
=
Rising Signal
tangent line [ VIH(DC)min - VREF(DC) ]
Delta TF
Hold Slew Rate
=
Falling Signal
Figure 16 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
42 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
16.0 Physical Dimensions :
16.1 64Mbx16 based 64Mx64 Module(1 Rank)
Units : Millimeters
67.60
Max 3.8
1.00 ± 0.10
3.00
2X 1.80
0.10 M C A B
(OPTIONAL HOLES)
2X 4.00 ± 0.10
0.10 M C A B
0.60
0.45 ± 0.03
4.00 ± 0.10
2.55
0.25 MAX
1.00 ± 0.10
Detail A
Detail B
The used device is 64M x16 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G1646D - HC**
43 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
16.2 64Mbx16 based 128Mx64 Module(2 Ranks)
Units : Millimeters
67.60
Max 3.8
1.00 ± 0.10
3.00
2X 1.80
0.10 M C A B
(OPTIONAL HOLES)
2X 4.00 ± 0.10
0.10 M C A B
0.60
0.45 ± 0.03
4.00 ± 0.10
2.55
0.25 MAX
1.00 ± 0.10
Detail A
Detail B
The used device is 64M x16 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G1646D - HC**
44 of 45
Rev. 1.2 August 2008
Unbuffered SoDIMM
DDR3 SDRAM
16.3 128Mbx8 based 256Mx64 Module(2 Ranks)
Units : Millimeters
67.60
Max 3.8
1.00 ± 0.10
3.00
2X 1.80
0.10 M C A B
(OPTIONAL HOLES)
2X 4.00 ± 0.10
0.10 M C A B
0.60
0.45 ± 0.03
4.00 ± 0.10
2.55
0.25 MAX
1.00 ± 0.10
Detail A
Detail B
The used device is 128M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G0846D - HC**
45 of 45
Rev. 1.2 August 2008
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