MD16R1624AF0-CN9_技术文档

Preliminary

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

32 Bit RIMM^®Module

Overview

Key Timing Parameters

®

T h e 3 2 b i t R I M M module is a general purpose high-perfor-

The following table lists the frequency and latency bins

a v a i l a b l e f o r 3 2 b i t R I M M m o d u l e s .

mance line of memory modules suitable for use in a broad

range of applications including computer memory, personal

computers, workstations, and other applications where high

bandwidth and low latency are required.

Table 1: 32 bit RIMM Module Frequency and Latency

T h e 3 2 b i t R I M M m o d u l e c o n s i s t s o f 2 5 6 M b / 2 8 8 M b

R D R A M devices. These are extremely high-speed CMOS

S p e e d

®

t

D R A M s o r g a n i z e d a s 1 6 M w o r d s b y 1 6 o r 1 8 b i t s . T h e u s e

o f R a m b u s S i g n a l i n g L e v e l ( R S L ) t e c h n o l o g y p e r m i t s t h e

use of conventional system and board design technologies.

R I M M 3 2 0 0 m o d u l e s s u p p o r t 8 0 0 M H z t r a n s f e r r a t e p e r p i n ,

resulting in total module bandwidth of 3200MB/s or

3 . 2 G B / s . R I M M 4 2 0 0 m o d u l e s s u p p o r t 1 0 6 6 M H z t r a n s f e r

rate per pin, resulting in total module bandwidth of

4 2 0 0 M B / s o r 4 . 2 G B / s .

RAC

O r g a n i -

( R o w

A c c e s s

T i m e )

n s

P a r t N u m b e r

I / O F r e q .

( M H z )

z a t i o n

32

35

32

35

32

35

M D 1 6 / 1 8 R 1 6 2 4 A F 0 - C N 9

M D 1 6 / 1 8 R 1 6 2 4 A F 0 - C M 9

M D 1 6 / 1 8 R 1 6 2 8 A F 0 - C N 9

M D 1 6 / 1 8 R 1 6 2 8 A F 0 - C M 9

M D 1 6 / 1 8 R 1 6 2 G A F 0 - C N 9

M D 1 6 / 1 8 R 1 6 2 G A F 0 - C M 9

3 2 M

x

1 0 6 6 M H z

3 2 / 3 6

T h e 3 2 b i t R I M M m o d u l e p r o v i d e s t w o i n d e p e n d e n t 1 6 o r 1 8

bit memory channels to facilitate compact system design.

The "Thru" Channel enters and exits the module to support a

connection to or from a controller, memory slot, or termina-

t i o n . T h e " T e r m " C h a n n e l i s t e r m i n a t e d o n t h e m o d u l e a n d

supports a connection from a controller or another memory

slot.

6 4 M

x

R I M M 4 2 0 0

3 2 / 3 6

1 2 8 M

3 2 / 3 6

x

3 2 M

x

M D 1 6 / 1 8 R 1 6 2 4 A F 0 - C M 8

M D 1 6 / 1 8 R 1 6 2 8 A F 0 - C M 8

M D 1 6 / 1 8 R 1 6 2 G A F 0 - C M 8

3 2 / 3 6

T h e R D R A M a r c h i t e c t u r e e n a b l e s t h e h i g h e s t s u s t a i n e d

bandwidth for multiple, simultaneous, randomly addressed

memory transactions. The separate control and data buses

w i t h i n d e p e n d e n t r o w a n d c o l u m n c o n t r o l y i e l d o v e r 9 5 %

bus efficiency. The RDRAM device multi-bank architecture

supports up to four simultaneous transactions per device.

6 4 M

x

R I M M 3 2 0 0

8 0 0 M H z

40

3 2 / 3 6

1 2 8 M

3 2 / 3 6

x

Features

¨

2 I n d e p e n d e n t R D R A M c h a n n e l s , 1 p a s s t h r o u g h a n d 1

t e r m i n a t e d o n 3 2 b i t R I M M m o d u l e

Form Factor

¨

H i g h s p e e d 8 0 0 a n d 1 0 6 6 M H z R D R A M d e v i c e s

2 3 2 e d g e c o n n e c t o r p a d s w i t h 1 m m p a d s p a c i n g

M o d u l e P C B s i z e : 1 3 3 . 3 5 m m x 3 4 . 9 3 m m x 1 . 2 7 m m

(5. 25” x 1. 375” x 0. 05” )

T h e 3 2 b i t R I M M m o d u l e s a r e o f f e r e d i n 2 3 2 - p a d 1 m m e d g e

c o n n e c t o r p a d p i t c h s u i t a b l e f o r 2 3 2 c o n t a c t R I M M c o n n e c -

t ors.

¨

Gold plated edge connector pad contacts

Serial Presence Detect (SPD) support

Operates from a 2. 5 volt supply (±5 % )

L o w p o w e r a n d p o w e r d o w n s e l f r e f r e s h m o d e s

S e p a r a t e R o w a n d C o l u m n b u s e s f o r h i g h e r e f f i c i e n c y

Figure 1 : 32 bit RIMM module with heat spreader

Page1

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

Table 2: Module Pad Numbers and Signal Names

Pin Pin Name

Pin Name

A 5 9

P i n N a m e

P i n

B 5 9

P i n N a m e

A 1

G n d

B 1

G n d

A 2

S C K _ T H R U _ L

G n d

B 2

C M D _ T H R U _ L

G n d

A 6 0

A 6 1

A 6 2

A 6 3

A 6 4

A 6 5

A 6 6

A 6 7

A 6 8

A 6 9

A 7 0

A 7 1

A 7 2

A 7 3

A 7 4

A 7 5

A 7 6

A 7 7

A 7 8

A 7 9

A 8 0

A 8 1

A 8 2

A 8 3

A 8 4

A 8 5

A 8 6

A 8 7

A 8 8

A 8 9

A 9 0

A 9 1

A 9 2

A 9 3

A 9 4

A 9 5

A 9 6

A 9 7

A 9 8

A 9 9

A 1 0 0

A 1 0 1

A 1 0 2

A 1 0 3

A 1 0 4

Vterm

B 6 0

B 6 1

B 6 2

B 6 3

B 6 4

B 6 5

B 6 6

B 6 7

B 6 8

B 6 9

B 7 0

B 7 1

B 7 2

B 7 3

B 7 4

B 7 5

B 7 6

B 7 7

B 7 8

B 7 9

B 8 0

B 8 1

B 8 2

B 8 3

B 8 4

B 8 5

B 8 6

B 8 7

B 8 8

B 8 9

B 9 0

B 9 1

B 9 2

B 9 3

B 9 4

B 9 5

B 9 6

B 9 7

B 9 8

B 9 9

B 1 0 0

B 1 0 1

B 1 0 2

B 1 0 3

B 1 0 4

Vterm

A 3

B 3

Vterm

A 4

D Q A 8 _ T H R U _ L

G n d

B 4

D Q A 7 _ T H R U _ L

G n d

A 5

B 5

D Q A 3 _ T H R U _ R

D Q A 4 _ T H R U _ R

A 6

D Q A 6 _ T H R U _ L

G n d

B 6

D Q A 5 _ T H R U _ L

G n d

A 7

B 7

D Q A 5 _ T H R U _ R

D Q A 6 _ T H R U _ R

A 8

D Q A 4 _ T H R U _ L

G n d

B 8

D Q A 3 _ T H R U _ L

G n d

A 9

B 9

D Q A 7 _ T H R U _ R

D Q A 8 _ T H R U _ R

G n d

A 1 0

A 1 1

A 1 2

A 1 3

A 1 4

A 1 5

A 1 6

A 1 7

A 1 8

A 1 9

A 2 0

A 2 1

A 2 2

A 2 3

A 2 4

A 2 5

A 2 6

A 2 7

A 2 8

A 2 9

A 3 0

A 3 1

A 3 2

A 3 3

A 3 4

A 3 5

A 3 6

A 3 7

A 3 8

A 3 9

A 4 0

A 4 1

A 4 2

A 4 3

A 4 4

A 4 5

A 4 6

D Q A 2 _ T H R U _ L

G n d

B 1 0

B 1 1

B 1 2

B 1 3

B 1 4

B 1 5

B 1 6

B 1 7

B 1 8

B 1 9

B 2 0

B 2 1

B 2 2

B 2 3

B 2 4

B 2 5

B 2 6

B 2 7

B 2 8

B 2 9

B 3 0

B 3 1

B 3 2

B 3 3

B 3 4

B 3 5

B 3 6

B 3 7

B 3 8

B 3 9

B 4 0

B 4 1

B 4 2

B 4 3

B 4 4

B 4 5

B 4 6

D Q A 1 _ T H R U _ L

G n d

V d d

D Q A 0 _ T H R U _ L

G n d

C T M N _ T H R U _ L

G n d

S C K _ T H R U _ R

C T M N _ T E R M _ L

G n d

C F M _ T H R U _ L

G n d

C T M _ T H R U _ L

G n d

C M D _ T H R U _ R

C T M _ T E R M _ L

G n d

C F M N _ T H R U _ L

G n d

R O W 2 _ T H R U _ L

G n d

V r e f

V c m o s

R O W 1 _ T H R U _ L

G n d

R O W 0 _ T H R U _ L

G n d

V d d

S V d d

S W P

C O L 4 _ T H R U _ L

G n d

C O L 3 _ T H R U _ L

G n d

V d d

S C L

S D A

C O L 2 _ T H R U _ L

G n d

C O L 1 _ T H R U _ L

G n d

V d d

S A 0

S A 1

C O L 0 _ T H R U _ L

G n d

D Q B 0 _ T H R U _ L

G n d

V d d

S A 2

S I N _ T E R M

G n d

D Q B 1 _ T H R U _ L

G n d

D Q B 2 _ T H R U _ L

G n d

D Q B 8 _ T E R M

G n d

D Q B 7 _ T E R M

G n d

D Q B 3 _ T H R U _ L

G n d

D Q B 4 _ T H R U _ L

G n d

D Q B 6 _ T E R M

G n d

D Q B 5 _ T E R M

G n d

D Q B 5 _ T H R U _ L

G n d

D Q B 6 _ T H R U _ L

G n d

D Q B 4 _ T E R M

G n d

D Q B 3 _ T E R M

G n d

D Q B 7 _ T H R U _ L

G n d

D Q B 8 _ T H R U _ L

G n d

D Q B 2 _ T E R M

G n d

D Q B 1 _ T E R M

G n d

S O U T _ T H R U

G n d

S I N _ T H R U

G n d

D Q B 0 _ T E R M

G n d

C O L 0 _ T E R M

G n d

D Q B 8 _ T H R U _ R

G n d

D Q B 7 _ T H R U _ R

G n d

C O L 1 _ T E R M

G n d

C O L 2 _ T E R M

G n d

D Q B 6 _ T H R U _ R

G n d

D Q B 5 _ T H R U _ R

G n d

C O L 3 _ T E R M

G n d

C O L 4 _ T E R M

G n d

D Q B 4 _ T H R U _ R

G n d

D Q B 3 _ T H R U _ R

G n d

R O W 0 _ T E R M

G n d

R O W 1 _ T E R M

G n d

D Q B 2 _ T H R U _ R

G n d

D Q B 1 _ T H R U _ R

G n d

R O W 2 _ T E R M

G n d

C F M N _ T E R M

G n d

D Q B 0 _ T H R U _ R

G n d

C O L 0 _ T H R U _ R

G n d

C T M _ T E R M _ R

G n d

C F M _ T E R M

G n d

C O L 1 _ T H R U _ R

C O L 2 _ T H R U _ R

Page2

Version 1.0 July 2002

Preliminary

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

32 Bit RIMM^®Module

Table 2: Module Pad Numbers and Signal Names (Continued)

A47

Pin Name

B47

Pin Name

Gnd

A105

A106

A107

A108

A109

A110

A111

A112

A113

A114

A115

A116

CTMN_TERM_R

Gnd

B105

B106

B107

B108

B109

B110

B111

B112

B113

B114

B115

B116

DQA0_TERM

Gnd

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

COL3_THRU_R

Gnd

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

COL4_THRU_R

Gnd

DQA1_TERM

Gnd

DQA2_TERM

Gnd

ROW0_THRU_R

Gnd

ROW1_THRU_R

Gnd

DQA3_TERM

Gnd

DQA4_TERM

Gnd

ROW2_THRU_R

Gnd

CFMN_THRU_R

Gnd

DQA5_TERM

Gnd

DQA6_TERM

Gnd

CTM_THRU_R

Gnd

CFM_THRU_R

Gnd

DQA7_TERM

Gnd

DQA8_TERM

Gnd

CTMN_THRU_R

Gnd

DQA0_THRU_R

Gnd

CMD_TERM

Gnd

SCK_TERM

Gnd

DQA1_THRU_R

DQA2_THRU_R

Table 3: Module Connector Pad Description

Signal

Module Connector Pads

A14

I/O

I

Type

RSL

Description

CFM_THRU_L

CFM_THRU_R

CFMN_THRU_L

CFMN_THRU_R

CMD_THRU_L

CMD_THRU_R

Clock From Master. Connects to left RDRAM device on "Thru"

Channel. Interface clock used for receiving RSL signals from the

controller. Positive polarity.

B54

A16

B52

B2

Clock From Master. Connects to right RDRAM device on "Thru"

Channel. Interface clock used for receiving RSL signals from the

controller. Positive polarity.

I

RSL

Clock From Master. Connects to left RDRAM device on "Thru"

Channel. Interface clock used for receiving RSL signals from the

controller. Negative polarity.

Clock From Master. Connects to right RDRAM device on "Thru"

Channel. Interface clock used for receiving RSL signals from the

controller. Negative polarity.

Serial Command Input used to read from and write to the control

V_CMOSregisters. Also used for power management. Connects to left

RDRAM device on "Thru" Channel.

A73

Serial Command Input used to read from and write to the control

V_CMOSregisters. Also used for power management. Connects to right

RDRAM device on "Thru" Channel.

COL4_THRU_L..C A20, B20, A22, B22, A24

OL0_THRU_L

"Thru" Channel Column bus. 5-bit bus containing control and

address information for column accesses. Connects to left RDRAM

device on "Thru" Channel.

RSL

COL4_THRU_R..C B48, A48, B46, A46, B44

OL0_THRU_R

"Thru" Channel Column bus. 5-bit bus containing control and

address information for column accesses. Connects to right

RDRAM device on "Thru" Channel.

CTM_THRU_L

B14

Clock To Master. Connects to left RDRAM device on "Thru"

Channel. Interface clock used for transmitting RSL signals to the

controller. Positive polarity.

Page 3

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

Table 3: Module Connector Pad Description (Continued)

Signal

M o d u l e C o n n e c t o r P a d s

I/O

T y p e

D e s c r i p t i o n

CTM_THRU_R

A54

B12

A56

Clock To Master. Connects to right RDRAM device on "Thru"

Channel. Interface clock used for transmitting RSL signals to the

controller. Positive polarity.

I

RSL

CTMN_THRU_L

CTMN_THRU_R

Clock To Master. Connects to left RDRAM device on "Thru"

Channel. Interface clock used for transmitting RSL signals to the

controller. Negative polarity.

I

RSL

Clock To Master. Connects to right RDRAM device on "Thru"

Channel. Interface clock used for transmitting RSL signals to the

controller. Negative polarity.

DQA8_THRU_L..

DQA0_THRU_L

A4, B4, A6, B6, A8, B8,

A10, B10, A12

"Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or

write data between the controller and RDRAM devices on “Thru”

Channel. Connects to left RDRAM device on "Thru" Channel.

DQA8_THRU_L is non-functional on modules with x16 RDRAM

devices.

I/O

RSL

DQA8_THRU_R..

DQA0_THRU_R

B67, A67, B65, A65, B63,

A63, B58, A58, B56

"Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or

write data between the controller and RDRAM devices on “Thru”

Channel. Connects to right RDRAM device on "Thru" Channel.

DQA8_THRU_R is non-functional on modules with x16 RDRAM

devices.

DQB8_THRU_L..

DQB0_THRU_L

B32, A32, B30, A30, B28,

A28, B26, A26, B24

"Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or

write data between the controller and RDRAM devices on “Thru”

Channel. Connects to left RDRAM device on "Thru" Channel.

DQB8_THRU_L is non-functional on modules with x16 RDRAM

devices.

DQB8_THRU_R..

DQB0_THRU_R

A36, B36, A38, B38, A40,

B40, A42, B42, A44

"Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or

w r i t e d a t a b e t w e e n t h e c o n t r o l l e r a n d R D R A M d e v i c e s o n “ T h r u ”

C h a n n e l . C o n n e c t s t o r i g h t R D R A M d e v i c e o n " T h r u " C h a n n e l .

D Q B 8 _ T H R U _ R i s n o n - f u n c t i o n a l o n m o d u l e s w i t h x 1 6 R D R A M

devices.

R O W 2 _ T H R U _ L . .

R O W 0 _ T H R U _ L

B 1 6 , A 1 8 , B 1 8

A 5 2 , B 5 0 , A 5 0

Row bus. 3-bit bus containing control and address information for

row accesses. C o n n e c t s t o l e f t R D R A M d e v i c e o n " T h r u " C h a n n e l .

I

R S L

R O W 2 _ T H R U _ R . .

R O W 0 _ T H R U _ R

Row bus. 3-bit bus containing control and address information for

row accesses. C o n n e c t s t o r i g h t R D R A M d e v i c e o n " T h r u " C h a n -

nel.

S C K _ T H R U _ L

S C K _ T H R U _ R

S I N _ T H R U

A 2

Serial Clock input. Clock source used to read from and write to

I

V _{C M O S}" T h r u " C h a n n e l R D R A M c o n t r o l r e g i s t e r s . Connects to left

R D R A M d e v i c e o n " T h r u " C h a n n e l .

A 7 1

B 3 4

Serial Clock input. Clock source used to read from and write to

V _{C M O S}" T h r u " C h a n n e l R D R A M c o n t r o l r e g i s t e r s . Connects to right

R D R A M d e v i c e o n " T h r u " C h a n n e l .

"Thru" Channel Serial I/O for reading from and writing to the con-

V _{C M O S}trol registers. Attaches to SIO0 of right RDRAM device on "Thru"

C h a n n e l .

I/O

Page4

Version 1.0 July 2002

Preliminary

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

32 Bit RIMM^®Module

Table 3: Module Connector Pad Description (Continued)

Signal

Module Connector Pads

I/O

Type

Description

S O U T _ T H R U

A 3 4

"Thru" Channel Serial I/O for reading from and writing to the con-

I/O

V _{C M O S}trol registers. Attaches to SIO1 of left RDRAM device on "Thru"

C h a n n e l .

C F M _ T E R M

C F M N _ T E R M

C M D _ T E R M

B 1 0 3

C l o c k f r o m m a s t e r . C o n n e c t s t o r i g h t R D R A M d e v i c e o n " T e r m "

I

R S L

Channel. Interface clock used for receiving RSL signals from the

controller. Positive polarity.

B 1 0 1

C l o c k f r o m m a s t e r . C o n n e c t s t o r i g h t R D R A M d e v i c e o n " T e r m "

Channel. Interface clock used for receiving RSL signals from the

controller. Negative polarity.

I

A 1 1 5

Serial Command Input used to read from and write to the control

I

V _{C M O S}registers. Also used for power management. Connects to right

RDRAM device on "Term" Channel.

COL4_TERM..

COL0_TERM

B97, A97, B95, A95, B93

"Term" Channel Column bus. 5-bit bus containing control and

address information for column accesses. Connects to right

RDRAM device on "Term" Channel.

I

RSL

CTM_TERM_L

CTM_TERM_R

CTMN_TERM_L

CTMN_TERM_R

B73

Clock To Master. Connects to left RDRAM device on "Term"

Channel. Interface clock used for transmitting RSL signals to the

controller. Positive polarity.

A103

B71

Clock To Master. Connects to right RDRAM device on "Term"

Channel. Interface clock used for transmitting RSL signals to the

controller. Positive polarity.

Clock To Master. Connects to left RDRAM device on "Term"

Channel. Interface clock used for transmitting RSL signals to the

controller. Negative polarity.

A105

Clock To Master. Connects to right RDRAM device on "Term"

Channel. Interface clock used for transmitting RSL signals to the

controller. Negative polarity.

DQA8_TERM..

DQA0_TERM

B113, A113, B111, A111,

B109, A109, B107, A107,

B105

"Term" Channel Data bus A. A 9-bit bus carrying a byte of read or

write data between the controller and RDRAM devices on “Term”

Channel. Connects to right RDRAM device on "Term" Channel.

DQA8_TERM is non-functional on modules with x16 RDRAM

devices.

I/O

RSL

DQB8_TERM..

DQB0_TERM

A85, B85, A87, B87, A89,

B89, A91, B91, A93

"Term" Channel Data bus B. A 9-bit bus carrying a byte of read or

write data between the controller and RDRAM devices on “Term”

Channel. Connects to right RDRAM device on "Term" Channel.

DQB8_TERM is non-functional on modules with x16 RDRAM

devices.

RSL

ROW2_TERM..

ROW0_TERM

A101, B99, A99

B115

"Term" Channel Row bus. 3-bit bus containing control and address

information for row accesses. Connects to right RDRAM device on

"Term" Channel.

I

SCK_TERM

Serial Clock input. Clock source used to read from and write to

V_CMOS"Term" Channel RDRAM control registers. Connects to right

RDRAM device on "Term" Channel.

Page 5

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

Table 3: Module Connector Pad Description (Continued)

Signal

SIN_TERM

Module Connector Pads

I/O

Type

Description

B83

"Term" Channel Serial I/O for reading from and writing to the con-

I/O V_CMOStrol registers. Attaches to SIO0 of left RDRAM device on "Term"

Channel.

V_TERM

Gnd

A60, B60, A61, B61

"Term" Channel Termination voltage.

A1, A3, A5, A7, A9, A11,

A13, A15, A17, A19, A21,

A23, A25, A27, A29, A31,

A33, A35, A37, A39, A41,

A43, A45, A47, A49, A51,

A53, A55, A57, A59, A62,

A64, A66, A68, A70, A72,

A74, A84, A86, A88, A90,

A92, A94, A96, A98, A100,

A102, A104, A106, A108,

A110, A112, A114, A116,

B1, B3, B5, B7, B9, B11,

B13, B15, B17, B19, B21,

B23, B25, B27, B29, B31,

B33, B35, B37, B39, B41,

B43, B45, B47, B49, B51,

B53, B55, B57, B59, B62,

B64, B66, B68, B70, B72,

B74, B84, B86, B88, B90,

B92, B94, B96, B98, B100,

B102, B104, B106, B108,

B110, B112, B114, B116

Ground reference for RDRAM core and interface.

SA0

A81

B81

A83

A79

B79

A77

Serial Presence Detect Address 0.

Serial Presence Detect Address 1.

Serial Presence Detect Address 2.

Serial Presence Detect Clock.

I

SV_DD

SA1

SA2

I

SCL

SDA

SV_DD

I

Serial Presence Detect Data (Open Collector I/O).

I/O

SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1 and

SA2.

SWP

B77

B75

Serial Presence Detect Write Protect (active high). When low, the

SPD can be written as well as read.

I

SV_DD

V_CMOS

Vdd

CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.

Supply voltage for the RDRAM core and interface logic.

A69, B69, A76, B76, A78,

B78, A80, B80, A82, B82

Vref

A75

Logic threshold reference voltage for both "Thru" Channel and

"Term" Channel RSL signals.

Page6

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

Vdd

2 per

RDRAM device

0.22mF

Gnd

V_REF

S I O 0

Left RDRAM Device of "Thru" Channel

S I O 1

S C K

C M D

V ref

1 per

2 RDRAM devices

P l u s o n e

(256/288Mb)

N e a r C o n n e c t o r

0.22mF

Gnd

.

V_CMOS

SIO0

SIO1

SCK

CMD

Vref

1 per

2 RDRAM devices

0.22mF

Right RDRAM Device of "Thru" Channel

(256/288Mb)

Gnd

SV_DD

0.22mF

Gnd

V_term

1 per

2 termination

resistors

Gnd

SIO 0

SIO 1

S C K

C M D

V ref

Left RDRAM Device of "Term" Channel

(256/288Mb)

Module

Capacity

N

.

512/576MB 16

256/288MB

128/144MB

8

4

SIO0

SIO1

SCK

CMD

Vref

Right RDRAM Device of "Term" Channel

(256/288Mb)

SV_DD

Vcc

SCL

SWP

SDA

SCL

WP

SDA

A0 A1 A2

SA0

SA1

SA2

U0

Serial Presence Detect

Figure 1: 32 bit RIMM Module Functional Diagram

Page7

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

Absolute Maximum Ratings

Table 4 : Absolute Maximum Ratings

Symbol

V_I,ABS

Parameter

Min

Max

Unit

Voltage applied to any RSL or CMOS signal pad with respect to Gnd

Voltage on VDD with respect to Gnd

Storage temperature

- 0.3

- 0.5

- 50

-

V_DD+ 0.3

V_DD+ 1.0

100

V

V_DD,ABS

T_STORE

T_PLATE

V

°C

Plate temperature

92

DC Recommended Electrical Conditions

Table 5 : DC Recommended Electrical Conditions

Symbol

V_DD

Parameter and Conditions

Min

Max

Unit

Supply voltage ^a

2.50 - 0.13

2.50 + 0.13

V

V_CMOS

CMOS I/O power supply at pad for 2.5V controllers:

CMOS I/O power supply at pad for 1.8V controllers:

VDD

1.8 - 0.1

VDD

1.8 + 0.2

V

V_REF

Reference voltage^a

1.4 - 0.2

1.4 + 0.2

3.6

V

SVdd

Serial Presence Detector- positive power supply

Termination Voltage

2.2

1.8 - 0.09

-

V_TERM

1.8 + 0.09

0.46

V_TERMV_REFNominal RSL signal half swing

a. see Direct RDRAM datasheet for more details

32 bit RIMM Module Capacity and Number of RDRAM device

Table 6: 32 bit RIMM Module Capacity and Number of RDRAM device

512/576MB

16

256/288MB

8

128/144MB

4

Unit

Number of 256/288Mb RDRAM Devices

pcs

channel 1

channel 2

8

4

2

Page8

Version 1.0 July 2002

Preliminary

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

32 Bit RIMM^®Module

32 bit RIMM Module Current Profile

Table 7 : 32bit RIMM Module Current Profile

5 1 2 / 5 7 6 M B

M a x

2 5 6 / 2 8 8 M B

M a x

1 2 8 / 1 4 4 M B

M a x

T o t a l 3 2 b i t R I M M M o d u l e C a p a c i t y

3 2 b i t R I M M m o d u l e p o w e r c o n d i t i o n s

I _{D D}

U n i t

a

R I M M 4 2 0 0

R I M M 3 2 0 0

R I M M 4 2 0 0

R I M M 3 2 0 0

R I M M 4 2 0 0

R I M M 3 2 0 0

R I M M 4 2 0 0

R I M M 3 2 0 0

R I M M 4 2 0 0

R I M M 3 2 0 0

R I M M 4 2 0 0

R I M M 3 2 0 0

1 5 1 6 / 1 6 4 2 ^c

1 1 7 6 / 1 2 7 6

3 3 5 0 / 3 4 7 6

2 2 4 0 / 2 3 4 0

4 4 7 0 / 4 5 9 6

2 8 0 0 / 2 9 0 0

1 6 6 8 / 1 8 2 4

1 2 9 6 / 1 4 1 6

3 5 0 2 / 3 6 5 8

2 3 6 0 / 2 4 8 0

4 6 2 2 / 4 7 7 8

2 9 2 0 / 3 0 4 0

1 4 8 4 / 1 6 1 0

1 1 4 4 / 1 2 4 4

2 2 7 0 / 2 3 9 6

1 6 0 0 / 1 7 0 0

2 7 5 0 / 2 8 7 6

1 8 4 0 / 1 9 4 0

1 6 3 6 / 1 7 9 2

1 2 6 4 / 1 3 8 4

2 4 2 2 / 2 5 7 8

1 7 2 0 / 1 8 4 0

2 9 0 2 / 3 0 5 8

1 0 6 0 / 2 0 8 0

1 4 6 8 / 1 5 9 4

1 1 2 8 / 1 2 2 8

1 7 3 0 / 1 8 5 6

1 2 8 0 / 1 3 8 0

1 8 9 0 / 2 0 1 6

1 3 6 0 / 1 4 6 0

1 6 2 0 / 1 7 7 6

1 2 4 8 / 1 3 6 8

1 8 8 2 / 2 0 3 8

1 4 0 0 / 1 5 2 0

2 0 4 2 / 2 1 9 8

1 4 8 0 / 1 6 0 0

O n e R D R A M d e v i c e p e r c h a n n e l i n R e a d^b

b a l a n c e i n N A P m o d e

,

I_{D D 1}

m A

O n e R D R A M d e v i c e p e r c h a n n e l i n R e a d^b

b a l a n c e i n S t a n d b y m o d e

I_{D D 2}

I_{D D 3}

I_{D D 4}

I_{D D 5}

I_{D D 6}

O n e R D R A M d e v i c e p e r c h a n n e l i n R e a d^b

balance in Active mode

O n e R D R A M d e v i c e p e r c h a n n e l i n W r i t e ,

b a l a n c e i n N A P m o d e

O n e R D R A M d e v i c e p e r c h a n n e l i n W r i t e ,

b a l a n c e i n S t a n d b y m o d e

O n e R D R A M d e v i c e p e r c h a n n e l i n W r i t e ,

balance in Active mode

a. Actual power will depend on memory controller and usage patterns. Power does not include Refresh Current.

b . I / O c u r r e n t i s a f u n c t i o n o f t h e % o f 1 ’ s , t o a d d I / O p o w e r f o r 5 0 % 1 ’ s f o r a X 1 6 n e e d t o a d d 2 5 7 m A o r 2 9 0 m A f o r X 1 8 E C C m o d u le for the follow-

ing: V = 2 . 5 V , V = 1 . 8 V , V = 1 . 4 V a n d V = V - 0 . 5 V .

DD

T E R M

R E F

DIL

R E F

c. Current values represent X32( N o n - E c c ) / X 3 6 ( E c c )

Page 9

Version 1.0 July 2002

Preliminary

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

32 Bit RIMM^®Module

AC Electrical Specifications

Table 8 : AC Electrical Specifications

P a r a m e t e r a n d C o n d i t i o n s : ^a

S y m b o l

M i n

T y p

M a x

Unit

1 2 8 M B , 2 5 6 M B , 5 1 2 M B M o d u l e s

Z _L

M o d u l e I m p e d a n c e o f R S L S i g n a l s

25.2

23.8

28.0

30.8

32.2

W

Z _{U L - C M O S}

M o d u l e I m p e d a n c e o f S C K a n d C M D s i g n a l s

T _{P D}

Propagation Delay variation of RSL signals. Average clock delay from

f i n g e r t o f i n g e r o f a l l R S L c l o c k n e t s ( C T M , C T M N , C F M , a n d

C F M N )

See

t a b l e 1 0 ^b

ps

a,c

DT_PD

Propagation delay variation of RSL signals with respect to T_PD

-21

21

ps

DT_PD-CMOS

Propagation delay variation of SCK signal with respect to an average clock

delay ^a

-250

250

DT_PD-SCK,CMD

Propagation delay variation of CMD signal with respect to SCK

signal

-200

200

ps

V_a/V_IN

V_XF/V_IN

V_XB/V_IN

R_DC

Attenuation Limit

17.0

4.0

%

Forward crosstalk coefficient (300ps input rise time @ 20%-80%)

Backward crosstalk coefficient (300ps input rise time @ 20%-80%)

DC Resistance Limit

2.0

0.8

%

-

W

a. Specifications apply per channel

b. T or Average clock delay is defined as the delay from finger to finger of RSL signal.

PD

c. If the module meets the following specification, it is compliant to the specification. If the module does not meet these specifications, the specifica-

tion can be adjusted by the “Adjusted DT Specification” table 9 below.

PD

Adjusted DT_PDSpecification

Table 9 : Adjusted

DT_PDSpecification

Adjusted

Min/Max

Absolute

Min / Max

Symbol

DT_PD

Parameter and Conditions

Unit

Propagation delay variation of RSL signals with

respect to T_PDfor 4, 8, and 16 device modules

+/-

[17+(18*(N/

2) *DZ0)]^a

-30

30

ps

a. Where:

N = Number of RDRAM devices installed on the RIMM module

DZ0 = delta Z0% = (max Z0 - min Z0)/(min Z0)

(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)

P a g e 1 0

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

32bit RIMM Module T_PDSpecification

Table 10 : 32 bit RIMM Module T_PDSpecification

32 bit RIMM Module Capacity

512MB

Max

256MB

Max

128MB

Max

I_DD

Unit

Parameter and Condition for RIMM4200,

RIMM3200

T_PD

Propagation delay per channel, all RSL signals

1.36

1.02

0.89

ns

Page11

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

Physical Dimensions -1 ( For PCB )

The following defines the 2 channel RDRAM module dimensions. All units are in millimeters with inches in brackets[ ], where appropriate.

The dimensions without tolerance specification use the default tolerance of ±0.127[±0.005].

133.35±0.127[5.250±0.005]

2.85[0.112]

120.65[4.75]

4.00±0.15

[0.157±0.006]

DIA 2.44

COMPONENT AREA

(A SIDE)

R 2.00

7 . 4 6 8 [ 0 . 2 9 4 ]

A-1

A-116

1.00[0.039]

5.68[0.2236]

8. 60[0. 339]

B - 1 1 6

B - 1

COMPONENT AREA

(B SIDE)

R 2 . 0 0

D I A 2 . 4 4

N o t e : T h e g r a y a r e a a b o v e r e p r e s e n t s t h e c o n t a c t s u r f a c e o f t h e h e a t s p r e a d e r .

0 . 8 0± 0 . 1 0

[ 0 . 0 3 1± 0. 004]

Heat spreader

1 . 0 0 [0. 039]

3.00 ± 0. 10

[ 0 . 1 2± 0. 004]

Min. 4. 88

[0. 192]

0. 3± 0 . 1 0

2. 99± 0. 05

[0. 12± 0. 002]

3 . 0 0± 0 . 1 0

[ 0 . 1 1 9± 0. 004]

[0. 012±0. 004]

DETAIL A

DETAIL B

Figure 3 : 32 bit RIMM Module PCB Physical Dimensions

Page12

Version 1.0 July 2002

Preliminary

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

32 Bit RIMM^®Module

Physical Dimensions -2 ( For Heat Spreader )

T h e f o l l o w i n g d e f i n e s t h e 2 c h a n n e l R D R A M m o d u l e d i m e n s i o n s . A l l u n i t s a r e i n m i l l i m e t e r s w i t h i n c h e s i n b r a c k e t s [ ] , w h e r e a p p ropriate.

The dimensions without tolerance specification use the default tolerance of ±0.127[±0.005].

132.76±0.25[5.226±0.009]

127.66±0.12[5.023±0.005]

112.7±0.12[4.436±0.005]

2.9[0.114]

DIA 2. 36± 0.05[0.09 ±0 . 0 0 1 ]

Center-Point

http://www.samsungsemi.com

WARNING ! HOT SURFACE

1.00±0.07

[0.04±0.002]

12.7±0.07[0.5±0.002] 12.7±0.07[0.5±0.002]

133.35±0.127[5.250±0.005]

A

http://www.samsungsemi.com

WARNING ! HOT SURFACE

A

SECTION A-A

Max 7.80

[0.307]

Max 4.70

[0.185]

Heat Spreader

CSP

Thermal

Conductive

Gap Filling

Material

Conductive

Gap Filling

Material

PCB

1.27±0.10

[0.050±0.004]

1.27±0.10

[0.050±0.004]

[ Single side module ]

[ Double side module]

Figure 4: 32 bit RIMM Heat Spreader Physical Dimensions

P a g e 1 3

Version 1.0 July 2002

Preliminary

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

32 Bit RIMM^®Module

32 bit RIMM Module Marking

T h e 3 2 b i t R I M M m o d u l e s a v a i l a b l e f r o m S a m s u n g a r e

marked like Figure 5 below. This marking also assists users

to specify and verify if the correct 32 bit RIMM modules are

installed in their systems. In the diagram, a label is shown

a t t a c h e d t o t h e 3 2 b i t R I M M m o d u l e ’s heat spreader.

Information contained on the label is specific to the 32 bit

R I M M m o d u l e a n d p r o v i d e s R D R A M i n f o r m a t i o n w i t h o u t

r e q u i r i n g r e m o v a l o f t h e 3 2 b i t R I M M m o d u l e ’ s h e a t

spreader.

A

B

C

D

E

F

G

J

I

H

K

Label Field

Description

Marked Text

Unit

A

B

C

Vendor Logo

Country

32 bit RIMM Vendor SAMSUNG Logo Area

Country of origin

SAMSUNG

KOREA

yyww

-

Year & Week code Manufactured Year & Week code

Module Memory

Capacity

Number of 8-bit or 9-bit MBytes of RDRAM storage in 32 bit

RIMM module

128/144MB, 256/288MB,

512/576MB

D

E

F

-

Number of

RDRAMs

Number of RDRAM devices contained in the 32 bit RIMM

module

RDRAM

devices

4/8/16

Indicates whether the 32 bit RIMM module supports 8 (no

ECC) or 9 (ECC) bit Bytes

blank = 8 bit Bytes

ECC = 9 bit Bytes

ECC Support

-

G

H

Notice!

Hot surface caution notice.

ISO Standard

-

Caution Logo

Gerber : 10 = 1.0 ver.

SPD : 2 = 1.3 ver.

Gerber & SPD

Version

PCB Gerber file & SPD code version used on 32 bit RIMM

Module

I

-

J

Product Name

Part No.

Product Name

RIMM4200, RIMM3200

See Table 1

ns

-

K

SAMSUNG 32 bit RIMM part No.

Figure 5 : 32 bit RIMM Marking Example

P a g e 1 4

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

Table Of Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Key Timing Parameters/Part Numbers . . . . . . . . . . . . . . . . 1

Module Pad Numbers and Signal Names . . . . . . . . . . . 2 - 3

Module Connector Pad Description . . . . . . . . . . . . . . . 3 - 6

32 bit RIMM Module Functional Diagram . . . . . . . . . . . . . 7

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 8

DC Recommended Electrical Conditions . . . . . . . . . . . . . . 8

32 bit RIMM Module Supply Current Profile . . . . . . . . . . . 9

AC Electrical Specifications . . . . . . . . . . . . . . . . . . . 10 - 11

Physical Dimensions -1 ( For PCB ) . . . . . . . . . . . . . . . . . 12

Physical Dimensions -2 ( For Heat Spreader) . . . . . . . . . . 13

Standard 32 bit RIMM Module Marking . . . . . . . . . . . . . 14

Direct Rambus and Direct RDRAM, SO-RIMM and RIMM

are trademarks of Rambus Inc. Rambus, RDRAM, and the

Rambus Logo are registered trademarks of Rambus Inc.

This document contains advanced information that is subject

to change by Samsung Electronics without notice

Document Version 1.0

Samsung Electronics Co. Ltd.

San #16 Banwol-ri, Taean-Eup Hwasung-City,

Gyeonggi-Do, KOREA

Telephone: 82-31-208-6369

Fax: 82-31-208-6799

http://www.intl.samsungsemi.com

Page15

Version 1.0 July 2002

Preliminary

32 Bit RIMM Module

MD16R1624(8/G)AF0

MD18R1624(8/G)AF0

®

Page16

Version 1.0 July 2002


型号：	MD16R1624AF0-CN9
厂家：	SAMSUNG
描述：	Rambus DRAM Module, 32MX32, CMOS, RIMM-232 动态存储器
文件：	总16页 (文件大小：201K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MD16R1624AF0-CN9 [SAMSUNG]

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