MR18R0828AM0-CG6 [SAMSUNG]
Rambus DRAM Module, 64MX18, 53.3ns, CMOS, MIRRORED, RIMM-184;
| 型号： | MR18R0828AM0-CG6 |
| 厂家： | 
SAMSUNG |
| 描述： | Rambus DRAM Module, 64MX18, 53.3ns, CMOS, MIRRORED, RIMM-184 时钟 动态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Change History
Version 1.0 (October 2000) - Preliminary
* First copy.
* Based on the 1.1ver. 128/144Mbit RDRAMs(A-die, 32s banks) base Normal RIMM Datasheet.
Version 1.0 Oct. 2000
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
TM
(8Mx16)*4(8)pcs Mirrored RIMM Module based on 128Mb A-die, 32s banks,16K/32ms Ref, 2.5V
TM
(8Mx18)*4(8)pcs Mirrored RIMM Module based on 144Mb A-die, 32s banks,16K/32ms Ref, 2.5V
Key Timing Parameters/Part Numbers
Overview
®
The following table lists the frequency and latency bins
available for Mirrored RIMM modules.
The Rambus Mirrored RIMM™ module is a general
purpose high- performance memory module suitable for use
in a broad range of applications including computer
memory, personal computers, workstations, and other appli-
cations where high bandwidth and low latency are required.
Table 1: Part Number by Freq. & Latency
Speed
The Rambus Mirrored RIMM module consists of
128Mb/144Mb Direct Rambus DRAM devices of mirrored
package. These are extremely high-speed CMOS DRAMs
organized as 8M words by 16 or 18 bits. The use of Rambus
Signaling Level (RSL) technology permits 600 MHz, 711
MHz or 800 MHz transfer rates while using conventional
system and board design technologies. RDRAM devices are
capable of sustained data transfers at 1.25 ns per two bytes
(10ns per 16 bytes).
t
Organiza-
tion
RAC
Part Number
I/O Freq.
(MHz)
(Row
Access
Time) ns
Bin
32M x 16/18 -CK8
800
711
600
800
711
600
45
45
MR16/18R0824AM0-CK8
MR16/18R0824AM0-CK7
MR16/18R0824AM0-CG6
MR16/18R0828AM0-CK8
MR16/18R0828AM0-CK7
MR16/18R0828AM0-CG6
-CK7
-CG6
53.3
45
64M x 16/18 -CK8
-CK7
45
The RDRAM architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed,
memory transactions. The separate control and data buses
with independent row and column control yield over 95%
bus efficiency. The RDRAM's 32-bank architecture supports
up to four simultaneous transactions per device.
-CG6
53.3
Form Factor
The Rambus Mirrored RIMM modules are offered in 184-
pad 1mm edge connector pad pitch suitable for 184 contact
RIMM connectors. Figure 1 below, shows a eight device
Rambus Mirrored RIMM module.
Features
¨ High speed 800, 711 and 600MHz RDRAM storage
¨ 184 edge connector pads with 1mm pad spacing
¨ Module PCB size : 133.35mm x 31.75mm x 1.27mm
(5.25” x 1.25” x 0.05”)
¨ Each RDRAM has 32 banks, for a total of 256, 128 banks
on each 128/144MB, 64/72MB module respectively
¨ Gold plated edge connector pad contacts
¨ Serial Presence Detect(SPD) support
¨ Operates from a 2.5 volt supply (±5%)
¨ Powerdown self refresh modes
¨ Separate Row and Column buses for higher efficiency
¨
m-BGA mirrored package(62 Balls)
Note: There is only single side type for Mirrored RIMM module
Figure 1: Rambus Mirrored RIMM module shown with heat spreader removed
Version 1.0 Oct. 2000
Page 1
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Table 2: Module Pad Numbers and Signal Names
Pin
A1
Pin Name
Gnd
Pin
B1
Pin Name
Gnd
Pin
Pin Name
NC
Pin
B47
Pin Name
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
NC
A2
LDQA8
Gnd
B2
LDQA7
Gnd
NC
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
NC
A3
B3
NC
NC
A4
LDQA6
Gnd
B4
LDQA5
Gnd
NC
NC
A5
B5
Vref
Vref
A6
LDQA4
Gnd
B6
LDQA3
Gnd
Gnd
Gnd
A7
B7
SCL
SA0
A8
LDQA2
Gnd
B8
LDQA1
Gnd
Vdd
Vdd
A9
B9
SDA
SA1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
LDQA0
Gnd
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
LCFM
Gnd
SVdd
SWP
SVdd
SA2
LCTMN
Gnd
LCFMN
Gnd
Vdd
Vdd
RSCK
Gnd
RCMD
Gnd
LCTM
Gnd
NC
Gnd
RDQB7
Gnd
RDQB8
Gnd
NC
LROW2
Gnd
Gnd
RDQB5
Gnd
RDQB6
Gnd
LROW1
Gnd
LROW0
Gnd
RDQB3
Gnd
RDQB4
Gnd
LCOL4
Gnd
LCOL3
Gnd
RDQB1
Gnd
RDQB2
Gnd
LCOL2
Gnd
LCOL1
Gnd
RCOL0
Gnd
RDQB0
Gnd
LCOL0
Gnd
LDQB0
Gnd
RCOL2
Gnd
RCOL1
Gnd
LDQB1
Gnd
LDQB2
Gnd
RCOL4
Gnd
RCOL3
Gnd
LDQB3
Gnd
LDQB4
Gnd
RROW1
Gnd
RROW0
Gnd
LDQB5
Gnd
LDQB6
Gnd
NC
RROW2
Gnd
LDQB7
Gnd
LDQB8
Gnd
Gnd
RCTM
Gnd
NC
LSCK
Vcmos
SOUT
Vcmos
NC
LCMD
Vcmos
SIN
Gnd
RCTMN
Gnd
RCFMN
Gnd
Vcmos
NC
RDQA0
Gnd
RCFM
Gnd
Gnd
Gnd
RDQA2
Gnd
RDQA1
Gnd
NC
NC
Vdd
Vdd
RDQA4
Gnd
RDQA3
Gnd
Vdd
Vdd
NC
NC
RDQA6
Gnd
RDQA5
Gnd
NC
NC
NC
NC
RDQA8
Gnd
RDQA7
Gnd
NC
NC
Version 1.0 Oct. 2000
Page 2
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Table 3: Module Connector Pad Description
Signal
Pins
I/O
Type
Description
Gnd
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
Ground reference for RDRAM core and interface. 72 PCB
connector pads.
LCFM
B10
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
I
I
I
I
I
I
RSL
RSL
LCFMN
LCMD
B12
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
B34
Serial Command used to read from and write to the control
registers. Also used for power management.
V
CMOS
LCOL4..
LCOL0
A20, B20, A22, B22, A24
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
RSL
LCTM
A14
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
RSL
RSL
LCTMN
A12
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
LDQA8..
LDQA0
A2, B2, A4, B4, A6, B6, A8, B8, A10
Data bus A. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. LDQA8 is non-func-
tional on modules with x16 RDRAM devices
I/O
I/O
RSL
LDQB8..
LDQB0
B32, A32, B30, A30, B28, A28, B26,
A26, B24
Data bus B. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. LDQB8 is non-func-
tional on modules with x16 RDRAM devices.
RSL
RSL
LROW2..
LROW0
B16, A18, B18
A34
Row bus. 3-bit bus containing control and address information
for row accesses.
I
I
LSCK
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
V
CMOS
NC
A16, B14, A38, B38, A40, B40, A43,
B43, A44, B44, A45, B45, A46, B46,
A47, B47, A48, B48, A49, B49, A50,
B50, A77, B79
These pads are not connected. These 24 connector pads are
reserved for future use.
RCFM
B83
B81
B59
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Positive polarity.
I
I
I
RSL
RSL
RCFMN
RCMD
Clock from master. Interface clock used for receiving RSL
signals from the Channel. Negative polarity.
Serial Command Input. Pin used to read from and write to the
control registers. Also used for power management.
V
CMOS
Version 1.0 Oct. 2000
Page 3
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Signal
Pins
I/O
I
Type
RSL
Description
RCOL4..
RCOL0
A73, B73, A71, B71, A69
Column bus. 5-bit bus containing control and address infor-
mation for column accesses.
RCTM
A79
A81
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Positive polarity.
I
I
RSL
RSL
RCTMN
Clock to master. Interface clock used for transmitting RSL
signals to the Channel. Negative polarity.
RDQA8..
RDQA0
A91, B91, A89, B89, A87, B87, A85,
B85, A83
Data bus A. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. RDQA8 is non-func-
tional on modules x16 RDRAM devices.
I/O
I/O
RSL
RDQB8..
RDQB0
B61, A61, B63, A63, B65, A65, B67,
A67, B69
Data bus B. A 9-bit bus carrying a byte of read or write data
between the Channel and the RDRAM. RDQB8 is non-func-
tional on modules x16 RDRAM devices.
RSL
RSL
RROW2..
RROW0
B77, A75, B75
A59
Row bus. 3-bit bus containing control and address information
for row accesses.
I
I
RSCK
Serial Clock input. Clock source used to read from and write
to the RDRAM control registers.
V
CMOS
SA0
SA1
SA2
SCL
SDA
SIN
B53
B55
B57
A53
A55
B36
Serial Presence Detect Address 0.
Serial Presence Detect Address 1.
Serial Presence Detect Address 2.
Serial Presence Detect Clock.
I
I
SV
DD
DD
DD
DD
DD
SV
SV
SV
SV
I
I
Serial Presence Detect Data (Open Collector I/O).
I/O
Serial I/O for reading from and writing to the control registers.
Attaches to SIO0 of the first RDRAM on the module.
I/O
I/O
V
V
CMOS
CMOS
SOUT
A36
Serial I/O for reading from and writing to the control registers.
Attaches to SIO1 of the last RDRAM on the module.
SV
A56, B56
SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1
and SA2.
DD
SWP
A57
Serial Presence Detect Write Protect (active high). When low,
the SPD can be written as well as read.
I
SV
DD
V
A35, B35, A37, B37
CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT.
Supply voltage for the RDRAM core and interface logic.
CMOS
Vdd
Vref
A41, A42, A54, A58, B41, B42, B54,
B58
A51, B51
Logic threshold reference voltage for RSL signals.
Version 1.0 Oct. 2000
Page 4
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Vdd
2 per
RDRAM
0.1mF
SIO0
SIO1
SCK
CMD
Vref
U1
Direct RDRAM (128/144Mb)
Gnd
V
REF
1 per
2 RDRAMs
Plus one
Near Connector
0.1mF
SIO0
SIO1
SCK
CMD
Vref
U2
Direct RDRAM (128/144Mb)
Gnd
V
CMOS
1 per
2 RDRAMs
0.1 mF
SIO0
SIO1
SCK
CMD
U3
Direct RDRAM (128/144Mb)
Gnd
Vref
·
·
·
·
·
·
Module
Capacity
N
SIO0
SIO1
SCK
CMD
Vref
UN
128/144MB
64/72MB
8
4
Direct RDRAM (128/144Mb)
Note 1. Rambus Channel signals form a loop through
the Mirrored RIMM module, with the exception of the SIO chain.
Note 2. See Serial Presence Detection Specification for
information on the SPD device and its contents.
SV
DD
Serial Presence Detect
SV
DD
Vcc
A1
SCL
WP
A0
SDA
A2
SCL
SWP
SDA
0.1 mF
47KW
U0
SA0
SA1
SA2
Gnd
Figure 2: Mirrored RIMM Module Functional Diagram
Version 1.0 Oct. 2000
Page 5
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Absolute Maximum Ratings
Table 4: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
V
V
Voltage applied to any RSL or CMOS signal pad with respect to Gnd
Voltage on VDD with respect to Gnd
Storage temperature
- 0.3
- 0.5
- 50
-
V
V
+ 0.3
+ 1.0
V
I,ABS
DD
DD
V
DD,ABS
STORE
PLATE
T
T
100
92
°C
Plate temperature
°C
DC Recommended Electrical Conditions
Table 5: DC Recommended Electrical Conditions
Symbol
Parameter and Conditions
Min
Max
Unit
V
Supply voltage
2.50 - 0.13
2.50 + 0.13
V
DD
V
CMOS I/O power supply at pad for 2.5V controllers:
CMOS I/O power supply at pad for 1.8V controllers:
V
V
V
V
CMOS
DD
DD
1.8 - 0.1
1.4 - 0.2
2.2
1.8 + 0.2
1.4 + 0.2
3.6
V
Reference voltage
V
V
REF
V
Serial Presence Detector- Positive power supply
RSL input low voltage
SPD
V
IL
V
V
- 0.5
V
V
- 0.2
REF
V
REF
V
RSL input high voltage
+ 0.2
+ 0.5
REF
V
IH
REF
V
CMOS input low voltage
CMOS input high voltage
- 0.3
0.5V
V
- 0.25
CMOS
V
IL,CMOS
V
0.5V
V
+ 0.25
+ 0.3
V
IH,CMOS
CMOS
CMOS
V
CMOS output low voltage @ I
= 1mA
OL,CMOS
0.3
V
OL,CMOS
V
CMOS output high voltage @ I
= -0.25mA
- 0.3
V
OH,CMOS
OH,CMOS
CMOS
a
a
a
a
I
V
current @ V
REF,MAX
-10 x no. RDRAMs
-10 x no. RDRAMs
-10.0
10 x no. RDRAMs
10 x no. RDRAMs
10.0
mA
mA
mA
REF
REF
I
CMOS input leakage current @ (0 £ V
CMOS input leakage current @ (0 £ V
£ V
£ V
)
DD
SCK,CMD
CMOS
CMOS
I
)
DD
SIN,SOUT
a. The table below shows the number of 128Mb or 144Mb RDRAM devices contained in a Mirrored RIMM module of listed memory storage capacity.
Table 6: Mirrored RIMM Module Capacity and Number of RDRAM device
Mirrored RIMM Module Capacity
128/144MB
64/72MB
Number of 128Mb or 144Mb RDRAM devices
8
4
Version 1.0 Oct. 2000
Page 6
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Mirrored RIMM Module Current Profile
Table 7 : Mirrored RIMM Module Current Profile
Mirrored RIMM Module Capacity
Number of 128/144Mb RDRAMs
128/144MB
64/72MB
I
8
4
Unit
DD
a
Mirrored RIMM Module power conditions
Freq.
Max
Max
b
I
I
I
I
I
I
One RDRAM in Read , balance in NAP mode
-800
-711
-600
-800
-711
-600
-800
-711
-600
-800
-711
-600
-800
-711
-600
-800
-711
-600
520/550
480/510
510/540
470/500
420/440
810/840
750/780
670/690
990/1020
920/950
820/840
590/640
540/600
470/520
890/940
830/880
730/770
1070/1120
990/1050
880/920
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
DD1
430/450
b
One RDRAM in Read , balance in Standby mode
1230/1260
1150/1180
1030/1050
1650/1680
1540/1570
1380/1400
610/660
DD2
DD3
DD4
DD5
DD6
b
One RDRAM in Read , balance in Active mode
One RDRAM in Write, balance in NAP mode
One RDRAM in Write, balance in Standby mode
One RDRAM in Write, balance in Active mode
560/610
490/530
1310/1360
1230/1280
1090/1130
1730/1780
1610/1670
1440/1480
a. Actual power will depend on individual RDRAM component specifications, memory controller and usage patterns. Power does not include Refresh
Current.
b. I/O current is a function of the % of 1’s, to add I/O power for 50% 1’s for a X16 need to add 257mA or 290mA for X18 ECC module for the following:
V
= 2.5V, V
= 1.8V, V
= 1.4V and V
= V
- 0.5V.
REF
DD
TERM
REF
DIL
Version 1.0 Oct. 2000
Page 7
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
AC Electrical Specifications
Table 8: AC Electrical Specifications
Symbol
Parameter and Conditions
Min
Typ
Max
Unit
W
Z
L
Module Impedance of RSL Signals
25.2
28
30.8
Z
Module Impedance of SCK and CMOS signals
23.8
-
28
32.2
W
UL-CMOS
T
Propagation Delay variation of RSL signals. Average clock
delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN)
See
Table10
PD
a,b
ns
b,c
DT
DT
DT
Propagation delay variation of RSL signals with respect to T
for 4, 8 device modules
-21
21
PD
PD
ps
ps
ps
%
%
%
Propagation delay variation of SCK signals with respect to an aver-
-250
-200
250
200
See
PD-CMOS
PD-SCK,CMD
b
age clock delay
Propagation delay variation of CMD signals with respect to SCK
signal
V /V
Attenuation Limit
a
IN
a
Table10
V
V
/V
Forward crosstalk coefficient (300ps input rise time @ 20%-80%)
Backward crosstalk coefficient (300ps input rise time @ 20%-80%)
See
XF IN
a
Table10
/V
See
XB IN
a
Table10
a. Table 10 lists parameters and specifications for different storage capacity Mirrored RIMM Modules that use 128Mb or 144Mb RDRAM devices.
b. T or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN).
PD
c. If the Mirrored RIMM module meets the following specification, then it is compliant to the specification. If the Mirrored RIMM module does not
meet these specifications, then the specification can be adjusted by the “Adjusted DT Specification“ table below.
PD
Adjusted
D
T
Specification
PD
Table 9: Adjusted
D
T
Specification
PD
Absolute
Min / Max
Symbol
Parameter and Conditions
Adjusted Min/Max
Unit
a
DT
Propagation delay variation of RSL signals with respect to
for 4, and 8 device modules
+/-[17+(18*N*DZ0)]
-30
30
PD
ps
T
PD
a. Where:
N = Number of RDRAM devices installed on the Mirrored RIMM module
DZ0 = delta Z0% = (max Z0 - min Z0)/(min Z0)
(max Z0 and min Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the modules)
Version 1.0 Oct. 2000
Page 8
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
AC Electrical Specifications for Mirrored RIMM Modules
Table 10: AC Electrical Specifications for Mirrored RIMM Modules
Mirrored RIMM Module Capacity
Number of 128/144Mb RDRAMs
128/144MB
64/72MB
Symbol
8
4
Unit
Parameter and Condition for Mirrored RIMM Modules
Freq.
Max
Max
Propagation Delay, all RSL signals
-800
-711
-600
-800
-711
-600
-800
-711
-600
-800
-711
-600
-800
-711
-600
1.56
1.56
1.56
16.0
16.0
12.5
4.0
1.28
1.28
1.28
12.0
12.0
10.5
2.0
ns
ns
ns
%
%
%
%
%
%
%
%
%
W
W
W
T
PD
Attenuation Limit
V /V
a
IN
Forward crosstalk coefficient (300ps input rise time
@ 20%-80%)
V
V
R
/V
4.0
2.0
XF IN
4.0
2.0
Backward crosstalk coefficient (300ps input rise time
@ 20%-80%)
2.0
1.5
/V
2.0
1.5
XB IN
2.0
1.5
DC Resistance Limit
0.8
0.6
0.8
0.6
DC
0.8
0.6
Version 1.0 Oct. 2000
Page 9
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Physical Dimensions -1 ( For PCB )
The following defines the Mirrored RIMM module dimensions. All units are in millimeters with inches in brackets[ ], where appropriate.
The dimensions without tolerance specification use the default tolerance of ±0.127[±0.005].
133.35±0.127[5.250±0.005]
6.35[0.25]
3.00[0.118]
120.65[4.75]
4.00±0.15
DIA 2.44
[0.157±0.006]
R 2.00
COMPONENT AREA
(A SIDE)
+
+
7.468[0.294]
A-1
A-92
45.00[1.772]
DETAIL A
DETAIL B
1.00[0.039]
45.00[1.772]
11.50[0.453]
R 1.00
5.68[0.2236]
4.50[0.177]
55.175±0.08[2.172±0.003]
78.175[3.078]
Note : The gray area above represents the contact surface of the heat spreader.
0.80±0.10
[0.031±0.004]
Heat spreader
1.00[0.039]
3.00±0.10
[0.12±0.004]
Min.4.88
[0.192]
0.15±0.10
[0.006±0.004]
2.99±0.05
2.00±0.10
[0.079±0.004]
[0.12±0.002]
DETAIL A
DETAIL B
Figure 3: Mirrored RIMM Module PCB Physical Dimensions
Version 1.0 Oct. 2000
Page10
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Physical Dimensions -2 ( For Heat Spreader )
The following defines the Mirrored RIMM module dimensions. All units are in millimeters with inches in brackets[ ], where appropriate.
The dimensions without tolerance specification use the default tolerance of ±0.12[±0.005].
127±0.25[5.0±0.009]
120.66±0.12[4.748±0.005]
108.97±0.12[4.290±0.005]
2.9[0.114]
DIA 2.36±0.05[0.09±0.001]
Center-Point
http://www.samsungsemi.com
WARNING ! HOT SURFACE
1.00±0.07
[0.04±0.002]
12.7±0.07[0.5±0.002]
12.7±0.07[0.5±0.002]
133.35±0.127[5.250±0.005]
127±0.25[5.0±0.009]
A
http://www.samsungsemi.com
WARNING ! HOT SURFACE
A
SECTION A-A
Max 4.70
[0.185]
Heat Spreader
CSP
Thermal
Conductive
Gap Filling
Material
PCB
1.27±0.10
[0.050±0.004]
[ Single side module ]
Figure 4: Heat Spreader Physical Dimensions
Version 1.0 Oct. 2000
Page11
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Standard RIMM Module Marking
RIMM module’s heat spreader. Information contained on the
label is specific to the RIMM module and provides RDRAM
information without requiring removal of the RIMM module’s
heat spreader.
The RIMM modules available from Samsung are marked like
Figure 5 below. This marking also assists users to specify and
verify if the correct RIMM modules are installed in their
systems. In the diagram, a label is shown attached to the
A
C
D
E
F
G
B
KOREA 0050 128MB /8 ECC
MR18R0828AM0-CK8 800-45 101
L
K
J
I
H
Marked Text
Unit
Label Field
Description
A
B
C
Vendor Logo
Country
RIMM Vendor SAMSUNG Logo Area
Country of origin
SAMSUNG
KOREA
yyww
-
-
-
Year & Week
code
Manufactured Year & Week code
D
E
F
Module Memory
Capacity
Number of 8-bit or 9-bit MBytes of RDRAM storage in
RIMM module
128MB, 64/MB
/8, /4
-
Number of
RDRAMs
Number of RDRAM devices contained in the RIMM
module
RDRAM
devices
ECC Support
Indicates whether the RIMM module supports 8 (no
ECC) or 9 (ECC) bit Bytes
blank = 8 bit Bytes
ECC = 9 bit Bytes
-
G
H
I
Notice!
Hot surface caution notice.
ISO Standard
-
-
-
-
Caution Logo
-
Gerber & SPD
Version
PCB Gerber file & SPD code version used on RIMM
Module
Gerber : 10 = 1.0 ver.
SPD
: 1 = 1.1ver.
J
tRAC
Row Access Time
-45, -53
ns
MHz
-
K
L
Memory Speed
Part No.
Data transfer speed for RDRAM RIMM module
SAMSUNG RIMM part No.
800, 711, 600
See Table 1
Figure 5: Mirrored RIMM Marking Example
Version 1.0 Oct. 2000
Page12
MR16R0824(8)AM0
MR18R0824(8)AM0
Preliminary
Table Of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Timing Parameters/Part Numbers . . . . . . . . . . . . . . . . 1
Module Pad Numbers and Signal Names . . . . . . . . . . . . . . 2
Module Connector Pad Description . . . . . . . . . . . . . . . 3 - 4
Mirrored RIMM Module Functional Diagram . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Recommended Electrical Conditions . . . . . . . . . . . . . . 6
Mirrored RIMM Module Supply Current Profile . . . . . . . . 7
AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . 8 - 9
Physical Dimensions -1 ( For PCB ). . . . . . . . . . . . . . . . . 10
Physical Dimensions -2 ( For Heat Spreader). . . . . . . . . . 11
Standard RIMM Module Marking . . . . . . . . . . . . . . . . . . 12
Copyright © October 2000, Samsung Electronics.
All rights reserved.
Direct Rambus and Direct RDRAM, SO-RIMM and RIMM
are trademarks of Rambus Inc. Rambus, RDRAM, and the
Rambus Logo are registered trademarks of Rambus Inc.
This document contains advanced information that is subject
to change by Samsung Electronics without notice
Document Version 1.0
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Kiheung-Eup Yongin-City
Kyunggi-Do, KOREA
Telephone: 82-331-209-3868
Fax: 82-2-760-7990
http://www.intl.samsungsemi.com
Version 1.0 Oct. 2000
Page13
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