S3C70F2XX-SO [SAMSUNG]
Microcontroller, 4-Bit, MROM, SAM47 CPU, 6MHz, CMOS, PDSO32, 0.450 INCH, SOP-32;
| 型号： | S3C70F2XX-SO |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, MROM, SAM47 CPU, 6MHz, CMOS, PDSO32, 0.450 INCH, SOP-32 微控制器 光电二极管 |
| 文件： | 总179页 (文件大小：1056K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C70F2/C70F4 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The S3P70F4 is the microcontroller which has 4 Kbyte one-time-programmable ROM and the functions are the
same to S3C70F2/C70F4. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and
its versatile 8-bit timer/counter, the S3C70F2/C70F4 offers an excellent design solution for a wide variety of
general-purpose applications.
Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response
to internal and external events. In addition, the S3C70F2/C70F4's advanced CMOS technology provides for very
low power consumption and a wide operating voltage range — all at a very low cost.
1-1
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
FEATURES SUMMARY
Memory
Bit Sequential Carrier
·
Supports 16-bit serial data transfer in arbitrary
format
·
·
512 ´ 4-bit data memory (RAM)
2048 ´ 8-bit program memory (ROM):S3C70F2
4096 ´ 8-bit program memory (ROM):S3C70F4
Interrupts
·
·
·
Two external interrupt vectors
24 I/O Pins
Three internal interrupt vectors
Two quasi-interrupts
·
I/O: 18 pins, including 8 high current pins
Input only: 6 pins
·
Memory-Mapped I/O Structure
Data memory bank 15
Comparator
·
·
4-channel mode:
Internal reference (4-bit resolution)
16-step variable reference voltage
Two Power-Down Modes
·
3-channel mode:
External reference
150 mV resolution (worst case)
·
·
Idle mode: Only CPU clock stops
Stop mode: System clock stops
8-bit Basic Timer
OSCILLATION SOURCES
·
·
Programmable interval timer
Watch-dog timer
·
·
·
Crystal, Ceramic for system clock
Crystal/ceramic: 0.4 - 6.0 MHz
CPU clock divider circuit (by 4. 8, or 64)
8-bit Timer/Counter 0
·
·
Programmable interval timer
Instruction Execution Times
External event counter function
Timer/counter clock output to TCLO0 pin
·
·
0.95, 1.91, 15.3 µs at 4.19 MHz
0.67, 1.33, 10.7 µs at 6.0 MHz
Watch Timer
·
Time interval generation: 0.5 s, 3.9 ms at 4.19
MHz
Operating Temperature
° °
– 40 C to 85 C
·
·
4 frequency outputs to BUZ pin
Operating Voltage Range
1.8 V to 5.5 V
8-bit Serial I/O Interface
·
·
·
·
·
8-bit transmit/receive mode
8-bit receive-only mode
Package Type
30 SDIP, 32 SOP
LSB-first or MSB-first transmission selectable
Internal or external clock source
·
1-2
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
FUNCTION OVERVIEW
SAM47 CPU
All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32 K bytes of program memory. The arithmetic logic unit (ALU) performs 4-bit addition, subtraction, logical,
and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two
cycles.
CPU REGISTERS
Program Counter
A 11-bit program counter (PC) stores addresses for instruction fetch during program execution. Usually, the PC is
incremented by the number of bytes of the instruction being fetched. An exception is the 1-byte instruction REF
which is used to reference instructions stored in a look-up table in the ROM. Whenever a reset operation or an
interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC13–12 is reserved to support future
expansion of the device's ROM size.
Stack Pointer
An 8-bit stack pointer (SP) stores addresses for stack operations. The stack area is located in the general-
purpose data memory bank 0. The SP is read or written by 8-bit instructions and SP bit 0 must always be set to
logic zero.
During an interrupt or a subroutine call, the PC value and the program status word (PSW) are saved to the stack
area in RAM. When the service routine has completed, the values referenced by the stack pointer are restored.
Then, the next instruction is executed.
The stack pointer can access the stack regardless of data memory access enable flag status. Since the reset
value of the stack pointer is not defined in firmware, it is recommended that the stack pointer be initialized to 00H
by program code. This sets the first register of the stack area to data memory location 0FFH.
PROGRAM MEMORY
In its standard configuration, the 4096 ´ 8-bit ROM is divided into three functional areas:
— 16-byte area for vector addresses
— 96-byte instruction reference area
— 1920-byte general purpose area (S3C70F2)
— 3968-byte general purpose area (S3C70F4)
The vector address area is used mostly during reset operations and interrupts. These 16 bytes can also be used
as general-purpose ROM.
The REF instruction references 2 ´ 1-byte and 2-byte instructions stored in locations 0020H–007FH. The REF
instruction can also reference 3-byte instructions such as JP or CALL. In order for REF to be able to reference
these instructions, however, JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written
to the reference area with the format TJP or TCALL instead of the normal instruction name. Unused locations in
the instruction reference area can be allocated to general-purpose use.
1-3
PRODUCT OVERVIEW
DATA MEMORY
S3C70F2/C70F4/P70F4
Overview
Data memory is organized into three areas:
— 32 ´ 4-bit working registers
— 224 ´ 4-bit general-purpose area in bank 0
— 256 ´ 4-bit general-purpose area in bank 1
— 128 ´ 4-bit area in bank 15 for memory-mapped I/O addresses
Data stored in data memory can be manipulated by 1-, 4-, and 8-bit instructions.
Data memory is organized into two memory banks — bank 0, bank 1 and bank 15. The select memory bank in-
struction (SMB) selects the bank to be used as working data memory. After power-on reset operation,
initialization values for data memory must be redefined by code.
Data Memory Addressing Modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15.
When the EMB flag is logic zero, restricted area can be accessed. When the EMB flag is set to logic one, all two
data memory banks can be accessed according to the current SMB value. The EMB = "0" addressing mode is
used for normal program execution, whereas the EMB = "1" mode is commonly used for interrupts, subroutines,
mapped I/O, and repetitive access of specific RAM addresses.
Working Registers
The RAM's working register area in data memory bank 0 is further divided into four register banks. Each register
bank has eight 4-bit registers that are addressable either by 1-bit or 4-bit instructions. Paired 4-bit registers can
be addressed as double registers by 8-bit instructions.
Register A is the 4-bit accumulator and double register EA is the 8-bit extended accumulator. Double registers
WX, WL, and HL are used as data pointers for indirect addressing. Unused working registers can be used as
general-purpose memory.
To limit the possibility of data corruption due to incorrect register bank addressing, register bank 0 is usually used
for the main program and banks 1, 2, and 3 for interrupt service routines.
1-4
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operations and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory enable flags.
Before an interrupt or subroutine is processed, the PSW values are pushed onto the stack in data memory bank
0. When the service routine is completed, the PSW values are restored.
IS1
C
IS0
EMB
SC1
ERB
SC0
SC2
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag (C) are 1- and 4-bit read/write or 8-bit read-only addressable. You can address the skip condition flags
(SC0–SC2) using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit registers store address values used to access specific memory and register banks: the select memory
bank register, SMB, and the select register bank register, SRB.
'SMB n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data memory
address in the SMB register. To select register bank 0, 1, 2, or 3, and store the address data in the SRB, you can
use the instruction 'SRB n'.
The instructions "PUSH SB" and "POP SB" move SRB and SMB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
System oscillation circuit generates the internal clock signals for the CPU and peripheral hardware.
The system clock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. To
drive S3C70F2/C70F4 using an external clock source, the external clock signal should be input to X , and its
in
inverted signal to X
out
.
4-bit power control register controls the oscillation on/off, and select the CPU clock. The internal system clock
signal (fx) can be divided internally to produce three CPU clock frequencies — fx/4, fx/8, or fx/64.
INTERRUPTS
Interrupt requests may be generated internally by on-chip processes (INTB, INTT0, and INTS) or externally by
peripheral devices (INT0 and INT1). There are two quasi-interrupts: INTK and INTW. INTK (KS0–KS2) detects
falling edges of incoming signals and INTW detects time intervals of 0.5 seconds or 3.91 milliseconds. The
following components support interrupt processing:
— Interrupt enable flags
— Interrupt request flags
— Interrupt priority registers
— Power-down termination circuit
1-5
PRODUCT OVERVIEW
POWER-DOWN
S3C70F2/C70F4/P70F4
To reduce power consumption, there are two power-down modes: idle and stop. The IDLE instruction initiates idle
mode; the STOP instruction initiates stop mode.
In idle mode, the CPU clock stops while peripherals continue to operate normally. In stop mode, system clock
oscillation stops completely, halts all operations except for a few basic peripheral functions. A power-down is
terminated either by a RESET or by an interrupt (with exception of the external interrupt INT0).
RESET
When RESET is input during normal operation or during power-down mode, a reset operation is initiated and the
CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
I/O PORTS
The S3C70F2/C70F4 has seven I/O ports. Pin addresses for all I/O ports are mapped to locations FF0H–FF6H
in bank 15 of the RAM. There are 6 input pins and 18 configurable I/O pins including 8 high current I/O pins for a
total of 24 I/O pins. The contents of I/O port pin latches can be read, written, or tested at the corresponding
address using bit manipulation instructions.
TIMERS and TIMER/COUNTER
The timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer.
The 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock
frequency.
The programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and
dividing external clock signals. The 8-bit timer/counter generates a clock signal (SCK) for the serial I/O interface.
The watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit.
Its functions include real-time, watch-time measurement, and clock generation for frequency output for buzzer
sound.
SERIAL I/O INTERFACE
The serial I/O interface supports the transmission or reception of 8-bit serial data with an external device. The
serial interface has the following functional components:
— 8-bit mode register
— Clock selector circuit
— 8-bit buffer register
— 3-bit serial clock counter
The serial I/O circuit can be set to transmit-and-receive, or to receive-only mode. MSB-first or LSB-first
transmission is also selectable.
The serial interface can operate with an internal or an external clock source, or using the clock signal generated
by the 8-bit timer/counter. Transmission frequency can be modified by setting the appropriate bits in the SIO
mode register.
1-6
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
BIT SEQUENTIAL CARRIER
The bit sequential carrier (BSC) is a 16-bit register that can be manipulated using 1-, 4-, and 8-bit instructions.
Using 1-bit indirect addressing, addresses and bit locations can be specified sequentially. In this way, programs
can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value
of the L register. BSC data can also be manipulated using direct addressing.
COMPARATOR
The S3C70F2/C70F4 contains a 4-channel comparator which can be multiplexed to normal input port.
— Conversion time: 15.2 µs, 121.6 µs at 4.19 MHz
— Two operation modes:
Three channels for analog input and one channel for external reference voltage input
Four channels for analog input and internal reference voltage level
— 16-level internal reference voltage generator
— 150 mV accuracy for input voltage level difference detection (maximum)
— Comparator enable and disable
The comparison results are read from the 4-bit CMPREG register after the specified conversion time.
1-7
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
BLOCK DIAGRAM
Basic Timer
Watch Timer
X
X
RESET
IN
OUT
8-Bit
Timer/Counter
P0.0/CLO
P0.1/TIO
P0.2/INT1
I/O Port 0
Interrupt
Control
Block
Stack
Pointer
Clock
P3.0/TCL0
P3.1/TCLO0
P3.2/CLO
Serial I/O Port
Input Port 1
I/O Port 3
Program
Counter
Internal
Interrupts
P0.0/SCK
P0.1/SO
P0.2/SI
I/O Port 4
I/O Port 5
P4.0 - P4.3
P5.0 - P5.3
P2.0/KS0/CIN0
P2.1/KS1/CIN1
P2.2/KS2/CIN2
P2.3/KS3/CIN3
Program
Status Word
Instruction Decoder
Input Port 2
Comparator
Arithmetic
and
Logic Unit
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
Flags
I/O Port 6
512 x 4-Bit
Data
Memory
Program Memory
KS57C01502: 2 KByte
KS57C01504: 4 KByte
Figure 1-1. S3C70F2/C70F4 Simplified Block Diagram
1-8
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
PIN ASSIGNMENTS
VSS
Xout
Xin
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
VDD
P6.3/BUZ
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P3.2/CLO
P3.1/TCLO0
TEST
P1.0/INT0
P1.1/INT1
RESET
P0.0/SCK
P0.1./SO
P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
S3C70F2
S3C70F4
(Top View)
9
10
11
12
13
14
15
30-SDIP
VSS
Xout
Xin
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P6.3/BUZ
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
NC
P3.2/CLO
P3.1/TCLO0
TEST
P1.0/INT0
P1.1/INT1
RESET
S3C70F2
S3C70F4
(Top View)
NC
P0.0/SCK
P0.1./SO
P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
9
10
11
12
13
14
15
16
30-SDIP
Figure 1-2. S3C70F2/C70F4 Pin Assignment Diagram
1-9
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
PIN DESCRIPTIONS
Table 1-1. S3C70F2/C70F4 Pin Descriptions
Description
Pin Name
Pin
Number
Share Pin
Type
P0.0
P0.1
P0.2
I/O
3-bit I/O port. 1-bit or 3-bit read/write and test are
possible. Pull-up resistors are assignable to input pins by
software and are automatically disabled for output pins.
Pins are individually configurable as input or output.
8(9)
9(10)
10(11)
SCK
SO
SI
P1.0
P1.1
I
I
2-bit input port. 1-bit or 2-bit read and test are possible.
Pull-up resistors are assignable by software.
5(5)
6(6)
INT0
INT1
P2.0–P2.3
4-bit input port. 1-bit or 4-bit read and test are possible.
11-14
CIN0–CIN3
(12-15)
P3.0
P3.1
P3.2
I/O
Same as port 0
15(16)
16(17)
17(18)
TCL0
TCLO0
CLO
P4.0–P4.3
P5.0–P5.3
I/O
I/O
4-bit I/O ports. 1-, 4-, or 8-bit read/write and test are
possible. Pins are individually configurable as input or
output. 4-bit pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. The N-channel open-drain or push-pull output can
be selected by software (1-bit unit)
18-21(20-23)
22-25(24-27)
–
P6.0
P6.1
P6.2
P6.3
4-bit I/O port.
26(28)
27(29)
28(30)
29(31)
KS0
KS1
KS2
BUZ
1-bit or 4-bit read/write and test are possible.
Pull-up resistors are assignable to input pins by software
and are automatically disabled for output pins. Pins are
individually configurable as input or output.
INT0
INT1
I
I
I
External interrupts with detection of rising and falling
edges
5(5)
6(6)
P1.0
P1.1
External interrupts with detection of rising or falling
edges
CIN0–CIN3
4-channel comparator input.
11-14(12-15)
P2.0–P2.3
CIN0–CIN2: comparator input only.
CIN3: comparator input or external reference input
I/O
Serial interface clock signal
P0.0
SCK
SO
8(9)
I/O
I/O
I/O
I/O
I/O
I/O
Serial data output
9(10)
P0.1
P0.2
P3.0
P3.1
P3.2
P6.3
SI
Serial data input
10(11)
15(16)
16(17)
17(18)
29(31)
TCL0
TCLO0
CLO
BUZ
External clock input for timer/counter
Timer/counter clock output
CPU clock output
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at 4.19
MHz for buzzer sound
NOTE: Pn numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
1-10
S3C70F2/C70F4/P70F4
PRODUCT OVERVIEW
Table 1-1. S3C70F2/C70F4 Pin Descriptions (Continued)
Description
Pin Name
Pin
Type
Number
26-28(28-30)
Share Pin
Quasi-interrupt input with falling edge detection
P6.0–P6.2
V
—
—
I
Main power supply
Ground
30(32)
1(1)
—
—
—
—
—
DD
V
SS
Reset signal
7(7)
RESET
Test signal input (must be connected to V
)
SS
TEST
I
4(4)
X , X
in out
—
Crystal or ceramic oscillator signal for system clock
3,2(3,2)
NOTE: Pin numbers shown in parentheses '( )' are for 32-pin SOP package; other pin numbers are for the 30-pin SDIP.
Table 1-2. Overview of S3C70F2/C70F4 Pin Data
SDIP Pin
Numbers
Pin
Names
Share
Pins
I/O
Type
Reset
Value
Circuit
Type
V
1
2,3
4
¾
¾
¾
I
¾
¾
¾
¾
SS
Xout, Xin
TEST
¾
¾
INT0, INT1
¾
¾
¾
5,6
7
P1.0, P1.1
I
Input
¾
A-3
B
I
RESET
8-10
11-14
15-17
P0.0 - P0.2
I/O
I
Input
Input
Input
D-1
SCK, SO, SI
F-1, F-2 (note)
D-1
P2.0 - P2.3
P3.0 - P3.2
CIN0 - CIN3
TCL0, TCLO0,
CLO
I/O
18-21
22-25
26-29
P4.0 - P4.3
P5.0 - P5.3
P6.0 - P6.3
I/O
I/O
I/O
Input
Input
Input
E
E
¾
¾
KS0, KS1, KS2,
BUZ
D-1
V
DD
30
¾
¾
¾
¾
NOTE: I/O circuit type F-2 is implemented for P2.3 only.
1-11
PRODUCT OVERVIEW
S3C70F2/C70F4/P70F4
PIN CIRCUIT DIAGRAMS
VDD
PULL-UP
VDD
RESISTOR
P-CHANNEL
IN
IN
-
N CHANNEL
SCHMITT TRIGGER
Figure 1-5. Pin Circuit Type B
Figure 1-3. Pin Circuit Type A
VDD
VDD
PULL-UP
RESISTOR
-
P CHANNEL
DATA
RESISTOR
ENABLE
OUT
P-CHANNEL
IN
-
N CHANNEL
OUTPUT
DISABLE
SCHMITT TRIGGER
Figure 1-6. Pin Circuit Type C
Figure 1-4. Pin Circuit Type A-3
1-12
KS57C01502/C01504/P01504
PRODUCT OVERVIEW
VDD
PULL-UP
RESISTOR
RESISTOR
ENABLE
DIGITAL INPUT
ANALOG INPUT
-
P CHANNEL
DATA
CIRCUIT
TYPE 4
I/O
OUTPUT
DISABLE
SCHMITT TRIGER
Figure 1-9. Pin Circuit Type F-1
Figure 1-7. Pin Circuit Type D-1
VDD
PNE
PULL-UP
RESISTOR
DIGITAL INPUT
ANALOG INPUT
VDD
PULL-UP
RESISTOR
ENABLE
DATA
P-CHANNEL
I/O
OUTPUT
DISABLE
N-CHANNEL
EXTERNAL V
REF
Figure 1-8. Pin Circuit Type E
Figure 1-10. Pin Circuit Type F-2
1-13
S3C70F2/C70F4/P70F4
ADDRESS SPACES
2
ADDRESS SPACES
PROGRAM MEMORY (ROM)
OVERVIEW
ROM maps for S3C70F2/C70F4 devices are mask programmable at the factory. In its standard configuration, the
device's 4096 ´ 8-bit program memory has four areas that are directly addressable by the program counter (PC):
— 16-byte area for vector addresses
— 16-byte general-purpose area
— 96-byte instruction reference area
— 1920-byte general-purpose area: S3C70F2
— 3968-byte general-purpose area: S3C70F4
General-Purpose Memory
Two program memory areas are allocated for general-purpose use: One area is 16 bytes and the other is 1920
bytes (S3C70F2) or 3968 bytes (S3C70F4).
Vector Addresses
You use the 16-byte vector address area to store the vector addresses required to execute system resets and
interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the
enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the
corresponding service routines. The 16-byte area can be used alternately as general-purpose ROM.
REF Instructions
Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. Using REF
instructions, you can reduce the byte size of instruction operands. REF can refer either one 2-byte, two 1-byte
and 3-byte instructions stored in the look-up table. Unused look-up table addresses can be used as general-
purpose ROM.
Table 2-1. Program Memory Address Ranges
ROM Area Function
Vector address area
Address Ranges
0000H–000FH
0010H–001FH
0020H–007FH
Area Size (in Bytes)
16
16
96
General-purpose program memory
REF instruction look-up table area
General-purpose program memory
0080H–07FFH
0080H–0FFFH
1920 (S3C70F2)
3968 (S3C70F4)
2-1
ADDRESS SPACES
S3C70F2/C70F4/P70F4
GENERAL-PURPOSE MEMORY AREAS
The 16-byte area at ROM locations 0010H–001FH and the 3968-byte area at ROM locations 0080H–0FFFH are
used as general-purpose program memory.
You can also use vacant locations in the vector address area and REF instruction look-up table areas as general-
purpose program memory. But please be careful not to overwrite live data when writing programs that use
special-purpose areas of the ROM.
VECTOR ADDRESS AREA
Use the 16-byte vector address area of the ROM to store the vector addresses for executing system resets and
interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable mem-
ory bank (EMB) and enable register bank (ERB) flag values that are needed to set EMB and ERB's initial values
for the service routines. A 16-byte vector address is organized as follows:
EMB
PC7
ERB
PC6
0
0
PC11
PC3
PC10
PC2
PC9
PC1
PC8
PC0
PC5
PC4
To set up the vector address area for specific programs, you use the instruction VENTn. The programming tips
on the next page explain how to do this.
2-2
S3C70F2/C70F4/P70F4
ADDRESS SPACES
0000H
Vector Address Area
(16 bytes)
7
6
5
4
3
2
1
0
000FH
0010H
0000H
0002H
0004H
0006H
0008H
000AH
RESET
INTB
INT0
General Purpose Area
(16 bytes)
001FH
0020H
Instruction Reference Area
(96 bytes)
007FH
0080H
INT1
S3C70F2
(1,920 Bytes)
General Purpose Area
General Purpose Area
INTS
INTT0
07FFH
0800H
S3C70F4
(3,968 Bytes)
07FFH
Figure 2-2. Vector Address Map
Figure 2-1. ROM Structure
2-3
ADDRESS SPACES
S3C70F2/C70F4/P70F4
+
PROGRAMMING TIP — Defining Vectored Interrupt Areas
The following examples show you several ways you can define the vectored interrupt and instruction reference
areas in program memory:
1.
When all vector interrupts are used:
ORG
0000H
;
VENT0
VENT1
VENT2
VENT3
VENT4
VENT5
1,0,RESET
0,0,INTB
0,0,INT0
0,0,INT1
0,0,INTS
0,0,INTT0
; EMB ¬ 1, ERB ¬ 0; Jump to RESET address
; EMB ¬ 0, ERB ¬ 0; Jump to INTB address
; EMB ¬ 0, ERB ¬ 0; Jump to INT0 address
; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address
; EMB ¬ 0, ERB ¬ 0; Jump to INTS address
; EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address
2.
;
When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt
locations must be skipped with the assembly instruction ORG so that jumps will address the correct
locations:
ORG
0000H
VENT0
VENT1
ORG
1,0,RESET
0,0,INTB
0006H
; EMB ¬ 1, ERB ¬ 0; Jump to RESET address
; EMB ¬ 0, ERB ¬ 0; Jump to INTB address;
; INT0 interrupt not used
VENT3
VENT4
0,0,INT1
0,0,INTS
; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address
; EMB ¬ 0, ERB ¬ 0; Jump to INTS address
;
ORG
0010H
; INTT0 interrupt not used
3.
If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is
not written by a ORG instruction as in Example 2, a CPU malfunction will occur:
ORG
0000H
;
VENT0
VENT1
VENT3
VENT4
VENT5
1,0,RESET
0,0,INTB
0,0,INT1
0,0,INTS
0,0,INTT0
; EMB ¬ 1, ERB ¬ 0; Jump to RESET address
; EMB ¬ 0, ERB ¬ 0; Jump to INTB address
; EMB ¬ 0, ERB ¬ 0; Jump to INT1 address
; EMB ¬ 0, ERB ¬ 0; Jump to INTS address
; EMB ¬ 0, ERB ¬ 0; Jump to INTT0 address
;
;
;
ORG
0010H
General-purpose ROM area
In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but
VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU
malfunction to occur.
2-4
S3C70F2/C70F4/P70F4
ADDRESS SPACES
INSTRUCTION REFERENCE AREA
Using 1-byte REF instructions, you can easily refer instructions with larger byte sizes that are stored in addresses
0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or look-up
table. Locations in the REF look-up table may contain two 1-byte instructions, a one 2-byte instruction, or one 3-
byte instructions such as a JP or CALL. The starting address of the instruction you are referring must always be
an even number. To refer a JP or CALL instruction, it must be written to the reference area in a two-byte format:
for JP, this format is TJP; for CALL, it is TCALL. In summary, there are three ways to the REF instruction:
— Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions,
— Branching to any location by referring a branch instruction stored in the look-up table,
— Calling subroutines at any location by referring a call instruction stored in the look-up table.
+
PROGRAMMING TIP — Using the REF Look-Up Table
Here is one example of how to use the REF instruction look-up table:
ORG
0020H
;
JMAIN
KEYCK
WATCH
INCHL
TJP
MAIN
KEYFG
CLOCK
@HL,A
INCS
•
; 0, MAIN
BTSF
TCALL
LD
; 1, KEYFG CHECK
; 2, CALL CLOCK
; 3, (HL) ¬ A
HL
•
•
ABC
LD
EA,#00H
ORG 0080
; 47, EA ¬ #00H
;
MAIN
NOP
NOP
•
•
•
REF KEYCK
REF JMAIN
REF WATCH
REF INCHL
; BTSF KEYFG (1-byte instruction)
; KEYFG = 1, jump to MAIN (1-byte instruction)
; KEYFG = 0, CALL CLOCK (1-byte instruction)
; LD @HL,A
; INCS HL
REF ABC
; LD EA,#00H (1-byte instruction)
•
•
•
2-5
S3C70F2/C70F4/P70F4
ADDRESS SPACES
DATA MEMORY (RAM)
OVERVIEW
In its standard configuration, the 512 ´ 4-bit data memory has five areas:
— 32 ´ 4-bit working register area
— 224 ´ 4-bit general-purpose area in bank 0 (also used as stack area)
— 256 ´ 4-bit general-purpose area in bank 1
— 128 ´ 4-bit area for memory-mapped I/O addresses
To simplify referring, the data memory area has three memory banks — bank 0, bank 1 and bank 15. You use
the select memory bank instruction (SMB) to select the bank you want to use as working data memory. Data
stored in RAM locations are 1-, 4-, and 8-bit addressable. Initialization values for the data memory area are not
defined by hardware and must therefore be initialized by program software following RESET. When RESET
signal is generated in power-down mode, the data memory contents are maintained.
000H
Working Registers
(32 x 4 Bits)
01FH
020H
Bank 0
Bank 1
General Purpose
Register and Stack Area
(224 x 4 Bits)
0FFH
100H
General Purpose
Registers
(256 x 4 Bits)
1FFH
F80H
~
~
Peripheral
Hardware
Registers
Bank 15
FFFH
Figure 2-3. Data Memory (RAM) Map
2-7
ADDRESS SPACES
S3C70F2/C70F4/P70F4
Memory Banks 0, 1 and 15
Bank 0
(000H–0FFH)
The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers;
the next 224 nibbles (020H–0FFH) can be used both as stack area and as
general-purpose data memory. Use the stack area for implementing subroutine
calls and returns, and for interrupt processing.
Bank 1
(100H–1FFH)
(F80H–FFFH)
This area is used as general-purpose data memory.
Bank 15
The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed
RAM locations for each peripheral hardware register are mapped into this area.
Data Memory Addressing Modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0 or 15. When the
EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or
indirect addressing is used. With direct addressing, you can access locations 000H–07FH of bank 0, bank 1 and
bank 15. With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic
one, all three data memory banks can be accessed according to the current SMB value.
For 8-bit addressing, two 4-bit registers are addressed as a register pair. When using 8-bit instructions to address
RAM locations, remember to use the even-numbered register address as the instruction operand.
Working Registers
The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2,
and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable.
Register A is used as a 4-bit accumulator and register pair EA is an 8-bit extended accumulator. The carry flag
bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for
indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable
to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.
Bit Sequential Carrier (BSC)
The bit sequential carrier (BSC) is a 16-bit general register mapped to RAM addresses FC0H–FC3H that can be
manipulated by 1-, 4-, and 8-bit RAM control instructions. RESET clears all bit values to logic zero.
You can specify addresses and bit locations sequentially using a 1-bit indirect addressing instruction. In this way,
a program can process 16-bit data by moving the bit location sequentially, incrementing or decrementing the
value of the L register. BSC data can also be manipulated by direct addressing. For 8-bit manipulations, you
must address the upper and lower 8 bits separately.
2-8
S3C70F2/C70F4/P70F4
Addresses
ADDRESS SPACES
Table 2-2. Data Memory Organization and Addressing
Register Areas
Bank
EMB Value
SMB Value
000H–01FH
020H–0FFH
100H–1FFH
F80H–FFFH
Working registers
0
0, 1
0
Stack and general-purpose registers
General-purpose registers
1
1
1
I/O-mapped hardware registers
15
0, 1
15
+
PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1
Clear bank 0 of the data memory area:
RAMCLR
BITS
SMB
LD
LD
LD
EMB
0
HL,#10H
A,#0H
@HL,A
HL
RMCL0
;
; RAM (010H–0FFH) clear
INCS
JR
RMCL0
2-9
ADDRESS SPACES
S3C70F2/C70F4/P70F4
WORKING REGISTERS
Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store
intermediate results during program execution, as well as pointer values used for indirect addressing. Unused
registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-
bit units or, using paired registers, as 8-bit units.
000H
001H
002H
A
E
L
003H
H
X
Working
Register
Bank 0
004H
005H
006H
007H
008H
W
Z
Data
Memory
Bank 0
Y
Register
Bank 1
A ...Y
A ...Y
A ...Y
00FH
010H
Register
Bank 2
017H
018H
Register
Bank 3
01FH
Figure 2-4. Working Register Map
2-10
S3C70F2/C70F4/P70F4
ADDRESS SPACES
Working Register Banks
For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2,
and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection
instruction (SRBn) and by setting the status of the register bank enable flag (ERB).
Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou-
tines. Following this convention helps to prevent possible data corruption during program execution due to con-
tention in register bank addressing.
Table 2-3. Working Register Organization and Addressing
ERB Setting
SRB Settings
Selected Register Bank
3
2
1
x
0
0
1
1
0
x
0
1
0
1
0
1
0
0
Always set to bank 0
Bank 0
0
0
Bank 1
Bank 2
Bank 3
NOTE: 'x' means don't care.
Paired Working Registers
Each of the register banks is subdivided into eight 4-bit registers. These registers are named Y, Z, W, X, H, L, E
and A. You can manipulate them individually using 4-bit instructions, or as register pairs for 8-bit data manipula-
tion.
The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z
always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit
registers or four 8-bit double registers in each of the four working register banks.
(MSB)
(LSB)
(MSB)
(LSB)
Y
W
H
E
Z
X
L
A
Figure 2-5. Register Pair Configuration
2-11
ADDRESS SPACES
S3C70F2/C70F4/P70F4
Special-Purpose Working Registers
You can use register A as a 4-bit accumulator and double register EA as an 8-bit accumulator. You can use the
carry flag as a 1-bit accumulator.
8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register
serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working reg-
isters as program loop counters by letting you transfer a value and increment or decrement L register value using
a single instruction.
C
1-Bit Accumulator
4-Bit Accumulator
8-Bit Accumulator
A
EA
Figure 2-6. 1-Bit, 4-Bit, and 8-Bit Accumulator
Recommendation for Multiple Interrupt Processing
If more than four interrupts are being processed at one time, you can avoid possible loss of working register data
by using the PUSH RR instruction to save register contents to the stack before the service routines are executed
in the same register bank. When the routines have executed successfully, you can restore the register contents
from the stack to working memory using the POP instruction.
2-12
S3C70F2/C70F4/P70F4
ADDRESS SPACES
+
PROGRAMMING TIP — Selecting Your Working Register Area
The following examples show the correct programming method for selecting working register area:
1.
When ERB = "0":
1,0,INT0
VENT2
;
; EMB ¬ 1, ERB ¬ 0, Jump to INT0 address
INT0
PUSH
SRB
PUSH
PUSH
PUSH
PUSH
SMB
LD
LD
LD
INCS
LD
LD
POP
POP
POP
POP
POP
IRET
SB
2
HL
WX
YZ
EA
0
EA,#00H
80H,EA
HL,#40H
HL
WX,EA
YZ,EA
EA
YZ
WX
HL
SB
; PUSH current SMB, SRB
; Non-essential instruction, since ERB = "0"
; PUSH HL register to stack
; PUSH WX register to stack
; PUSH YZ register to stack
; PUSH EA register to stack
; POP EA register from stack
; POP YZ register from stack
; POP WX register from stack
; POP HL register from stack
; POP current SMB, SRB
The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an
interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and
SRB values, as shown in Example 2 below.
2.
VENT2
;
When ERB = "1":
1,1,INT0
; EMB ¬ 1, ERB ¬ 1, Jump to INT0 address
INT0
PUSH
SRB
SMB
LD
LD
LD
INCS
LD
LD
POP
IRET
SB
2
0
EA,#00H
80H,EA
HL,#40H
HL
WX,EA
YZ,EA
SB
; Store current SMB, SRB
; Select register bank 2
; Restore SMB, SRB
;
2-13
ADDRESS SPACES
S3C70F2/C70F4/P70F4
STACK OPERATIONS
STACK POINTER (SP)
The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data
memory set aside for temporary storage of data and addresses. The SP is mapped to RAM addresses
F80H-F81H, and can be read or written by 8-bit control instructions. When addressing the SP, bit 0 must always
remain cleared to logic zero.
F80H
F81H
SP3
SP7
SP2
SP6
SP1
SP5
"0"
SP4
There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack
(pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the
last data to be written to the stack.
The program counter contents and program status word are stored in the stack area prior to the execution of a
CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out)
type. The stack area is located in general-purpose data memory bank 0.
During an interrupt or a subroutine, the PC value and the PSW values are saved to the stack area. When the
routine has completed, the stack pointer is referrred to restore the PC and PSW, and the next instruction is
executed.
The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the en-
able memory bank (EMB) flag and the select memory bank (SMB) flag.
Since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack
pointer by program code to location 00H. This sets the first register of the stack area to 0FFH.
NOTE
A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or
interrupt routines are used continuously, the stack area should be set in accordance with the maximum
number of subroutine levels. To do this, estimate the number of nibbles that will be used for the
subroutines or interrupts and set the stack area correspondingly.
Although you may use general-purpose register areas for stack operations, be careful to avoid data loss due to
simultaneous use of the same register(s).
+
PROGRAMMING TIP — Initializing the Stack Pointer
To initialize the stack pointer (SP):
1. When EMB = "1":
SMB
LD
LD
15
EA,#00H
SP,EA
; Select memory bank 15
; Bit 0 of accumulator A is always cleared to "0"
; Stack area initial address (0FFH) ¬ (SP) – 1
2. When EMB = "0":
LD
LD
EA,#00H
SP,EA
; Memory addressing area (00H–7FH, F80H–FFFH)
2-14
S3C70F2/C70F4/P70F4
ADDRESS SPACES
PUSH OPERATIONS
Three kinds of push operations reference the stack pointer (SP) to write data from the source register to the
stack: PUSH instructions, CALL instructions, and interrupts. In each case, the SP is decremented by a number
determined by the type of push operation and then points to the next available stack location.
PUSH Instructions
A PUSH instruction refers the SP to write two 4-bit data nibbles from the PC to the stack. Two 4-bit stack
addresses are referred by the stack pointer: one for the upper register value and another for the lower register.
After the PUSH has executed, the SP is decremented by two and points to the next available stack location.
CALL Instructions
When a subroutine call is issued, the CALL instruction refers the SP to write the PC's contents to six 4-bit stack
locations. Current values for the enable memory bank (EMB) flag and the enable register bank (ERB) flag are
also pushed to the stack. After the CALL has executed, the SP is decremented by six and points to the next
available stack location. Since six 4-bit stack locations are used per CALL, you may nest subroutine calls up to
the number of levels permitted in the stack.
Interrupt Routines
An interrupt routine refers the SP to push the contents of the PC, as well as current values for the program status
word (PSW) to the stack. Six 4-bit stack locations are used to store this data. After the interrupt has executed,
the SP is decremented by six and points to the next available stack location. During an interrupt sequence,
subroutines may be nested up to the number of levels which are permitted in the stack area.
INTERRUPT
PUSH
(After PUSH, SP
CALL
(After CALL, SP
(When INT is acknowledged,
SP - 2)
SP - 6)
SP
SP - 6)
SP - 6
SP - 5
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC 11-PC 8
PC 11-PC 8
SP - 6
SP - 5
SP - 4
SP - 3
SP - 2
SP - 1
SP
0
0
0
0
0
0
0
0
PC3 - PC0
PC7 - PC4
PC3 - PC0
PC7 - PC4
IS1
C
IS0 EMB ERB
0
0
0
0
EMB ERB
LOWER REGISTER
UPPER REGISTER
SP - 2
SP - 1
SP
PSW
SC2 SC1 SC0
0
0
Figure 2-7. Push-Type Stack Operations
2-15
ADDRESS SPACES
POP OPERATIONS
S3C70F2/C70F4/P70F4
For each push operation there is a corresponding pop operation to write data from the stack back to the source
register or registers: for the PUSH instruction it is the POP instruction; for CALL, the instruction RET or SRET;
for interrupts, the instruction IRET. When a pop operation occurs, the SP is incremented by a number determined
by the type of operation and points to the next free stack location.
POP Instructions
A POP instruction refers the SP to write data stored in two 4-bit stack locations back to the register pairs and SB
register. The value for the lower 4-bit register is popped first, followed by the value for the upper 4-bit register.
After the POP has executed, the SP is incremented by two and points to the next free stack location.
RET and SRET Instructions
The end of a subroutine call is signaled by the return instruction, RET or SRET. The RET or SRET uses the SP
to refer the six 4-bit stack locations used for the CALL and to write this data back to the PC, the EMB, and ERB.
After the RET or SRET has executed, the SP is incremented by six and points to the next free stack location.
IRET Instructions
The end of an interrupt sequence is signaled by the instruction IRET. IRET refers the SP to locate the six 4-bit
stack addresses used for the interrupt and to write this data back to the PC and the PSW. After the IRET has
executed, the SP is incremented by six and points to the next free stack location.
POP
RET OR SRET
(SP SP + 6)
IRET
(SP
SP + 2)
(SP
SP + 6)
PC11-PC8
PC11-PC8
SP
LOWER REGISTER
UPPER REGISTER
SP
SP
0
0
0
0
0
0
0
0
SP + 1
SP + 2
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
PC3 - PC0
PC7 - PC4
PC3 - PC0
PC7 - PC4
0
0
0
0
EMB ERB
IS1
C
IS0 EMB ERB
PSW
SC2 SC1 SC0
0
0
Figure 2-8. Pop-Type Stack Operations
2-16
S3C70F2/C70F4/P70F4
ADDRESS SPACES
BIT SEQUENTIAL CARRIER (BSC)
The bit sequential carrier (BSC) is a 16-bit register that is mapped to RAM addresses FC0H–FC3H. You can
manipulate the BSC register using 1-, 4-, and 8-bit RAM control instructions. RESET clears all BSC bit values to
logic zero.
Using the BSC, you can specify addresses and bit locations sequentially using 1-bit indirect addressing
(memb.@L). Bit addressing is independent of the current EMB value. In this way, programs can process 16-bit
data by moving the bit location sequentially and then incrementing or decrementing the value of the L register.
BSC data can also be manipulated using direct addressing. For 8-bit manipulations, specify the 4-bit register
names BSC0 and BSC2 and manipulate the upper and lower 8 bits manipulated separately.
If the values of the L register are 0H at BSC0.@L, the address and bit location assignment is FC0H.0. If the L
register content is FH at BSC0.@L, the address and bit location assignment is FC3H.3.
Table 2-4. BSC Register Organization
Name
BSC0
BSC1
BSC2
BSC3
Address
FC0H
Bit 3
Bit 2
Bit 1
Bit 0
BSC0.3
BSC1.3
BSC2.3
BSC3.3
BSC0.2
BSC1.2
BSC2.2
BSC3.2
BSC0.1
BSC1.1
BSC2.1
BSC3.1
BSC0.0
BSC1.0
BSC2.0
BSC3.0
FC1H
FC2H
FC3H
+
PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data
To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin:
BITS
SMB
LD
LD
LD
LD
SMB
LD
LDB
LDB
INCS
JR
EMB
15
EA,#37H
BSC0,EA
EA,#59H
BSC2,EA
0
L,#0H
C,BSC0.@L
P3.0,C
L
;
; BSC0 ¬ A, BSC1 ¬ E
;
; BSC2 ¬ A, BSC3 ¬ E
;
;
AGN
; P3.0 ¬ C
AGN
RET
2-17
ADDRESS SPACES
S3C70F2/C70F4/P70F4
PROGRAM COUNTER (PC)
A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Whenever a
reset operation or an interrupt occurs, bits PC11 through PC0 are set to the vector address. Bit PC12–PC13 is
reserved to support future expansion of the device's ROM size.
Usually, the PC is incremented by the number of bytes of the instruction being fetched. One exception is the 1-
byte REF instruction which is used to reference instructions stored in the ROM.
PROGRAM STATUS WORD (PSW)
The program status word (PSW) is an 8-bit word, mapped to RAM locations FB0H–FB1H, that defines system
status and program execution status and which permits an interrupted process to resume operation after an inter-
rupt request has been serviced. PSW values are mapped as follows:
FB0H
FB1H
IS1
C
IS0
EMB
SC1
ERB
SC0
SC2
The PSW can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the specific
bit or bits being addressed. The PSW can be addressed during program execution regardless of the current
value of the enable memory bank (EMB) flag.
Part or all of the PSW is saved to stack prior to execution of a subroutine call or hardware interrupt. After the in-
terrupt has been processed, the PSW values are popped from the stack back to the PSW address.
When a RESET is generated, the EMB and ERB values are set according to the RESET vector address, and the
carry flag is left undefined (or the current value is retained). PSW bits IS0, IS1, SC0, SC1, and SC2 are all
cleared to logic zero.
Table 2-5. Program Status Word Bit Descriptions
PSW Bit Identifier
IS1, IS0
Description
Interrupt status flags
Enable memory bank flag
Enable register bank flag
Carry flag
Bit Addressing
Read/Write
R/W
1, 4
1
EMB
R/W
ERB
1
R/W
C
1
R/W
SC2, SC1, SC0
Program skip flags
8
R
2-18
S3C70F2/C70F4/P70F4
ADDRESS SPACES
INTERRUPT STATUS FLAGS (IS0, IS1)
PSW bits IS0 and IS1 contain the current interrupt execution status values. They are mapped to RAM bit loca-
tions FB0H.2 and FB0H.3, respectively. You can manipulate IS0 and IS1 flags directly using 1-bit RAM control
instructions
By manipulating interrupt status flags in conjunction with the interrupt priority register (IPR), you can process
multiple interrupts by anticipating the next interrupt in an execution sequence. The interrupt priority control circuit
determines the IS0 and IS1 settings in order to control multiple interrupt processing. When both interrupt status
flags are set to "0", all interrupts are allowed. The priority with which interrupts are processed is then determined
by the IPR.
When an interrupt occurs, IS0 and IS1 are pushed to the stack as part of the PSW and are automatically
incremented to the next higher priority level. Then, when the interrupt service routine ends with an IRET instruc-
tion, IS0 and IS1 values are restored to the PSW. Table 2–6 shows the effects of IS0 and IS1 flag settings.
Table 2-6. Interrupt Status Flag Bit Settings
IS1
Value
IS0
Value
Status of Currently
Executing Process
Effect of IS0 and IS1 Settings
on Interrupt Request Control
0
0
0
1
0
1
All interrupt requests are serviced
Only high-priority interrupt(s) as determined in the
interrupt priority register (IPR) are serviced
1
1
0
1
2
No more interrupt requests are serviced
—
Not applicable; these bit settings are undefined
Since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter-
rupt processing status. Before interrupt status flags can be addressed, however, you must first execute a DI in-
struction to inhibit additional interrupt routines. When the bit manipulation has been completed, execute an EI in-
struction to re-enable interrupt processing.
+
PROGRAMMING TIP — Setting ISx Flags for Interrupt Processing
The following instruction sequence shows how to use the IS0 and IS1 flags to control interrupt processing:
INTB
DI
; Disable interrupt
BITR
BITS
EI
IS1
IS0
; IS1 ¬ 0
; Allow interrupts according to IPR priority level
; Enable interrupt
2-19
ADDRESS SPACES
EMB FLAG (EMB)
S3C70F2/C70F4/P70F4
The enable memory bank flag EMB is mapped to registers FB0H–FB1H in bank 15 of the RAM. The EMB flag
occupies bit location 1 in register FB0H.
The EMB flag is used to allocate specific address locations in the RAM by modifying the upper 4 bits of 12-bit
data memory addresses. In this way, it controls the addressing mode for data memory banks 0, bank 1 or 15.
When the EMB flag is "0", the data memory address space is restricted to bank 15 and addresses 000H–07FH of
memory bank 0, regardless of the SMB register contents. When the EMB flag is set to "1", you can access
general-purpose areas of bank 0, bank 1, and bank 15 by using the appropriate SMB value.
+
PROGRAMMING TIP — Using the EMB Flag to Select Memory Banks
EMB flag settings for memory bank selection:
1.
When EMB = "0":
SMB
LD
LD
SMB
LD
LD
0
; Non-essential instruction, since EMB = "0"
; (F90H) ¬ A, bank 15 is selected
; (034H) ¬ A, bank 0 is selected
; Non-essential instruction, since EMB = "0"
; (020H) ¬ A, bank 0 is selected
90H,A
34H,A
15
20H,A
90H,A
; (F90H) ¬ A, bank 15 is selected
;
2.
When EMB = "1":
SMB
LD
LD
SMB
LD
LD
0
; Select memory bank 0
90H,A
34H,A
15
20H,A
90H,A
; (090H) ¬ A, bank 0 is selected
; (034H) ¬ A, bank 0 is selected
; Select memory bank 15
; Program error, but assembler does not detect it
; (F90H) ¬ A, bank 15 is selected
;
2-20
S3C70F2/C70F4/P70F4
ERB FLAG (ERB)
ADDRESS SPACES
The 1-bit register bank enable flag (ERB) determines the range of addressable working register area. When the
ERB flag is "1", you can select the working register area from register banks 0 to 3 according to the register bank
selection register (SRB). When the ERB flag is "0", you select register bank 0 as the working register area,
regardless of the current value of the register bank selection register (SRB).
When an internal RESET is generated, bit 6 of program memory address 0000H is written to the ERB flag. This
automatically initializes the flag. When a vectored interrupt is generated, bit 6 of the respective vector address
table in program memory is written to the ERB flag, setting the correct flag status before the interrupt service
routine is executed.
During the interrupt routine, the ERB value is automatically pushed to the stack area along with the other PSW
bits. Afterwards, it is popped back to the FB0H.0 bit location. The initial ERB flag settings for each vectored inter-
rupt are defined using VENTn instructions.
+
PROGRAMMING TIP — Using the ERB Flag to Select Register Banks
ERB flag settings for register bank selection:
1.
When ERB = "0":
SRB
1
; Register bank 0 is selected (since ERB = "0", the
; SRB is configured to bank 0)
; Bank 0 EA ¬ #34H
; Bank 0 HL ¬ EA
; Register bank 0 is selected
; Bank 0 YZ ¬ EA
LD
LD
SRB
LD
SRB
LD
EA,#34H
HL,EA
2
YZ,EA
3
; Register bank 0 is selected
; Bank 0 WX ¬ EA
WX,EA
;
2.
When ERB = "1":
SRB
LD
LD
SRB
LD
SRB
LD
1
; Register bank 1 is selected
; Bank 1 EA ¬ #34H
EA,#34H
HL,EA
2
YZ,EA
3
; Bank 1 HL ¬ Bank 1 EA
; Register bank 2 is selected
; Bank 2 YZ ¬ BANK 2 EA
; Register bank 3 is selected
; Bank 3 WX ¬ Bank 3 EA
WX,EA
;
2-21
ADDRESS SPACES
S3C70F2/C70F4/P70F4
SKIP CONDITION FLAGS (SC2, SC1, SC0)
The skip condition flags SC2, SC1, and SC0 indicate the current program skip conditions and are set and reset
automatically during program execution. These flags are mapped to RAM bit locations FB1H.0, FB1H.1, and
FB1H.2 of the PSW.
Skip condition flags can only be addressed by 8-bit read instructions. Direct manipulation of the SC2, SC1, and
SC0 bits is not allowed.
CARRY FLAG (C)
The carry flag is mapped to bit location FB1H.3 in the PSW. It is used to save the result of an overflow or borrow
when executing arithmetic instructions involving a carry (ADC, SBC). The carry flag can also be used as a 1-bit
accumulator for performing Boolean operations involving bit-addressed data memory.
If an overflow or borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), the carry
flag is set to "1". Otherwise, its value is "0". When a RESET occurs, the current value of the carry flag is retained
during power-down mode, but when normal operating mode resumes, its value is undefined.
The carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other
bits in the PSW. Only the ADC and SBC instructions, and the instructions listed in Table 2–7, affect the carry
flag.
Table 2-7. Valid Carry Flag Manipulation Instructions
Operation Type
Instructions
Carry Flag Manipulation
Set carry flag to "1"
Direct manipulation
SCF
RCF
CCF
Clear carry flag to "0" (reset carry flag)
Invert carry flag value (complement carry flag)
Test carry and skip if C = "1"
BTST C
(1)
Bit transfer
Load carry flag value to the specified bit
Load contents of the specified bit to carry flag
Rotate right with carry flag
LDB (operand) ,C
(1)
LDB C,(operand)
Data transfer
RRC A
(1)
Boolean manipulation
AND the specified bit with contents of carry flag and save
the result to the carry flag
BAND C,(operand)
(1)
OR the specified bit with contents of carry flag and save
the result to the carry flag
BOR C,(operand)
BXOR C,(operand)
(1)
XOR the specified bit with contents of carry flag and save
the result to the carry flag
(2)
Interrupt routine
Save carry flag to stack with other PSW bits
INTn
Return from interrupt
IRET
Restore carry flag from stack with other PSW bits
NOTES:
1. The operand has three bit addressing formats: mema.a, memb.@L, and @H + DA.b.
2. INTn refers to the specific interrupt being executed and is not an instruction.
2-22
S3C70F2/C70F4/P70F4
ADDRESS SPACES
+
PROGRAMMING TIP — Using the Carry Flag as a 1-Bit Accumulator
1.
Set the carry flag to logic one:
SCF
LD
LD
; C ¬ 1
; EA ¬ #0C3H
; HL ¬ #0AAH
EA,#0C3H
HL,#0AAH
EA,HL
ADC
; EA ¬ #0C3H + #0AAH + #1H, C ¬ 1
2.
Logical-AND bit 3 of address 3FH with P3.3 and output the result to P5.0:
LD
H,#3H
; Set the upper four bits of the address to the H register
; value
LDB
BAND
LDB
C,@H+0FH.3
C,P3.3
P5.0,C
; C ¬ bit 3 of 3FH
; C ¬ C AND P3.3
; Output result from carry flag to P5.0
2-23
S3C70F2/C70F4/P70F4
ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW
The enable memory bank flag, EMB, controls the two addressing modes for data memory. When you enable the
EMB flag, you can address the entire RAM area. When you clear the EMB flag to logic zero, the addressable
RAM is restricted to specific areas.
The EMB flag works in connection with the select memory bank instruction, SMB n. You will recall that the SMB n
instruction is used to select RAM bank 0, bank 1 or 15. The SMB setting is always contained in the upper four
bits of a 12-bit RAM address. For this reason, both addressing modes (EMB = "0" and EMB = "1") apply
specifically to the memory bank indicated by the SMB instruction, and any restrictions to the addressable area
within banks 0, 1 or 15. Direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used.
In addition, there are several RAM locations that can always be addressed using specific addressing methods,
regardless of the current EMB flag setting.
Here are a few things to remember about addressing data memory areas:
— When you address peripheral hardware locations in bank 15, you can use the mnemonic for the memory-
mapped hardware component as the operand in place of the actual address location.
— Always use an even-numbered RAM address as the operand in 8-bit direct and indirect addressing.
— With direct addressing, use the RAM address as the instruction operand; with indirect addressing, the
insttruction specifies a register which contains the operand's address.
3-1
ADDRESSING MODES
S3C70F2/C70F4/P70F4
Addressing
Mode
DA
DA.b
@HL
@H+DA.b
@WX
@WL
mema.b memb.@L
RAM
Areas
EMB = 0 EMB = 1 EMB = 0 EMB = 1
X
X
X
000H
Working
Registers
01FH
020H
07FH
080H
Bank 0
(General
Registers
and Stack)
SMB = 0
SMB = 0
0FFH
100H
Bank 1:
(General
Registers )
SMB = 1
SMB = 1
1FFH
F80H
FB0H
FBFH
FC0H
Bank 15
(Peripheral
Hardware
Registers)
SMB = 15
SMB = 15
FF0H
FFFH
NOTES:
1. 'X' means don't care.
2. Blank columns indicate RAM areas that are not addressable, given the addressing method and
enable memory bank (EMB) flag setting shown in the column headers.
Figure 3-1. RAM Address Structure
3-2
S3C70F2/C70F4/P70F4
ADDRESSING MODES
EMB AND ERB INITIALIZATION VALUES
The EMB and ERB flag bits are set automatically by the values of the RESET vector address and the interrupt
vector address.
When a RESET is generated internally, bit 7 of program memory address 0000H is written to the EMB flag, ini-
tializing it automatically. When a vectored interrupt is generated, bit 7 of the respective vector address table is
written to the EMB. This automatically sets the EMB flag status for the interrupt service routine. When the
interrupt is serviced, the EMB value is automatically saved to stack and then restored when the interrupt routine
has completed.
At the beginning of a program, the initial EMB and ERB flag value for each vectored interrupt must be set by
using VENT instruction. The EMB and ERB can be set or reset by bit manipulation instructions (BITS, BITR)
despite the current SMB setting.
+
PROGRAMMING TIP — Initializing the EMB and ERB Flags
The following assembly instructions show how to initialize the EMB and ERB flag settings:
ORG
VENT0
VENT1
VENT2
VENT3
VENT4
VENT5
•
0000H
; ROM address assignment
1,0,RESET
0,1,INTB
0,1,INT0
0,1,INT1
0,1,INTS
0,1,INTT0
; EMB ¬ 1, ERB ¬ 0, branch RESET
; EMB ¬ 0, ERB ¬ 1, branch INTB
; EMB ¬ 0, ERB ¬ 1, branch INT0
; EMB ¬ 0, ERB ¬ 1, branch INT1
; EMB ¬ 0, ERB ¬ 1, branch INTS
; EMB ¬ 0, ERB ¬ 1, branch INTT0
•
•
BITR
EMB
RESET
3-3
ADDRESSING MODES
S3C70F2/C70F4/P70F4
ENABLE MEMORY BANK SETTINGS
EMB = "1"
When you set the enable memory bank flag, EMB, to logic one, you can address the data memory bank specified
by the select memory bank (SMB) value (0,1 or 15) using 1-, 4-, or 8-bit instructions. You can use both direct and
indirect addressing modes. The addressable RAM areas when the EMB flag is set to logic one are as follows:
If SMB = 0,
If SMB = 1
If SMB = 15,
000H–0FFH
100H–1FFH
F80H–FFFH
EMB = "0"
When the enable memory bank flag EMB is set to logic zero, the addressable area is defined independently of
the SMB value, and is restricted to specific locations depending on whether a direct or indirect address mode is
used.
If EMB = "0", the addressable area is restricted to locations 000H–07FH in bank 0 and to locations F80H–FFFH
in bank 15 for direct addressing. For indirect addressing, only locations 000H–0FFH in bank 0 are addressable,
regardless of SMB value.
To address the peripheral hardware register (bank 15) using indirect addressing, the EMB flag must first be set to
"1" and the SMB value to "15". When a RESET occurs, the EMB flag is set to the value contained in bit 7 of
ROM address 0000H.
EMB-Independent Addressing
You can address several areas of the data memory at any time, despite the status of the EMB flag. These ex-
ceptions are described in Table 3–1.
Table 3-1. RAM Addressing Not Affected by the EMB Value
Address
Addressing Method
Affected Hardware
Program Examples
LD A,@WX
000H–0FFH
4-bit indirect addressing using WX
and WL register pairs;
Not applicable
8-bit indirect addressing using SP
PUSH
POP
FB0H–FBFH
FF0H–FFFH
1-bit direct addressing
PSW,
IEx, IRQx, I/O
BITS EMB
BITR IE1
FC0H–FFFH
1-bit indirect addressing using the
L register
BSC,
I/O
BTST FC3H.@L
BAND C,P3.@L
3-4
S3C70F2/C70F4/P70F4
ADDRESSING MODES
SELECT BANK REGISTER (SB)
The select bank register (SB) is used to assign the memory bank and register bank. The 8-bit SB register consists
of the 4-bit select register bank register (SRB) and the 4-bit select memory bank register (SMB), as shown in
Figure 3-2.
SMB
SRB
0 SRB 1 SRB 0
SB
REGISTER
SMB 3 SMB 2 SMB 1 SMB 0
0
Figure 3-2. 4-Bit SMB and SRB Values in the SB Register
During interrupts and subroutine calls, SB register contents can be saved to stack in 8-bit units by the PUSH SB
instruction. You later restore the value to the SB using the POP SB instruction.
Select Register Bank (SRB) Instruction
The select register bank (SRB) value specifies which register bank is to be used as a working register bank. The
SRB value is set by the 'SRB n' instruction, where n = 0, 1, 2, 3. One of the four register banks is selected by the
combination of ERB flag status and the SRB value that you set using the 'SRB n' instruction. The current SRB
value is retained until another register is requested by program software.
PUSH SB and POP SB instructions are used to save and restore the contents of SRB during interrupts and
subroutine calls. RESET clears the 4-bit SRB value to logic zero.
Select Memory Bank (SMB) Instruction
To select one of the three available data memory banks, you must execute an SMB n instruction specifying the
number of the memory bank you want (0, 1 or 15). For example, the instruction 'SMB 1' selects bank 1 and
'SMB 15' selects bank 15. You must also remember to enable the memory bank you select by the appropriate
enable memory bank flag (EMB) setting.
The upper four bits of the 12-bit data memory address are stored in the SMB register. If the SMB value is not
specified by software (or if a RESET does not occur) the current value is retained. RESET clears the 4-bit SMB
value to logic zero.
PUSH SB and POP SB instructions save and restore the contents of the SMB register to and from the stack area
during interrupts and subroutine calls.
3-5
ADDRESSING MODES
S3C70F2/C70F4/P70F4
DIRECT AND INDIRECT ADDRESSING
You can directly address 1-bit, 4-bit, and 8-bit data stored in data memory locations using a specific register or bit
address as the instruction operand.
In indirect addressing the instruction specifies a specfic register pair which contain the address of the operand.
The KS57 instruction set supports 1-bit, 4-bit, and 8-bit indirect addressing. For 8-bit indirect addressing, an
even-numbered RAM address must always be used as the instruction operand, and the address register can be
HL, WX, or WL of the selected register bank.
1-BIT ADDRESSING
Table 3-2. 1-Bit Direct and Indirect RAM Addressing
Instruction
Notation
Addressing Mode
Description
EMB
Flag
Addressable
Area
Memory
Bank
Hardware I/O
Mapping
Setting
000H–07FH
F80H–FFFH
Bank 0
Bank15
—
DA.b
Direct: bit is indicated by the
RAM address (DA), memory
bank selection, and specified
bit number (b).
0
All 1-bit
addressable
peripherals
(SMB = 15)
1
x
000H–FFFH
SMB = 0, 1, 15
Bank 15
mema.b
Direct: bit is indicated by ad-
dressable area (mema) and
bit number (b).
FB0H–FBFH
FF0H–FFFH
IS0, IS1, EMB,
ERB, IEx, IRQx,
Pn.n
memb.@L
Indirect: lower two bits of reg-
ister L is indicated by the up-
per 10 bits of RAM area
(memb) and the upper two
bits of register L.
x
FC0H–FFFH
Bank 15
Bank 0
BSCn.x
Pn.n
@H + DA.b
Indirect: bit indicated by the
lower four bits of the address
(DA), memory bank selection,
and the H register identifier.
0
1
000H–0FFH
000H–FFFH
—
SMB = 0, 1, 15 All 1-bit
addressable
peripherals
(SMB = 15)
NOTE: 'x' means don't care.
3-6
S3C70F2/C70F4/P70F4
ADDRESSING MODES
+
PROGRAMMING TIP — 1-Bit Addressing Modes
1-Bit Direct Addressing
1.
If EMB = "0":
AFLAG
BFLAG
CFLAG
EQU
EQU
EQU
SMB
BITS
BITS
BTST
BITS
BITS
34H.3
85H.3
0BAH.0
0
AFLAG
BFLAG
CFLAG
BFLAG
P3.0
; Non-essential instruction, since EMB = "0"
; 34H.3 ¬ 1
; F85H.3 (BMOD.3) ¬ 1
; If FBAH.0 (IRQW) = 1, skip
; Else if FBAH.0 (IRQW) = 0, F85H.3 (BMOD.3) ¬ 1
; FF3H.0 (P3.0) ¬ 1
;
2. If EMB = "1":
AFLAG
BFLAG
CFLAG
EQU
EQU
EQU
SMB
BITS
BITS
BTST
BITS
BITS
34H.3
85H.3
0BAH.0
0
AFLAG
BFLAG
CFLAG
BFLAG
P3.0
; Select memory bank 0
; 34H.3 ¬ 1
; 85H.3 ¬ 1
; If 0BAH.0 = 1, skip
; Else if 0BAH.0 = 0, 085H.3 ¬ 1
; FF3H.0 (P3.0) ¬ 1
;
3-7
ADDRESSING MODES
S3C70F2/C70F4/P70F4
+
PROGRAMMING TIP — 1-Bit Addressing Modes (Continued)
1-Bit Indirect Addressing
1.
If EMB = "0":
AFLAG
BFLAG
CFLAG
EQU
EQU
EQU
SMB
LD
34H.3
85H.3
0BAH.0
0
H,#0BH
@H+CFLAG
CFLAG
; Non-essential instruction, since EMB = "0"
; H ¬ #0BH
; If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip
; Else if 0BAH.0 = 0, FBAH.0 (IRQW) ¬ 1
BTSTZ
BITS
;
2. If EMB = "1":
AFLAG
BFLAG
CFLAG
EQU
EQU
EQU
SMB
LD
34H.3
85H.3
0BAH.0
0
H,#0BH
@H+CFLAG
CFLAG
; Select memory bank 0
; H ¬ #0BH
; If 0BAH.0 = 1, 0BAH.0 ¬ 0 and skip
; Else if 0BAH.0 = 0, 0BAH.0 ¬ 1
BTSTZ
BITS
;
3-8
S3C70F2/C70F4/P70F4
4-BIT ADDRESSING
ADDRESSING MODES
Table 3-3. 4-Bit Direct and Indirect RAM Addressing
Instruction
Notation
Addressing Mode
Description
EMB Flag
Setting
Addressable
Area
Memory
Hardware I/O
Mapping
Bank
Bank 0
Bank15
000H–07FH
F80H–FFFH
—
DA
Direct: 4-bit address indicated
by the RAM address (DA) and
the memory bank selection
0
All 4-bit
addressable
peripherals
1
0
000H–FFFH
000H–0FFH
SMB = 0,1,15 (SMB = 15)
Bank 0
@HL
Direct: 4-bit address indicated
by the memory bank selection
and register HL
—
1
000H–FFFH
SMB = 0,1,15 All 4-bit
addressable
peripherals
(SMB = 15)
@WX
@WL
Indirect: 4-bit address indi-
cated by register WX
x
x
000H–0FFH
000H–0FFH
Bank 0
Bank 0
—
Indirect: 4-bit address indi-
cated by register WL
NOTE: 'x' means don't care.
+
PROGRAMMING TIP — 4-Bit Addressing Modes
4-Bit Direct Addressing
1. If EMB = "0":
ADATA
BDATA
EQU
EQU
SMB
LD
SMB
LD
46H
8EH
15
A,P3
0
; Non-essential instruction, since EMB = "0"
; A ¬ (P3)
; Non-essential instruction, since EMB = "0"
; (046H) ¬ A
ADATA,A
BDATA,A
LD
; (F8EH) ¬ A
;
2. If EMB = "1":
ADATA
BDATA
EQU
EQU
SMB
LD
SMB
LD
46H
8EH
15
A,P3
0
; Select memory bank 15
; A ¬ (P3)
; Select memory bank 0
; (046H) ¬ A
ADATA,A
BDATA,A
LD
; (08EH) ¬ A
;
3-9
ADDRESSING MODES
S3C70F2/C70F4/P70F4
+
PROGRAMMING TIP — 4-Bit Addressing Modes (Continued)
4-Bit Indirect Addressing
1.
If EMB = "0", compare bank 0, locations 040H–046H with 060H–066H:
ADATA
BDATA
EQU
EQU
SMB
LD
LD
LD
CPSE
SRET
DECS
JR
46H
66H
15
HL,#BDATA
WX,#ADATA
A,@WL
A,@HL
; Non-essential instruction, since EMB = "0"
COMP
; A ¬ bank 0 (040H–046H)
; If bank 0 (060H–066H) = A, skip
L
COMP
RET
;
2.
If EMB = "1", exchange bank 0, 040H–046H with 060H–066H:
ADATA
BDATA
EQU
EQU
SMB
LD
LD
LD
46H
66H
0
HL,#BDATA
WX,#ADATA
A,@WL
A,@HL
TRANS
; Select memory bank 0
TRANS
;
; A ¬ bank 0 (040H–046H)
; Bank 0 (060H–066H) ¬ A
XCHD
JR
3-10
S3C70F2/C70F4/P70F4
8-BIT ADDRESSING
ADDRESSING MODES
Table 3-4. 8-Bit Direct and Indirect RAM Addressing
Instructio
n
Addressing Mode
EMB Flag
Setting
Addressable
Area
Memory
Bank
Hardware I/O
Mapping
Description
Notation
000H–07FH
F80H–FFFH
Bank 0
Bank15
—
DA
Direct: 8-bit address indicated
by the RAM address (DA =
even number) and memory
bank selection
0
All 8-bit
addressable pe-
ripherals
(SMB = 15)
1
0
000H–FFFH
000H–0FFH
SMB = 0, 1, 15
Bank 0
@HL
Indirect: the 8-bit address
indicated by the memory bank
selection and register HL; (the
4-bit L register value must be
an even number)
—
1
000H–FFFH
SMB = 0, 1, 15 All 8-bit
addressable pe-
ripherals
(SMB = 15)
+
PROGRAMMING TIP — 8-Bit Addressing Modes
8-Bit Direct Addressing:
1. If EMB = "0":
ADATA
BDATA
EQU
EQU
SMB
LD
LD
LD
46H
8EH
15
EA,P4
ADATA,EA
BDATA,EA
; Non-essential instruction, since EMB = "0"
; E ¬ (P5), A ¬ (P4)
; (046H) ¬ A, (047H) ¬ E
; (F8EH) ¬ A, (F8FH) ¬ E
;
2.
If EMB = "1":
ADATA
BDATA
EQU
EQU
SMB
LD
SMB
LD
46H
8EH
15
EA,P4
0
; Select memory bank 15
; E ¬ (P5), A ¬ (P4)
; Select memory bank 0
; (046H) ¬ A, (047H) ¬ E
; (08EH) ¬ A, (08FH) ¬ E
ADATA,EA
BDATA,EA
LD
;
3-11
ADDRESSING MODES
S3C70F2/C70F4/P70F4
+
PROGRAMMING TIP — 8-Bit Addressing Modes (Continued)
8-Bit Indirect Addressing
1. If EMB = "0":
ADATA
EQU
LD
LD
8EH
HL,#ADATA
EA,@HL
;
;
A ¬ (08EH), E ¬ (08FH)
;
2. If EMB = "1":
ADATA
EQU
SMB
LD
46H
0
HL,#ADATA
EA,@HL
LD
A ¬ (046H), E ¬ (047H)
;
3-12
S3C70F2/C70F4/P70F4
MEMORY MAP
4
MEMORY MAP
OVERVIEW
To support program control of peripheral hardware, I/O addresses for peripherals are memory-mapped to bank
15 of the RAM. Memory mapping lets you use a mnemonic as the operand of an instruction in place of the
specific memory location.
Access to bank 15 is controlled by the select memory bank (SMB) instruction and by the enable memory bank
flag (EMB) setting. If the EMB flag is "0", bank 15 can be addressed using direct addressing, regardless of the
current SMB value. You can use 1-bit direct and indirect addressing, however, for specific locations in bank 15,
regardless of the current EMB value.
I/O MAP FOR HARDWARE REGISTERS
Table 4–1 contains detailed information about I/O mapping for peripheral hardware in bank 15 (register locations
F80H–FFFH). Use the I/O map as a quick-reference source when writing application programs. The I/O map
gives you the following information:
— Register address
— Register name (mnemonic for program addressing)
— Bit values (both addressable and non-manipulable)
— Read-only, write-only, or read and write addressability
— 1-bit, 4-bit, or 8-bit data manipulation characteristics
MEMORY MAP
S3C70F2/C70F4/P70F4
Addressing Mode
Table 4-1. I/O Map for Memory Bank 15
Memory Bank 15
Address
F80H
F81H
F82H
F83H
F85H
F86H
F87H
F88H
F89H
•
Register
Bit 3
.3
Bit 2
.2
Bit 1
.1
Bit 0
"0"
R/W
1-Bit
4-Bit
8-Bit
SP
R/W
No
No
Yes
.7
.6
.5
.4
SB
“0”
“0”
SRB1
SMB1
.1
SRB0
SMB0
.0
–
No
No
No
SMB3
.3
SMB2
.2
BMOD
BCNT
W
R
.3
Yes
No
No
No
Yes
(1)
WMOD
"0"
.7
.2
.1
.5
W
No
No
Yes
"0"
"0"
.4
•
F90H
F91H
F92H
F93H
F94H
F95H
F96H
F97H
F98H
F99H
F9AH
•
TMOD0
.3
.2
.6
"0"
.5
"0"
.4
W
R/W
R
.3
No
Yes
No
No
No
No
Yes
No
"0"
"0"
TOE0
"0"
"0"
Yes
No
TCNT0
TREF0
Yes
Yes
Yes
No
W
No
WDMOD
.3
.7
.2
.6
.1
.5
.0
.4
W
No
WDFLAG WDTCF
"0"
"0"
"0"
W
Yes
•
FB0H
FB1H
FB2H
FB3H
FB4H
FB5H
FB6H
FB7H
PSW
IS1
(2)
IS0
SC2
.2
EMB
SC1
.1
ERB
SC0
.0
R/W
R
Yes
No
Yes
No
Yes
C
IPR
IME
.3
W
IME
No
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
PCON
IMOD0
IMOD1
IMODK
.2
.1
.0
W
.3
"0"
"0"
.2
.1
.0
W
No
"0"
"0"
"0"
.1
.0
W
No
.0
W
N o
4-2
S3C70F2/C70F4/P70F4
MEMORY MAP
Table 4-1. I/O Map for Memory Bank 15 (Continued)
Memory Bank 15
Addressing Mode
Address
FB8H
FB9H
FBAH
FBBH
FBCH
FBDH
FBEH
FBFH
FC0H
FC1H
FC2H
FC3H
•
Register
Bit 3
Bit 2
Bit 1
Bit 0
R/W
1-Bit
4-Bit
8-Bit
"0"
"0"
IEB
IRQB
R/W
Yes
Yes
No
"0"
"0"
IEW
IRQW
R/W
R/W
Yes
Yes
Yes
Yes
Yes
No
No
"0"
"0"
IE1
"0"
"0"
"0"
IET0
IES
IE0
IRQT0
IRQS
IRQ0
IRQK
IRQ1
"0"
IEK
BSC0
BSC1
BSC2
BSC3
R/W
R/W
R/W
R/W
Yes
Yes
Yes
Yes
Yes
Yes
•
FD0H
•
CLMOD
.3
"0"
.1
.0
W
No
Yes
No
•
FD4H
FD5H
FD6H
FD7H
•
CMPREG
CMOD
R
No
No
Yes
No
No
.3
.7
.2
.6
.1
.5
.0
R/W
Yes
"0"
•
FDAH
FDBH
FDCH
FDDH
FDEH
FDFH
FE0H
FE1H
PNE
PNE4.3 PNE4.2 PNE4.1 PNE4.0
PNE5.3 PNE5.2 PNE5.1 PNE5.0
W
W
No
No
No
No
Yes
Yes
PUMOD
.3
"0"
.6
.1
.5
.0
.4
"0"
SMOD
.3
.7
.2
.6
.1
.5
.0
W
.3
No
Yes
"0"
MEMORY MAP
S3C70F2/C70F4/P70F4
Addressing Mode
Table 4-1. I/O Map for Memory Bank 15 (Concluded)
Memory Bank 15
Address
FE2H
FE3H
FE4H
FE5H
FE6H
FE7H
FE8H
FE9H
FEAH
FEBH
FECH
FEDH
FEEH
FEFH
FF0H
FF1H
FF2H
FF3H
FF4H
FF5H
FF6H
•
Register
Bit 3
Bit 2
Bit 1
Bit 0
R/W
1-Bit
4-Bit
8-Bit
P2MOD
.3
.2
.1
.0
W
No
Yes
No
SBUF
R/W
No
No
Yes
PMG1
PMG2
PMG3
"0"
"0"
PM0.2
PM3.2
PM4.2
"0"
PM0.1
PM3.1
PM4.1
"0"
PM0.0
PM3.0
PM4.0
"0"
W
W
W
No
No
No
No
No
No
Yes
Yes
Yes
PM4.3
"0"
PM5.3
PM6.3
PM5.2
PM6.2
PM5.1
PM6.1
PM5.0
PM6.0
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
—
—
.2
—
.1
.1
.0
.0
R/W
R
Yes
Yes
No
No
.3
.2
.1
.0
R
No
—
.2
.1
.0
R/W
R/W
R/W
R/W
No
.3
.2
.1
.0
Yes
.3 / .7
.3
.2 / .6
.2
.1 / .5
.1
.0 / .4
.0
No
•
•
FFFH
NOTES:
1. Bit 0 in the WMOD register must be set to logic "0".
2. The carry flag can be read or written by specific bit manipulation instructions only.
4-4
S3C70F2/C70F4/P70F4
MEMORY MAP
REGISTER DESCRIPTIONS
In this section, register descriptions are presented in a consistent format to familiarize you with the memory-
mapped I/O locations in bank 15 of the RAM. Figure 4–1 describes features of the register description format.
Register descriptions are arranged in alphabetical order.
Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are
not included in these descriptions.
This section can be used as a quick-reference source when writing application programs.
More detailed information about each of these registers is included in Part II of this manual, "Hardware
Descriptions," in the context of the corresponding peripheral hardware module descriptions.
MEMORY MAP
S3C70F2/C70F4/P70F4
Bit identifiers used
for bit addressing
Name of individual
bit or related bits
Register location
in RAM bank 15
Register ID
Register name
IPR — Interrupt Priority Register
FB2H
3
2
1
0
Bit
.2
IME
.1
.0
Identifier
Value
Read/Write
Bit Addressing
0
0
W
4
0
W
4
0
W
4
RESET
W
1/4
Global Interrupt Enable Bit
IME
0
1
Disable interrupt processing globally
Enable interrupt processing globally
Interrupt Priority Assignment Bits
.2 – .0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
1
Process all interrupt requests at low priority
Process INTB interrupts only
Process INT0 interrupts only
Process INT1 interrupts only
Process INTT interrupts only
R = Read-only
W = Write-only
R/W = Read/write
'–' = Not used
Bit value immediately
following a reset
Bit number in
MSB to LSB order
Type of addressing
that must be used to
address the bit
Description of the
effect of specific bit
settings
Bit identifier used
for bit addressing
(1-bit, 4-bit, or 8-bit)
Figure 4-1. Register Description Format
4-6
S3C70F2/C70F4/P70F4
MEMORY MAP
BMOD — Basic Timer Mode Register
F85H
Bit
3
.3
0
2
.2
0
1
.1
0
0
.0
0
Identifier
RESET Value
Read/Write
W
W
4
W
4
W
4
Bit Addressing
1/4
BMOD.3
Basic Timer Restart Bit
Restart basic timer, then clear IRQB flag, BCNT and BMOD.3 to logic zero
1
BMOD.2 – .0
Input Clock Frequency and Signal Stabilization Interval Control Bits
fx / 212 (1.02 kHz)
220 / fx (250 ms)
0
0
1
1
0
1
0
1
0
1
1
1
Input clock frequency:
Signal stabilization interval:
fx / 29 (8.18 kHz)
217 / fx (31.3 ms)
Input clock frequency:
Signal stabilization interval:
fx / 27 (32.7 kHz)
215 / fx (7.82 ms)
Input clock frequency:
Signal stabilization interval:
fx / 25 (131 kHz)
213 / fx (1.95 ms)
Input clock frequency:
Signal stabilization interval:
NOTES:
1. Signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by
an interrupt.
2. When a RESET occurs, the oscillation stabilization time is 31.3 ms at 4.19 MHz.
3. 'fx' is the system clock rate given a clock frequency of 4.19 MHz.
MEMORY MAP
S3C70F2/C70F4/P70F4
CMOD — Comparator Mode Register
FD7H, FD6H
Bit
7
.7
0
6
.6
0
5
.5
0
4
"0"
0
3
.3
0
2
.2
0
1
.1
0
0
.0
0
Identifier
RESET Value
Read/Write
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
R/W
8
Bit Addressing
CMOD.7
CMOD.6
Comparator Enable/Disable Bit
0
1
Comparator operation disable
Comparator operation enable
Conversion Time Control Bit
4
0
1
8 ´ 2 / fx, 244.4 µs @4.19 MHz
7
8 ´ 2 / fx, 30.5 µs @4.19 MHz
CMOD.5
External/Internal Reference Selection Bit
0
1
Internal reference, CIN0–3: analog input
External reference at CIN3, CIN0–2: analog input
CMOD.4
Bit 4
0
Always logic zero
CMOD.3 – .0
Reference Voltage Selection Bits
Selected V
REF
(n + 0.5)
16
V
DD
´
, n = 0 to 15
4-8
S3C70F2/C70F4/P70F4
MEMORY MAP
CLMOD — Clock Output Mode Register
FD0H
Bit
3
.3
0
2
"0"
0
1
.1
0
0
.0
0
Identifier
RESET Value
Read/Write
W
4
W
4
W
4
W
4
Bit Addressing
CLMOD.3
Enable/Disable Clock Output Control Bit
0
1
Disable clock output
Enable clock output
CLMOD.2
Bit 2
0
Always logic zero
CLMOD.1 – .0
Clock Source and Frequency Selection Control Bits
0
0
Select CPU clock source fx/4, fx/8, or fx/64 (1.05 MHz, 524 kHz, or 65.6
kHz)
0
1
1
1
0
1
Select system clock fx/8 (524 kHz)
Select system clock fx/16 (262 kHz)
Select system clock fx/64 (65.5 kHz)
NOTE: ’fx' is the system clock given a clock frequency of 4.19 MHz.
MEMORY MAP
S3C70F2/C70F4/P70F4
IE0/1, IRQ0/1 — INT0/1 Interrupt Enable/Request Flags
FBEH
Bit
3
IE1
0
2
IRQ1
0
1
IE0
0
0
IRQ0
0
Identifier
RESET Value
Read/Write
R/W
1/4
R/W
1/4
R/W
1/4
R/W
1/4
Bit Addressing
IE1
INT1 Interrupt Enable Flag
0
1
Disable interrupt requests at the INT1 pin
Enable interrupt requests at the INT1 pin
IRQ1
IE0
INT1 Interrupt Request Flag
Generate INT1 interrupt (bit is set and cleared by hardware when rising or
falling edge detected at INT1 pin.)
–
INT0 Interrupt Enable Flag
0
1
Disable interrupt requests at the INT0 pin
Enable interrupt requests at the INT0 pin
IRQ0
INT0 Interrupt Request Flag
–
Generate INT0 interrupt (bit is set and cleared by hardware when rising or
falling edge detected at INT0 pin.)
4-10
S3C70F2/C70F4/P70F4
MEMORY MAP
IEK, IRQK — Key Interrupt Enable/Request Register
FBFH
Bit
3
0
0
2
0
0
1
IEK
0
0
IRQK
0
Identifier
RESET Value
Read/Write
R/W
1/4
R/W
1/4
R/W
1/4
R/W
1/4
Bit Addressing
.3 – .2
IEK
Bits 3–2
0
Always logic zero
Key Interrupt Request Enable Flag
0
1
Disable INTK interrupt requests at the KS0–KS2 pins
Enable INTK interrupt requests at the KS0–KS2 pin
IRQK
Key Interrupt Request Flag
–
Generate INTK interrupt. (This bit is set when falling edge detected any at one
of the KS0–KS2 pins. INTK is a quasi-interrupt and IRQK must be cleared by
software.)
MEMORY MAP
S3C70F2/C70F4/P70F4
IEB, IRQB — INTB Interrupt Enable/Request Flags
FB8H
Bit
3
0
0
2
0
0
1
IEB
0
0
IRQB
0
Identifier
RESET Value
Read/Write
R/W
1/4
R/W
1/4
R/W
1/4
R/W
1/4
Bit Addressing
.3 – .2
IEB
Bits 3–2
0
Always logic zero
INTB Interrupt Enable Flag
0
1
Disable INTB interrupt requests
Enable INTB interrupt requests
IRQB
INTB Interrupt Request Flag
–
Generate INTB interrupt (bit is set and cleared automatically by hardware when
reference interval signal received from basic timer.)
4-12
S3C70F2/C70F4/P70F4
MEMORY MAP
IES, IRQS — INTS Interrupt Enable/Request Flags
FBDH
Bit
3
0
0
2
0
0
1
IES
0
0
IRQS
0
Identifier
RESET Value
Read/Write
R/W
1/4
R/W
1/4
R/W
1/4
R/W
1/4
Bit Addressing
.3 – .2
IES
Bits 3–2
0
Always logic zero
INTS Interrupt Enable Flag
0
1
Disable INTS interrupt requests
Enable INTS interrupt requests
IRQS
INTS Interrupt Request Flag
–
Generate INTS interrupt (bit is set and cleared automatically by hardware when
transmit or receive operation is completed.)
MEMORY MAP
S3C70F2/C70F4/P70F4
IET0, IRQT0 — INTT0 Interrupt Enable/Request Flags
FBCH
Bit
3
0
0
2
0
0
1
IET0
0
0
IRQT0
0
Identifier
RESET Value
Read/Write
R/W
1/4
R/W
1/4
R/W
1/4
R/W
1/4
Bit Addressing
.3 – .2
IET0
Bits 3–2
0
Always logic zero
INTT0 Interrupt Enable Flag
0
1
Disable INTT0 interrupt requests
Enable INTT0 interrupt requests
IRQT0
INTT0 Interrupt Request Flag
Generate INTT0 interrupt (bit is set and cleared automatically by hardware
when contents of TCNT0 and TREF0 registers match.)
–
4-14
S3C70F2/C70F4/P70F4
MEMORY MAP
IEW, IRQW — INTW Interrupt Enable/Request Flags
FBAH
Bit
3
0
0
2
0
0
1
IEW
0
0
IRQW
0
Identifier
RESET Value
Read/Write
R/W
1/4
R/W
1/4
R/W
1/4
R/W
1/4
Bit Addressing
.3 – .2
IEW
Bits 3–2
0
Always logic zero
INTW Interrupt Enable Flag
0
1
Disable INTW interrupt requests
Enable INTW interrupt requests
IRQW
INTW Interrupt Request Flag
Generate INTW interrupt (bit is set when timer interval = 0.5 s or 3.19 ms at
4.19 MHz)
NOTE: INTW is a quasi-interrupt and its request flag must be cleared by software.
–
MEMORY MAP
S3C70F2/C70F4/P70F4
IMOD0 — External Interrupt 0 (INT0) Mode Register
FB4H
Bit
3
.3
0
2
"0"
0
1
.1
0
0
.0
0
Identifier
RESET Value
Read/Write
W
4
W
4
W
4
W
4
Bit Addressing
IMOD0.3
Interrupt Sampling Clock Selection Bit
0
1
Select CPU clock as a sampling clock
Select sampling clock frequency of the system clock (fx)/64
IMOD0.2
Bit 2
0
Always logic zero
IMOD0.1 – .0
External Interrupt Mode Control Bits
0
0
1
1
0
1
0
1
Interrupt requests are triggered by a rising signal edge
Interrupt requests are triggered by a falling signal edge
Interrupt requests are triggered by both rising and falling signal edges
Interrupt request flag (IRQ0) cannot be set to logic one
4-16
S3C70F2/C70F4/P70F4
MEMORY MAP
IMOD1 — External Interrupt 1 (INT1) Mode Register
FB5H
Bit
3
"0"
0
2
"0"
0
1
"0"
0
0
.0
0
Identifier
RESET Value
Read/Write
W
4
W
4
W
4
W
4
Bit Addressing
IMOD1.3 – .1
IMOD1.0
Bits 3–1
0
Always logic zero
External Interrupt 1 Edge Detection Control Bit
0
1
Rising edge detection
Falling edge detection
MEMORY MAP
S3C70F2/C70F4/P70F4
IMODK — Key Interrupt Mode Register
FB6H
Bit
3
"0"
0
2
.2
0
0
.0
0
Identifier
RESET Value
Read/Write
W
4
W
4
W
4
Bit Addressing
IMODK.3
Bits 3
0
Always logic zero
IMODK.2 – .0
Key Interrupt Edge Detection Selection Bit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Interrupt request is disabled
Interrupt request at KS0 triggered by falling edge
Interrupt request at KS1 triggered by falling edge
Interrupt request at KS0–KS1 triggered by falling edge
Interrupt request at KS2 triggered by falling edge
Interrupt request at KS0, KS2 triggered by falling edge
Interrupt request at KS1–KS2 triggered by falling edge
Interrupt request at KS0–KS2 triggered by falling edge
4-18
S3C70F2/C70F4/P70F4
MEMORY MAP
IPR — Interrupt Priority Register
FB2H
Bit
3
IME
0
2
.2
0
1
.1
0
0
.0
0
Identifier
RESET Value
Read/Write
W
W
4
W
4
W
4
Bit Addressing
1/4
IME
Interrupt Master Enable Bit
0
1
Inhibit all interrupt processing
Enable processing for all interrupt service requests
IPR.2 – .0
Interrupt Priority Assignment Bits
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Normal interrupt handling according to default priority settings
Process INTB interrupt at highest priority
Process INT0 interrupts at highest priority
Process INT1 interrupts at highest priority
Process INTS interrupts at highest priority
Process INTT0 interrupts at highest priority
MEMORY MAP
S3C70F2/C70F4/P70F4
PCON — Clock Power Control Register
FB3H
Bit
3
.3
0
2
.2
0
1
.1
0
0
.0
0
Identifier
RESET Value
Read/Write
W
4
W
4
W
4
W
4
Bit Addressing
PCON.3 – .2
CPU Operating Mode Control Bits
0
0
1
0
1
0
Enable normal CPU operating mode
Initiate idle power-down mode
Initiate stop power-down mode
PCON.1 – .0
CPU Clock Frequency Selection Bits
0
1
1
0
0
1
Select (fx)/64
Select fx/8
Select fx/4
NOTE: fx = system clock
4-20
S3C70F2/C70F4/P70F4
MEMORY MAP
PMG1 — Port I/O Mode Flags (Group 1: Port 0, 3)
FE9H, FE8H
Bit
7
"0"
0
6
PM3.2
0
5
PM3.1
0
4
PM3.0
0
3
"0"
0
2
PM0.2
0
1
0
PM0.1
PM0.0
Identifier
0
0
RESET Value
Read/Write
W
8
W
8
W
8
W
8
W
8
W
8
W
8
W
8
Bit Addressing
.7
Bit 7
0
Always logic zero
PM3.2
P3.2 I/O Mode Selection Flag
0
1
Set P3.2 to input mode
Set P3.2 to output mode
PM3.1
PM3.0
P3.1 I/O Mode Selection Flag
0
1
Set P3.1 to input mode
Set P3.1 to output mode
P3.0 I/O Mode Selection Flag
0
1
Set P3.0 to input mode
Set P3.0 to output mode
.4
Bit 4
0
Always logic zero
PM0.2
P0.2 I/O Mode Selection Flag
0
1
Set P0.2 to input mode
Set P0.2 to output mode
PM0.1
PM0.0
P0.1 I/O Mode Selection Flag
0
1
Set P0.1 to input mode
Set P0.1 to output mode
P0.0 I/O Mode Selection Flag
0
1
Set P0.0 to input mode
Set P0.0 to output mode
MEMORY MAP
S3C70F2/C70F4/P70F4
PMG2 — Port I/O Mode Flags (Group 2: Port 4)
FEBH, FEAH
Bit
7
"0"
0
6
"0"
0
5
"0"
0
4
"0"
0
3
PM4.3
0
2
PM4.2
0
1
PM4.1
0
0
PM4.0
0
Identifier
RESET Value
Read/Write
W
8
W
8
W
8
W
8
W
8
W
8
W
8
W
8
Bit Addressing
.7
Bit 7
0
Always logic zero
Always logic zero
Always logic zero
Always logic zero
.6
Bit 6
0
.5
Bit 5
0
.4
Bit 4
0
PM4.3
P4.3 I/O Mode Selection Flag
0
1
Set P4.3 to input mode
Set P4.3 to output mode
PM4.2
PM4.1
PM4.0
P4.2 I/O Mode Selection Flag
0
1
Set P4.2 to input mode
Set P4.2 to output mode
P4.1 I/O Mode Selection Flag
0
1
Set P4.1 to input mode
Set P4.1 to output mode
P4.0 I/O Mode Selection Flag
0
1
Set P4.0 to input mode
Set P4.0 to output mode
4-22
S3C70F2/C70F4/P70F4
MEMORY MAP
PMG3 — Port I/O Mode Flags (Group 3: Port 5, 6)
FEDH, FECH
Bit
7
PM6.3
0
6
PM6.2
0
5
PM6.1
0
4
PM6.0
0
3
PM5.3
0
2
PM5.2
0
1
0
Identifier
PM5.1
PM5.0
0
0
RESET Value
Read/Write
W
8
W
8
W
8
W
8
W
8
W
8
W
8
W
8
Bit Addressing
PM6.3
PM6.2
PM6.1
PM6.0
PM5.3
PM5.2
PM5.1
PM5.0
P6.3 I/O Mode Selection Flag
0
1
Set P6.3 to input mode
Set P6.3 to output mode
P6.2 I/O Mode Selection Flag
0
1
Set P6.2 to input mode
Set P6.2 to output mode
P6.1 I/O Mode Selection Flag
0
1
Set P6.1 to input mode
Set P6.1 to output mode
P6.0 I/O Mode Selection Flag
0
1
Set P6.0 to input mode
Set P6.0 to output mode
P5.3 I/O Mode Selection Flag
0
1
Set P5.3 to input mode
Set P5.3 to output mode
P5.2 I/O Mode Selection Flag
0
1
Set P5.2 to input mode
Set P5.2 to output mode
P5.1 I/O Mode Selection Flag
0
1
Set P5.1 to input mode
Set P5.1 to output mode
P5.0 I/O Mode Selection Flag
0
1
Set P5.0 to input mode
Set P5.0 to output mode
MEMORY MAP
S3C70F2/C70F4/P70F4
PNE — N-channel Open-drain Mode Register
FDAH
Bit
7
6
5
4
3
2
1
0
Identifier
PNE5.3 PNE5.2 PNE5.1 PNE5.0 PNE4.3 PNE4.2 PNE4.1 PNE4.0
0
0
0
0
0
0
0
0
RESET Value
Read/Write
W
8
W
8
W
8
W
8
W
8
W
8
W
8
W
8
Bit Addressing
.7
.6
.5
.4
.3
.2
.1
.0
P5.3 N-channel Open-drain Enable Bit
0
1
Set P5.3 Open-drain Disabled
Set P5.3 Open-drain Enabled
P5.2 N-channel Open-drain Enable Bit
0
1
Set P5.2 Open-drain Disabled
Set P5.2 Open-drain Enabled
P5.1 N-channel Open-drain Enable Bit
0
1
Set P5.1 Open-drain Disabled
Set P5.1 Open-drain Enabled
P5.0 N-channel Open-drain Enable Bit
0
1
Set P5.0 Open-drain Disabled
Set P5.0 Open-drain Enabled
P4.3 N-channel Open-drain Enable Bit
0
1
Set P4.3 Open-drain Disabled
Set P4.3 Open-drain Enabled
P4.2 N-channel Open-drain Enable Bit
0
1
Set P4.2 Open-drain Disabled
Set P4.2 Open-drain Enabled
P4.1 N-channel Open-drain Enable Bit
0
1
Set P4.1 Open-drain Disabled
Set P4.1 Open-drain Enabled
P4.0 N-channel Open-drain Enable Bit
0
1
Set P4.0 Open-drain Disabled
Set P4.0 Open-drain Enabled
4-24
S3C70F2/C70F4/P70F4
MEMORY MAP
PSW — Program Status Word
FB1H, FB0H
Bit
7
6
SC2
0
5
SC1
0
4
SC0
0
3
IS1
0
2
IS0
0
1
0
Identifier
C
(1)
EMB
ERB
0
0
RESET Value
Read/Write
R/W
R
8
R
8
R
8
R/W
R/W
R/W
R/W
(2)
Bit Addressing
1/4/8
1/4/8
1/4/8
1/4/8
C
Carry Flag
0
1
No overflow or borrow condition exists
An overflow or borrow condition does exist
SC2 – SC0
IS1, IS0
Skip Condition Flags
0
1
No skip condition exists; no direct manipulation of these bits is allowed
A skip condition exists; no direct manipulation of these bits is allowed
Interrupt Status Flags
0
0
0
1
Service all interrupt requests
Service only the high-priority interrupt(s) as determined in the interrupt
priority register (IPR)
1
1
0
1
Do not service any more interrupt requests
Undefined
EMB
Enable Data Memory Bank Flag
0
Restrict program access to data memory to bank 15 (F80H–FFFH) and to
the locations 000H–07FH in the bank 0 only
1
Enable full access to data memory banks 0, 1, and 15
ERB
Enable Register Bank Flag
0
1
Select register bank 0 as working register area
Select register banks 0, 1, 2, or 3 as working register area in accordance with
the select register bank (SRB) instruction operand
NOTES:
1. The value of the carry flag after a RESET occurs during normal operation is undefined. If a RESET occurs during
power-down mode (IDLE or STOP), the current value of the carry flag is retained.
2. The carry flag can only be addressed by a specific set of 1-bit manipulation instructions. See Section 2 for
detailed information.
MEMORY MAP
S3C70F2/C70F4/P70F4
P2MOD — Port 2 Mode Register
FE2H
Bit
3
.3
0
2
.2
0
1
.1
0
0
.0
0
Identifier
RESET Value
Read/Write
W
4
W
4
W
4
W
4
Bit Addressing
P2MOD.3
P2MOD.2
P2MOD.1
P2MOD.0
P2.3 Analog/digital Selection Bit
0
1
Configure P2.3 as an comparator input pin
Configure P2.3 as an digital input pin
P2.2 Analog/digital Selection Bit
0
1
Configure P2.2 as an comparator input pin
Configure P2.2 as an digital input pin
P2.1 Analog/digital Selection Bit
0
1
Configure P2.1 as an comparator input pin
Configure P2.1 as an digital input pin
P2.0 Analog/digital Selection Bit
0
1
Configure P2.0 as an comparator input pin
Configure P2.0 as an digital input pin
4-26
S3C70F2/C70F4/P70F4
MEMORY MAP
PUMOD — Pull-Up Register Mode Register
FDCH, FDDH
Bit
7
"0"
0
6
.6
0
5
.5
0
4
.4
0
3
.3
0
2
"0"
0
1
0
.0
0
Identifier
.1
0
RESET Value
Read/Write
W
8
W
8
W
8
W
8
W
8
W
8
W
8
W
8
Bit Addressing
.7
.6
Bit 7
0
Always logic zero
Connect/Disconnect Port 6 Pull-Up Resistor Control Bit
0
1
Disconnect port 6 pull-up resistor
Connect port 6 pull-up resistor
.5
.4
.3
Connect/Disconnect Port 5 Pull-Up Resistor Control Bit
0
1
Disconnect port 5 pull-up resistor
Connect port 5 pull-up resistor
Connect/Disconnect Port 4 Pull-Up Resistor Control Bit
0
1
Disconnect port 4 pull-up resistor
Connect port 4 pull-up resistor
Connect/Disconnect Port 3 Pull-Up Resistor Control Bit
0
1
Disconnect port 3 pull-up resistor
Connect port 3 pull-up resistor
.2
.1
Bit 2
0
Always cleared to logic zero
Connect/Disconnect Port 1 Pull-Up Resistor Control Bit
0
1
Disconnect port 1 pull-up resistor
Connect port 1 pull-up resistor
.0
Connect/Disconnect Port 0 Pull-Up Resistor Control Bit
0
1
Disconnect port 0 pull-up resistor
Connect port 0 pull-up resistor
MEMORY MAP
S3C70F2/C70F4/P70F4
SMOD — Serial I/O Mode Register
FE1H, FE0H
Bit
7
.7
0
6
.6
0
5
.5
0
4
"0"
0
3
.3
0
2
.2
0
1
.1
0
0
.0
0
Identifier
RESET Value
Read/Write
W
8
W
8
W
8
W
8
R/W
1/8
W
8
W
8
W
8
Bit Addressing
SMOD.7 – .5
Serial I/O Clock Selection and SBUF R/W Status Control Bits
0
0
0
Use an external clock at the SCK pin;
Enable SBUF when SIO operation is halted or when SCK goes high
0
0
0
1
1
x
Use the TOL0 clock from timer/counter 0;
Enable SBUF when SIO operation is halted or when SCK goes high
Use the selected CPU clock (fx/4, 8, or 64; 'fx' is the system clock)
then, enable SBUF read/write operation. 'x' means 'don't care.'
10
1
1
0
1
0
1
4.09 kHz clock (fx/2
)
4
4
262 kHz clock (fx/2 ); Note: You cannot select a fx/2 clock fre-
quency if you have selected a CPU clock of fx/64
NOTE: All kHz frequency ratings assume a system clock of 4.19 MHz.
SMOD.4
Bit 4
0
Always logic zero
SMOD.3
Initiate Serial I/O Operation Bit
1
Clear IRQS flag and 3-bit clock counter to logic zero; then initiate serial trans-
mission. When SIO transmission starts, this bit is cleared by hardware to logic
zero
SMOD.2
Enable/Disable SIO Data Shifter and Clock Counter Bit
0
Disable the data shifter and clock counter; retain contents of IRQS flag when
serial transmission is completed
1
Enable the data shifter and clock counter; The IRQS flag is set to logic one
when serial transmission is completed
SMOD.1
SMOD.0
Serial I/O Transmission Mode Selection Bit
0
1
Receive-only mode
Transmit-and-receive mode
LSB/MSB Transmission Mode Selection Bit
0
1
Transmit the most significant bit (MSB) first
Transmit the least significant bit (LSB) first
4-28
S3C70F2/C70F4/P70F4
MEMORY MAP
TMOD0 — Timer/Counter 0 Mode Register
F91H, F90H
Bit
7
"0"
0
6
.6
0
5
.5
0
4
.4
0
3
.3
0
2
.2
0
1
"0"
0
0
"0"
0
Identifier
RESET Value
Read/Write
W
8
W
8
W
8
W
8
W
W
8
W
8
W
8
Bit Addressing
1/8
.7
Bit 7
0
Always logic zero
.6 – .4
Timer/Counter 0 Input Clock Selection Bits
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
External clock input at TCL0 pin on rising edge
External clock input at TCL0 pin on falling edge
10
Internal system clock (fx) of 4.19 MHz / 2 (4.09 kHz)
6
Selected clock: fx/2 (65.5 kHz)
4
Selected clock: fx/2 (262 kHz)
Selected clock: fx (4.19 MHz)
.3
.2
Clear Counter and Resume Counting Control Bit
1
Clear TCNT0, IRQT0, and TOL0 and resume counting immediately. (This bit is
cleared automatically when counting starts.)
Enable/Disable Timer/Counter 0 Bit
0
1
Disable timer/counter 0; retain TCNT0 contents
Enable timer/counter 0
.1
.0
Bit 1
0
Always logic zero
Always logic zero
Bit 0
0
NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.
MEMORY MAP
S3C70F2/C70F4/P70F4
TOE0 — Timer Output Enable Flag
F92H
Bit
3
0
0
2
TOE0
0
1
0
0
0
0
0
Identifier
RESET Value
Read/Write
R/W
1/4
R/W
1/4
R/W
1/4
W
Bit Addressing
1/4
.3
Bit 3
0
Always logic zero
TOE0
Timer/Counter 0 Output Enable Flag
0
1
Disable timer/counter 0 output to the TCLO0 pin
Enable timer/counter 0 output to the TCLO0 pin
.1
.0
Bit 1
0
Always logic zero
Always logic zero
Bit 0
0
4-30
S3C70F2/C70F4/P70F4
MEMORY MAP
WDMOD — Watch-Dog Timer Mode Register
F98H, F99H
Bit
7
.7
1
6
.6
0
5
.5
1
4
.4
0
3
.3
0
2
.2
1
1
.1
0
0
.0
1
Identifier
RESET Value
Read/Write
W
8
W
8
W
8
W
8
W
8
W
8
W
8
W
8
Bit Addressing
.7 - .0
Watch-Dog Timer Enable/Disable Control
5AH
Disable watch-dog timer function
Enable watch-dog timer function
Any other value
MEMORY MAP
S3C70F2/C70F4/P70F4
WDTCF — Watch-Dog Timer Flag
F9AH
Bit
3
WDTCF
0
2
“0”
0
1
“0”
0
0
“0”
0
Identifier
RESET Value
Read/Write
W
1
¾
¾
¾
¾
¾
¾
Bit Addressing
.3
Watch-dog timer’s counter clear bit
Clear and restart the watch-dog timer’s counter
1
NOTE: Instruction that clear the watch-dog timer (“BITS WDTCF”) should be executed at proper points in a program within
a given period. If not executed within a given period and watch-dog timer overflows, RESET signal is generated and
system is restarted with reset status.
4-32
S3C70F2/C70F4/P70F4
MEMORY MAP
WMOD — Watch Timer Mode Register
F89H, F88H
Bit
7
.7
0
6
"0"
0
5
.5
0
4
.4
0
3
"0"
0
2
.2
0
1
.1
0
0
"0"
0
Identifier
RESET Value
Read/Write
W
8
W
8
W
8
W
8
R
1
W
8
W
8
W
8
Bit Addressing
WMOD.7
Enable/Disable Buzzer Output Bit
0
1
Disable buzzer (BUZ) signal output
Enable buzzer (BUZ) signal output
WMOD.6
Bit 6
0
Always logic zero
WMOD.5 – .4
Output Buzzer Frequency Selection Bits
0
0
1
1
0
1
0
1
fw/16 buzzer (BUZ) signal output (2 kHz)
fw/8 buzzer (BUZ) signal output (4 kHz)
fw/4 buzzer (BUZ) signal output (8 kHz)
fw/2 buzzer (BUZ) signal output (16 kHz)
WMOD.3
WMOD.2
Bit 3
0
Always logic zero
Enable/Disable Watch Timer Bit
0
1
Disable watch timer and clear frequency dividing circuits
Enable watch timer
WMOD.1
WMOD.0
Watch Timer Speed Control Bit
0
1
Normal speed; set IRQW to 0.5 seconds at 4.19 MHz
High-speed operation; set IRQW to 3.91 ms at 4.19 MHz
Bit 0
0
Always logic zero (must be set to zero)
S3C70F2/C70F4/P70F4
OSCILLATOR CIRCUIT
6
OSCILLATOR CIRCUITS
OVERVIEW
The S3C70F2/C70F4 has a system clock circuit. The CPU and peripheral hardware operate on the system clock
frequency supplied through these on-chip circuits. Specifically, a clock is required by the following peripheral
modules:
— Basic timer
— Timer/counter 0
— Watch timer
— Serial I/O interface
— Clock output circuit
— Comparator
The system clock frequency can be divided by 4, 8, or 64. By manipulating PCON bits 1 and 0, you can select
one of the following frequencies as the CPU clock.
fx
4
fx
8
fx
64
,
,
When the PCON register is cleared to zero after RESET, the normal CPU operating mode is enabled, a system
clock of fx/64 is selected.
Bits 3 and 2 of the PCON register can be manipulated by a STOP or IDLE instruction to engage stop or idle
power-down mode.
6-1
OSCILLATOR CIRCUIT
S3C70F2/C70F4/P70F4
SYSTEM
OSCILLATOR
CIRCUIT
fx
Xin
Xout
WATCH TIMER
BASIC TIMER
FREQUENCY
DIVIDING
TIMER/COUNTER 0
CLOCK OUTPUT CIRCIT
COMPARATOR
CIRCUIT
OSCILLATOR
STOP
1/2
1/16
CPU
CLOCK
SELECTOR
1/4
CPU STOP SIGNAL
( IDLE MODE)
PCON.0
PCON.1
PCON.2
PCON.3
IDLE
WAIT RELEASE SIGNAL
INTERNAL SIGNAL
OSCILLATOR
CONTROL
CIRCUIT
STOP
RESET
POWER-DOWN RELEASE SIGNAL
PCON.3,2 CLEAR
Figure 6-1. Clock Circuit Diagram
6-2
S3C70F2/C70F4/P70F4
OSCILLATOR CIRCUIT
SYSTEM OSCILLATOR CIRCUITS
Xin
Xin
Xout
Xout
Figure 6-3. External Clock
Figure 6-2. Crystal/Ceramic Oscillator
6-3
OSCILLATOR CIRCUIT
S3C70F2/C70F4/P70F4
POWER CONTROL REGISTER (PCON)
The power control register, PCON, is a 4-bit register that is used to select the CPU clock frequency and to control
CPU operating and power-down modes. PCON is mapped to RAM address FB3H and can be addressed directly
by 4-bit write instructions or by the instructions IDLE and STOP.
FB3H
PCON.3
PCON.2
PCON.1
PCON.0
PCON bits 3 and 2 are controlled by the STOP and IDLE instructions to engage the idle and stop power-down
modes. Idle and stop modes can be initiated by these instruction despite the current value of the enable memory
bank flag (EMB). PCON bits 1 and 0 are used to select a specific system clock frequency.
RESET sets PCON register values to logic zero. PCON.1 and PCON.0 divide the frequency (fx) by 64, 8, and 4.
PCON.3 and PCON.2 enable normal CPU operating mode.
Table 6-1. Power Control Register (PCON) Organization
PCON Bit Settings
Resulting CPU Operating Mode
PCON.3
PCON.2
0
0
1
0
1
0
Normal CPU operating mode
Idle power-down mode
Stop power-down mode
PCON Bit Settings
Resulting CPU Clock Frequency
PCON.1
PCON.0
0
1
1
0
0
1
fx/64
fx/8
fx/4
+
PROGRAMMING TIP — Setting the CPU Clock
To set the CPU clock to 0.95 µs at 4.19 MHz:
BITS
SMB
LD
EMB
15
A,#3H
PCON,A
LD
6–4
S3C70F2/C70F4/P70F4
OSCILLATOR CIRCUIT
INSTRUCTION CYCLE TIMES
The unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided (by
4, 8, or 64). Table 6-2 shows corresponding cycle times in microseconds.
Table 6-2. Instruction Cycle Times for CPU Clock Rates
Selected CPU Clock
Resulting Frequency
65.5 kHz
Oscillation Source
Cycle Time (µsec)
fx/64
fx/8
15.3
1.91
0.95
524.0 kHz
fx = 4.19 MHz
fx/4
1.05 MHz
CLOCK OUTPUT MODE REGISTER (CLMOD)
The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the
CLO pin and to select the CPU clock source and frequency. CLMOD is mapped to RAM address FD0H and is ad-
dressable by 4-bit write instructions only.
FD0H
CLMOD.3
"0"
CLMOD.1 CLMOD.0
RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without
initiating clock oscillation), and disables clock output.
CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four
possible clock sources and frequencies: normal CPU clock, fx/8, fx/16, or fx/64.
Table 6-3. Clock Output Mode Register (CLMOD) Organization
CLMOD Bit Settings
Resulting Clock Output
CLMOD.1
CLMOD.0
Clock Source
Frequency
1.05 MHz, 524 kHz, 65.5 kHz
524 kHz
0
0
1
1
0
1
0
1
CPU clock (fx/4, fx/8, fx/64)
fx/8
fx/16
fx/64
262 kHz
65.5 kHz
CLMOD.3
Result of CLMOD.3 Setting
0
1
Clock output is disabled
Clock output is enabled
NOTE: Frequencies assume that fx = 4.19 MHz.
6-5
OSCILLATOR CIRCUIT
S3C70F2/C70F4/P70F4
CLOCK OUTPUT CIRCUIT
The clock output circuit, used to output clock pulses to the CLO pin, has the following components:
— 4-bit clock output mode register (CLMOD)
— Clock selector
— Output latch
— Port mode flag
— CLO output pin (P3.2)
CLMOD.3
CLO
CLMOD.2
4
CLMOD.1
CLOCK
P3.2 OUTPUT LATCH
PM3.2
SELECTOR
CLMOD.0
CLOCKS
(fx/8, fx/16, fx/64, CPU clock)
Figure 6-4. CLO Output Pin Circuit Diagram
CLOCK OUTPUT PROCEDURE
To output clock pulses to the CLO pin, follow this general procedure:
1. Disable clock output by clearing CLMOD.3 to logic zero.
2. Set the clock output frequency (CLMOD.1, CLMOD.0).
3. Load a "0" to the output latch of the CLO pin (P3.2).
4. Set the P3.2 mode flag (PM3.2) to output mode.
5. Enable clock output by setting CLMOD.3 to logic one.
+
PROGRAMMING TIP — CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin:
BITS
SMB
LD
LD
BITR
LD
EMB
15
; Or BITR EMB
EA,#40H
PMG1,EA
P3.2
A,#9H
CLMOD,A
; P3.2 ¬ Output mode
; Clear P3.2 output latch
LD
6–6
S3C70F2/C70F4/P70F4
INTERRUPTS
7
INTERRUPTS
OVERVIEW
S3C70F2/C70F4 microcontrollers process three types of interrupts:
— Internal interrupts generated by on-chip processes
— External interrupts generated by external peripheral devices
— Quasi-interrupts used for edge detection and clock sources
Table 7-1. Interrupts and Corresponding I/O Pin(s)
Interrupt Name
Interrupt Type
External Interrupts
Internal Interrupts
Quasi-interrupts
I/O Port Pin(s)
INT0, INT1
INTB, INTT0, INTS
INTK
P1.0, P1.1
Not applicable
P6.0–P6.2 (KS0–KS2)
Not applicable
INTW
The interrupt control circuit has four functional components:
— Interrupt enable flags (IEx)
— Interrupt request flags (IRQx)
— Interrupt priority registers (IME and IPR)
— Power-down release signal circuit
Vectored Interrupts
Interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program
software. A vectored interrupt is generated when the following flags and register settings, corresponding to the
specific interrupt, are enabled (set to logic one):
— Interrupt enable flag (IEx)
— Interrupt master enable flag (IME)
— Interrupt request flag (IRQx)
— Interrupt status flags (IS0, IS1)
— Interrupt priority register (IPR)
If all conditions are satisfied, the start address of the interrupt is loaded into the program counter and the pro-
gram starts executing the service routine from this address.
7-1
INTERRUPTS
S3C70F2/C70F4/P70F4
Vectored Interrupts (Continued)
EMB and ERB flags for RAM memory bank and registers are stored in the vector address area of the ROM
during interrupt service routines. The flags are stored at the beginning of the program with the VENT instruction.
Enable flag values are saved during the main routine, as well as during service routines. Any changes you make
to enable flag values during a service routine are not stored in the vector address.
When an interrupt occurs, the EMB and ERB values before the interrupt is initiated are saved along with the pro-
gram status word (PSW), and the EMB and ERB values for the interrupt are fetched from the respective vector
address.
Then, if required, you can modify the enable flags during the interrupt service routine. When the interrupt service
routine is returned to the main routine by the IRET instruction, however, the original values saved in the stack
are restored and the main program continues program execution with these values.
Software-Generated Interrupts
To generate an interrupt request from software, the program manipulates the appropriate IRQx flag. When the
interrupt request value in the IRQx flag is set, it is retained until all other conditions for the interrupt have been
met, and the service routine can be initiated.
Multiple Interrupts
By manipulating the two interrupt status flags (IS0 and IS1), you can control service routine initialization and
thereby process multiple interrupts simultaneously.
Power-Down Mode Release
An interrupt (with the exception of INT0) can be used to release power-down mode (stop or idle). Interrupts for
power-down mode release are initiated by setting the corresponding interrupt enable flag. Even if the IME flag is
cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag
has been set. In such cases, the interrupt routine will not be executed since IME = "0".
7-2
S3C70F2/C70F4/P70F4
INTERRUPTS
Interrupt is generated (INT xx)
Request flag (IRQx) <-- 1
NO
IEx = 1?
Retain value until IEx = 1
YES
Generate corresponding vector interrupt
and release power-down mode
NO
IME = 1?
Retain value until IME = 1
YES
YES
Retain value until interrupt
service routine is completed
IS1,0 = 0,0?
NO
NO
IS1,0 = 0,1 ?
YES
NO
High-priority interrupt?
YES
IS1,0 = 0,1
IS1,0 = 1,0
Store contents of PC and PSW in the stack area;
set PC contents to corresponding vector address
Reset corresponding IRQx flag
Jump to interrupt start address
Figure 7-1. Interrupt Execution Flowchart
7-3
INTERRUPTS
S3C70F2/C70F4/P70F4
IMOD1
IMOD0
IEW
IET0
IES
IE1
IE0
IEK
IEB
INTB
IRQB
IRQ0
IRQ1
IRQS
IRQT0
IRQW
IRQK
INT0
INT1
#
@
@
INTS
INTT0
INTW
INTK (KS0–KS2)
IMODK
POWER-DOWN
MODE
RELEASE SIGNAL
IME
IPR
INTERRUPT CONTROL UNIT
IS1 IS0
# = Noise filtering circuit
@ = Edge detection circuit
VECTOR INTERRUPT
GENERATOR
Figure 7-2. Interrupt Control Circuit Diagram
7-4
S3C70F2/C70F4/P70F4
INTERRUPTS
MULTIPLE INTERRUPTS
The interrupt controller can serve multiple interrupts in two ways: as two-level interrupts, where either all interrupt
requests or only those of highest priority are served, or as multi-level interrupts, when the interrupt service
routine for a lower-priority request is accepted during the execution of a higher priority routine.
Two-Level Interrupt Handling
Two-level interrupt handling is the standard method for processing multiple interrupts. When the IS1 and IS0 bits
of the PSW (FB0H.3 and FB0H.2, respectively) are both logic zero, program execution mode is normal and all
interrupt requests are served. See Figure 7-3.
Whenever an interrupt request is accepted, IS1 and IS0 are incremented by one, and the values are stored in the
stack along with the other PSW bits. After the interrupt routine has been served, the modified IS1 and IS0 values
are automatically restored from the stack by an IRET instruction.
IS0 and IS1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable
memory bank flag (EMB). Before you can modify an interrupt service flag, however, you must first disable
interrupt processing with a DI instruction.
When you set IS1 to "0" and IS0 to "1", you inhibit all interrupt service routines except for the highest priority in-
terrupt currently defined by the interrupt priority register (IPR).
High or Low Level
Interrupt Processing
(Status 1)
Normal Program
Processing
(Status 0)
High Level Interrupt
Processing
INT Disable
(Status 2)
Set IPR
INT Enable
Low or
High Level
Interrupt
High Level
Interrupt
Generated
Generated
Figure 7-3. Two-Level Interrupt Handling
Multi-Level Interrupt Handling
With multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter-
rupt is being served. This is done by manipulating the interrupt status flags, IS0 and IS1. See Table 7-2.
When an interrupt is requested during normal program execution, the interrupt status flags IS0 and IS1 are set to
"1" and "0", respectively. This setting allows only highest-priority interrupts to be served. When a high-priority
request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority
level can be served. In this way, the high-priority and low-priority requests will be served in parallel.
7-5
INTERRUPTS
S3C70F2/C70F4/P70F4
After INT ACK
Table 7-2. IS1 and IS0 Function
Effect of ISx Bit Setting
Process Status
Before INT
IS1 IS0
IS1
0
IS0
1
0
1
0
0
All interrupt requests are served.
0
1
Only high-priority interrupts as determined by the
current settings in the IPR register are serced.
1
0
2
–
1
1
0
1
No additional interrupt requests will be served.
Value undefined
–
–
–
–
Normal Program
Processing
Single
Interrupt
(Status 0)
2-Level
Interrupt
INT Disable
Set IPR
Status 1
3-Level
INT Disable
Interrupt
INT Enable
Modify Status
INT Enable
Status 0
Low or
High Level
Interrupt
Low or
High Level
Interrupt
High Level
Interrupt
Status 1
Status 2
Generated
Generated
Generated
Status 0
Figure 7-4. Multiple-Level Interrupt Handling
7-6
S3C70F2/C70F4/P70F4
INTERRUPTS
INTERRUPT PRIORITY REGISTER (IPR)
The 4-bit interrupt priority register (IPR) is used to control multi-level interrupt handling. The IPR is mapped to
RAM address FB2H, and its reset value is logic zero. Before the IPR can be modified by 4-bit write instructions,
all interrupts must first be disabled by a DI instruction.
FB2H
IME
IPR.2
IPR.1
IPR.0
By manipulating the IPR settings, you can choose to process all interrupt requests with the same priority level, or
you can select one type of interrupt for high-priority processing. A low-priority interrupt can itself be interrupted by
a high-priority interrupt, but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by
any other interrupt source.
Interrupt
INTB
Default Priority
1
2
3
4
5
INT0
INT1
INTS
INTT0
The MSB of the IPR, the interrupt master enable flag (IME), enables and disables all interrupt processing. Even if
an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the
IME flag is set to logic one.
The IME flag is mapped to FB2H.3 and can be directly manipulated by EI and DI instructions, regardless of the
current enable memory bank (EMB) value.
Table 7-4. Interrupt Priority Register Settings
IPR.2
IPR.1
IPR.0
Result of IPR Bit Setting
Normal interrupt handling according to default priority settings
Process INTB interrupt at highest priority.
Process INT0 interrupts at highest priority.
Process INT1 interrupts at highest priority.
Process INTS interrupts at highest priority.
Process INTT0 interrupts at highest priority.
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
NOTE: When all interrupts are low priority (the lower three bits of the IPR register are logic zero), the interrupt generated
first will become high priority. Therefore, the first generated interrupt cannot be superceded by any other interrupt. If
two or more interrupt requests are received simultaneously, the priority level is determined according to the
standard interrupt priorities in Table 7.4 (e.g., the default priority assigned by hardware when the lower three IPR
bits = "0"). In this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. Then,
when the high-priority interrupt is returned from its service routine by an IRET instruction, the inhibited interrupt
service routine is started.
7-7
INTERRUPTS
S3C70F2/C70F4/P70F4
+
PROGRAMMING TIP — Setting the INT Interrupt Priority
Set the INT1 interrupt to high priority:
BITS
SMB
DI
LD
LD
EMB
15
; IPR.3 (IME) ¬ 0
; IPR.3 (IME) ¬ 1
A,#3H
IPR,A
EI
EXTERNAL INTERRUPT MODE REGISTERS (IMOD0, IMOD1)
The following components are used to process external interrupts at the INT0 and INT1 pin:
— Noise filtering circuit for INT0
— Edge detection circuit
— Two mode registers, IMOD0 and IMOD1
The mode registers are used to control the triggering edge of the input signal. IMOD 0, 1 settings let you choose
either the rising or falling edge of the incoming signal at the INT0 and INT1 pins as the interrupt request trigger.
FB4H
FB5H
IMOD0.3
"0"
"0"
"0"
IMOD0.1
"0"
IMOD0.0
IMOD1.0
IMOD0 and IMOD1 bits are mapped to RAM addresses FB4H (IMOD0) and FB5H (IMOD1), and are addressable
by 4-bit write instructions. RESET clears all IMOD values to logic zero, selecting rising edges as the trigger for
incoming interrupt requests.
Table 7-5. IMOD0 and IMOD1 Register Organization
IMOD0
IMOD0.3
0
IMOD0.1
IMOD0.0
Effect of IMOD0 Settings
Select CPU clock for sampling
Select fx/64 sampling clock
Rising edge detection
0
1
0
0
1
1
0
1
0
1
Falling edge detection
Both rising and falling edge detection
IRQ0 flag cannot be set to "1"
IMOD1
0
0
0
IMOD1.0
Effect of IMOD1 Settings
Rising edge detection
0
1
Falling edge detection
7-8
S3C70F2/C70F4/P70F4
INTERRUPTS
EXTERNAL INTERRUPT 0 and 1 MODE REGISTERS (Continued)
When a sampling clock rate of fx/64 is used for INT0, an interrupt request flag must be cleared before 16 ma-
chine cycles have elapsed. Since the INT0 pin has a clock-driven noise filtering circuit built into it, please take
the following precautions when you use it:
— To trigger an interrupt, the input signal width at INT0 must be at least two times wider than the pulse width of
the clock selected by IMOD0. This is true even when the INT0 pin is used for general-purpose input.
— Since the INT0 input sampling clock does not operate during stop or idle mode, you cannot use INT0 to re-
lease power-down mode.
INT0
NOISE FILTER
EDGE DETECTION
IRQ0
IRQ1
CLOCK
SELECTOR
CPU clock
fx/64
INT1
EDGE DETECTION
IMOD0
IMOD1
P1.1
P1.0
Figure 7-5. Circuit Diagram for INT0 and INT1 Pins
When modifying the IMOD0 and IMOD1 registers, it is possible to accidentally set an interrupt request flag. To
avoid unwanted interrupts, take these precautions when writing your programs:
1. Disable all interrupts with a DI instruction.
2. Modify the IMOD0 or IMOD1 register.
3. Clear all relevant interrupt request flags.
4. Enable the interrupt by setting the appropriate IEx flag.
5. Enable all interrupts with an EI instructions.
7-9
INTERRUPTS
S3C70F2/C70F4/P70F4
KEY INTERRUPT MODE REGISTER (IMODK)
The mode register for external interrupts at the KS0–KS2 pins, IMODK, is a 4-bit register at RAM address FB6H.
IMODK is addressable only by 4-bit write instructions. RESET clears all IMODK bits to logic zero.
FB6H
"0"
IMODK.2 IMODK.1 IMODK.0
When bits in the IMODK register are set to logic one, INTK uses the falling edge of an incoming signal at
corresponding pins as the interrupt request trigger. When a falling edge is detected at any one of the pins KS0–
KS2, the IRQK flag is set to logic one and a release signal for power-down mode is generated.
Table 7-6. IMODK Register Bit Settings
IMODK
0
IMODK.2
IMODK.1
IMODK.0
Effect of IMODK Settings
Disable key interrupt
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Select falling edge at KS0
Select falling edge at KS1
Select falling edge at KS0–KS1
Select falling edge at KS2
Select falling edge at KS0, KS2
Select falling edge at KS1–KS2
Select falling edge at KS0–KS2
KS2
KS1
KS0
FALLING
EDGE
DETECTION
CIRCUIT
IMODK
IRQK
NOTES:
1. To generate a key interrupt on a falling edge at KS0–KS2, all KS0–KS2 pins must be configured
to input mode.
2. If anyone of the KS0-KS2 pins used for interrupt stays low, a key interrupt is not generated.
Since all KS0-KS2 pins are ANDed, the falling edge detection circuit cannot detects a falling edge
Figure 7-6. Circuit Diagram for KS0–KS2 Pins
7-10
S3C70F2/C70F4/P70F4
INTERRUPTS
+
PROGRAMMING TIP — Using INTK as a Key Input Interrupt
When the INTK interrupt used as a key interrupt, the key interrupt pin must be set to input.
1. When KS0–KS2 are selected:
BITS
SMB
LD
EMB
15
A,#7H
LD
LD
LD
LD
IMODK,A
EA,#00H
PMG3,EA
EA,#40H
PUMOD,EA
; (IMODK) ¬ #7H, KS0–KS2 falling edge select
; P6 ¬ Input mode
LD
; Enable P6 pull-up resistors
7-11
INTERRUPTS
S3C70F2/C70F4/P70F4
INTERRUPT FLAGS
There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in-
terrupt, the interrupt master enable flag, which enables or disables all interrupt processing.
Interrupt Master Enable Flag (IME)
The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an
IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the
IME flag is set to logic one.
The IME flag is located in the IPR register (IPR.3), and is mapped to bit address FB2H.3. It can be directly be
manipulated by EI and DI instructions, regardless of the current value of the enable memory bank flag (EMB).
Interrupt Enable Flags (IEx)
IEx flags, when set to logic one, enable specific interrupt requests to be served. When the interrupt request flag
is set to logic one, an interrupt will not be served until its corresponding IEx flag is also enabled.
Interrupt enable flags are mapped to the RAM address area FB8H–FBFH, and can be read, written, or tested
directly by 1-bit instructions (BITS and BITR). IEx flags can be addressed directly at their specific RAM
addresses, despite the current value of the enable memory bank (EMB) flag.
Interrupt Request Flags (IRQx)
Interrupt request flags, located in the RAM area FB8H-FBFH, are read/write addressable by 1-bit or 4-bit in-
structions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value
of the enable memory bank (EMB) flag.
When a specific IRQx lag is set to logic one, the corresponding interrupt request is generated. The flag is then
automatically cleared to logic zero by hardware when the interrupt has been served. Exceptions are the watch
timer interrupt request flag, IRQW, and key interrupt request flag IRQK, which must be cleared by software after
the interrupt service routine has executed. IRQx flags are also used to execute interrupt requests from software.
In summary, follow these guidelines for using IRQx flags:
1. IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.
2. IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been served (with the
exception of IRQW and IRQK).
3. When IRQx is set to "1" by software, an interrupt is generated.
7-12
S3C70F2/C70F4/P70F4
INTERRUPTS
INTERRUPT MASTER ENABLE FLAG (IME)
The interrupt master enable flag, IME, inhibits or enables all interrupt processing. Therefore, even when an IRQx
flag and its corresponding IEx flag is enabled, an interrupt request will not be serviced until the IME flag is set to
logic one. The IME flag is the most significant bit of the 4-bit IPR register at RAM location FB2H.
IME
0
IPR.2
IPR.1
IPR.0
Effect of Bit Settings
Inhibit all interrupts
Enable all interrupts
1
You can manipulate the IME flag using EI and DI instructions, despite the current value of the enable memory
bank (EMB) flag.
INTERRUPT ENABLE FLAGS (IEx)
Interrupt enable flags are used to control the execution of service routines for specific interrupt requests. The
enable flag has priority over a request flag — even if the IRQx flag is enabled, the interrupt request will not be
serviced until the corresponding IEx flag is set to logic one.
Using 1-bit or 4-bit instructions and direct addressing, you can read, write, or test IEx (and IRQx) flags despite
the current enable memory bank (EMB) value. The IEx and IRQx flags are mapped to RAM area FB8H–FBFH.
Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses
Address
FB8H
Bit 3
Bit 2
Bit 1
IEB
IEW
0
Bit 0
IRQB
IRQW
0
0
0
0
FBAH
FBBH
FBCH
FBDH
FBEH
FBFH
0
0
0
0
0
0
IET0
IES
IE0
IEK
IRQT0
IRQS
IRQ0
IRQK
0
IE1
0
IRQ1
0
NOTES:
1. IEx refers generically to all interrupt enable flags.
2. IRQx refers generically to all interrupt request flags.
3. IEx = 0 is interrupt disable mode.
4. IEx = 1 is interrupt enable mode.
7-13
INTERRUPTS
S3C70F2/C70F4/P70F4
INTERRUPT REQUEST FLAGS (IRQx)
When an interrupt request flag (IRQx) is set, a software-generated interrupt is enabled for the corresponding in-
terrupt. IRQx flags can be written by 1- or 4-bit RAM control instructions. IRQx flags are then cleared
automatically when the interrupt has been serviced. Exceptions to the general rule are the watch timer interrupt
request flag, IRQW and key interrupt request flag, IRQK; they must be cleared by software after the interrupt
service routine has executed.
Table 7-8. Interrupt Request Flag Conditions and Priorities
Interrupt
Source
Internal /
External
Pre-condition for IRQx Flag Setting
Interrupt
Priority
IRQx Flag
Name
INTB
INT0
INT1
INTS
I
Reference time interval signal from basic timer
Rising or falling edge detected at INT0 pin
Rising or falling edge detected at INT1 pin
1
2
3
4
IRQB
IRQ0
IRQ1
IRQS
E
E
I
Completion signal for serial transmit-and-receive
or receive-only operation
INTT0
I
Signals for TCNT0 and TREF0 registers coincide
5
IRQT0
IRQK
INTK (note)
E
Falling edge is detected at any one of the KS0–
KS2 pins
—
INTW (note)
I
Time interval of 0.5 secs or 3.19 msecs
—
IRQW
NOTE: INTK and INTW are quasi-interrupts and INTK is used only for testing incoming signals.
7-14
S3C70F2/C70F4/P70F4
POWER-DOWN
8
POWER-DOWN
OVERVIEW
The S3C70F2/C70F4 microcontroller has two power-down modes to reduce power consumption: idle and stop.
Idle mode is initiated by the IDLE instruction and stop mode by the instruction STOP. (Several NOP instructions
must always follow an IDLE or STOP instruction in a program.) In idle mode, the CPU clock stops while pe-
ripherals and the oscillation source continue to operate normally.
When RESET occurs during normal operation or during a power-down mode, a reset operation is initiated and
the CPU enters idle mode. When the standard oscillation stabilization time interval (31.3 ms at 4.19 MHz) has
elapsed, normal CPU operation resumes.
In stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hardware
components are powered-down. The effect of stop mode on specific peripheral hardware components — CPU,
basic timer, serial I/O, timer/ counters 0, and watch timer — and on external interrupt requests, is detailed in
Table 8-1.
NOTE
Do not use stop mode if you are using an external clock source because X input must be restricted
in
internally to V to reduce current leakage.
SS
Idle or stop modes are terminated either by a RESET, or by an interrupt with the exception of INT0, which are
enabled by the corresponding interrupt enable flag, IEx. When power-down mode is terminated by RESET input,
a normal reset operation is executed. Assuming that both the interrupt enable flag and the interrupt request flag
are set to "1", power-down mode is released immediately upon entering power-down mode.
When an interrupt is used to release power-down mode, the operation differs depending on the value of the
interrupt master enable flag (IME):
— If the IME flag = "0", program execution is started immediately after the instruction which issues the request
to enter power-down mode. The interrupt request flag remains set to logic one.
— If the IME flag = "1", two instructions are executed after the power-down mode release. Then, the vectored
interrupt is initiated. However, when the release signal is caused by INTK or INTW, the operation is identical
to the IME = 0 condition. That is, a vector interrupt is not generated.
8-1
POWER-DOWN
S3C70F2/C70F4/P70F4
Table 8-1. Hardware Operation During Power-Down Modes
Operation
Stop Mode (STOP)
Idle Mode (IDLE)
CPU clock oscillation stops (system
Clock oscillator
System clock oscillation stops
clock oscillation continues)
Basic timer
Basic timer stops
Basic timer operates (with IRQB set at
each reference interval)
Serial interface
Operates if a clock other than the CPU
clock is selected as the serial I/O clock
Operates only if external SCK input is
selected as the serial I/O clock
Timer/counter 0
Operates only if TCL0 is selected as the Timer/counter 0 operates
counter clock
Comparator
Comparator operation is stopped
Watch timer operation is stopped
Comparator operates
Watch timer operates
Watch timer
External interrupts
INT1 and INTK are acknowledged; INT0 INT1 and INTK are acknowledged;
is not serviced
INT0 is not serviced
CPU
All CPU operations are disabled
All CPU operations are disabled
Power-down mode
release signal
Interrupt request signals (except INT0)
are enabled by an interrupt enable flag or are enabled by an interrupt enable flag or
by RESET input by RESET input
Interrupt request signals (except INT0)
8-2
S3C70F2/C70F4/P70F4
POWER-DOWN
IDLE MODE TIMING DIAGRAMS
OSCILLATION
STABILIZATION
(31.3 ms / 4.19 MHz)
IDLE
INSTRUCTION
RESET
NORMAL MODE
IDLE MODE
NORMAL MODE
NORMAL OSCILLATION
CLOCK
SIGNAL
Figure 8-1. Timing When Idle Mode is Released by RESET
IDLE
INSTRUCTION
MODE
RELEASE
SIGNAL
INTERRUPT ACKNOWLEDGE (IME = 1)
NORMAL MODE
NORMAL MODE
IDLE MODE
NORMAL OSCILLATION
CLOCK
SIGNAL
Figure 8-2. Timing When Idle Mode is Released by an Interrupt
8-3
POWER-DOWN
S3C70F2/C70F4/P70F4
STOP MODE TIMING DIAGRAMS
OSCILLATION
STABILIZATION
(31.3 ms / 4.19 MHz)
STOP
INSTRUCTION
RESET
NORMAL MODE
STOP MODE
IDLE MODE
NORMAL MODE
OSCILLATION
STOPS
OSCILLATION RESUMES
CLOCK
SIGNAL
Figure 8-3. Timing When Stop Mode is Released by RESET
OSCILLATION
STABILIZATION
STOP
(BMOD SETTING)
INSTRUCTION
INT ACK (IME = 1)
NORMAL MODE
MODE
RELEASE
SIGNAL
NORMAL MODE
STOP MODE
IDLE MODE
OSCILLATION
STOPS
OSCILLATION RESUMES
CLOCK
SIGNAL
Figure 8-4. Timing When Stop Mode is Released by an Interrupt
8-4
S3C70F2/C70F4/P70F4
POWER-DOWN
I/O PORT PIN CONFIGURATION FOR POWER-DOWN
The following method describes how to configure I/O port pins to reduce power consumption during power-down
modes (stop, idle):
Condition 1:
If the microcontroller is not configured to an external device:
1. Connect unused port pins according to the information in Table 8-2.
2. Disable all pull-up resistors for output pins by making the appropriate modifications to the pull-up resistor
mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be un-
expected surges of current through the pull-up.
3. Disable pull-up resistors for input pins configured to V
DD
or V levels in order to check the current input
SS
option. Reason: If the input level of a port pin is set to V when a pull-up resistor is enabled, it will draw an
SS
unnecessarily large current.
Condition 2: If the microcontroller is configured to an external device and the external device's V
source is
DD
turned off in power-down mode.
1. Connect unused port pins according to the information in Table 8-2.
2. Disable the pull-up resistors of output pins by making the appropriate modifications to the pull-up resistor
mode register, PUMOD. Reason: If output goes low when the pull-up resistor is enabled, there may be un-
expected surges of current through the pull-up.
3. Disable pull-up resistors for input pins configured to V
DD
or V levels in order to check the current input
SS
option. Reason: If the input level of a port pin is set to V when a pull-up resistor is enabled, it will draw an
SS
unnecessarily large current.
4. Disable the pull-up resistors of input pins connected to the external device by making the necessary modi-
fications to the PUMOD register.
5. Configure the output pins that are connected to the external device to low level. Reason: When the external
device's V
source is turned off, and if the microcontroller's output pins are set to high level, V
of the external device through its input pin. This causes the device to operate at the
DD
– 0.7 V. In this case, total current consumption would not be reduced.
– 0.7 V is
DD
supplied to the V
DD
level V
DD
6. Determine the correct output pin state necessary to block current pass in according with the external tran-
sistors (PNP, NPN).
8-5
POWER-DOWN
S3C70F2/C70F4/P70F4
RECOMMENDED CONNECTIONS FOR UNUSED PINS
To reduce overall power consumption, please configure unused pins according to the guidelines described in
Table 8-2.
Table 8-2. Unused Pin Connections for Reducing Power Consumption
Pin/Share Pin Names
P0.0/SCK
Recommended Connection
Input mode: Connect to V
DD
Output mode: Do not connect
P0.1/SO
P0.2/SI
Connect to V
DD
P1.0/INT0 – P1.1/INT1
Connect to V
DD
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
P3.1/TCLO0
P3.2/CLO
P4.0–P4.3
P5.0–P5.3
P6.0/KS0 – P6.2/KS2
P6.3/BUZ
Connect to VSS
Test
8-6
S3C70F2/C70F4/P70F4
RESET
9
RESET
OVERVIEW
When a RESET signal is input during normal operation or power-down mode, a reset operation is initiated and
the CPU enters idle mode. Then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 MHz has
elapsed, normal system operation resumes.
Regardless of when the RESET occurs — during normal operating mode or during power-down mode — the
effect on most hardware register values is almost identical. The exceptions are as follows:
— Carry flag
— Data memory values
— General-purpose registers E, A, L, H, X, W, Z, and Y
— Serial I/O buffer register (SBUF)
If a RESET occurs during idle or stop mode, the current values in these registers are retained. Otherwise, their
values are undefined.
OSCILLATION
STABILIZATION
(31.3 ms / 4.19 MHz)
RESET
INPUT
NORMAL MODE
IDLE MODE
OPERATING MODE
OR
POWER-DOWN
MODE
RESET OPERATION
Figure 9-1. Timing for Oscillation Stabilization After RESET
HARDWARE REGISTER VALUES AFTER RESET
Table 9-1 gives you detailed information about hardware register values after a RESET occurs during power-
down mode or during normal operation.
9-1
RESET
S3C70F2/C70F4/P70F4
Table 9-1. Hardware Register Values After RESET
Hardware Component
or Subcomponent
If RESET Occurs During
If RESET Occurs During
Power-Down Mode
Normal Operation
Program counter (PC)
Lower three bits of address 0000H Lower three bits of address
are transferred to PC11-8, and the 0000H are transferred to PC11-8,
contents of 0001H to PC7-0.
and the contents of 0001H to
PC7-0.
Program Status Word (PSW):
Carry flag (C)
Retained
Undefined
Skip flag (SC0-SC2)
0
0
0
0
Interrupt status flags (IS0, IS1)
Bank enable flags (EMB, ERB)
Bit 6 of address 0000H in program Bit 6 of address 0000H in
memory is transferred to the ERB program memory is transferred
flag, and bit 7 of the address to
the EMB flag.
to the ERB flag, and bit 7 of the
address to the EMB flag.
Stack pointer (SP)
Undefined
Undefined
Data Memory (RAM):
General registers E, A, L, H, X, W, Z, Y
General-purpose registers
Bank selection registers (SMB, SRB)
BSC register (BSC0-BSC3)
Clocks:
Values retained
Undefined
Undefined
0, 0
(Note)
Values retained
0, 0
0
0
Power control register (PCON)
Clock output mode register (CLMOD)
Interrupts:
0
0
0
0
Interrupt request flags (IRQx)
Interrupt enable flags (IEx)
Interrupt priority flag (IPR)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Interrupt master enable flag (IME)
INT0 mode register (IMOD0)
INT1 mode register (IMOD1)
INTK mode register (IMODK)
NOTE: The values of the 0F8H-0FDH are not retained when a RESET signal is input
9-2
S3C70F2/C70F4/P70F4
RESET
Table 9-1. Hardware Register Values After RESET (Continued)
Hardware Component
or Subcomponent
If RESET Occurs During
If RESET Occurs During
Power-Down Mode
Normal Operation
I/O Ports:
Output buffers
Off
0
Off
0
Output latches
Port mode flags (PM)
0
0
Pull-up resistor mode reg (PUMOD)
Port 2 mode register (P2MOD)
N-channel open-drain mode register (PNE)
Watch-dog Timer:
0
0
0
0
0
0
WDT mode register (WDMOD)
WDT clear flag (WDTCF)
Basic Timer:
A5H
0
A5H
0
Count register (BCNT)
Mode register (BMOD)
Timer/Counter 0:
Undefined
0
Undefined
0
Count registers (TCNT0)
Reference registers (TREF0)
Mode registers (TMOD0)
Output enable flags (TOE0)
Watch Timer:
0
0
FFH, FFFFH
FFH, FFFFH
0
0
0
0
Watch timer mode register (WMOD)
0
0
Comparator
Comparator mode register (CMOD)
Comparison result register (CMPREG)
Serial I/O Interface:
0
0
Undefined
Undefined
SIO mode register (SMOD)
SIO interface buffer (SBUF)
0
0
Values retained
Undefined
9-3
S3C70F2/C70F4/P70F4
I/O PORTS
10 I/O PORTS
OVERVIEW
The S3C70F2/C70F4 has 2 input ports and 5 I/O ports. Pin addresses for all I/O ports are mapped to locations
FF0H–FF6H in bank 15 of the RAM. The contents of I/O port pin latches can be read, written, or tested at the
corresponding address using bit manipulation instructions.
There are total of 6 input pins and 18 configurable I/O pin, including 8 high current I/O pins for a maximum
number of 24 I/O pins.
Port Mode Flags
Port mode flags (PM) are used to configure I/O ports 0 and 3 (port mode group 1), port 4 (port mode group 2),
and ports 5 and 6 (port mode group 3) to input or output mode by setting or clearing the corresponding I/O buffer.
PM flags are stored in three 8-bit registers in RAM area FE8H–FEDH, and are addressable by 8-bit write
instructions only.
Port 2 Mode Register
Port 2 (P2.0–P2.3) can be used as either for analog input or for digital input. P2MOD register settings determines
port 2 mode (analog or digital input) for specific port 2 pins.
Pull-Up Resistors
Pull-up resistors are assignable to input pins of ports 0, 1, 3, 4, 5 and 6. When a configurable I/O port pin serves
as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up resistor is
enabled by a corresponding bit setting in the pull-up resistor mode register (PUMOD).
PUMOD Control Register
The pull-up mode register (PUMOD) is an 8-bit register used to assign internal pull-up resistors by software to
specific I/O ports.
When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor is automatically disabled,
even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.
PUMOD is mapped to RAM address FDCH–FDDH and is addressable by 8-bit write instructions only. RESET
clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up
resistors.
10-1
I/O PORTS
S3C70F2/C70F4/P70F4
Table 10-1. I/O Port Overview
Port
I/O
Pins
Pin Names
Address
Function Description
3-bit I/O port.
0
I/O
3
P0.0–P0.2
FF0H
1-bit and 3-bit read/write and test is possible.
Individual pins are software configurable as in-
put or output. 3-bit pull-up resistors are
assignable by software.
1
2
I
I
2
4
P1.0–P1.1
FF1H
2-bit input port.
1-bit and 2-bit read and test is possible.
2-bit pull-up resistors are software assignable.
P2.0–P2.3
P3.0–P3.2
FF2H
FF3H
4-bit analog or digital input port.
1-bit or 4-bit read and test possible.
3
I/O
I/O
3
8
Same as port 0.
4, 5
P4.0–P4.3
P5.0–P5.3
FF4H
FF5H
4-bit I/O ports. 1-, 4-, and 8-bit read/write/test
is possible. Pins are individually configurable
as input or output. Ports 4 and 5 can be paired
to support 8-bit data transfer. 4-bit pull-up
registers are software assignable to input pins
and are automatically disabled for output pins.
The N-channel open drain or push-pull output
can be selected by software (1-bit unit)
6
I/O
4
P6.0–P6.3
FF6H
4-bit I/O ports. Pins are individually software
configurable as input or output. 1-bit and 4-bit
read/write/test is possible. 4-bit pull-up
resistors are software assignable.
Table 10-2. I/O Port Pin Status During Instruction Execution
Instruction Type
Example
Input Mode Status
Output Mode Status
1-bit test
BTST P0.1
Input or test data at each pin
Input or test data at output latch
1-bit input
4-bit input
8-bit input
LDB
LD
LD
C,P1.3
A,P6
EA,P4
1-bit output
BITR P3.0
Output latch contents undefined
Output pin status is modified
4-bit output
8-bit output
LD
LD
P2,A
P6,EA
Transfer accumulator data to the Transfer accumulator data to the
output latch output pin
10-2
S3C70F2/C70F4/P70F4
I/O PORTS
PORT MODE FLAGS (PM FLAGS)
Port mode flags (PM) are used to configure I/O ports 0 and 3–6 to input or output mode by setting or clearing the
corresponding I/O buffer. PM flags are stored in three 8-bit registers in RAM area FE8H–FEDH, and are ad-
dressable by 8-bit write instructions only.
For convenient program reference, PM flags are organized into three groups — PMG1, PMG2, and PMG3, as
shown in Table 10-3.
Table 10-3. Port Mode Groups and Corresponding I/O Ports
Port Mode Group ID
PMG1
Corresponding I/O Ports
Ports 0 and 3
Port Mode Group Address
FE8H–FE9H
PMG2
Port 4
FEAH–FEBH
PMG3
Ports 5 and 6
FECH–FEDH
When a PM flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. RESET clears
all port mode flags to logic zero, automatically configuring the corresponding I/O ports to input mode.
Table 10-4. Port Mode Flag Map
PM Group ID
Address
FE8H
Bit 3
"0"
Bit 2
PM0.2
PM3.2
PM4.2
"0"
Bit 1
PM0.1
PM3.1
PM4.1
"0"
Bit 0
PM0.0
PM3.0
PM4.0
"0"
PMG1
FE9H
"0"
PMG2
PMG3
FEAH
FEBH
FECH
FEDH
PM4.3
"0"
PM5.3
PM6.3
PM5.2
PM6.2
PM5.1
PM6.1
PM5.0
PM6.0
NOTE: If bit = "0", the corresponding I/O pin is set to input mode. If bit = "1", the pin is set to output mode. All flags are
cleared to "0" following RESET.
+
PROGRAMMING TIP — Configuring I/O Ports as Input or Output
Configure P0.0 and P3.0 as an output port and the other ports as input ports:
BITS
SMB
LD
LD
LD
LD
LD
LD
EMB
15
EA,#11H
PMG1,EA
EA,#00H
PMG2,EA
EA,#00H
PMG3,EA
; P0.0 and P3.0 ¬ Output
; P4 ¬ Input
; P5, P6 ¬ Input
10-3
I/O PORTS
S3C70F2/C70F4/P70F4
PORT 2 MODE REGISTER (P2MOD)
P2MOD register settings determine if port 2 is used either for analog input or for digital input. P2MOD register is
4-bit write only register. P2MOD is mapped to address FE2H and initialized to zero by a RESET, configuring port
2 as an analog input port.
FE2H
P2MOD.3 P2MOD.2 P2MOD.1 P2MOD.0
When bit is set to "1", the corresponding pin is configured as a digital input pin. When set to "0", configured as an
analog input pin: P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3 for P2.3.
PULL-UP RESISTOR MODE REGISTER (PUMOD)
The pull-up resistor mode register (PUMOD) is an 8-bit register used to assign internal pull-up resistors by soft-
ware to specific I/O ports. When a configurable I/O port pin is used as an output pin, its assigned pull-up resistor
is automatically disabled, even though the pin's pull-up is enabled by a corresponding PUMOD bit setting.
PUMOD is mapped to RAM address FDCH–FDDH and is addressable by 8-bit write instructions only. RESET
clears PUMOD register values to logic zero, automatically disconnecting all software-assignable port pull-up
resistors.
Table 10-5. Pull-Up Resistor Mode Register (PUMOD) Organization
Address
FDCH
Bit 3
PUMOD.3
"0"
Bit 2
"0"
Bit 1
Bit 0
PUMOD.1
PUMOD.5
PUMOD.0
PUMOD.4
FDDH
PUMOD.6
NOTE: When bit = "1", a pull-up resistor is assigned to the corresponding I/O port: PUMOD.3 for port 3, PUMOD.6 for
port 6, and so on.
N-CHANNEL OPEN-DRAIN ENABLE REGISTER (PNE)
Address
FDAH
Bit 3
Bit 2
Bit 1
Bit 0
PNE
PNE4.3
PNE5.3
PNE4.2
PNE5.2
PNE4.1
PNE5.1
PNE4.0
PNE5.0
FDBH
The N-channel, open-drain mode register, PNE, is used to configure ports 4 and 5 to n-channel open-drain mode
or as push-pull outputs.
When a bit in the PNE register is set to "1", the corresponding output pin is configured to n-channel open-drain,
when set to "0", the output pin is configured to push-pull; PNE4.3 for P4.3, PNE4.2 for P4.2, PNE4.1 for P4.1,
PNE4.0 for P4.0, PNE5.3 for P5.3, PNE5.2 for P5.2, PNE5.1 for P5.1 and PNE5.0 for P5.0.
+
PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors
P6 enable pull-up resistors, P0, P1, P3, P4 and P5 disable pull-up resistors.
BITS
SMB
LD
EMB
15
EA,#40H
PUMOD,EA
LD
; P6 enable
10-4
S3C70F2/C70F4/P70F4
I/O PORTS
PORT 0 CIRCUIT DIAGRAM
SCK
SMOD.1
SO
P0.0
P0.1
P0.2
LATCH
LATCH
LATCH
SMOD.7
SMOD.6
SMOD.5
VDD
SCK
SI
PUMOD.0
PUMOD.0
PUMOD.0
PM0.2
PM0.1
PM0.0
P0.0 /
SCK
P0.1 / SO
P0.2 / SI
When a port pin acts as an output, its pull-up resistor is automatically disabled,
even though the port's pull-up resistor is enabled by bit settings to the pull-up
resistor mode register (PUMOD).
NOTE:
Figure 10-1. I/O Port 0 Circuit Diagram
10-5
I/O PORTS
S3C70F2/C70F4/P70F4
PORT 1 CIRCUIT DIAGRAM
VDD
VDD
INT0
INT1
PUMOD.1
IMOD0
N/R
Circuit
P1.0 / INT0
P1.1 / INT1
N/R = Noise reduction
Figure 10-2. Input Port 1 Circuit Diagram
10-6
S3C70F2/C70F4/P70F4
I/O PORTS
PORT 2 CIRCUIT DIAGRAM
P2.0 / CIN0
P2.1 / CIN1
P2.2 / CIN2
P2.3 / CIN3
DIGITAL INPUT
ANALOG INPUT
DIGITAL INPUT
ANALOG INPUT
DIGITAL INPUT
ANALOG INPUT
DIGITAL INPUT
ANALOG INPUT
EXTERNAL REFERENCE
Figure 10-3. Port 2 Circuit Diagram
10-7
I/O PORTS
S3C70F2/C70F4/P70F4
PORT 3 CIRCUIT DIAGRAM
VDD
TC0 CLOCK OUTPUT
CLOCK OUTPUT
PUMOD.3
PUMOD.3
PUMOD.3
PM3.2
PM3.1
PM3.0
P3.0 / TCL0
P3.1 / TCLO0
P3.2 / CLO
OUTPUT
LATCH
1, 4
M
U
X
1, 4
TCL0
When a port pin acts as an output, its pull-up resistor is automatically disabled,
even though the port's pull-up resistor is enabled by bit settings to the pull-up
resistor mode register (PUMOD).
NOTE:
Figure 10-4. Port 3 Circuit Diagram
10-8
S3C70F2/C70F4/P70F4
I/O PORTS
PORTS 4 AND 5 CIRCUIT DIAGRAM
VDD
b=4, 5
P-CH
8
8
PUMOD.b
PNE
P-CH
OUTPUT
LATCH
Px.b
1, 4, 8
N-CH
8
PMx.b
x=4, 5
b=0, 1, 2, 3
VSS
M
U
X
Figure 10-5. Circuit Diagram for Port 4 and 5
10-9
I/O PORTS
S3C70F2/C70F4/P70F4
PORT 6 CIRCUIT DIAGRAM
V
DD
PUMOD.6
PUMOD.6
PUMOD.6
PUMOD.6
PM6.3
PM6.2
PM6.1
PM6.0
P6.0 / KS0
P6.1 / KS1
P6.2 / KS2
P6.3 / BUZ
OUTPUT
1, 4
LATCH
M
1, 4
U
X
When a port pin acts as an output, its pull-up resistor is automatically disabled,
even though the port's pull-up resistor is enabled by bit settings to the pull-up
resistor mode register (PUMOD).
NOTE:
Figure 10-6. Port 6 Circuit Diagram
10-10
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
11 TIMERS and TIMER/COUNTERS
OVERVIEW
There are three timer and timer/counter function modules:
— 8-bit basic timer (BT)
— 8-bit timer/counter 0 (TC0)
— Watch timer (WT)
The 8-bit basic timer (BT) is the microcontroller's main interval timer. It generates a interrupt request at a fixed
time interval by making the appropriate modification to the mode register.
The basic timer also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time
when stop mode is released by an interrupt or a RESET.
The 8-bit timer/counter 0 (TC0) is programmable timer/counter that is used primarily for event counting and for
clock frequency modification and output. In addition, TC0 generates a clock signal that can be used by the serial
I/O interface.
The watch timer (WT) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency
divider circuit. Watch timer functions include real-time and watch-time measurement, system clock interval
timing, and generation of buzzer output.
11-1
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
BASIC TIMER (BT)
OVERVIEW
The 8-bit basic timer (BT) has five functional components:
— Clock selector logic
— 4-bit mode register (BMOD)
— 8-bit counter register (BCNT)
— Watchdog timer control register (WDMOD)
— Watchdog timer clear flag (WDTCF)
The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock.
You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize
clock oscillation when stop mode is released by an interrupt or RESET.
Use the basic timer mode register, BMOD, to turn the BT on and off, to select input clock frequency, and to con-
trol interrupt or stabilization intervals.
Interval Timer Function
The measurement of elapsed time intervals is the basic timer's primary function. The standard interval is 256 BT
clock pulses.
To restart the basic timer, set bit 3 of the mode register BMOD to logic one. The input clock frequency and the
interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2–BMOD.0.
The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the
frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs.
An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time
interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting
continues from 00H.
Watchdog Timer Function
The basic timer can also be used as a "watch-dog" timer to detects inadvertent program loop, that is, system or
program operation error. For this purpose, instruction that clears the watch-dog timer(BITS WDTCF) should be
executed at proper points in a program within a given period. If an instruction that clears the watch-dog timer is
not executed within the period and the watch-dog timer overflows, reset signal is generated and system is
restarted with reset status. An operation of watch-dog timer is as follows:
¾
¾
Write some value(except #5AH) to Watch-Dog Timer Mode register, WDMOD.
If WDCNT overflows, system reset is generated.
Oscillation Stabilization Interval Control
Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also
determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when
power-down mode is released by an interrupt. When a RESET signal is generated, the standard stabilization
interval for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
11-2
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
Table 11-1. Basic Timer Register Overview
Register
Name
Type
Description
Size
RAM
Address
Addressing
Mode
Reset
Value
BMOD
Control Controls the clock frequency (mode) 4-bit
of the basic timer; also, the
F85H
4-bit write-
only;
"0"
oscillation stabilization interval after
BMOD.3: also
1-bit writeable
power-down mode release or RESET
U (note)
A5H
"0"
BCNT
Counter Counts clock pulses matching the
BMOD frequency setting
8-bit
F86H–F87H
F98H–F99H
F9AH.3
8-bit
read-only
WDMOD Control Controls watch-dog timer operation. 8-bit
8-bit write-
only
WDTCF Control Clear the watch-dog timer's counter. 1-bit
1-bit write-
only
NOTE: 'U' means the value is undetermined after a RESET.
"CLEAR" SIGNAL
CLEAR
IRQB
CLEAR
BCNT
BITS
INSTRUCTION
BMOD.3
INTERRUPT
REQUEST
1-BIT R/W
BMOD.2
OVERFLOW
CLOCK
4
BCNT
IRQB
SELECTOR
BMOD.1
BMOD.0
8
CPU CLOCK
START SIGNAL
(POWER-DOWN RELEASE)
CLOCK INPUT
1 pulse period=BT input clock 28 (1/2 duty)
3-BIT COUNTER
OVERFLOW
RESET
GENERATION
RESET
WDTCNT
WDMOD
8
WDTCF
DELAY
CLEAR
WAIT* RESET STOP
*WAIT means
-Stabilization time after RESET
- Stabilization time after STOP mode release
BITS
INSTRUCTION
Figure 11-1. Basic Timer Circuit Diagram
11-3
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
BASIC TIMER MODE REGISTER (BMOD)
The basic timer mode register, BMOD, is a 4-bit write-only register located at RAM address F85H. Bit 3, the basic
timer start control bit, is also 1-bit addressable. All BMOD values are set to logic zero following RESET and
interrupt request signal generation is set to the longest interval. (BT counter operation cannot be stopped.) BMOD
settings have the following effects:
— Restart the basic timer,
— Control the frequency of clock signal input to the basic timer, and
— Determine time interval required for clock oscillation to stabilize following the release of stop modes by an
interrupt.
By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency
12
5
during program execution. Four BT frequencies, ranging from fx/2 (1.02 kHz) to fx/2 (131 kHz), are se-
12
lectable. Since BMOD's reset value is logic zero, the default clock frequency setting is fx/2 . (kHz frequencies
assume a system clock (fx) frequency of 4.19 MHz.)
The most significant bit of the BMOD register, BMOD.3, is used to start the basic timer again. When BMOD.3 is
set to logic one (enabled) by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT
interrupt request flag (IRQB) are both cleared to logic zero, and timer operation is restarted.
The combination of bit settings in the remaining three registers — BMOD.2, BMOD.1, and BMOD.0 — determine
the clock input frequency and oscillation stabilization interval.
Table 11-2. Basic Timer Mode Register (BMOD) Organization
BMOD.3
Basic Timer Enable/Disable Control Bit
1
Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0"
BMOD.2
BMOD.1
BMOD.0
Basic Timer Input Clock
fx/212 (1.02 kHz)
fx/29 (8.18 kHz)
Oscillation Stabilization
220/fx (250 ms)
0
0
1
1
0
1
0
1
0
1
1
1
217/fx (31.3 ms)
fx/27 (32.7 kHz)
215/fx (7.82 ms)
fx/25 (131 kHz)
213/fx (1.95 ms)
NOTES:
1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fx) of 4.19 MHz.
2. fx = system clock frequency.
3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released.
4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
11-4
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
BASIC TIMER COUNTER (BCNT)
BCNT is an 8-bit counter register for the basic timer. It is mapped to RAM addresses F86H–F87H and can be
addressed by 8-bit read instructions.
RESET leaves the BCNT register value undetermined. BCNT is automatically cleared to logic zero whenever the
BMOD register control bit (BMOD.3) is set to "1" to restart the basic timer. It is incremented each time a clock
pulse of the frequency determined by the current BMOD bit settings is detected.
When BCNT has incremented to hexadecimal 'FFH' (256 clock pulses), it is cleared to '00H' and an overflow is
generated. The overflow causes the interrupt request flag, IRQB, to be set to logic one. When the interrupt
request is generated, BCNT immediately resumes counting incoming clock signals.
NOTE
Always execute a BCNT read operation twice to eliminate the possibility of reading unstable data while
the counter is incrementing. If, after two consecutive reads, the BCNT values match, you can select the
latter value as valid data. Until the results of the consecutive reads match, however, the read operation
must be repeated until the validation condition is met.
BASIC TIMER OPERATION SEQUENCE
The basic timer's sequence of operations may be summarized as follows:
1. Set bit BMOD.3 to logic one to restart basic timer operation
2. BCNT is incremented by one after each clock pulse corresponding to BMOD selection
3. BCNT overflows if BCNT ³ 255 (FFH)
4. When an overflow occurs, the IRQB flag is set to logic one by hardware
5. The interrupt request is generated
6. BCNT is automatically cleared to logic zero (BCNT = 00H)
7. BCNT resumes counting BT clock pulse
11-5
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
+
PROGRAMMING TIP — Using the Basic Timer
1. To read the basic timer count register (BCNT):
BITS
SMB
LD
LD
LD
EMB
15
BCNTR
EA,BCNT
YZ,EA
EA,BCNT
EA,YZ
BCNTR
CPSE
JR
2. When stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms:
BITS
SMB
LD
EMB
15
A,#0BH
BMOD,A
LD
; Wait time is 31.3 ms
STOP
NOP
NOP
NOP
; Set stop power-down mode
NORMAL
OPERATING MODE
NORMAL
OPERATING MODE
STOP MODE
IDLE MODE
(31.3 ms)
CPU
OPERATION
STOP
INSTRUCTION
STOP MODE IS
RELEASED BY
INTERRUPT
3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz):
BITS
SMB
LD
EMB
15
A,#0FH
BMOD,A
LD
EI
BITS
IEB
; Basic timer interrupt enable flag is set to "1"
4. Clear BCNT and the IRQB flag and restart the basic timer:
BITS
SMB
BITS
EMB
15
BMOD.3
11-6
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
WATCH-DOG TIMER MODE REGISTER (WDMOD)
The watch-dog timer mode register, WDMOD, is a 8-bit write-only register located at RAM address F98H - F99H.
WDMOD register controls to enable or disable the watch-dog timer function. WDMOD values are set to logic
"A5H" following RESET and this value enable the watch-dog timer, and watch-dog timer's period is set to the
longest interval because BT overflow signal is generated with the longest interval. (BT counter operation cannot
be stopped.)
WDMOD – Watchdog Timer Mode Control Register
F99H, F98H
Bit
7
.7
1
6
.6
0
5
.5
1
4
.4
0
3
.3
0
2
.2
1
1
.1
0
0
.0
1
Identifier
RESET Value
Read/Write
W
W
W
W
W
W
W
W
WDMOD
Watch-Dog Timer Enable/Disable Control
Disable Watch-dog timer function
5AH
Any other Value
Enable Watch-dog timer function
WATCH-DOG TIMER COUNTER (WDCNT)
WDCNT is an 3-bit counter. WDCNT is automatically cleared to logic zero whenever the WDTCF register control
bit (WDTCF) is set to "1" to restart the WDCNT. Reset, stop, and wait signal clear the WDCNT to logic zero also.
WDCNT is incremented each time a clock pulse of the overflow frequency determined by the current BMOD bit
settings. When WDCNT has incremented to hexadecimal '07H' (8 BT overflow pulses), it is cleared to '00H' and
an overflow is generated. The overflow causes the system reset. When the interrupt request is generated, BCNT
immediately resumes counting incoming clock signals.
WATCH-DOG TIMER COUNTER CLEAR FLAG(WDTCF)
WDTCF(F9AH.3) setting clear the WDT's counter to zero and restart the WDT's counter.
Table 11-3. Watch-Dog Timer Interval Time
BMOD
x000b
x011b
x101b
x111b
BT Input Clock
WDCNT input clock
WDT interval time
Main clock
212 /fx
2 sec
212 /fx ´ 28
212 /fx ´ 28 ´ 23
29/fx
27/fx
25/fx
250 msec
62.5 msec
15.6 msec
29/fx ´ 28
27/fx ´ 28
25/fx ´ 28
29/fx ´ 28 ´ 23
27/fx ´ 28 ´ 23
25/fx ´ 28 ´ 23
NOTES:
1. Clock frequencies assume a system oscillator clock frequency (fx) of: Main clock 4.19MHz
2. fx = system clock frequency.
11-7
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
8-BIT TIMER/COUNTER 0 (TC0)
Timer/counter 0 (TC0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of
incoming square wave signals. To indicate that an event has occurred, or that a specified time interval has
elapsed, TC0 generates an interrupt request. By counting signal transitions and comparing the current counter
value with the reference register value, TC0 can be used to measure specific time intervals.
TC0 has a reloadable counter that consists of two parts: an 8-bit reference register (TREF0) into which you write
the counter reference value, and an 8-bit counter register (TCNT0) whose value is automatically incremented by
counter logic.
An 8-bit mode register, TMOD0, is used to activate the timer/counter 0 and to select the basic clock frequency to
be used for timer/counter 0 operations. You can modify the basic frequency dynamically by loading new values
into TMOD0 during program execution.
TC0 FUNCTION SUMMARY
8-bit programmable timer
External event counter
Generates interrupts at specific time intervals based on the selected clock fre-
quency.
Counts various system "events" based on edge detection of external clock sig-
nals at the TC0 input pin, TCL0. To start the event counting operation,
TMOD0.2 is set to "1" and TMOD0.6 is cleared to "0".
Arbitrary frequency output
External signal divider
Outputs selectable clock frequencies to the TC0 output pin, TCLO0.
Divides the frequency of an incoming external clock signal according to a
modifiable reference value (TREF0), and outputs the modified frequency to the
TCLO0 pin.
Serial I/O clock source
Outputs a modifiable clock signal for use as the SCK clock source.
11-8
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
TC0 COMPONENT SUMMARY
Mode register (TMOD0)
Activates the timer/counter 0 and selects the internal clock frequency or the
external clock source at the TCL0 pin.
Reference register (TREF0)
Counter register (TCNT0)
Clock selector circuit
8-bit comparator
Stores the reference value for the desired number of clock pulses between in-
terrupt requests.
Counts internal or external clock pulses based on the bit settings in TMOD0
and TREF0.
Together with the mode register (TMOD0), lets you select one of four internal
clock frequencies, or external clock frequency.
Determines when to generate an interrupt by comparing the current value of
the counter register (TCNT0) with the reference value previously programmed
into the reference register (TREF0).
Output latch (TOL0)
Where a TC0 interrupt request or clock pulse is stored pending output to the
serial I/O circuit or to the TC0 output pin, TCLO0.
When the contents of the TCNT0 and TREF0 registers coincide, the
timer/counter 0 interrupt request flag (IRQT0) is set to "1", the status of TOL0
is inverted, and an interrupt is generated.
Output enable flag (TOE0)
You must set this flag to logic one before the contents of the TOL0 latch can
be output to TCLO0.
Interrupt request flag (IRQT0) This flag is cleared when TC0 operation starts and the TC0 interrupt service
routine is executed and is enabled whenever the counter value and reference
value coincide.
Interrupt enable flag (IET0)
Must be set to logic one before the interrupt requests generated by
timer/counter 0 can be processed.
Table 11-4. TC0 Register Overview
Register
Name
Type
Description
Size
RAM
Address
Addressing
Mode
Reset
Value
TMOD0
Control
Controls TC0 enable/disable
(bit 2); clears and resumes
counting operation (bit 3); sets
input clock and clock frequency
(bits 6–4)
8-bit
F90H–F91H
8-bit write-
only;
(TMOD0.3 is
also 1-bit
write-only)
"0"
TCNT0
TREF0
TOE0
Counter
Counts clock pulses matching
the TMOD0 frequency setting
8-bit
8-bit
F94H–F95H
F96H–F97H
F92H.2
8-bit
read-only
"0"
Reference Stores reference value for the
timer/counter 0 interval setting
8-bit
write-only
FFH
"0"
Flag
Controls timer/counter 0 output 1-bit
to the TCLO0 pin
1-bit
write-only
11-9
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
CLOCKS
10
P3.0
6
4
(fx/2 , fx/2 , fx/2 , fx)
TCL0
8
8
TMOD0.7
TMOD0.6
8-BIT
COMPARATOR
TCNT0
TREF0
CLOCK
SELECTOR
TMOD0.5
8
TMOD0.4
CLEAR
TMOD0.3
TMOD0.2
TMOD0.1
TMOD0.0
CLEAR
SET
INVERTED
CLEAR
TOL0
IRQT0
SERIAL
I/O
TCLO0
PM3.1
P3.1 LATCH
TOE0
Figure 11-2. TC0 Circuit Diagram
TC0 ENABLE/DISABLE PROCEDURE
Enable Timer/Counter 0
— Set TMOD.2 to logic one (RAM address F90H.2)
— Set the TC0 interrupt enable flag IET0 to logic one (RAM address FBCH.1)
— Set TMOD0.3 to logic one (RAM address F90H.3)
TCNT0, IRQT0, and TOL0 are cleared to logic zero, and timer/counter operation starts.
Disable Timer/Counter
— Set TMOD0.2 to logic zero (RAM address F90H.2)
Clock signal input to the counter register TCNT0 is halted. The current TCNT0 value is retained and can be read
if necessary.
11-10
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
TC0 PROGRAMMABLE TIMER/COUNTER FUNCTION
Timer/counter 0 can be programmed to generate interrupt requests at various intervals, based on the system
clock frequency you select.
The 8-bit TC0 mode register, TMOD0, is used to activate the timer/counter 0 and to select the clock frequency.
The reference register, TREF0, stores your value for the number of clock pulses to be generated between inter-
rupt requests. The counter register, TCNT0, counts the incoming clock pulses, which are compared to the TREF0
value as TCNT0 is incremented. When there is a match (TREF0 = TCNT0), an interrupt request is generated.
To program timer/counter to generate interrupt requests at specific intervals, you choose one of four internal
clock frequencies (divisions of the system clock, fx) and load your own counter reference value into the TREF0
register.
TCNT0 is incremented each time an internal counter pulse is detected with the reference clock frequency
specified by TMOD0.4–TMOD0.6 settings. To generate an interrupt request, the TC0 interrupt request flag
(IRQT0) is set to logic one, the status of TOL0 is inverted, and the interrupt is generated. The content of TCNT0
is then cleared to 00H, and TC0 continues counting.
The interrupt request mechanism for the programmable timer/counter consists of the TC0 interrupt enable flag
IET0 and the TC0 interrupt request flag IRQT0.
TC0 OPERATION SEQUENCE
The general sequence of operations when using TC0 as a programmable timer/counter can be summarized as
follows:
1. Set TMOD0.2 to "1" to enable TC0
2. Set TMOD0.6 to "1" to enable the system clock (fx) input
n
3. Set TMOD0.5 and TMOD0.4 bits to desired internal frequency (fx/2 )
4. Load a value to TREF0 to specify the interval between interrupt requests
5. Set the TC0 interrupt enable flag (IET0) to "1"
6. Set TMOD0.3 bit to "1" to clear TCNT0, IRQT0, and TOL0, and start counting
7. TCNT0 increments with each internal clock pulse
8. When the comparator shows TCNT0 = TREF0, the IRQT0 flag is set to "1"
9. Output latch (TOL0) logic toggles high or low
10. Interrupt request is generated
11. TCNT0 is cleared to 00H and counting resumes
12. Programmable timer/counter 0 operation continues until TMOD0.2 is cleared to "0".
11-11
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
TC0 EVENT COUNTER FUNCTION
Timer/counter 0 can be used to monitor or detect system 'events' by using the external clock input at the TCL0
pin (I/O port 3.0) as the counter source. The TC0 mode register is used to specify rising or falling edge detection
for incoming clock signals. The counter register TCNT0 is incremented each time the selected state transition of
the external clock signal occurs. To activate the TC0 event counter function,
— Set TMOD0.2 to "1" to enable TC0
— Clear TMOD0.6 to "0" to select the external clock source at the TCL0 pin
— Select TCL0 edge detection for rising or falling signal edges by loading the appropriate values to TMOD0.5
and TMOD0.4.
— P3.0 must be set to input mode.
Table 11-5. TMOD0 Settings for TCL0 Edge Detection
TMOD0.5
TMOD0.4
TCL0 Edge Detection
Rising edges
0
0
0
1
Falling edges
With the exception of the different TMOD0.4–TMOD0.6 settings, the operation sequence for TC0’s event counter
function is identical to its programmable counter/timer 0 function.
11-12
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
TC0 CLOCK FREQUENCY OUTPUT
Using timer/counter 0, you can output a modifiable clock frequency to the TC0 clock output pin, TCLO0. To
select the clock frequency, you load appropriate values to the TC0 mode register, TMOD0. The clock interval is
determined by loading the desired reference value into the reference register TREF0. Then, to enable the output
to the TCLO0 pin at I/O port 3.1, the following conditions must be met:
— TC0 output enable flag TOE0 must be set to "1"
— I/O mode flag for P3.1 (PM3.1) must be set to output mode ("1")
— Output latch value for P3.1 must be set to "0"
In summary, the operational sequence required to output a TC0-generated clock signal to the TCLO0 pin is as
follows:
1. Load your reference value to TREF0
2. Set the clock frequency in TMOD0
3. Initiate TC0 clock output to TCLO0 (TMOD0.2 = "1")
4. Set port 3 mode flag (PM3.1) to "1"
5. Set P3.1 output latch to "0"
6. Set TOE0 flag to "1"
Each time TCNT0 overflows and an interrupt request is generated, the state of the output latch TOL0 is inverted
and the TC0-generated clock signal is output to the TCLO0 pin.
+
PROGRAMMING TIPS — TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin:
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BITS
EMB
15
EA,#79H
TREF0,EA
EA,#4CH
TMOD0,EA
EA,#20H
PMG1,EA
P3.1
; P3.1 ¬ Output mode
; P3.1 clear
TOE0
11-13
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
TC0 SERIAL I/O CLOCK GENERATION
Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter
and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register,
SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface.
Use TMOD0 and TREF0 register settings to select the frequency and interval of the TC0 clock signals to be used
as SCK input to the serial interface. The generated clock signal is then sent directly to the serial I/O clock
selector circuit — not through the port 3.1 latch and TCLO0 pin.
TC0 EXTERNAL INPUT SIGNAL DIVIDER
By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you
can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the
TCLO0 pin. The sequence of operations used to divide external clock input may be summarized as follows:
1. Load a signal divider value to the TREF0 buffer register
2. Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin
3. Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection
4. Set port 3.1 mode flag (PM3.1) to output ("1")
5. Set P3.1 output latch to "0"
6. Set TOE0 flag to "1" to enable output of the divided frequency
Divided clock signals are then output to the TCLO0 pin.
+
PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin
Output external TCL0 clock pulse to the TCLO0 pin (divide by four):
EXTERNAL (TCL0)
CLOCK PULSE
TCLO0
OUTPUT
PULSE
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BITS
EMB
15
EA,#01H
TREF0,EA
EA,#0CH
TMOD0,EA
EA,#20H
PMG1,EA
P3.1
; P3.1 ¬ Output mode
; P3.1 clear
TOE0
11-14
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
TC0 MODE REGISTER (TMOD0)
TMOD0 is the 8-bit mode control register for timer/counter 0. It is located at RAM addresses F90H–F91H and is
addressable by 8-bit write instructions. One bit, TMOD0.3, is also 1-bit writable. RESET clears all TMOD0 bits to
logic zero and disables TC0 operations.
F90H
F91H
TMOD0.3
"0"
TMOD0.2
TMOD0.6
"0"
"0"
TMOD0.5
TMOD0.4
TMOD0.2 is the enable/disable bit for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0,
IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal
TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register, TCNT0,
are retained until TC0 is re-enabled.
Use TMOD0.6, TMOD0.5, and TMOD0.4 bit settings together to select the TC0 clock source. This selection
involves two variables:
— Synchronization of timer/counter 0 operations with either the rising edge or the falling edge of the clock signal
input at the TCL0 pin, and
— Selection of one of four frequencies, based on division of the incoming system clock frequency, for use in
internal TC0 operation.
Table 11-6. TC0 Mode Register (TMOD0) Organization
Bit Name
TMOD0.7
TMOD0.6
TMOD0.5
TMOD0.4
TMOD0.3
Setting
Resulting TC0 Function
MSB value always logic zero
Address
0
F91H
0,1
1
Specify external input clock edge and internal frequency
Clear TCNT0, IRQT0, and TOL0 and resume counting
immediately (This bit is automatically cleared to logic zero
immediately after counting resumes.)
TMOD0.2
0
1
0
0
Disable timer/counter 0; retain TCNT0 contents
Enable timer/counter 0
F90H
TMOD0.1
TMOD0.0
Always logic zero
Always logic zero
11-15
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
Table 11-7. TMOD0.6, TMO0.5, and TMOD0.4 Bit Settings
TMOD0.6
TMOD0.5
TMOD0.4
Resulting Counter Source and Clock Frequency
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
External clock input (TCL0) on rising edges
External clock input (TCL0) on falling edges
10
fx/2
= 4.09 kHz
6
fx /2 = 65.5 kHz
4
fx/2 = 262 kHz
fx = 4.19 MHz
NOTE: 'fx' = system clock
+
PROGRAMMING TIP — Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz:
BITS
SMB
LD
EMB
15
EA,#4CH
TMOD0,EA
LD
EI
BITS
IET0
2. Clear TCNT0, IRQT0, and TOL0 and restart TC0 counting operation:
BITS
SMB
BITS
EMB
15
TMOD0.3
11-16
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
TC0 COUNTER REGISTER (TCNT0)
The 8-bit counter register for timer/counter 0, TCNT0, is mapped to RAM addresses F94H–F95H. It is read-only
and can be addressed by 8-bit RAM control instructions. RESET sets all TCNT0 register values to logic zero
(00H).
Whenever TMOD0.3 are enabled, TCNT0 is cleared to logic zero and counting begins. The TCNT0 register value
is incremented each time an incoming clock signal is detected that matches the signal edge and frequency
setting of the TMOD0 register (specifically, TMOD0.6, TMOD0.5, and TMOD0.4).
Each time TCNT0 is incremented, the new value is compared to the reference value stored in the TC0 reference
register, TREF0. When TCNT0 = TREF0, an overflow occurs in the TCNT0 register, the interrupt request flag,
IRQT0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter 0
interval has elapsed.
COUNT
CLOCK
TREF0
TCNT0
REFERENCE VALUE = n
. . . n-1
n
n-1
n
. . .
0
1
2
0
1
2
. . .
0
1
2
TOL0
INTERVAL TIME
IRQT0
SET
IRQT0
SET
COUNTING
STARTS
Figure 11-3. TC0 Timing Diagram
11-17
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
TC0 REFERENCE REGISTER (TREF0)
The TC0 reference register TREF0 is an 8-bit write-only register that is mapped to RAM locations F96H and
F97H. It is addressable by 8-bit RAM control instructions. RESET initializes the TREF0 value to 'FFH'.
TREF0 is used to store a reference value to be compared to the incrementing TCNT0 register in order to identify
an elapsed time interval. Reference values will differ depending upon the specific function that TC0 is being used
to perform — as a programmable timer/counter 0, event counter, clock signal divider, or arbitrary frequency
output source.
During timer/counter 0 operation, the value loaded into the reference register compared to the TCNT0 value.
When TCNT0 = TREF0, the TC0 output latch (TOL0) is inverted and an interrupt request is generated to signal
the interval or event.
The TREF0 value, together with the TMOD0 clock frequency selection, determines the specific TC0 timer in-
terval. Use the following formula to calculate the correct value to load to the TREF0 reference register:
1
TC0 timer interval = (TREF0 value + 1) ´
TMOD0 frequency setting
( assuming a TREF0 value ¹ 0 )
TC0 OUTPUT ENABLE FLAG (TOE0)
The 1-bit timer/counter 0 output enable flag TOE0 controls output from timer/counter 0 to the TCLO0 pin. TOE0
is mapped to RAM location F92H.2 and is addressable by 1-bit read and write instructions.
Bit 2
Bit 3
0
Bit 1
0
Bit 0
0
TOE0
F92H
When you set the TOE0 flag to "1", the contents of TOL0 can be output to the TCLO0 pin. Whenever a RESET
occurs, TOE0 is automatically set to logic zero, disabling all TC0 output. Even when the TOE0 flag is disabled,
timer/counter 0 can continue to output an internally-generated clock frequency, via TOL0, to the serial I/O clock
selector circuit.
TC0 OUTPUT LATCH (TOL0)
TOL0 is the output latch for timer/counter 0. When the 8-bit comparator detects a correspondence between the
value of the counter register TCNT0 and the reference value stored in the TREF0 buffer, the TOL0 value is
inverted — the latch toggles high-to-low or low-to-high.
Whenever the state of TOL0 is switched, the TC0 signal is output. TC0 output may be directed to the TCLO0 pin
at P3.1, or it can be output directly to the serial I/O clock selector circuit as the SCK signal.
Assuming TC0 is enabled, when bit 3 of the TMOD0 register is set to "1", the TOL0 latch is cleared to logic zero,
along with the counter register TCNT0 and the interrupt request flag, IRQT0, and counting resumes immediately.
When TC0 is disabled (TMOD0.2 = "0"), the contents of the TOL0 latch are retained and can be read, if
necessary.
11-18
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
+
PROGRAMMING TIP — Setting a TC0 Timer Interval
To set a 30 ms timer interval for TC0, given fx = 4.19 MHz, follow these steps.
1.
2.
Select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the TC0 counter
clock = fx/2 , and TREF0 is set to FFH):
10
Calculate the TREF0 value:
TREF0 value + 1
30 ms =
4.09 kHz
30 ms
244 µs
TREF0 + 1 =
= 122.9 = 7AH
TREF0 value = 7AH – 1 = 79H
3.
Load the value 79H to the TREF0 register:
BITS
SMB
LD
LD
LD
EMB
15
EA,#79H
TREF0,EA
EA,#4CH
TMOD0,EA
LD
11-19
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
WATCH TIMER
OVERVIEW
The watch timer is a multi-purpose timer consisting of three basic components:
— 8-bit watch timer mode register (WMOD)
— Clock selector
— Frequency divider circuit
Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. It
is also used as a clock source for generating buzzer output.
Real-Time and Watch-Time Measurement
To start watch timer operation, set bit 2 of the watch timer mode register, WMOD.2, to logic one. The watch timer
starts, the interrupt request flag IRQW is automatically set to logic one, and interrupt requests commence in 0.5-
second intervals.
Since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the IRQW flag should be
cleared to logic zero by program software as soon as a requested interrupt service routine has been executed.
Using a System Clock Source
The watch timer can generate interrupts based on the system clock frequency. The system clock (fx) is used as
the signal source, according to the following formula:
System clock (fx)
Watch timer clock (fw) =
= 32.768 kHz
128
(assuming fx = 4.19 MHz)
Buzzer Output Frequency Generator
The watch timer can generate a steady 2 kHz, 4 kHz, 8 kHz, or 16 kHz signal to the BUZ pin. To select the BUZ
frequency you want, load the appropriate value to the WMOD register. This output can then be used to actuate
an external buzzer sound. To generate a BUZ signal, three conditions must be met:
— The WMOD.7 register bit at F89H.3 is set to "1"
— The output latch for I/O port 6.3 is cleared to "0"
— The port 6.3 output mode flag (PM6.3) set to 'output' mode
Timing Tests in High-Speed Mode
By setting WMOD.1 (F88H.1) to "1", the watch timer will function in high-speed mode, generating an interrupt
every 3.91 ms. At its normal speed (WMOD.1 = '0'), the watch timer generates an interrupt request every 0.5
seconds. High-speed mode is useful for timing events for program debugging sequences.
11-20
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
WATCH TIMER CIRCUIT
P6.3 LATCH
PM6.3
WMOD.7
0
BUZ
WMOD.5
fx = SYSTEM CLOCK
fw = WATCH TIMER FREQUENCY
MUX
8
WMOD.4
0
fw/16
(2 KHz)
fw/8
(4 kHz)
fw/4
(8 kHz)
ENABLE /
DISABLE
WMOD.2
WMOD.1
0
SELECTOR
CIRCUIT
IRQW
fw/2
(16 kHz)
7
14
fw/2 (2 Hz)
fw/2
FREQUENCY
DIVIDING
CIRCUIT
fw
32.768 kHz
CLOCK
SELECTOR
GND fx/128
Figure 11-4. Watch Timer Circuit Diagram
11-21
TIMERS and TIMER/COUNTERS
S3C70F2/C70F4/P70F4
WATCH TIMER MODE REGISTER (WMOD)
The watch timer mode register WMOD is used to select specific watch timer operations. It is mapped to RAM lo-
cations F88H–F89H and is 8-bit write-only addressable.
RESET sets all WMOD bits to logic zero.
F88H
F89H
"0"
WMOD.2
"0"
WMOD.1
WMOD.5
"0"
WMOD.7
WMOD.4
In brief, WMOD settings control the following watch timer functions:
— Watch timer speed control
— Enable/disable watch timer
— Buzzer frequency selection
(WMOD.1)
(WMOD.2)
(WMOD.4)
(WMOD.5)
— Enable/disable buzzer output
(WMOD.7)
Table 11-8. Watch Timer Mode Register (WMOD) Organization
Bit Name
Values
Function
Disable buzzer (BUZ) signal output
Enable buzzer (BUZ) signal output
Address
WMOD.7
0
1
WMOD.6
"0"
Always logic zero
WMOD.5 – .4
0
0
1
1
0
1
0
1
2 kHz buzzer (BUZ) signal output
4 kHz buzzer (BUZ) signal output
8 kHz buzzer (BUZ) signal output
16 kHz buzzer (BUZ) signal output
Always logic zero
F89H
WMOD.3
WMOD.2
"0"
0
Disable watch timer; clear frequency dividing circuits
Enable watch timer
1
F88H
WMOD.1
WMOD.0
0
Normal speed mode; sets IRQW to 0.5 seconds at 4.19 kHz
High-speed mode; sets IRQW to 3.91 ms at 4.19 kHz
Always logic zero
1
0
NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.
11-22
S3C70F2/C70F4/P70F4
TIMERS and TIMER/COUNTERS
+
PROGRAMMING TIP — Using the Watch Timer
1. Select a 0.5 second interrupt, and 2 kHz buzzer enable:
BITS
SMB
LD
LD
BITR
LD
EMB
15
EA,#80H
PMG3,EA
P6.3
EA,#84H
WMOD,EA
IEW
; P6.3 ¬ Output mode
; Clear P6.3 output latch
LD
BITS
2. Sample real-time clock processing method:
CLOCK
BTSTZ
RET
IRQW
; 0.5 second check
; No, return
•
•
•
; Yes, 0.5 second interrupt generation
; Increment HOUR, MINUTE, SECOND
11-23
S3C70F2/C70F4/P70F4
COMPARATOR
12 COMPARATOR
OVERVIEW
Port 2 can be used as a analog input port for a comparator. The reference voltage for the 4-channel comparator
can be supplied either internally or externally at P2.3. When internal reference voltage is used, four channels
(P2.0–P2.3) are used for analog inputs and the internal reference voltage is varies at 16 levels. If an external
reference voltage is input at P2.3, the other three pins (P2.0–P2.2) in port 2 are used for analog input. Unused
port 2 pins must be connected to V
.
DD
When a conversion is completed, the result is saved in the comparison result register CMPREG. The initial
values of the CMPREG are undefined and the comparator operation is disabled by a RESET. The comparator
has following components:
— Comparator
— Internal reference voltage generator (4-bit resolution)
— External reference voltage source at P2.3
— Comparator mode register (CMOD)
— Comparison result register (CMPREG)
12-1
COMPARATOR
S3C70F2/C70F4/P70F4
P2.0 / CIN0
M
U
X
P2.1 / CIN1
P2.2 / CIN2
P2.3 / CIN3
COMPARISON
+
–
RESULT
REGISTER
(CMPREG)
4
VREF
(EXTERNAL)
M
U
X
V
DD
CMOD.7
CMOD.6
CMOD.5
0
1/2R
VREF
(INTERNAL)
M
U
X
R
R
8
CMOD.3
CMOD.2
CMOD.1
CMOD.0
1/2R
Figure 12-1. Comparator Circuit Diagram
12-2
S3C70F2/C70F4/P70F4
COMPARATOR
COMPARATOR MODE REGISTER (CMOD)
The comparator mode register CMOD is an 8-bit register that is used to set the operation mode of the
comparator. It is mapped to addresses FD6H–FD7H and can be manipulated using 8-bit memory instructions.
Based on the CMOD.5 bit setting, an internal or an external reference voltage is input for the comparator, as
follows:
When CMOD.5 is set to logic zero:
— A reference voltage is selected by the CMOD.0 to CMOD.3 bit settings.
— P2.0 to P2.3 are used as analog input pins.
— The internal digital to analog converter generates 16 reference voltages.
— The comparator can detect 150 mV difference between the reference voltage and the analog input voltages.
— Comparator results are written into 4-bit comparison result register (CMPREG).
When CMOD.5 is set to logic one:
— An external reference voltage is supplied from P2.3/CIN3.
— P2.0 to P2.2 are used as the analog input pins.
— The comparator can detect 150 mV difference between the reference voltage and the analog input voltages.
— Bits 0–2 in the CMPREG register contain the results; the content of bit 3 is not used.
Bit 6 in the CMOD register controls conversion time while bit 7 enables or disables comparator operation to
reduce power consumption. A RESET signal clears all bits to logic zero, causing the comparator operation to
enter stop mode.
CMOD.0 FD6H-FD7H
CMOD.7 CMOD.6 CMOD.5
0
CMOD.3 CMOD.2 CMOD.1
Reference voltage (VREF) selection:
VDD x (n + 0.5)/16, n=0 to 15
0 = Internal reference, CIN0-3; analog input
1 = CIN3; external reference, CIN0-2; analog input
0 = Conversion time (8 x 27/fx, 244.4 us @4.19MHz)
1 = Conversion time (8 x 24/fx, 30.5 us @4.19MHz)
0 = Comparator operation disable
1 = Comparator operation enable
Figure 12-2. Comparator Mode Register Organization
12-3
COMPARATOR
S3C70F2/C70F4/P70F4
PORT 2 MODE REGISTER (P2MOD)
P2MOD register settings determine if port 2 is used for analog or digital input. The P2MOD register is 4-bit write
only register. P2MOD is mapped to address FE2H and initialized to logic zero by a RESET, which configures port
2 as an analog input port.
FE2H
P2MOD.3 P2MOD.2 P2MOD.1 P2MOD.0
When bit is set to "1", the corresponding pin is configured as a digital input pin. When set to "0", configured as an
analog input pin: P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3 for P2.3.
COMPARATOR OPERATION
The comparator compares analog voltage input at CIN0–CIN3 with an external or internal reference voltage
(V
) that is selected by CMOD register. The result is written to the comparison result register CMPREG at
REF
address FD4H. The comparison result is calculated as follows.
If "1" Analog input voltage ³ V
If "0" Analog input voltage £ V
+ 150 mV
– 150 mV
REF
REF
To obtain a comparison result, the data must be read out from the CMPREG register after V
changing the CMOD value after a conversion time has elapsed.
is updated by
REF
Analog Input
Voltage (CIN0-3)
Reference
Voltage (VREF)
Comparison Time (CMPCLK x 8)
Comparator Clock
(CMPCLK, fx/16, fx/128)
Comparison Start
Comparison End
1
Comparison Result
(CMPREG)
1
0
Unknown
Unknown
Figure 12-3. Conversion Characteristics
12-4
S3C70F2/C70F4/P70F4
COMPARATOR
+
PROGRAMMING TIP — Programming the Comparator
The following code converts the analog voltage input at CIN0–CIN3 pins into 4-bit digital code.
BITR
LD
EMB
A,#00H
LD
LD
P2MOD,A
EA,#0CXH
; Comparator input selection (CIN0–CIN3)
; x = 0–F, comparator enable
; Internal reference, conversion time
; (30.5 us at 4.19 MHz)
LD
LD
LD
CMOD,EA
L,#1H
W,A
WAIT0
WAIT1
LD
INCS
JR
LD
DECS
JR
CPSE
JR
LD
A,#0H
A
WAIT2
A,CMPREG
L
WAIT1
A,W
WAIT0
P3,A
WAIT2
; Read the result
; Output the result from port 2
12-5
S3C70F2/C70F4/P70F4
SERIAL I/O INTERFACE
13 SERIAL I/O INTERFACE
OVERVIEW
The serial I/O interface (SIO) has the following functional components:
— 8-bit mode register (SMOD)
— Clock selector circuit
— 8-bit buffer register (SBUF)
— 3-bit serial clock counter
Using the serial I/O interface, you can exchange 8-bit data with an external device. You control the transmission
frequency by the appropriate bit settings to the SMOD register.
The serial interface can run off an internal or an external clock source, or the TOL0 signal that is generated by
the 8-bit timer/counter 0, TC0. If you use the TOL0 clock signal, you can modify its frequency to adjust the serial
data transmission rate.
13-1
SERIAL I/O INTERFACE
S3C70F2/C70F4/P70F4
SIO OPERATION SEQUENCE
The general sequence of operations for the serial I/O interface may be summarized as follows:
1. Set SIO mode to transmit-and-receive or to receive-only.
2. Select MSB-first or LSB-first transmission mode.
3. Set the SCK clock signal in the mode register, SMOD.
4. Set SIO interrupt enable flag (IES) to "1".
5. Initiate SIO transmission by setting bit 3 of the SMOD to "1".
6. When the SIO operation is complete, IRQS flag is set and an interrupt is generated.
Internal Bus
LSB or MSB first
8
SO
SBUF (8-Bit)
SI
R
CLK
Q
D
IRQS
CK
CLK
SCLK
TOL0
fx/210
fx/24
Q0
Q1
Q2
3-Bit Counter
CLK
Clock
Selector
R
S
Q
Clear
-
SMOD.7 SMOD.6 SMOD.5
SMOD.3 SMOD.2 SMOD.1 SMOD.0
8
Figure 13-1. Serial I/O Interface Circuit Diagram
13-2
S3C70F2/C70F4/P70F4
SERIAL I/O INTERFACE
SERIAL I/O MODE REGISTER (SMOD)
The serial I/O mode register, SMOD, is an 8-bit register that specifies the operation mode of the serial interface.
SMOD is mapped to RAM address FE0H–FE1H and its reset value is logic zero. SMOD is organized in two 4-bit
registers, as follows:
FE0H
FE1H
SMOD.3
SMOD.7
SMOD.2
SMOD.6
SMOD.1
SMOD.5
SMOD.0
0
SMOD register settings enable you to select either MSB-first or LSB-first serial transmission, and to operate in
transmit-and-receive mode or receive-only mode.
SMOD is a write-only register and can be addressed only by 8-bit RAM control instructions. One exception to this
is SMOD.3, which can be written by a 1-bit RAM control instruction. When SMOD.3 is set to 1, the contents of
the serial interface interrupt request flag, IRQS, and the 3-bit serial clock counter are cleared, and SIO
operations are initiated. When the SIO transmission starts, SMOD.3 is cleared to logic zero.
Table 13-1. SIO Mode Register (SMOD) Organization
SMOD.0
SMOD.1
SMOD.2
0
1
0
1
0
Most significant bit (MSB) is transmitted first
Least significant bit (LSB) is transmitted first
Receive-only mode; output buffer is off
Transmit-and-receive mode
Disable the data shifter and clock counter; retain contents of IRQS flag when
serial transmission is halted
1
1
0
Enable the data shifter and clock counter; set IRQS flag to "1" when serial
transmission is halted
SMOD.3
SMOD.4
Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then
reset this bit to logic zero
Bit not used; value is always "0"
SMOD.7
SMOD.6
SMOD.5
Clock Selection
R/W Status of SBUF
0
0
0
0
0
1
SBUF is enabled when SIO
External clock at SCK pin
Use TOL0 clock from TC0
operation is halted or when
SCK goes high.
0
1
1
1
0
1
x
0
1
CPU clock: fx/4, fx/8, fx/64
Enable SBUF read/write
10
SBUF is enabled when SIO
4.09 kHz clock: fx/2
4
operation is halted or when
262 kHz clock: fx/2
SCK goes high.
NOTES:
1. 'fx' = system clock; 'x' means 'don't care.'
2. kHz frequency ratings assume a system clock (fx) running at 4.19 MHz.
3. The SIO clock selector circuit cannot select a fx/24 clock if the CPU clock is fx/64.
13-3
SERIAL I/O INTERFACE
S3C70F2/C70F4/P70F4
SERIAL I/O TIMING DIAGRAMS
SCK
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO
IRQS
TRANSMIT
COMPLETE
SET SMOD.3
Figure 13-2. SIO Timing in Transmit/Receive Mode
SCK
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI
HIGH IMPEDANCE
SO
IRQS
TRANSMIT
COMPLETE
SET SMOD.3
Figure 13-3. SIO Timing in Receive-Only Mode
13-4
S3C70F2/C70F4/P70F4
SERIAL I/O INTERFACE
SERIAL I/O BUFFER REGISTER (SBUF)
When the serial interface operates in transmit-and-receive mode (SMOD.1 = "1"), transmit data in the SIO buffer
register are output to the SO pin (P0.1) at the rate of one bit for each falling edge of the SIO clock. Receive data
is simultaneously input from the SI pin (P0.2) to SBUF at the rate of one bit for each rising edge of the SIO clock.
When receive-only mode is used, incoming data is input to the SIO buffer at the rate of one bit for each rising
edge of the SIO clock.
SBUF can be read or written using 8-bit RAM control instructions. It is mapped to addresses FE4H–FE5H.
Following a RESET, the value of SBUF is undetermined.
+
PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O
4
1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fx/2 and in
MSB-first mode:
BITS
SMB
LD
EMB
15
EA,#03H
LD
LD
LD
LD
LD
PMG1,EA
EA,#48H
SBUF,EA
EA,#0EEH
SMOD,EA
; P0.0 / SCK and P0.1 / SO ¬ Output
;
;
; SIO data transfer
/ P0.0
EXTERNAL
DEVICE
SCK
SO / P0.1
2. Use CPU clock to transfer and receive serial data at high speed:
BITS
SMB
LD
EMB
15
EA,#03H
LD
LD
LD
LD
PMG1,EA
EA,TDATA
SBUF,EA
EA,#4FH
SMOD,EA
IES
; P0.0 / SCK and P0.1 / SO ¬ Output, P0.2 / SI ¬ Input
LD
; SIO start
BITR
BTSTZ
JR
STEST
IRQS
STEST
LD
SMB
LD
EA,SBUF
0
RDATA,EA
13-5
SERIAL I/O INTERFACE
S3C70F2/C70F4/P70F4
+
PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode:
BITS
SMB
LD
EMB
15
EA,#03H
LD
LD
LD
LD
PMG1,EA
EA,TDATA
SBUF,EA
EA,#8FH
; P0.0 / SCK and P0.1 / SO ¬ Output, P0.2/SI ¬ Input
LD
SMOD,EA
; SIO start
EI
BITS
•
IES
•
INTS
PUSH
PUSH
LD
SMB
XCH
SMB
LD
BITS
POP
POP
IRET
SB
EA
EA,TDATA
15
EA,SBUF
0
RDATA,EA
SMOD.3
EA
; Store SMB, SRB
; Store EA
; EA ¬ Transmit data
; EA ¬ Receive data
; RDATA ¬ Receive data
; SIO start
SB
/ P0.0
EXTERNAL
DEVICE
SCK
SO / P0.1
SI / P0.2
13-6
S3C70F2/C70F4/P70F4
SERIAL I/O INTERFACE
+
PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
4. Transmit and receive an external clock in LSB-first mode:
BITS
SMB
LD
EMB
15
EA,#02H
LD
LD
LD
LD
PMG1,EA
EA,TDATA
SBUF,EA
EA,#0FH
; P0.1 / SO ¬ Output, P0.0 / SCK and P0.2 / SI ¬ Input
LD
SMOD,EA
; SIO start
EI
BITS
•
IES
•
INTS
PUSH
PUSH
LD
SMB
XCH
SMB
LD
BITS
POP
POP
IRET
SB
EA
EA,TDATA
15
EA,SBUF
0
RDATA,EA
SMOD.3
EA
; Store SMB, SRB
; Store EA
; EA ¬ Transmit data
; EA ¬ Receive data
; RDATA ¬ Receive data
; SIO start
SB
/ P0.0
EXTERNAL
DEVICE
SCK
SO / P0.1
SI / P0.2
High Speed SIO Transmission
13-7
SERIAL I/O INTERFACE
S3C70F2/C70F4/P70F4
+
PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Concluded)
Use CPU clock to transfer and receive serial data at high speed:
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BTSTZ
JR
LD
SMB
LD
EMB
15
EA,#03H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#4FH
SMOD,EA
IES
; P0.0 / SCK and P0.1 / SO ¬ Output, P0.2 / SI ¬ Input
; SIO start
STEST
IRQS
STEST
EA,SBUF
0
RDATA,EA
13-8
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
14 ELECTRICAL DATA
Table 14-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
V
VI
VO
IOH
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 5
All I/O ports
V
V
Output Voltage
Output Current High
–
One I/O port active
mA
All I/O ports active
Ports 0, 3, and 6
– 15
5
IOL
Output Current Low
mA
Ports 4 and 5
All ports, total
–
30
+ 100
TA
°
Operating Temperature
Storage Temperature
– 40 to + 85
C
Tstg
°
C
–
– 65 to + 150
Table 14-2. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Ports 4 and 5
Min
Typ
Max
Units
VIH1
0.7VDD
VDD
Input High
Voltage
–
V
VIH2
VIH3
VIL1
0.8VDD
VDD – 0.1
–
VDD
VDD
–
–
–
Ports 0, 1, 2, 3, 6, and RESET
XIN and XOUT
0.3VDD
Input Low
Voltage
Ports 4 and 5
V
V
VIL2
VIL3
VOH
0.2VDD
0.1
Ports 0, 1, 2, 3, 6, and RESET
XIN and XOUT
VDD = 4.5 V to 5.5 V
VDD - 1.0
Output High
Voltage
–
–
IOH = – 1 mA
Ports 0, 3, 4, 5, 6
14-1
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Output Low
Voltage
–
–
2
V
Ports 4, 5
VDD = 4.5V to 5.5 V
–
–
2
3
IOL = 4.0mA
All output pins except Ports 4, 5
ILIH1
VIN = VDD
All input pins except XIN and XOUT
Input High
Leakage
Current
–
–
mA
mA
ILIH2
VIN = VDD
XIN and XOUT
20
ILIL1
VIN = 0 V
Input Low
Leakage
Current
–
– 3
All input pins except XIN, XOUT
and RESET
ILIL2
VIN = 0 V
XIN and XOUT
– 20
3
ILOH
VO = VDD
Output High
Leakage
Current
–
–
–
–
mA
mA
kW
All output pins
ILOL
VO = 0 V
Output Low
Leakage
Current
– 3
RL1
VI = 0 V; VDD = 5 V
Port 0, 1, 3, 4, 5, 6
VDD = 3 V
Pull-Up
Resistor
25
50
100
50
100
250
200
400
RL2
100
VDD = 5 V; VI = 0 V; RESET
VDD = 3 V
200
500
800
14-2
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter Symbol
Conditions
Min
Typ
Max Units
mA
8.0
IDD1
IDD2
IDD3
Supply
6.0MHz
–
3.0
Run mode; VDD = 5.0 V ± 10%
Current (1)
Crystal oscillator; C1=C2=22pF
4.19MHz
6.0MHz
2.0
1.3
5.5
4.0
VDD = 3 V ± 10%
4.19MHz
6.0MHz
1.0
0.8
3.0
mA
2.5
–
–
Idle mode; VDD = 5.0 V ± 10%
Crystal oscillator; C1=C2=22pF
4.19MHz
6.0MHz
0.6
0.6
1.8
1.5
VDD = 3 V ± 10%
4.19MHz
0.4
0.5
1.0
3.0
2.0
Stop mode; VDD = 5.0 V ± 10%
Stop mode; VDD = 3.0 V ± 10%
mA
0.3
NOTES:
1. D.C. electrical values for Supply current (I
to I
) do not include current drawn through internal pull-up resistor,
DD3
DD1
output port drive currents and comparator.
2. The supply current assumes a CPU clock of fx/4.
Main Osc. Freq. ( Divided by 4 )
6 MHz
CPU CLOCK
1.5 MHz
1.05 MHz
4.2 MHz
400 kHz
15.625 kHz
2.7
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-1. Standard Operating Voltage Range
14-3
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-3. Oscillators Characteristics
= 1.8 V to 5.5 V)
DD
°
°
(T = – 40 C + 85 C, V
A
Oscillator
Clock
Configuration
Parameter
Test Condition
Min Typ Max Units
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Xin
Xout
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3.0 V
0.4
–
–
–
–
4.2
4
Stabilization time (2)
ms
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Xin
Xout
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3.0 V
0.4
–
–
–
–
4.2
10
Stabilization time (2)
ms
XIN input frequency (1)
VDD = 2.7 V to 5.5 V
External
Clock
0.4
6.0
MHz
Xin
Xout
VDD = 1.8 V to 5.5 V
–
0.4
–
–
4.2
XIN input high and low
level width (tXH, tXL)
83.3
1250
ns
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
14-4
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-4. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
15
15
pF
pF
I/O Capacitance
Table 14-5. Comparator Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.5V, VSS = 0 V)
°
°
Parameter
Symbol
–
Condition
Min
Typ
Max
Units
VDD
Input Voltage Range
–
0
–
V
VREF
VDD
Reference Voltage
Range
–
0
–
V
VCIN
Input Voltage Accuracy
Input Leakage Current
–
–
–
–
–
mV
±150
ICIN
I
REF
– 3
3
mA
,
Table 14-6. A.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Parameter
Instruction Cycle
Time
Symbol
Conditions
Min
0.67
0.95
0
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
–
–
–
–
64
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
fTI
TCL0 Input
1.5
1
MHz
MHz
ms
Frequency
tTIH, tTIL
TCL0 Input High,
Low Width
0.48
1.8
–
tKCY
VDD = 2.7 V to 5.5 V
800
–
ns
SCK Cycle Time
External SCK source
670
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
3200
3800
Internal SCK source
14-5
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
Table 14-6. A.C. Electrical Characteristics ( Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tKH, tKL VDD = 2.7 V to 5.5 V
335
–
–
ns
SCK High, Low
Width
External SCK source
tKCY/2 – 50
1600
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
tKCY/2 – 150
100
Internal SCK source
tSIK
VDD = 2.7 V to 5.5 V
SI Setup Time to
–
–
–
–
ns
ns
ns
SCK High
External SCK source
150
150
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
500
400
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
tKSI
SI Hold Time to
–
SCK High
400
600
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
500
–
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
(1)
Output Delay for
300
tKSO
SCK to SO
250
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
1000
1000
–
Internal SCK source
(2)
tINTH
tINTL
,
Interrupt Input
High, Low Width
INT0
–
–
ms
ms
INT1, KS0–KS2
Input
10
10
t
–
RSL
RESET Input
Low Width
NOTES:
1. R (1 Kohm) and C (100 pF) are the load resistance and load capacitance of the SO output line.
2. Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
14-6
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Min
1.8
–
Typ
–
Max
5.5
10
Unit
VDDDR
Data retention supply voltage
Data retention supply current
–
V
IDDDR
VDDDR = 1.8 V
0.1
mA
tSREL
tWAIT
Release signal set time
–
0
–
–
–
–
ms
217 / fx
Oscillator stabilization wait
time (1)
ms
Released by RESET
(2)
Released by interrupt
–
–
ms
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-
up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 14-2. Stop Mode Release Timing When Initiated by RESET
14-7
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
DD
V
DDDR
V
SREL
t
EXECUTION OF
STOP INSTRUCTION
WAIT
t
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
Figure 14-4. A.C. Timing Measurement Points (Except for XIN)
1 / fx
tXL
tXH
VDD - 0.2 V
0.2 V
Xin
Figure 14-5. Clock Timing Measurement at XIN
14-8
S3C70F2/C70F4/P70F4
ELECTRICAL DATA
TI
1 / f
TIL
t
TIH
t
TCL
0.8 VDD
0.2 VDD
Figure 14-6. TCL Timing
tRSL
RESET
0.2 VDD
Figure 14-7. Input Timing for RESET Signal
tINTL
tINTH
0.8 VDD
0.2 VDD
INT0, 1
KS0 to KS2
Figure 14-8. Input Timing for External Interrupts
14-9
ELECTRICAL DATA
S3C70F2/C70F4/P70F4
tCKY
tKL
tKH
0.8 VDD
SCK
V
0.2
DD
tSIK
tKSI
0.8 VDD
0.2 VDD
SI
INPUT DATA
tKSO
SO
OUTPUT DATA
Figure 14-9. Serial Data Transfer Timing
14-10
S3C70F2/C70F4/P70F4
MECHANICAL DATA
15 MECHANICAL DATA
OVERVIEW
The S3C70F2/C70F4/P70F4microcontroller is available in a 30-pin SDIP package (Samsung part number 30-
SDIP-400) and a 32-SOP package (Samsung part number 30-SOP-450A).
#30
#16
0-15
30-SDIP-400
#1
#15
27.88 MAX
27.48 ± 0.20
0.56 ± 0.10
1.12 ± 0.10
1.778
(1.30)
NOTE: Dimensions are in millimeters.
Figure 15-1. 30-SDIP-400 Package Dimensions
15-1
MECHANICAL DATA
S3C70F2/C70F4/P70F4
0-8
#32
#17
32-SOP-450A
+ 0.10
0.25 - 0.05
#1
#16
20.30 MAX
19.90 ± 0.20
0.10 MAX
1.27
(0.43)
0.40 ± 0.10
NOTE: Dimensions are in millimeters.
Figure 15-2. 30-SOP-450A Package Dimensions
15-2
S3C70F2/C70F4/P70F4
S3P70F4 OTP
16 S3P70F4 OTP
OVERVIEW
The S3P70F4 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C70F2/C70F4 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P70F4 is fully compatible with the S3C70F2/C70F4, both in function and in pin configuration. Because of
its simple programming requirements, the S3P70F4 is ideal for use as an evaluation chip for the
S3C70F2/C70F4.
VSS/VSS
Xout
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
VDD/VDD
P6.3/BUZ/SCLK
P6.2/KS2/SDAT
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
P3.2/CLO
P3.1/TCLO0
Xin
VPP/TEST
P1.0/INT0
P1.1/INT1
RESET /RESET
P0.0/SCK
P0.1./SO
P0.2/SI
S3C70F4
(30-SDIP)
9
10
11
12
13
14
15
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. S3P70F4 Pin Assignments (30-SDIP Package)
16-1
S3P70F4 OTP
S3C70F2/C70F4/P70F4
VSS/VSS
Xout
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD/VDD
P6.3/BUZ/SCLK
P6.2/KS2/SDAT
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P4.3
P4.2
P4.1
P4.0
NC
P3.2/CLO
P3.1/TCLO0
Xin
VPP/TEST
P1.0/INT0
P1.1/INT1
RESET /RESET
NC
S3P70F4
(32-SOP)
P0.0/SCK
P0.1./SO
P0.2/SI
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
9
10
11
12
13
14
15
16
NOTE:
The bolds indicate an OTP pin name.
Figure 16-2. S3P70F4 Pin Assignments (32-SOP Package)
16-2
S3C70F2/C70F4/P70F4
Main Chip
S3P70F4 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P6.2
SDAT
28 (30)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input /
push-pull output port.
P6.3
SCLK
29 (31)
4 (4)
I/O
I
Serial clock pin. Input only pin.
VPP(TEST)
TEST
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
7 (7)
I
I
Chip initialization
RESET
RESET
VDD / VSS
VDD / VSS
Logic power supply pin. V
should be tied to +5 V
DD
30/1 (32/1)
during programming.
NOTE: ( ) means the 32-SOP OTP pin number.
Table 16-2. Comparison of S3P70F4 and S3C70F2/C70F4 Features
Characteristic S3P70F4 S3C70F2/C70F4
4 K-byte EPROM
Program Memory
2 K-byte mask ROM: S3C70F2
4 K-byte mask ROM: S3C70F4
Operating Voltage (VDD
)
2.0 V to 5.5 V
1.8 V to 5.5V
–
VDD = 5 V, VPP(TEST)=12.5V
OTP Programming Mode
Pin Configuration
30 SDIP, 32 SOP
30 SDIP, 32 SOP
EPROM Programmability
User Program one time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P70F4, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16–3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
Vpp(TEST)
REG/MEM
ADDRESS(A15-A0)
R/W
MODE
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
EPROM program
EPROM verify
12.5 V
12.5 V
12.5 V
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-3
S3P70F4 OTP
S3C70F2/C70F4/P70F4
OTP ELECTRICAL DATA
Table 16-4. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
VI
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 5
V
All I/O ports
V
V
VO
IOH
Output Voltage
Output Current High
–
One I/O port active
mA
All I/O ports active
Ports 0, 3, and 6
– 15
5
IOL
Output Current Low
mA
Ports 4 and 5
All ports, total
–
30
+ 100
°
TA
Operating Temperature
Storage Temperature
– 40 to + 85
C
°
C
Tstg
–
– 65 to + 150
Table 16-5. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 2.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Ports 4 and 5
Min
Typ
Max
Units
VIH1
0.7VDD
VDD
Input High
Voltage
–
V
VIH2
VIH3
VIL1
0.8VDD
VDD – 0.1
–
VDD
VDD
–
–
–
Ports 0, 1, 2, 3, 6, and RESET
XIN and XOUT
0.3VDD
Input Low
Voltage
Ports 4 and 5
V
V
VIL2
VIL3
VOH
0.2VDD
0.1
Ports 0, 1, 2, 3, 6, and RESET
XIN and XOUT
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
VDD - 1.0
Output High
Voltage
–
–
Ports 0, 3, 4, 5, 6
16-4
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-5. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Output Low
Voltage
–
–
2
V
Ports 4, 5
VDD = 4.5 V to 5.5 V
IOL = 4.0mA
–
–
2
3
All output pins except Ports 4, 5
ILIH1
VIN = VDD
All input pins except XIN and XOUT
Input High
Leakage
Current
–
–
mA
mA
ILIH2
VIN = VDD
XIN and XOUT
20
ILIL1
V
IN
= 0 V
Input Low
Leakage
Current
–
– 3
All input pins except XIN, XOUT
and RESET
ILIL2
VIN = 0 V
XIN and XOUT
– 20
3
ILOH
VO = VDD
Output High
Leakage
Current
–
–
–
–
mA
mA
kW
All output pins
ILOL
VO = 0 V
Output Low
Leakage
Current
– 3
RL1
VI = 0 V; VDD = 5 V
Port 0, 1, 3, 4, 5, 6
VDD = 3 V
Pull-Up
Resistor
25
50
100
50
100
250
200
400
RL2
100
VDD = 5 V; VI = 0 V; RESET
VDD = 3 V
200
500
800
16–5
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-5. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 2.0 V to 5.5 V)
Parameter Symbol
Conditions
Min
Typ
Max Units
mA
8.0
IDD1
Supply
Current (1)
6.0MHz
–
3.0
2.0
Run mode; VDD = 5.0 V ± 10%
Crystal oscillator; C1=C2=22pF
4.19MHz
5.5
6.0MHz
4.19MHz
6.0MHz
4.19MHz
6.0MHz
4.19MHz
1.3
1.0
0.8
0.6
0.6
0.4
0.5
0.3
4.0
3.0
VDD = 3 V ± 10%
mA
2.5
IDD2
–
–
Idle mode; VDD = 5.0 V ± 10%
Crystal oscillator; C1=C2=22pF
VDD = 3 V ± 10%
1.8
1.5
1.0
IDD3
3.0
2.0
Stop mode; VDD = 5.0 V ± 10%
Stop mode; VDD = 3.0 V ± 10%
mA
NOTES:
1. D.C. electrical values for Supply current (I
to I
) do not include current drawn through internal pull-up registers,
DD3
DD1
output port drive currents and comparator.
2. The supply current assumes a CPU clock of fx/4.
Main Osc. Freq. ( Divided by 4 )
6 MHz
CPU CLOCK
1.5 MHz
1.05 MHz
4.2 MHz
400 kHz
15.625 kHz
2.7
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 16-3. Standard Operating Voltage Range
16–6
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-6. Oscillators Characteristics
(TA = – 40 C + 85 C, VDD = 2.0 V to 5.5 V)
°
°
Oscillator
Clock
Parameter
Test Condition
Min Typ Max Units
Configuration
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Xin
Xout
C1
C2
VDD = 2.0 V to 5.5 V
VDD = 3.0 V
0.4
–
–
–
–
4.2
4
Stabilization time (2)
ms
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Xin
Xout
C1
C2
VDD = 2.0 V to 5.5 V
VDD = 3.0 V
0.4
–
–
–
–
4.2
10
Stabilization time (2)
ms
X input frequency (1)
in
VDD = 2.7 V to 5.5 V
External
Clock
0.4
6.0
MHz
Xin
Xout
VDD = 2.0 V to 5.5 V
–
0.4
–
–
4.2
XIN input high and low
level width (tXH, tXL)
83.3
1250
ns
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
16–7
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-7. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
15
15
pF
pF
I/O Capacitance
Table 16-8. Comparator Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.5V, VSS = 0 V)
°
°
Parameter
Symbol
–
Condition
Min
Typ
Max
Units
VDD
Input Voltage Range
–
0
–
V
VREF
VDD
Reference Voltage
Range
–
0
–
V
VCIN
Input Voltage Accuracy
Input Leakage Current
–
–
–
–
–
mV
±150
ICIN
I
REF
– 3
3
mA
,
Table 16-9. A.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 2.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
V
DD
= 2.7 V to 5.5 V
Instruction Cycle
Time
0.67
–
64
ms
V
V
= 2.0 V to 5.5 V
= 2.7 V to 5.5 V
0.95
0
DD
fTI
TCL0 Input
Frequency
–
–
–
1.5
MHz
DD
V
V
= 2.0 V to 5.5 V
= 2.7 V to 5.5 V
1
–
MHz
DD
tTIH, tTIL
TCL0 Input High,
Low Width
0.48
ms
DD
V
V
= 2.0 V to 5.5 V
= 2.7 V to 5.5 V
1.8
DD
tKCY
800
–
ns
DD
SCK Cycle Time
External SCK source
Internal SCK source
670
V
DD
= 2.0 V to 5.5 V
3200
External SCK source
Internal SCK source
3800
16–8
S3C70F2/C70F4/P70F4
S3P70F4 OTP
Table 16-9. A.C. Electrical Characteristics ( Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tKH, tKL VDD = 2.7 V to 5.5 V
335
–
–
ns
SCK High, Low
Width
External SCK source
tKCY/2 - 50
1600
Internal SCK source
VDD = 2.0 V to 5.5 V
External SCK source
tKCY/2 - 150
100
Internal SCK source
tSIK
VDD = 2.7 V to 5.5 V
SI Setup Time to
–
–
–
–
ns
ns
ns
SCK High
External SCK source
150
150
Internal SCK source
VDD = 2.0 V to 5.5 V
External SCK source
500
400
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
tKSI
SI Hold Time to
–
SCK High
400
600
Internal SCK source
VDD = 2.0 V to 5.5 V
External SCK source
500
–
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
(1)
Output Delay for
300
tKSO
SCK to SO
250
Internal SCK source
VDD = 2.0 V to 5.5 V
External SCK source
1000
1000
–
Internal SCK source
(2)
tINTH
tINTL
,
Interrupt Input
High, Low Width
INT0
–
–
ms
ms
INT1, KS0–KS2
Input
10
10
tRSL
–
RESET Input
Low Width
NOTES:
1. R(1Kohm) and C (100pF) are the load resistance and load capacitance of the SO output line.
2. Minimum value for INT0 is based on a clock of 2tCY or 128 / fx as assigned by the IMOD0 register setting.
16–9
S3P70F4 OTP
S3C70F2/C70F4/P70F4
Table 16-10. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
–
Min
Typ
Max
Unit
VDDDR
Data retention supply voltage
2.0
–
5.5
V
IDDDR
VDDDR = 2.0 V
Data retention supply current
–
0.1
10
mA
tSREL
tWAIT
Release signal set time
–
0
–
–
–
–
ms
217 / fx
Oscillator stabilization wait
time (1)
ms
Released by RESET
(2)
Released by interrupt
–
–
ms
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
16–10
S3C70F2/C70F4/P70F4
S3P70F4 OTP
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-4. OTP Programming Algorithm
16–11
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