S3C7295 [SAMSUNG]
The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M; 该S3C7295单芯片CMOS微控制器已经使用三星最新的4位CPU内核， SAM47 （三星可布置M设计的高性能
| 型号： | S3C7295 |
| 厂家： | 
SAMSUNG |
| 描述： | The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M |
| 文件： | 总31页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C7295/P7295
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-704-dot LCD direct drive capability, and flexible 8-bit timer/counter, the S3C7295 offers an
excellent design solution for a mid-end LCD game.
Up to 8 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to
internal and external events. In addition, the S3C7295's advanced CMOS technology provides for low power
consumption.
OTP
The S3C7295 microcontroller is also available in OTP (One Time Programmable) version, S3P7295. S3P7295
microcontroller has an on-chip 16K-byte one-time-programable EPROM instead of masked ROM.
The S3P7295 is comparable to S3C7295, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7295/P7295
FEATURES
Memory
Memory-Mapped I/O Structure
Data memory bank 15
•
•
•
256 ´ 4-bit RAM (excluding LCD display RAM)
16,384 ´ 8-bit ROM
Power-Down Modes
•
•
•
Idle mode (only CPU clock stops)
8 I/O Pins
Stop mode (main system oscillation stops)
Sub system clock stop mode
•
I/O: 8 pins
LCD Controller/Driver
Oscillation Sources
•
44 segments and 16 common terminals
(8, 12 and 16 common selectable)
Internal resistor circuit for LCD bias
Voltage doubler
•
•
•
Crystal, ceramic, or RC for main system clock
Crystal oscillator for subsystem clock
•
•
•
Main system clock frequency: 4.19 MHz
(typical)
All dot can be switched on/off
•
•
Subsystem clock frequency: 32.768 kHz
CPU clock divider circuit (by 4, 8, or 64)
8-bit Basic Timer
•
•
4 interval timer functions
Watch-dog timer
Instruction Execution Times
•
•
0.95, 1.91, 15.3 µs at 4.19 MHz (main)
122 µs at 32.768 kHz (subsystem)
8-bit Timer/Counter
•
•
Programmable 8-bit timer
Operating Temperature
Arbitrary clock output (TCLO0)
° °
– 40 C to 85 C
•
•
Inverted clock output (TCLO0)
Operating Voltage Range
2.2 V to 3.4 V (0.4 MHz to 4.19 MHz)
Watch Timer
•
•
Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
Package Type
80-pin QFP or pellet
•
•
Four frequency outputs to BUZ pin and BUZ pin
•
Clock source generation for LCD
Interrupts
•
•
•
Two internal vectored interrupts
Four external vectored interrupts
Two quasi-interrupts
1-2
S3C7295/P7295
PRODUCT OVERVIEW
BLOCK DIAGRAM
Xin
Xout
RESET
XTin XTout
BASIC
TIMER
WATCH-DOG
TIMER
P0.3/BUZ/K3
INTERRUPT
CONTROL
BLOCK
INSTRUCTION
REGISTER
P0.2/CLO/
/K2
BUZ
CLOCK
I/O PORT 0
I/O PORT 1
P0.1/
TCLO0
/K1
P0.0/TCLO0/K0
WATCH
TIMER
PROGRAM
COUNTER
INTERNAL
INTERRUPT
P1.3/INT
P1.2/INT2
P1.1/INT1
P1.0/INT0
BIAS
CA
CB
VOLTAGE
DOUBLER
PROGRAM
STATUS
WORD
INSTRUCTION DECODER
ARITHMETIC
AND
LOGIC UNIT
STACK
POINTER
LCD
DRIVER/
SEG0-SEG43
COM0-COM15
8-BIT
TIMER/
COUNTER
CONTROLLER
VLC0
256 x 4-BIT
DATA
MEMORY
16K BYTES
PROGRAM
MEMORY
Figure 1-1. S3C7295 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7295/P7295
PIN ASSIGNMENTS
SEG41
SEG42
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
2
SEG43
3
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
4
5
6
7
P0.3/BUZ/K3
8
P0.2/CLO/ BUZ/K2
9
P0.1/TCLO0/K1
P0.0/TCLO0/K0
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S3C7295
(TOP VIEW)
VSS
Xout
Xin
TEST
XTin
SEG8
XTout
SEG7
RESET
CA
SEG6
SEG5
CB
SEG4
VLC0
SEG3
BIAS
SEG2
COM15
SEG1
Figure 1-2. S3C7295 80-QFP Pin Assignment Diagram
1-4
S3C7295/P7295
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7295 Pin Descriptions
Description
Pin Name
Pin
Circuit Number
Share Pin
Type
Type
P0.0
P0.1
P0.2
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
E-1
11
10
9
TCLO0/K0
TCLO0/K1
Individual pins are software configurable as input or
output.
CLO/BUZ/K2
BUZ/K3
Individual pins are software configurable as open-
drain or push-pull output.
8
P0.3
Individual pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
P1.0
P1.1
P1.2
P1.3
I/O Same as port 0.
E-1
7
6
5
4
INT0
INT1
INT2
INT4
INT0, INT1
I/O External interrupts. The triggering edge for INT0
and INT1 is selectable.
7, 6
P1.0, P1.1
INT2
I/O Quasi-interrupt with detection of rising or falling
edges
5
P1.2
INT4
I/O External interrupt with detection of rising or falling
edges.
4
P1.3
BUZ
I/O 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer sound.
8
P0.3/K3
P0.2/CLO/K2
I/O Inverted BUZ signal
9
9
BUZ
CLO
I/O Clock output
P0.2/BUZ/K2
I/O Inverted Timer/counter 0 clock output
I/O Timer/counter 0 clock output
10
P0.1/K1
TCLO0
TCLO0
11
P0.0/K0
COM0–COM15
SEG0–SEG43
O
O
LCD common signal output
LCD segment signal output
H-6
H-6
39–24
–
–
40–80,
1–3
1-5
PRODUCT OVERVIEW
S3C7295/P7295
Table 1-1. S3C7295 Pin Descriptions (Continued)
Description
Pin Name
Pin
Type
Circuit Number Share Pin
Type
K0–K3
I/O
–
External interrupt (triggering edge is selectable)
E-1
–
11–8
12
P0.0–P0.3
V
DD
Power supply
–
–
–
V
SS
–
Ground
–
13
I
Reset input (active low)
B
19
RESET
CA, CB
VCL0
–
–
Capacitor terminal for voltage doubling
LCD power supply input
–
–
–
–
20, 21
22
–
–
–
–
BIAS
O
–
Doubling voltage level output
23
X
X
Crystal, ceramic or RC oscillator pins for system
clock
15, 14
in, out
XT XT
in,
–
I
Crystal oscillator pins for subsystem clock
–
–
17, 18
16
–
–
out
Test input (must be connected to V
)
SS
TEST
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
S3C7295/P7295
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
DD
VDD
PULL-UP
RESISTOR
PNE
VDD
RESISTOR
ENABLE
P-CH
N-CH
P-CHANNEL
I/O
DATA
IN
-
N CHANNEL
OUTPUT
DISABLE
SCHMITT TRIGGER
Figure 1-5. Pin Circuit Type E-1
Figure 1-3. Pin Circuit Type A
V
V
LC0
LC1
V
DD
V
LC2
PULL-UP
RESISTOR
OUT
SEG/COM DATA
IN
V
LC3
SCHMITT TRIGGER
V
V
LC4
SS
Figure 1-6. Pin Circuit Type H-6
Figure 1-4. Pin Circuit Type B
1-7
S3C7295/P7295
ELECTRICAL DATA
13 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7295 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X
in
— Clock timing measurement at XT
in
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
13-1
ELECTRICAL DATA
S3C7295/P7295
Table 13-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
– 0.3 to + 4.5
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 15
Units
V
V
DD
Supply Voltage
Input Voltage
–
V
I
Ports 0, 1
V
V
O
Output Voltage
Output Current High
–
V
I
One I/O pin active
All I/O pins active
One I/O pin active
mA
OH
– 30
I
Output Current Low
+ 30 (Peak value)
mA
OL
+ 15(note)
+ 100 (Peak value)
+ 60(note)
Total for pins 0, 1
T
A
°
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
– 65 to + 150
C
T
°
C
stg
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value ´
Duty .
Table 13-2. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 2.2 V to 3.4 V)
DD
A
Parameter
Symbol
Conditions
Ports 0, 1, and RESET
Min
Typ
Max
Units
V
IH1
0.8VDD
VDD
Input High
Voltage
–
V
V
X , X , and XT
in out in
VDD – 0.1
–
VDD
IH2
V
0.2VDD
Input Low
Voltage
–
V
IL1
Ports 0, 1, and RESET
V
V
X , X , and XT
0.1
–
IL2
in
out
in
V
I
= 2.2 V to 3.4 V
= – 1 mA
VDD – 1.0
Output High
Voltage
–
–
V
V
OH
DD
OH
Ports 0, 1
V = 2.2 V to 3.4 V
V
Output Low
Voltage
–
1.0
OL
DD
= 5 mA
I
OL
Ports 0, 1
13-2
S3C7295/P7295
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 2.2 V to 3.4 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
I
V = V
I
Input High
Leakage
Current
–
–
3
µA
LIH1
DD
All input pins except those
specified below for I
LIH2
I
V = V
I
20
LIH2
DD
X , X
in out
and XT
in
I
V = 0 V
I
Input Low
Leakage
Current
–
–
– 3
µA
LIL1
All input pins except RESET
X , X
in out
and XT
in
I
V = 0 V
I
– 20
3
LIL2
RESET, X , X
and XT
in
in
out
I
V = V
DD
Output High
Leakage
Current
–
–
–
–
µA
µA
kW
LOH
O
All output pins
I
V = 0 V
O
Output Low
Leakage
Current
– 3
LOL
All output pins
R
V = 0 V; V
= 3V
Pull-Up
Resistor
50
100
200
L1
I
DD
DD
Ports 0, 1
R
L2
200
50
450
100
800
150
V = 0 V; V
I
= 3V; RESET
R
LCD1
LCD Voltage
Dividing
Ta = + 25 °C
kW
(1)
Resistor
R
25
–
50
–
75
Ta = + 25 °C
LCD2
V
V
V
= 3.0 V
120
mV
½ DD-COMi½
DC
LCD
– 15 µA per common pin
Voltage Drop
(i = 0–15)
V
V
DS
V
= 3.0 V
–
–
120
½ LCD-
LCD
– 15 µA per common pin
SEGx½
Voltage Drop
(x = 0–43)
V
LC0
V
LC0 =
5.0 V
V -0.2
LC0
V
LC0
V +0.2
LC0
Middle Output
V
(2)
V
LC1
V
LC2
V
LC3
V
LC4
0.8V
0.6V
0.4V
0.2V
-0.2
0.8V
0.6V
0.4V
0.2V
0.8V
0.6V
0.4V
0.2V
+0.2
LC0
LC0
LC0
LC0
LC0
LC0
LC0
LC0
LC0
LC0
LC0
LC0
Voltage
-0.2
-0.2
-0.2
+0.2
+0.2
+0.2
NOTES:
1. RLCD1 is LCD voltage dividing resistor when LCON.2 = "0", and RLCD2 when LCON.2 = "1".
2. It is middle output voltage when 1/16 duty and 1/5 bias.
13-3
ELECTRICAL DATA
S3C7295/P7295
Table 13-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 40 C to + 85 C, V
= 2.2 V to 3.4 V)
A
DD
Parameter
Symbol
Conditions
Min Typ Max
Units
I
V
= 3V ± 10%
Supply
Current
–
1.3
3.0
mA
DD1
DD
(1)
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
I
Idle mode; V
= 3 V ± 10%
DD
0.4
1.0
DD2
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
(2)
V
= 3 V ± 10%
–
15
5
30
15
3
µA
DD
32 kHz crystal oscillator
Idle mode; V = 3 V ± 10%
I
I
DD3
(2)
DD
32 kHz crystal oscillator
DD4
I
Stop mode; V
= 3 V ± 10%
SCMOD=0000B,
XTin=0V
0.5
0.2
DD5
DD
Stop mode; V
= 3 V ± 10%
SCMOD=0100B
2
DD
NOTES:
1. Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
voltage doubler, and output port drive currents.
2. Data includes power consumption for subsystem clock oscillation.
3. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
13-4
S3C7295/P7295
ELECTRICAL DATA
Table 13-3. Main System Clock Oscillator Characteristics
°
°
(T = – 40 C to + 85 C, V
= 2.2 V to 3.4 V)
DD
A
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max Units
Ceramic
Oscillator
Oscillation frequency
(1)
–
0.4
–
4.19
MHz
Xin Xout
C1
C2
(2)
Stabilization occurs
–
–
–
4
ms
Stabilization time
when V
is equal to
DD
the minimum
oscillator voltage
range; V
= 3.0 V
DD
Crystal
Oscillator
Oscillation frequency
(1)
–
0.4
4.19
MHz
Xin
Xout
C1
C2
(2)
V
DD
= 3.0 V
–
–
–
–
10
ms
Stabilization time
(1)
External
Clock
0.4
4.19
MHz
Xin
Xout
X input frequency
in
X input high and low
in
–
83.3
0.4
–
–
1250
1.5
ns
level width (t , t
)
XH XL
V
DD
= 3 V
RC
Frequency
MHz
Xin
Xout
Oscillator
R
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
in
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
13-5
ELECTRICAL DATA
S3C7295/P7295
Table 13-4. Recommended Oscillator Constants
°
°
(T = – 40 C to + 85 C, V
= 2.2 V to 3.4 V)
DD
A
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.2
MAX
3.4
TDK
3.58 MHz–4.2 MHz
3.58 MHz–4.2 MHz
Leaded Type
FCR” ðÿM5
2.2
3.4
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz–4.2 MHz
2.2
3.4
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 13-5. Subsystem Clock Oscillator Characteristics
°
°
(T = – 40 C to + 85 C, V
= 2.2 V to 3.4 V)
DD
A
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
(1)
Crystal
Oscillator
–
32 32.768 35
kHz
XTin XTout
Oscillation frequency
C1
C2
(2)
V
DD
= 2.2 V to 3.4 V
–
1.0
–
3
s
Stabilization time
(1)
External
Clock
–
32
100
kHz
XT input frequency
in
XTin XTout
XT input high and low
in
–
5
–
15
µs
level width (t
, t )
XTL XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
in
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
13-6
S3C7295/P7295
ELECTRICAL DATA
Table 13-6. Input/Output Capacitance
°
(T = 25 C, V = 0 V )
A
DD
Parameter
Symbol
Condition
Min
Typ
Max
Units
C
Input
Capacitance
f = 1 MHz; Unmeasured pins
–
–
15
15
15
pF
IN
are returned to V
SS
C
OUT
Output
Capacitance
–
–
–
–
pF
pF
C
IO
I/O Capacitance
Table 13-7. Voltage Doubler Output
°
°
(T = -40 C to + 85 C, V = 2.2 V to 3.4 V)
A
DD
Parameter
Symbol
Condition
Min
Typ
Max
Units
V
DD
= 2.2 V to 3.4 V
2 V
DD
Voltage Doubler
Output
Vbias
–
–
V
Table 13-8. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 2.2 V to 3.4 V)
DD
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
t
V
DD
= 2.2 V to 3.4 V
Instruction Cycle
Time
0.95
–
64
µs
CY
(note)
With subsystem clock (fxt)
114
10
122
–
125
–
f
f
Interrupt Input
High, Low Width
INT0–INT2, INT4
K0–K3
INTH,
INTL
t
Input
10
–
–
RSL
RESET Input Low
Width
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
13-7
ELECTRICAL DATA
S3C7295/P7295
CPU CLOCK
1.05 MHz
Main OSC frequency (Divided by 4)
4.2 MHz
15.6 kHz
1
2
3
4
5
6
7
2.2V
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-9. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
–
Min
2.2
–
Typ
–
Max
Unit
V
V
DDDR
Data retention supply voltage
Data retention supply current
3.4
10
I
V
= 2.2 V
0.1
µA
DDDR
DDDR
t
Release signal set time
–
0
–
–
–
–
µs
SREL
217 / fx
t
Oscillator stabilization wait
ms
WAIT
Released by RESET
(1)
time
(2)
Released by interrupt
–
–
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
13-8
S3C7295/P7295
ELECTRICAL DATA
TIMING WAVEFORMS
RESET
INTERNAL
OPERATION
IDLE MODE
NORMAL MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 13-2. Stop Mode Release Timing When Initiated by RESET
IDLE MODE
NORMAL MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 13-3. Stop Mode Release Timing When Initiated by Interrupt Request
13-9
ELECTRICAL DATA
S3C7295/P7295
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
Figure 13-4. A.C. Timing Measurement Points (Except for X and XT )
in in
1 / f
x
t
XL
t
XH
X
in
V -0.5 V
DD
0.4 V
Figure 13-5. Clock Timing Measurement at X
in
1 / f
xt
t
t
XTH
XTL
V
- 0.5 V
XT
in
DD
0.4 V
Figure 13-6. Clock Timing Measurement at XT
in
13-10
S3C7295/P7295
ELECTRICAL DATA
t
RSL
RESET
0.2 V
DD
Figure 13-7. Input Timing for RESET Signal
t
t
INTL
INTH
0.8 V
0.2 V
DD
INT0, 1, 2, 4, K0 to K3
DD
Figure 13-8. Input Timing for External Interrupts
13-11
ELECTRICAL DATA
S3C7295/P7295
NOTES
13-12
S3C7295/P7295
ELECTRICAL DATA
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements.
They do not, however, represent guaranteed operating values.
(T = 25 °C, fx = 4.2 MHz)
A
5.0
4.5
I
, CPU Clock = fx/4
DD1
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
I
, CPU Clock = fx/64
DD1
I
DD2
0
2.7
4.0
4.5
6.0
V
(V)
DD
, I
Figure 13-11. I
VS. V
DD
DD1 DD2
13-13
ELECTRICAL DATA
S3C7295/P7295
(T = 25 °C, fx = 32.768 kHz)
A
50
45
40
35
30
25
20
15
10
5
I
DD3
I
DD4
DD5
I
0
2.0
2.5
3.0
3.5
4.0
V
4.5
5.0
5.5
6.0
6.5
(V)
DD
Figure 13-12. I
, I
, I
VS. V
DD3 DD4 DD5
DD
13-14
S3C7295/P7295
ELECTRICAL DATA
(T = 25 °C, CPU CLOCK = fx/4)
A
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 6.0 V
= 4.5 V
DD
DD
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Main System Clock Frequency (MHz)
Figure 13-13. I
VS. Main System Clock Frequency
DD1
(T = 25 °C)
A
1.6
V
= 6.0 V
= 4.5 V
DD
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
DD
0.5
1.0
Main System Clock Frequency (MHz)
Figure 13-13. I VS. Main System Clock Frequency
1.5
2.0
2.5
3.0
3.5
4.0
4.5
DD2
13-15
ELECTRICAL DATA
S3C7295/P7295
(T = 25 °C, Ports 0, 2, 3, 4, 5, 6, 7)
A
–25.0
–22.5
–20.0
–17.5
–15.0
–12.5
–10.0
–7.5
–5.0
–2.5
V
= 4.5 V
4.0
V
= 6.0 V
DD
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.5
5.0
5.5
6.0
V
(V)
OH
Figure 13–15. I
OH
VS. V
(P0, 2, 3, 4, 5, 6, 7)
OH
13-16
S3C7295/P7295
ELECTRICAL DATA
(T = 25 °C, Ports 8, 9)
A
–25.0
–22.5
–20.0
–17.5
–15.0
–12.5
–10.0
–7.5
–5.0
–2.5
V
= 4.5 V
4.0
V
= 6.0 V
DD
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.5
5.0
5.5
6.0
V
(V)
OH
Figure 13–16. I
OH
VS. V (P8, 9)
OH
13-17
ELECTRICAL DATA
S3C7295/P7295
(T = 25 °C, Ports 0, 2, 3, 4, 5, 6, 7)
A
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
V
= 6.0 V
DD
V
= 4.5 V
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
OL
3.5
4.0
4.5
5.0
5.5
6.0
V
(V)
Figure 13–17. I
OL
VS. V
(P0, 2, 3, 4, 5, 6, 7)
OL
13-18
S3C7295/P7295
ELECTRICAL DATA
(T = 25 °C, Ports 8, 9)
A
55.0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
V
= 6.0 V
DD
V
= 4.5 V
DD
0
0.5
1.0
1.5
2.0
2.5
3.0
OL
3.5
4.0
4.5
5.0
5.5
6.0
V
(V)
Figure 13–18. I
OL
VS. V
OL
(P8, 9)
13-19
S3C7295/P7295
MECHANICAL DATA
14 MECHANICAL DATA
OVERVIEW
The S3C7295/P7295 is available in a 80-QFP-1420 package.
23.90 ± 0.30
20.00 ± 0.20
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
80-QFP-1420C
#80
#1
0.35 + 0.10
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.80
0.15 MAX
(0.80)
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 14-1. 80-QFP-1420C Package Dimensions
14-1
S3C7295/P7295
S3P7295 OTP
15 S3P7295 OTP
OVERVIEW
The S3P7295 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7295
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P7295 is fully compatible with the S3C7295, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7295 is ideal for use as an evaluation chip for the S3C7295.
15-1
S3P7295 OTP
S3C7295/P7295
SEG41
SEG42
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
2
SEG43
3
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ/K3
4
5
6
7
8
P0.2/CLO/
SDAT / P0.1/
/K2
BUZ
9
/K1
TCLO0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SCLK /P0.0/TCLO0/K0
VDD/VDD
VSS/VSS
Xout
S3P7295
(TOP VIEW)
Xin
VPP/TEST
XTin
SEG8
XTout
SEG7
RESET / RESET
CA
SEG6
SEG5
CB
SEG4
VLC0
SEG3
BIAS
SEG2
COM15
SEG1
Figure 15-1. S3P7295 Pin Assignments (80-QFP Package)
15-2
S3C7295/P7295
S3P7295 OTP
Table 15-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P0.1
Pin Name
Pin No.
I/O
Function
SDAT
10
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P0.0
SCLK
11
16
I/O
I
Serial clock pin. Input only pin.
V
(TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
PP
19
I
I
Chip initialization
RESET
RESET
V /V
DD SS
V
/V
12/13
Logic power supply pin. VDD should be tied to
+5 V during programming.
DD SS
Table 15-2. Comparison of S3P7295 and S3C7295 Features
S3P7295
Characteristic
S3C7295
Program Memory
16 Kbyte EPROM
2.2 V to 3.4 V
16 Kbyte mask ROM
2.2 V to 3.4 V
Operating Voltage (V
)
DD
V
= 5 V, V (TEST)=12.5V
PP
OTP Programming Mode
DD
80 QFP
User Program 1 time
Pin Configuration
80 QFP
EPROM Programmability
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P7295, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15–3 below.
Table 15-3. Operating Mode Selection Criteria
VDD
VPP (TEST)
REG/MEM
Address
(A15–A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
15-3
S3P7295 OTP
S3C7295/P7295
Table 15-4. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 2.2 V to 3.4 V)
A
DD
Parameter
Symbol
Conditions
Min Typ Max Units
V
DD
= 3V ± 10%
Supply
IDD1
–
1.3
3.0
mA
Current (1)
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
Idle mode; V
= 3 V ± 10%
IDD2
0.4
1.0
DD
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
V
= 3 V ± 10%
IDD3 (2)
IDD4 (2)
IDD5
–
15
5
30
15
3
µA
DD
32 kHz crystal oscillator
Idle mode; V = 3 V ± 10%
DD
32 kHz crystal oscillator
Stop mode; V
= 3 V ± 10%
SCMOD=0000B,
XTin=0V
0.5
0.2
DD
Stop mode; V
= 3 V ± 10%
SCMOD=0100B
2
DD
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3. Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
voltage doubler, and output port drive currents.
CPU CLOCK
1.05 MHz
Main OSC frequency (Divided by 4)
4.2 MHz
15.6 kHz
1
2
3
4
5
6
7
2.2V
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 15-2. Standard Operating Voltage Range
15-4
相关型号：
S3C72B5
The S3C72B5/C72B7/C72B9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung A
SAMSUNG
S3C72B7
The S3C72B5/C72B7/C72B9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung A
SAMSUNG
S3C72B9
The S3C72B5/C72B7/C72B9 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung A
SAMSUNG
S3C72C8
The S3C72C8 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M
SAMSUNG
S3C72E8
The S3C72E8/P72E8 is a SAM47 core-based 4-bit CMOS single-chip microcontroller. It has a timer/counter and LCD drivers.
SAMSUNG
S3C72F5
The S3C72F5 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core, SAM47 (Samsung Arrangeable M
SAMSUNG
©2020 ICPDF网 联系我们和版权申明