S3C7324XX-QT [SAMSUNG]
Microcontroller, 4-Bit, MROM, SAM47 CPU, 6MHz, CMOS, PQFP64, 14 X 20 MM, QFP-64;
| 型号： | S3C7324XX-QT |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, MROM, SAM47 CPU, 6MHz, CMOS, PQFP64, 14 X 20 MM, QFP-64 时钟 微控制器 外围集成电路 |
| 文件： | 总37页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C7324/P7324
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7324 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 4-channel A/D converter, 24-bit AM/FM frequency counter and
watch timer, the S3C7324 offers an excellent design solution for a wide variety of applications that require LCD
functions and audio applications.
Up to 32 pins of the 64-pin QFP package, it can be dedicated to I/O. Five vectored interrupts provide fast
response to internal and external events. In addition, the S3C7324 's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C7324 microcontroller is also available in OTP (One Time Programmable) version, S3P7324 . The
S3P7324 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P7324 is comparable to S3C7324, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7324/P7324
FEATURES
Memory
Bit Sequential Carrier
— Support 16-bit serial data transfer in arbitrary
format
— 256 ´ 4-bit RAM
— 4096 ´ 8-bit ROM
Interrupts
I/O Pins
— Two internal vectored interrupts
— Three external vectored interrupts
— Two quasi-interrupts
— Input only: 8 pins
— I/O: 16 pins
— Output only: 8 pins sharing with segment driver
outputs
Memory-Mapped I/O Structure
— Data memory bank 15
LCD Controller/Driver
Two Power-Down Modes
— Maximum 14-digit LCD direct drive capability
— 28 segment and 4 common pins
— Idle mode (only CPU clock stops)
— Stop mode (main system clock stops)
— Subsystem clock stops
— Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
— Internal resistor circuit for LCD bias
Oscillation Sources
8-Bit Basic Timer
— Crystal, ceramic, or RC for main system clock
— Crystal or external oscillator for subsystem clock
— Main system clock frequency: 4.19 MHz (typical)
— Subsystem clock frequency: 32.768 kHz
— CPU clock divider circuit (by 4, 8, or 64)
— Programmable interval timer
— Watchdog timer
8-Bit Timer
— Programmable 8-bit timer
Instruction Execution Times
Watch Timer
— 0.95, 1.91, 15.3 µs at 4.19 MHz (main)
— 122 µs at 32.768 kHz (subsystem)
— Real-time and interval time measurement
— Four frequency outputs to BUZ pin
— Clock source generation for LCD
Operating Temperature
°
°
— – 40 C to 85 C
24-Bit Frequency Counter (FC)
— Level = 300mVpp (Min.)
Operating Voltage Range
— 1.8 V to 5.5 V at 3 MHz
— 3.0 V to 5.5 V at FC mode
— AMF input range = 0.5 MHz to 10 MHz
— FMF input range = 30 MHz to 150 MHz
A/D Converter
Package Type
— 4-channels with 8-bit resolution
— 17 ms (Min.) conversion speed
— 64-pin QFP
1-2
S3C7324/P7324
PRODUCT OVERVIEW
BLOCK DIAGRAM
X
X
N
I
XT
XT
IN
OUT
OUT
Watchdog
RESET
Timer
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
Basic
Timer
Watch
Timer
I/O Port 1
Interrupt
Control
Block
Instruction
Register
Clock
P2.0
P2.1
P2.2/FMF
P2.3/AMF
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
Input
Port 2
Freq.
Counter
FMF
Program
Counter
AMF
Internal
Interrupts
Input
Port 3
8-Bit
Timer
Program
Status Word
Instruction Decoder
A/D
Converter
COM0-COM3
SEG0-SEG19
LCD Driver/
Countroller
Arithmetic
and
Logic Unit
Stack
Pointer
I/O
Port 4, 5
P4.0-P4.3
P5.0-P5.3
P8.0-P8.3/
SEG27-SEG24
Output
Port 8,9
P9.0-P9.3/
SEG23-SEG20
P6.0/BUZ
P6.1/KS0
P6.2/KS1
P6.3/KS2
I/O Port 6
256 x 4-Bit
Data
Memory
4-Kbyte
Program
Memory
Figure 1-1. S3C7324 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7324/P7324
PIN ASSIGNMENTS
P2.0
P2.1
1
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG9
2
SEG10
P2.2/FMF
P2.3/AMF
3
SEG11
4
SEG12
P3.0/ADC0
P3.1/ADC1
P3.2/ADC2
P3.3/ADC3
5
SEG13
6
SEG14
7
SEG15
8
SEG16
V
9
S3C7324
DD
SEG17
V
10
11
12
13
14
15
16
17
18
19
SS
SEG18
X
OUT
SEG19
(Top View)
X
IN
P9.3/SEG20
P9.2/SEG21
P9.1/SEG22
P9.0/SEG23
P8.3/SEG24
P8.2/SEG25
P8.1/SEG26
P8.0/SEG27
TEST
XT
IN
XT
OUT
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
Figure 1-2. S3C7324 64-QFP Pin Assignment
1-4
S3C7324/P7324
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7324 Pin Descriptions
Description Number
Pin Name
P1.0
P1.1
P1.2
P1.3
Pin
Type
Share
Pin
Reset Circuit
Value
Type
I/O
4-bit I/O port.
17
18
19
20
INT0
INT1
INT2
INT4
Input
D-4
1-bit or 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can
be configured by software.
P2.0
P2.1
P2.2
P2.3
I
I
4-bit input port. 1-bit and 4-bit read and
test are possible.
Pull-up resistors can be configured by
software.
1
2
3
4
–
–
FMF
AMF
Input
Input
Input
A-4
A-4
B-4
B-4
P3.0
P3.1
P3.2
P3.3
4-bit input port.
5
6
7
8
ADC0
ADC1
ADC2
ADC3
F-13
1-bit and 4-bit read and test are possible
Pull-up resistors can be configured by
software.
P4.0–P4.3
P5.0–P5.3
I/O
4-bit I/O ports. N-channel open-drain
output up to 5 V. 1-bit and 4-bit read,
write, and test are possible. Ports 4 and
5 can be paired to support 8-bit data.
Pull-up resistors can be configured by
software.
21–24
25–28
–
–
E-2
P6.0
P6.1
P6.2
P6.3
I/O
1-bit and 4-bit read, write, and test are
possible. Each pin can be specified as
input or output port. Pull-up resistors can
be configured by software.
29
30
31
32
BUZ
KS0
KS1
KS2
Input
D-2
D-4
D-4
D-4
SEG0–SEG19
O
O
LCD segment signal output
60–41
–
Output
H-16
H-16
P8.0–P8.3
P9.0–P9.3
4-bit output ports. 1-bit and 4-bit write
and test are possible. Ports 8 and 9 can
be paired to support 8-bit data.
33–36
37–40
SEG27– Output
SEG20
COM0–COM3
VDD
O
–
LCD common signal output
Main power supply
64–61
9
–
–
Output
–
H-16
–
VSS
–
–
Main ground
10
–
–
–
–
–
–
XOUT, XIN
Crystal, ceramic, or RC oscillator pins for
main system clock. (For external clock
input, use XIN and input XIN's reverse
11,12
phase to XOUT
)
XTOUT, XTIN
–
Crystal oscillator pin for a subsystem
15,14
–
–
–
clock. (For external clock input, use XTIN
and input XTIN's reverse phase to
XTOUT
)
1-5
PRODUCT OVERVIEW
S3C7324/P7324
Reset Circuit
Table 1-1. S3P7324 Pin Descriptions (Continued)
Pin Name
SEG20–SEG27
ADC0–ADC3
Pin
Description
Number
40–33
5–8
Share
Pin
Type
Value
Type
O
LCD segment signal output
P9.0–P9.3 Output
P8.0–P8.3
H-16
I
I
ADC input ports
P3.0–P3.3
Input
Input
F-13
B-4
FMF
AMF
External FM/AM frequency inputs
3
4
P2.2
P2.3
INT4
I
I
I
External interrupt input with detection of
rising or falling edges.
20
P1.3
Input
Input
Input
A-4
A-4
A-4
INT2
Quasi-interrupt with detection of rising
edge signals.
19
P1.2
INT1
INT0
External interrupt. The triggering edges
for INT0 and INT1 are able to be
selected. Only INT0 is synchronized with
the system clock.
18
17
P1.1
P1.0
BUZ
O
I
2, 4, 8, or 16 kHz frequency output for
buzzer sound with 4.19 MHz main
system clock.
29
P6.0
Input
D-2
D-4
KS0–KS2
Quasi-interrupt input with falling edge
detection.
30–32
P6.1–P6.3 Input
I
System reset signal
16
13
–
Input
–
B
–
RESET
TEST
–
System test pin(must be connected to
VSS)
–
NOTE: Pull-up resistors forall I/O ports automatically disabled if they are configured to output mode.
1-6
S3C7324/P7324
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
V
DD
V
DD
P-CHANNEL
IN
IN
N-CHNNEL
Figure 1-5. Pin Circuit Type B
Figure 1-3. Pin Circuit Type A
V
DD
Type A
Feedback
Enable
Pull-up
Enable
Pull-down
Enable
In
Figure 1-6. Pin Circuit Type B-4
Figure 1-4. Pin Circuit Type A-4
1-7
PRODUCT OVERVIEW
S3C7324/P7324
V
DD
V
DD
Pull-up
Enable
Data
Out
Data
Circuit
I/O
TYPE C
Output
Output
Disable
Disable
Figure 1-7. Pin Circuit Type C
Figure 1-9. Pin Circuit Type D-4
V
V
DD
DD
PNE
V
DD
Pull-up
Enable
Data
Pull-up
Enable
I/O
Data
Output
Disable
Circuit
TYPE C
I/O
Output
Disable
Figure 1-8. Pin Circuit Type D-2
Figure 1-10. Pin Circuit Type E-2
1-8
S3C7324/P7324
PRODUCT OVERVIEW
V
DD
Pull-up Enable
Data
In
ADCEN
ADC Select
To ADC
Figure 1-11. Pin Circuit Type F-13
1-9
PRODUCT OVERVIEW
S3C7324/P7324
V
DD
V
LC0
V
LC1
SEG/COM
and Port Data
Out
V
LC2
Figure 1-12. Pin Circuit Type H-16
1-10
S3C7324/P7324
ELECTRICAL DATA
15 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7324 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— Input timing for RESET
— Input timing for external interrupts
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
15-1
ELECTRICAL DATA
S3C7324/P7324
Table 15-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
VIN
VO
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
V
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
All I/O ports
Output Voltage
Output Current High
–
IOH
One I/O port active
– 15
mA
All I/O ports active
One I/O port active
– 30
IOL
Output Current Low
+ 30 (Peak value)
+ 15 (note)
Total value for ports 1, 4, 5 and 6 + 100 (Peak value)
(note)
+ 60
TA
°
C
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
– 65 to + 150
T
stg
NOTE: The values for Output Current Low ( I ) are calculated as Peak Value ´ Duty .
OL
Table 15-2. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those
specified below
–
V
VIH2
0.8 VDD
VDD
P1, P3, RESET, P2.0- 1 and
P6.1- 3
VIH3
VIL1
XIN, XOUT, XTIN, and XTOUT
VDD – 0.1
–
VDD
0.3 VDD
Input low
voltage
All input pins except those
specified below
–
–
V
V
VIL2
0.2 VDD
P1, P3, RESET, P2.0- 1 and
P6.1- 3
VIL3
XIN, XOUT, XTIN, and XTOUT
0.1
–
VOH1
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
VDD – 1.0
VDD – 2.0
Output high
voltage
Ports 1, 4, 5, and 6
VOH2
VDD = 4.5 V to 5.5 V
IOH = –100 µA Port 8 and 9
15-2
S3C7324/P7324
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 1, 4, 5, and 6
Output low
voltage
–
0.4
2
V
VOL2
VDD = 4.5 V to 5.5 V
–
–
–
–
1
3
IOL = 100 mA ; Ports 8and 9
ILIH1
VIN = VDD
Input high
leakage
current (note)
mA
All input pins
ILIL1
ILOH1
ILOL
RL1
VIN = 0 V
Input low
leakage
–
–
–
–
– 3
3
All input pins
current (note)
VOUT = VDD
Output high
leakage
current (note)
All output pins
VOUT = 0 V
Output low
leakage
current (note)
– 3
80
All output pins
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
VDD = 3 V
Pull-up
resistor
20
40
KW
30
95
200
400
RL2
VIN = 0 V; VDD = 5 V
100
230
RESET
VDD = 3 V
200
480
800
NOTE: Except for X , X
, XT , and XT
OUT
IN OUT
IN
15-3
ELECTRICAL DATA
S3C7324/P7324
Table 15-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
RLCD
LCD voltage
dividing
60
84
130
KW
TA = 25 øC
resistor
RCOM
RSEG
VDC
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
COM output
impedance
SEG output
impedance
3
5
6
15
6
-
–
–
3
5
15
± 90
COM output
voltage
deviation
VDD = 5 V (VLC0-COMi)
mV
± 45
Io = ± 15uA (I = 0–3)
VDD = 5 V (VLC0-SEGi)
SEG output
voltage
deviation
VDS
–
± 45
600
± 90
1500
4000
Io = ± 15uA (I = 0–27)
ROSC1
VDD = 5.0 V; TA = 25; XIN = VDD
XOUT = 0 V
,
Oscillator
feedback
resistor
300
1230
KW
ROSC2
VDD = 5.0 V; TA = 25; XTIN = VDD
XTOUT = 0 V
,
2630
15-4
S3C7324/P7324
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter Symbol
Conditions
Min
Typ
Max
Units
Main operating:
IDD1
Supply
Current(1)
4.19 MHz
6.0 MHz
–
5.2
10
mA
FC enable
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
(2)
Main operating:
–
3.5
2.5
8
IDD2
PCON = 0011B, SCMOD = 0000B 4.19 MHz
Crystal oscillator
5.5
C1 = C2 = 22 pF
VDD = 5 V ± 10%
6.0 MHz
1.6
4
VDD = 3 V ± 10%
4.19 MHz
6.0 MHz
1.2
1.0
3
(2)
IDD3
Main idle mode(3):
–
2.5
PCON = 0111B, SCMOD =0000B
Crystal oscillator
4.19 MHz
0.9
2.0
C1 = C2 = 22 pF
VDD = 5 V ± 10%
6.0 MHz
0.5
1.0
VDD = 3 V ± 10%
4.19 MHz
0.4
15
0.8
30
(2)
(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
VDD = 3 V ± 10%
–
–
uA
IDD4
32 kHz crystal oscillator
Sub idle mode:
6
15
3
IDD5
PCON = 0111B, SCMOD = 1001B
VDD = 3 V ± 10%
32 kHz crystal oscillator
(2)
(2)
Stop mode:
CPU = fxt/4, SCMOD = 1101B
VDD = 5 V ± 10%
–
–
0.5
IDD6
Stop mode:
IDD7
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. AMF or FMF is a normal input mode.
3. Data includes the power consumption for sub-system clock oscillation.
15-5
ELECTRICAL DATA
S3C7324/P7324
Table 15-3. Main System Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Ceramic
Oscillator
Oscillation frequency
(1)
–
0.4
–
6.0
MHz
X
IN
X
OUT
C1
C2
Stabilization time (2)
Stabilization occurs
when VDD is equal to
–
–
–
4
ms
the minimum oscillator
voltage range.
Crystal
Oscillator
Oscillation frequency
–
0.4
6.0
MHz
X
IN
X
OUT
(1)
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 2.7 V
–
–
–
–
–
–
10
30
ms
XIN input frequency (1)
External
Clock
0.4
6.0
MHz
X
IN
X
OUT
XIN input high and low
level width (tXH, tXL)
–
83.3
0.4
–
–
ns
Frequency (1)
VDD = 5 V
RC
Oscillator
2.5
MHz
-
X
IN
X
OUT
2.0
1.0
R = 15 KW, VDD = 5 V
R = 25 KW, VDD = 3 V
R
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
15-6
S3C7324/P7324
ELECTRICAL DATA
Table 15-4. Subsystem Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max
Units
Configuration
Crystal
Oscillator
Oscillation frequency
(1)
–
32
32.768
35
kHz
XT
XT
OUT
IN
C1
C2
(2)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 2.7 V
–
–
–
1.0
–
2
s
Stabilization time
10
XTIN input frequency
External
Clock
32
–
100
kHz
XT
XT
OUT
IN
(1)
XT input high and
IN
–
5
–
15
ms
low level width (tXTL
,
tXTH
)
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
15-7
ELECTRICAL DATA
S3C7324/P7324
Table 15-5. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
fCLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
COUT
CIO
Output
capacitance
–
–
–
–
15
15
pF
pF
I/O capacitance
Table 15-6. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
0.67
1.3
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction cycle
–
64
64
–
ms
(1)
VDD = 1.8 V to 5.5 V
INT0
time
(2)
tINTH, tINTL
Interrupt input
high, low width
–
–
ms
ms
INT1, INT2, INT4, KS0–KS2
Input
10
10
tRSL
–
RESET Input Low
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2t or 128/fxx as assigned by the IMOD0 register setting.
CY
Table 15-6. A.C. Electrical Characteristics (continued)
(TA = – 10 C to + 70 C, VDD = 3.5 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
8
8
8
bits
Absolute accuracy
–
–
–
–
–
LSB
± 2
34/fxx (note)
tCON
AD conversion
time
17
–
ms
VIAN
RAN
VSS
2
VDD
–
Analog input
voltage
–
–
–
V
Analog input
impedance
1000
MW
NOTE: fxx stands for the system clock (fx or fxt).
15-8
S3C7324/P7324
ELECTRICAL DATA
Table 15-6. A.C. Electrical Characteristics (continued)
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIN
VDD
Input voltage
(peak to peak)
AMF/FMF mode, sine
wave input
0.3
–
V
fAMF
fFMF
Frequency
AMF mode, sine wave
input; VIN = 300mVP-P
0.5
30
–
10
MHz
FMF mode, sine wave
input; VIN = 300mVP-P
150
CPU CLOCK
Main OSC. Freq.
1.5 MHz
6 MHz
4.19 MHz
1.0475 MHz
3 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
400 kHz
7
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
When FC operates, operating voltage range is 3.0 V to 5.5 V.
Figure 15-1. Standard Operating Voltage Range
Table 15-7. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Normal operation
VDDDR = 1.8 V
Min
1.8
–
Typ
–
Max
5.5
1
Unit
VDDDR
Data retention supply voltage
Data retention supply current
V
IDDDR
0.1
mA
15-9
ELECTRICAL DATA
S3C7324/P7324
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
STOP MODE
DATA RETENTION MODE
MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 15-2. Stop Mode Release Timing When Initiated by RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 15-3. Stop Mode Release Timing When Initiated by an Interrupt Request
15-10
S3C7324/P7324
ELECTRICAL DATA
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
Figure 15-4. A.C. Timing Measurement Points (Except for X and XT )
in in
1 / f
x
t
t
XH
XL
X
in
V
DD
– 0.1 V
0.1 V
Figure 15-5. Clock Timing Measurement at X
in
1 / f
xt
t
t
XTH
XTL
XT
in
V
DD
– 0.1 V
0.1 V
Figure 15-6. Clock Timing Measurement at XT
in
15-11
ELECTRICAL DATA
S3C7324/P7324
t
RSL
RESET
0.2 V
DD
Figure 15-7. Input Timing for RESET Signal
t
t
INTL
INTH
INT0, 1, 2, 4
KS0 to KS2
0.8 V
0.2 V
DD
DD
Figure 15-8. Input Timing for External Interrupts and Quasi-Interrupts
15-12
S3C7324/P7324
MECHANICAL DATA
16 MECHANICAL DATA
OVERVIEW
The S3C7324 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F).
Package dimensions are shown in Figure 16-1.
23.90 ± 0.3
20.00 ± 0.2
0-8°
+0.10
0.15 - 0.05
64-QFP-1420F
0.10 MAX
#64
#1
0.05~0.25
2.65 ± 0.10
+0.10
0.40
- 0.05
1.00
(1.00)
±
0.15MAX
3.00 MAX
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 16-1. 64-QFP-1420F Package Dimensions
16-1
S3C7324/P7324
S3P7324 OTP
17 S3P7324 OTP
OVERVIEW
The S3P7324 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C7324microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial
data format.
The S3P7324 is fully compatible with the S3C7324, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7324 is ideal for use as an evaluation chip for the S3C7324.
17-1
S3P7324 OTP
S3C7324/P7324
1
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG9
P2. 0
P2.1
2
SEG10
3
SEG11
P2.2/FMF
4
SEG12
P2.3/AMF
P3.0/ADC0
5
SEG13
6
SEG14
P3.1/ADC1
7
SEG15
SDAT/P3.2/ADC2
SCLK /P3.3/ADC3
8
SEG16
9
S3P7324
SEG17
V
/V
DD DD
/V
SS SS
10
11
12
13
14
15
16
17
18
19
SEG18
V
SEG19
X
OUT
(Top View)
P9.3/ SEG20
P9.2/ SEG21
P9.1/SEG22
P9.0/ SEG23
P8.3/ SEG24
P8.2/ SEG25
P8.1/SEG26
P8.0/ SEG27
X
IN
/TEST
V
PP
XT
IN
XT
OUT
RESET /RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
Figure 17-1. S3P7324 Pin Assignments (64-QFP)
17-2
S3C7324/P7324
S3P7324 OTP
Table 17-1. Pin Descriptions Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P3.2
Pin Name
SDAT
Pin No.
I/O
Function
7
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input or push-pull output port.
P3.3
SCLK
VPP (TEST)
8
I/O
I
Serial clock pin. Input only pin.
TEST
13
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
16
I
I
Chip initialization
RESET
RESET
VDD / VSS
VDD / VSS
Logic power supply pin. VDD should be tied to +5
V during programming.
9/10
Table 17-2. Comparison of S3P7324 and S3C7324 Features
Characteristic S3P7324
4K bytes EPROM
S3C7324
Program Memory
4K bytes mask ROM
Operating Voltage (VDD
)
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
64 QFP
64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P7324, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 17-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
MEM
Address
(A15-A0)
Mode
R/W
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means low level; "1" means high level.
17-3
S3P7324 OTP
S3C7324/P7324
Table 17-4. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those
specified below
–
V
VIH2
0.8 VDD
VDD
P1, P3, RESET, P2.0- 1 and
P6.1- 3
VIH3
VIL1
XIN, XOUT, XTIN, and XTOUT
VDD – 0.1
–
VDD
0.3 VDD
Input low
voltage
All input pins except those
specified below
–
–
V
V
VIL2
0.2 VDD
P1, P3, RESET, P2.0- 1 and
P6.1- 3
VIL3
XIN, XOUT, XTIN, and XTOUT
0.1
–
VOH1
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
VDD – 1.0
VDD – 2.0
Output high
voltage
Ports 1, 4, 5, and 6
VOH2
VDD = 4.5 V to 5.5 V
IOH = –100 µA Port 8 and 9
17-4
S3C7324/P7324
S3P7324 OTP
Table 17-4. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 1, 4, 5, and 6
Output low
voltage
–
0.4
2
V
VOL2
VDD = 4.5 V to 5.5 V
–
–
–
–
1
3
IOL = 100 mA ; Ports 8 and 9
ILIH1
VIN = VDD
Input high
leakage
current(note)
mA
All input pins
ILIL1
ILOH1
ILOL
RL1
VIN = 0 V
Input low
leakage
–
–
–
–
– 3
3
All input pins
current(note)
VOUT = VDD
Output high
leakage
current(note)
All output pins
VOUT = 0 V
Output low
leakage
current (note)
–
–
– 3
80
All output pins
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
VDD = 3 V
Pull-up
resistor
20
40
KW
30
95
200
400
RL2
VIN = 0 V; VDD = 5 V
100
230
RESET
VDD = 3 V
200
480
800
NOTE: Except for X , X
, XT , and XT
OUT
IN OUT
IN
17-5
S3P7324 OTP
S3C7324/P7324
Table 17-4. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
RLCD
LCD voltage
dividing
60
84
130
KW
TA = 25 øC
resistor
RCOM
RSEG
VDC
VDD = 5 V
VDD = 3 V
VDD = 5 V
VDD = 3 V
COM output
impedance
SEG output
impedance
3
5
6
15
6
-
–
–
3
5
15
± 90
VDD = 5 V (VLC0-COMi)
COM output
voltage
deviation
mV
± 45
Io = ± 15uA (I = 0–3)
VDD = 5 V (VLC0-SEGi)
SEG output
voltage
deviation
VDS
–
± 45
600
± 90
Io = ± 15uA (I = 0–27)
ROSC1
VDD = 5.0 V; TA = 25; XIN = VDD
XOUT = 0 V
,
Oscillator
feedback
resistor
300
1230
1500
4000
KW
ROSC2
VDD = 5.0 V; TA = 25; XTIN = VDD
XTOUT = 0 V
,
2630
17-6
S3C7324/P7324
S3P7324 OTP
Table 17-4. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter Symbol
Conditions
Min
Typ
Max
Units
Main operating:
IDD1
Supply
Current(1)
4.19 MHz
6.0 MHz
–
5.2
10
mA
FC enable
PCON = 0011B, SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
(2)
Main operating:
–
3.5
2.5
8
IDD2
PCON = 0011B, SCMOD = 0000B 4.19 MHz
Crystal oscillator
5.5
C1 = C2 = 22 pF
VDD = 5 V ± 10%
6.0 MHz
1.6
4
VDD = 3 V ± 10%
4.19 MHz
6.0 MHz
1.2
1.0
3
(2)
IDD3
Main idle mode(3):
–
2.5
PCON = 0111B, SCMOD =0000B
Crystal oscillator
4.19 MHz
0.9
2.0
C1 = C2 = 22 pF
VDD = 5 V ± 10%
6.0 MHz
0.5
1.0
VDD = 3 V ± 10%
4.19 MHz
0.4
15
0.8
30
(2)
(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
VDD = 3 V ± 10%
–
–
uA
IDD4
32 kHz crystal oscillator
Sub idle mode:
6
15
3
IDD5
PCON = 0111B, SCMOD = 1001B
VDD = 3 V ± 10%
32 kHz crystal oscillator
(2)
(2)
Stop mode:
CPU = fxt/4, SCMOD = 1101B
VDD = 5 V ± 10%
–
–
0.5
IDD6
Stop mode:
IDD7
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. AMF or FMF is a normal input mode.
3. Data includes the power consumption for sub-system clock oscillation.
17-7
S3P7324 OTP
S3C7324/P7324
Table 17-5. Main System Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Ceramic
Oscillator
Oscillation frequency
(1)
–
0.4
–
6.0
MHz
X
IN
X
OUT
C1
C2
Stabilization time (2)
Stabilization occurs
when VDD is equal to
–
–
–
4
ms
the minimum oscillator
voltage range.
Crystal
Oscillator
Oscillation frequency
–
0.4
6.0
MHz
IN
OUT
X
X
X
X
(1)
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 2.7 V
–
–
–
–
–
–
10
30
ms
XIN input frequency (1)
External
Clock
0.4
6.0
MHz
IN
OUT
X
XIN input high and low
level width (tXH, tXL)
–
83.3
0.4
–
–
ns
Frequency (1)
VDD = 5 V
RC
Oscillator
2.5
MHz
-
X
OUT
IN
2.0
1.0
R = 15 KW, VDD = 5 V
R = 25 KW, VDD = 3 V
R
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
17-8
S3C7324/P7324
S3P7324 OTP
Table 17-6. Subsystem Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max
Units
Configuration
Crystal
Oscillator
Oscillation frequency
(1)
–
32
32.768
35
kHz
XT
XT
OUT
IN
C1
C2
(2)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 2.7 V
–
–
–
1.0
–
2
s
Stabilization time
10
XTIN input frequency
External
Clock
32
–
100
kHz
IN
OUT
XT
XT
(1)
XT input high and
IN
–
5
–
15
ms
low level width (tXTL
,
tXTH
)
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
17-9
S3P7324 OTP
S3C7324/P7324
Table 17-7. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
fCLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
COUT
CIO
Output
capacitance
–
–
–
–
15
15
pF
pF
I/O capacitance
Table 17-8. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction cycle
0.67
–
64
64
–
ms
(1)
VDD = 1.8 V to 5.5 V
INT0
1.3
time
(2)
tINTH, tINTL
Interrupt input
high, low width
–
–
ms
ms
INT1, INT2, INT4, KS0–KS2
Input
10
10
tRSL
–
RESET Input Low
Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2t or 128/fxx as assigned by the IMOD0 register setting.
CY
Table 17-8. A.C. Electrical Characteristics (continued)
(TA = – 10 C to + 70 C, VDD = 3.5 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
8
8
8
bits
Absolute accuracy
–
–
–
–
–
LSB
± 2
34/fxx (note)
tCON
AD conversion
time
17
–
ms
VIAN
RAN
VSS
2
VDD
–
Analog input
voltage
–
–
–
V
Analog input
impedance
1000
MW
NOTE: fxx stands for the system clock (fx or fxt).
17-10
S3C7324/P7324
S3P7324 OTP
Table 17-8. A.C. Electrical Characteristics (continued)
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIN
VDD
Input voltage
(peak to peak)
AMF/FMF mode, sine
wave input
0.3
–
V
fAMF
fFMF
Frequency
AMF mode, sine wave
input; VIN = 300mVP-P
0.5
30
–
10
MHz
FMF mode, sine wave
input; VIN = 300mVP-P
150
CPU CLOCK
Main OSC. Freq.
1.5 MHz
6 MHz
4.19 MHz
1.0475 MHz
3 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
400 kHz
7
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
When FC operates, operating voltage range is 3.0 V to 5.5 V.
Figure 17-2. Standard Operating Voltage Range
Table 17-9. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Normal operation
VDDDR = 1.8 V
Min
Typ
Max
Unit
VDDDR
Data retention supply voltage
1.8
–
5.5
V
IDDDR
Data retention supply current
–
0.1
1
mA
17-11
S3P7324 OTP
S3C7324/P7324
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
STOP MODE
DATA RETENTION MODE
MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 17-3. Stop Mode Release Timing When Initiated by RESET
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 17-4. Stop Mode Release Timing When Initiated by an Interrupt Request
17-12
S3C7324/P7324
S3P7324 OTP
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
MEASUREMENT
POINTS
Figure 17-5. A.C. Timing Measurement Points (Except for X and XT )
in in
1 / f
x
t
t
XH
XL
X
in
V
DD
– 0.1 V
0.1 V
Figure 17-6. Clock Timing Measurement at X
in
1 / f
xt
t
t
XTH
XTL
XT
in
V
DD
– 0.1 V
0.1 V
Figure 17-7. Clock Timing Measurement at XT
in
17-13
S3P7324 OTP
S3C7324/P7324
t
RSL
RESET
0.2 V
DD
Figure 17-8. Input Timing for RESET Signal
t
t
INTL
INTH
INT0, 1, 2, 4
KS0 to KS2
0.8 V
0.2 V
DD
DD
Figure 17-9. Input Timing for External Interrupts and Quasi-Interrupts
17-14
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