S3C7335XX-QW [SAMSUNG]
Microcontroller, 4-Bit, MROM, SAM47 CPU, 6MHz, CMOS, PQFP80, 14 X 20 MM, QFP-80;
| 型号： | S3C7335XX-QW |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, MROM, SAM47 CPU, 6MHz, CMOS, PQFP80, 14 X 20 MM, QFP-80 时钟 微控制器 外围集成电路 |
| 文件： | 总41页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C7335/P7335
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7335 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 4-channel A/D converter, 8-bit timer/counter, watch timer and
PLL frequency synthesizer, it offers you an excellent design solution for a wide variety of applications that require
LCD functions and audio applications.
Up to 56 pins of the 80-pin QFP package, it can be dedicated to I/O. Eight vectored interrupts provide fast
response to internal and external events. In addition, the S3C7335's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C7335 microcontroller is also available in OTP (One Time Programmable) version, S3P7335. The
S3P7335 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM.
The S3P7335 is comparable to S3C7335, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7335/P7335
FEATURES
Memory
A/D Converter
·
·
512-nibble RAM
16K-byte ROM
·
4-channels with 8-bit resolution
Bit Sequential Carrier Buffer
I/O Pins
·
Support 16-bit serial data transfer in arbitrary
format
·
·
·
Input only: 4 pins
PLL Frequency Synthesizer
Output only: 28 pins
I/O: 24 pins
·
·
·
Level = 300 mVp-p (min)
AMVCO range = 0.5 MHz to 30 MHz
FMVCO range = 30 MHz to 150 MHz
LCD Controller/Driver
·
·
·
Maximum 14-digit LCD direct drive capability
28 segment x 4 common signals
16-Bit Intermediate Frequency (IF) Counter
·
·
·
Level = 300 mVp-p (min)
Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
AMIF range = 100 kHz to 1 MHz
FMIF range = 5 MHz to 15 MHz
8-Bit Basic Timer
·
·
Programmable interval timer functions
Watch-dog timer function
8-Bit Timer/Counter
·
·
·
·
·
Programmable 8-bit timer
External event counter
Arbitrary clock frequency output
External clock signal divider
Serial I/O interface clock generator
Watch Timer
·
Time interval generation
: 0.5 s, 3.9 ms at 32.768 kHz
Frequency outputs to BUZ pin
Clock source generation for LCD
·
·
8-Bit Serial I/O Interface
·
·
·
·
8-bit transmit/receive mode
8-bit receive mode
Data direction selectable (LSB-first or MSB-first)
Internal or external clock source
1-2
S3C7335/P7335
PRODUCT OVERVIEW
FEATURES (Continued)
Interrupts
Instruction Execution Times
·
·
·
Four internal vectored interrupts
Four external vectored interrupts
Two quasi-interrupts
·
·
0.9, 1.8, 14.2 ms at 4.5 MHz
122 ms at 32.768 kHz (subsystem)
Operating Temperature
Memory-Mapped I/O Structure
Data memory bank 15
°
°
·
– 40 C to 85 C
·
Operating Voltage Range
Three Power-Down Modes
·
·
1.8 V to 5.5 V at 3MHz
·
·
·
·
Idle: Only CPU clock stops
PLL/IFC operation: 2.5V to 3.5V or 4.0V to 5.5V
Stop1: Main system or subsystem clock stops
Stop2: Main system and subsystem clock stop
CE low: PLL and IFC stop
Package Type
80-pin QFP
·
Oscillation Sources
·
Crystal or ceramic oscillator for main system
clock
·
·
·
·
Crystal for subsystem clock
Main system clock frequency: 4.5 MHz (Typ)
Subsystem clock frequency: 32.768 kHz (Typ)
CPU clock divider circuit (by 4, 8, or 64)
1-3
PRODUCT OVERVIEW
S3C7335/P7335
BLOCK DIAGRAM
P0.0/BTCO
P0.1/TCLO0
P0.2/TCL0
P0.3/BUZ
INT0-INT4
RESET
Basic
Timer
Watch
Timer
Watchdog
Timer
I/O Port 0
X
IN
XTIN
OUT
XT
OUT
X
CE
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
Timer/
Counter 0
Input Port 1
I/O Port 2
I/O Port 3
Interrupt
Control
Block
Instruction
Register
AMIF
IF
Clock
P2.0
P2.1
P2.2
P2.3
Counter
FMIF
VCOAM
VCOFM
EO
PLL
Synthesizer
Program
Counter
P3.0
P3.1
P3.2
P3.3
Internal
Interrupts
BIAS
VLC0-VLC2
COM0-COM3
LCD Driver/
Controller
Program
Status Word
Serial
I/O Port
Instruction Decoder
P13.0-P13.3
/SEG24-SEG27
P12.0-P12.3
/SEG20-SEG23
P11.0-P11.3
/SEG16-SEG19
Arithmetic
and
Logic Unit
Output Port
11,12,13
P4.0/SCK
P4.1/SO
P4.2/SI
Stack
Pointer
I/O Port 4
I/O Port 5
P4.3/CLO
P10.0-P10.3
/SEG12-SEG15
P9.0-P9.3
/SEG8-SEG11
P8.0-P8.3
/SEG4-SEG7
P7.0-P7.3
/SEG0-SEG3
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
Output Port
7,8,9,10
512 x 4-Bit
Data Memory
16K-Byte
Program Memory
A/D
Converter
I/O Port 6
P6.0-P6.3
KS0-KS3
Figure 1-1. S3C7335 Simplified Block Diagram
1-4
S3C7335/P7335
PRODUCT OVERVIEW
PIN ASSIGNMENTS
P4.1/SO
P4.2/SI
P4.3/CLO
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
VDD0
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
FMIF
AMIF
VSS1
VCOAM
VCOFM
P2.3
P2.2
P2.1
P2.0
SEG27/P13.3
SEG26/P13.2
SEG25/P13.1
SEG24/P13.0
SEG23/P12.3
SEG22/P12.2
SEG21/P12.1
SEG20/P12.0
SEG19/P11.3
SEG18/P11.2
SEG17/P11.1
SEG16/P11.0
SEG15/P10.3
SEG14/P10.2
SEG13/P10.1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S3C7335
(80-QFP-Top View)
VSS0
XOUT
XIN
TEST
XTIN
XTOUT
RESET
BIAS
VLC0
VLC1
VLC2
COM0
Figure 1-2. S3C7335 80-QFP Pin Assignment
1-5
PRODUCT OVERVIEW
S3C7335/P7335
PIN DESCRIPTIONS
Table 1-1. S3C7335 Pin Descriptions
Description
Pin Name
Pin
Number Share Reset Circuit
Type
Pin
Value
Type
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit or 4-bit read, write, and test are possible.
Pull-up resistors can be configured by software.
72
73
74
75
BTCO Input
TCLO0
TCL0
D-2
D-2
D-4
D-2
BUZ
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit or 4-bit read and test are possible.
Pull-up resistors can be configured by software.
76
77
78
79
INT0
INT1
INT2
INT4
Input
Input
A-4
P2.0-P2.3
P3.0-P3.3
I/O
4-bit I/O ports.
56-59
–
D-2
1-bit, 4-bit or 8-bit read, write and test are possible. 68-71
Pull-up resistors can be configured by software.
Ports 2 and 3 can be paired to support 8-bit data
transfer.
P4.0
P4.1
P4.2
P4.3
I/O
4-bit I/O ports.
1-bit, 4-bit or 8-bit read, write and test are possible.
Pull-up resistors can be configured by software.
80
1
2
Input
D-4
D-2
D-4
D-2
SCK
SO
SI
3
CLO
P5.0
P5.1
P5.2
P5.3
I/O
I/O
O
Ports 4 and 5 can be paired to support 8-bit data
transfer.
4
5
6
7
ADC0
ADC1
ADC2
ADC3
Input
Input
F-10
P6.0
P6.1
P6.2
P6.3
4-bit I/O port.
1-bit, 4-bit or 8-bit read, write and test are possible.
Pull-up resistors can be configured by software.
8
9
10
11
KS0
KS1
KS2
KS3
D-7
P7.0
P7.1
P7.2
P7.3
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
28
29
30
31
SEG0 Output
SEG1
SEG2
H-28
H-28
H-28
H-28
SEG3
P8.0
P8.1
P8.2
P8.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
32
33
34
35
SEG4 Output
SEG5
SEG6
SEG7
P9.0
P9.1
P9.2
P9.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
36
37
38
39
SEG8 Output
SEG9
SEG10
SEG11
P10.0
P10.1
P10.2
P10.3
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
40
41
42
43
SEG12 Output
SEG13
SEG14
SEG15
1-6
S3C7335/P7335
Pin Name
PRODUCT OVERVIEW
Table 1-1. S3C7335 Pin Descriptions (Continued)
Description Number Share Reset Circuit
Pin
Type
Pin
Value
Type
P11.0
P11.1
P11.2
P11.3
O
O
O
O
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
44
45
46
47
SEG16 Output
SEG17
SEG18
H-28
SEG19
P12.0
P12.1
P12.2
P12.3
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
48
49
50
51
SEG20 Output
SEG21
SEG22
H-28
H-28
H
SEG23
P13.0
P13.1
P13.2
P13.3
1-bit or 4-bit output port.
Alternatively used for LCD segment output.
52
53
54
55
SEG24 Output
SEG25
SEG26
SEG27
COM0-
COM3
Common signal output for LCD display
LCD power control
24-27
–
Output
BIAS
VLC0
I
I
20
–
–
Input
Input
–
–
LCD power supply.
Voltage dividing resistors are assignable by
software
21
22
23
VLC1
VLC2
VDD0
VSS0
–
–
I
Main power supply
Main Ground
12
13
19
–
–
–
–
–
–
–
B
–
System reset pin
Input
–
RESET
XOUT
–
Crystal, or ceramic oscillator pin for main system
clock. (For external clock input, use XIN and input
XIN’s reverse phase to XOUT
14
15
–
XIN
)
XTOUT
XTIN
–
Crystal oscillator pin for subsystem clock. (For
external clock input, use XTIN and input XTIN’s
18
17
–
–
–
reverse phase to XTOUT
)
Test signal input (must be connected to VSS for
normal operation)
TEST
CE
I
I
16
67
–
–
–
–
Input pin for checking device power.
Normal operation is high level and PLL/IFC
operation is stopped at low level.
Input
B-5
VCOFM
VCOAM
I
External VCOFM/AM signal inputs.
60
61
–
Input
B-4
EO
O
I
PLL’s phase error output
66
–
Output
–
A-2
B-4
FMIF
AMIF
FM/AM intermediate frequency signal inputs.
64
63
Input
VDD1
VSS1
–
–
PLL/IFC power supply
PLL/IFC ground
65
62
–
–
–
–
–
–
1-7
PRODUCT OVERVIEW
S3C7335/P7335
Table 1-1. S3C7335 Pin Descriptions (Concluded)
Pin Name
Pin
Description
Number Share Reset Circuit
Type
Pin
Value
Input
Input
Input
Input
Type
D-2
D-2
D-4
D-2
BTCO
TCLO0
TCL0
BUZ
I/O
I/O
I/O
I/O
Basic timer overflow output signal
Timer/counter 0 clock output signal
External clock input for timer/counter 0
72
73
74
75
P0.0
P0.1
P0.2
P0.3
2,4,8 or 16 kHz frequency output for buzzer sound
for 4.19 MHz main system clock or 32.768 kHz
subsystem clock
INT0
INT1
I
External interrupt. The triggering edges
(rising/falling) are selectable. Only INT0 is
synchronized with system clock.
76
77
P1.0
P1.1
Input
A-4
INT2
INT4
I
I
Quasi-interrupt with detection of rising edge signal.
78
79
P1.2
P1.3
External interrupt input with detection of rising or
falling edges.
I/O
SIO interface clock signal
80
P4.0
Input
D-4
SCK
SI
I/O
I/O
I/O
I/O
SIO interface data input signal
SIO interface data output signal
CPU clock output
1
2
P4.2
P4.1
P4.3
SO
CLO
KS0-KS3
3
Quasi-interrupt input with falling edge detection
8-11
P6.0-
P6.3
Input
Input
D-7
ADC0-
ADC3
I/O
O
ADC input ports.
4-7
P5.0-
P5.3
F-10
H-28
H-28
SEG0-
SEG3
LCD segment signal output.
LCD segment signal output.
28-31
P7.0- Output
P7.3
SEG4-
SEG27
O
32-55 P8-P13 Output
1-8
S3C7335/P7335
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
In
In
N-Channel
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-6. Pin Circuit Type B (RESET)
VDD
In
Type A
P-Channel
Up
Feedback
Enable
Out
Down
N-Channel
N-CH
Pull-Down
Enable
Figure 1-4. Pin Circuit Type A-2(EO)
Figure 1-7. Pin Circuit Type B-4
VDD
In
Pull-Up
Enable
In
Figure 1-5. Pin Circuit Type A-4 (P1)
Figure 1-8. Pin Circuit Type B-5(CE)
1-9
PRODUCT OVERVIEW
S3C7335/P7335
VDD
VDD
Pull-up
Enable
P-Channel
I/O
P-Channel
Out
Data
Data
Circuit
Type C
Output
Disable
N-Channel
Output
Disable
Schmitt Trigger
Figure 1-9. Pin Circuit Type C
Figure 1-11. Pin Circuit Type D-4
VDD
VDD
Pull-up
Enable
P-Channel
Pull-up
Enable
P-Channel
I/O
Data
I/O
Circuit
Type C
Data
Circuit
Type C
Output
Disable
Output
Disable
Port
Enable
Schmitt Trigger
Figure 1-10. Pin Circuit Type D-2
Figure 1-12. Pin Circuit Type D-7 (P6)
1-10
S3C7335/P7335
PRODUCT OVERVIEW
VDD
VLC0
VLC1
Pull-up
Enable
Data
Circuit
Output
Disable
Type C
I/O
SEG
Out
ADCEN
Output
Disable
ADC Select
Data
VLC2
TO ADC
Figure1-13. Pin Circuit Type F-10 (P5)
Figure 1-15. Pin Circuit Type H-4
VLC0
VDD
PNE
VLC1
P-CH
N-CH
Data
Output
LCD
COM
Out
Output
DIsable
VLC2
Circuit
Type H-4
SEG
Figure 1-16. Pin Circuit Type H-28 (P7-P13)
Figure 1-14. Pin Circuit Type H (COM0-COM3)
1-11
S3C7335/P7335
ELECTRICAL DATA
17 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7335 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— Input timing for RESET
— Input timing for external interrupts and Quasi-Interrupts
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
17-1
ELECTRICAL DATA
S3C7335/P7335
Table 17-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
VIN
VO
Supply voltage
Input voltage
–
- 0.3 to + 6.5
- 0.3 to VDD + 0.3
V
Applies to all I/O ports
- 0.3 to VDD + 0.3
- 15
Output voltage
Output current high
–
IOH
One I/O port active
mA
All I/O ports active
One I/O port active
-30
IOL
Output current low
+ 30 (peak value)
+ 15 (note)
+ 100 (peak value)
+ 60 *
Total value for output ports
TA
Operating temperature
Storage temperature
- 40 to + 85
°
C
TSTG
- 65 to + 150
NOTE: The values for output current low ( IOL ) are calculated as Peak Value ´ Duty .
17-2
S3C7335/P7335
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those specified
below
–
V
VIH2
0.8 VDD
VDD
P0.2, P1, P4.0, P4.2, P5, P6, CE and
RESET
VIH3
VIL1
XIN, XOUT, XTIN, and XTOUT
VDD–0.1
–
VDD
0.3 VDD
Input low
voltage
All input pins except those specified
below
–
–
VIL2
0.2 VDD
P0.2, P1, P4.0, P4.2, P5, P6, CE and
RESET
VIL3
XIN, XOUT, XTIN, and XTOUT
0.1
VOH1
VDD = 4.5 V to 5.5 V, EO;
IOH = – 1 mA
VDD–2.0
VDD–1.0
VDD
Output high
voltage
VOH2
VDD = 4.5 V to 5.5 V;
VDD
Other output ports;
IOH = – 1 mA
VOL1
VOL2
ILIH
VDD = 4.5 V to 5.5 V, EO;
IOL = 1 mA,
Output low
voltage
–
–
–
–
–
–
2.0
2
VDD = 4.5 V to 5.5 V
Other output ports; IOL = 10 mA
VIN = VDD
Input high
leakage
current(note)
3
mA
All input pins
ILIL
VIN = 0 V
Input low
leakage
–
–
–
–
- 3
3
All input pins
current(note)
ILOH
VOUT = VDD
Output high
leakage
current(note)
All output pins
NOTE: Except for X
X XT and XT
,
OUT IN OUT
,
.
IN
17-3
ELECTRICAL DATA
S3C7335/P7335
Table 17-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
°
VLC0 output
voltage
VLC0
0.6 VDD
0.2
–
–
–
0.6 VDD
0.6 VDD
+ 0.2
V
TA = 25 C
°
VLC1 output
voltage
VLC1
VLC2
VDC
0.4 VDD
0.2
0.4 VDD
0.2 VDD
± 45
0.4 VDD
+ 0.2
TA = 25 C
°
VLC2 output
voltage
0.2 VDD
0.2
0.2 VDD
+ 0.2
TA = 25 C
VDD = 5V, (VLC0 - COMi I = 0 - 3
)
)
COM output
voltage
deviation
–
mV
± 120
± 120
150
IO = ± 15 mA (I = 0 - 3)
VDS
VDD = 5V, (VLC0 - COMi I = 0 - 3
SEG output
voltage
deviation
± 45
100
IO = ± 15 mA (I = 0 - 3)
°
RLCD
LCD output
voltage
70
KW
TA = 25 C
deviation
°
ROSC1
Oscillator
feed back
resistors
300
600
1500
4500
VDD = 5.0 V, TA = 25 C
XIN = VDD, XOUT = 0 V
°
ROSC2
1500
3000
VDD = 5.0 V, TA = 25 C
XTIN = VDD, XTOUT = 0 V
RD
VDD = 5.0 V, VIN = VDD;
Pull-down
resistor
15
25
30
47
45
VCOFM, VCOAM, AMIF, and FMIF
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
VDD = 3 V
RL1
Pll-up
Resistor
100
50
95
200
400
RL2
VIN = 0 V; VDD = 5 V
100
220
RESET
VDD = 3 V
200
450
800
17-4
S3C7335/P7335
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter Symbol
Conditions
Min
Typ
Max
Units
(2)
Supply
Current(1)
Main operating, PLL operating:
4.5 MHz
–
5.5
27
mA
IDD1
PCON = 0011B, SCMOD = 0000B
CE = VDD
;
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
(2)
CE Low,
6.0 MHz
–
3.5
2.5
8
IDD2
PCON = 0011B, SCMOD = 0000B 4.5 MHz
CE = 0 V
5.5
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
6.0 MHz
4.5 MHz
6.0 MHz
4.5 MHz
1.6
1.2
1.0
0.9
4
VDD = 3 V ± 10%
3
(2)
Main idle mode,
–
2.5
2.0
IDD3
PCON = 0111B, SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
6.0 MHz
4.5MHz
0.5
0.4
15
1.0
0.8
30
VDD = 3 V ± 10%
(2)
(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
CE = 0 V;
–
–
uA
IDD4
VDD = 3 V ± 10%
32 kHz crystal oscillator
Sub idle mode:
6
15
3
IDD5
PCON = 0111B, SCMOD = 1001B
CE = 0 V;
VDD = 3 V ± 10%
32 kHz crystal oscillator
Stop mode:
(2)
(2)
–
–
0.5
IDD6
CPU = fxt/4, SCMOD = 1101B
CE = 0 V;
VDD = 5 V ± 10%
Stop mode:
IDD7
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. Data includes the power consumption for sub-system clock oscillation.
17-5
ELECTRICAL DATA
S3C7335/P7335
Table 17-3. Main System Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
Oscillation frequency
(1)
0.4
–
6
MHz
XIN
XOUT
C1
C2
Stabilization time (2)
Stabilization occurs
when VDD is equal to
–
–
–
4
6
ms
the minimum oscillator
voltage range.
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
Oscillation frequency
(1)
0.4
MHz
XIN
XOUT
C1
C2
Stabilization time (2)
VDD = 4.5 V to 5.5 V
VDD = 1.8 V to 4.5 V
–
–
–
–
–
–
10
30
6
ms
XIN input frequency (1)
External
Clock
0.4
MHz
XIN
XOUT
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
17-6
S3C7335/P7335
ELECTRICAL DATA
Table 17-4. Subsystem Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Crystal
Oscillator
Oscillation frequency
(1)
–
32
32.768
35
kHz
XTIN XTOUT
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 4.5 V
–
–
–
1.0
–
2
s
10
XTIN input frequency
(1)
External
Clock
32
–
100
kHz
XTIN XTOUT
XT input high and
IN
–
5
–
15
ms
low level width (tXTL
,
tXTH
)
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
17-7
ELECTRICAL DATA
S3C7335/P7335
Table 17-5. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Symbol
Condition
Min
Typ
Max
Units
CIN
fCLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
capacitance
COUT
CIO
Output
capacitance
–
–
–
–
15
15
pF
pF
I/O capacitance
Table 17-6. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction cycle
0.67
–
64
ms
time (1)
VDD = 1.8 V to 5.5 V
INT0
1.3
64
–
(2)
tINTH, tINTL
Interrupt input
high, low width
–
1
ms
ms
INT1, INT2, INT4, KS0–KS2
Input
10
10
tRSL
–
RESET and CE
Input Low Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2t or 128/fxx as assigned by the IMOD0 register setting.
CY
Table 17-6. A.C. Electrical Characteristics (Continued)
(TA = – 10 C to + 70 C, VDD = 3.5 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
–
8
–
bits
Absolute accuracy
–
–
–
–
–
LSB
± 2
34/fxx (note)
tCON
AD conversion
time
17
–
ms
VIAN
RAN
VSS
2
VDD
–
Analog input
voltage
–
–
V
VDD = 5 V
Analog input
impedance
1000
MW
NOTE: fxx stands for the system clock (fx or fxt).
17-8
S3C7335/P7335
ELECTRICAL DATA
Table 17-6. A.C. Electrical Characteristics (Continued)
(TA = – 40 C to + 85 C, VDD = 2.5 V to 3.5 V or VDD = 4.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Sine wave input
Min
Typ
Max
Units
VIN
VDD
VCOFM, VCOAM,
FMIF and AMIF
Input Voltage
0.3
–
V
(Peak to Peak)
fVCOAM
fVCOFM
fAMIF
Frequency
VCOAM mode, sine wave input;
VIN = 0.3VP-P
0.5
30
0.1
5
–
30
150
1.0
15
MHz
VCOFM mode, sine wave input;
VIN = 0.3VP-P
AMIF mode, sine wave input;
VIN = 0.3VP-P
fFMIF
FMIF mode, sine wave input;
VIN = 0.3VP-P
17-9
ELECTRICAL DATA
S3C7335/P7335
Table 17-6. A.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction cycle
time (1)
0.67
–
64
ms
VDD = 1.8 V to 5.5 V
1.3
–
64
With subsystem clock (fxt)
VDD = 2.7 V to 5.5 V
114
0
122
–
125
1.5
fTI
TCL0 input
frequency
MHz
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7. V to 5.5 V
1
–
tTIH, tTIL
TCL0 input high,
low width
0.48
–
–
VDD = 1.8. V to 5.5 V
1.8
tKCY
VDD = 2.7 V to 5.5 V
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
Internal SCK source
800
–
–
ns
SCK cycle time
650
3200
3800
400
tKH, tKL
–
SCK high, low
width
tKCY/2- 50
1600
VDD = 1.8 V to 5.5 V
External SCK source
tKCY/2-150
100
Internal SCK source
External SCK source
Internal SCK source
tSIK
SI setup time to
–
–
–
–
–
150
SCK high
tKSI
SI hold time to
400
External SCK source
Internal SCK source
400
SCK high
tKSO
VDD = 2.7 V to 5.5 V
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
Output delay for
–
300
SCK to SO
250
1000
1000
Internal SCK source
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
17-10
S3C7335/P7335
ELECTRICAL DATA
CPU Clock
1.5 MHz
Main Oscillator Frequency
6 MHz
1.0475 MHz
1 MHz
4.19 MHz
3 MHz
750 kHz
250 kHz
15.6 kHz
400 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
When PLL/IFC operation, operating voltage range is 2.5 V
to 3.5 V or 4.0 V to 5.5 V.
Figure 17-1. Standard Operating Voltage Range
Table 17-7. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Normal operation
VDDDR = 1.8 V
Min
Typ
Max
Unit
VDDDR
Data retention supply voltage
1.8
–
5.5
V
IDDDR
Data retention supply current
–
0.1
1
mA
17-11
ELECTRICAL DATA
S3C7335/P7335
TIMING WAVEFORMS
Internal RESET
Operation
Idle Mode
Stop Mode
Operating Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instruction
RESET
tWAIT
tSREL
Figure 17-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
Normal
Operating
Mode
Stop Mode
Data Retention
VDD
VDDDR
tSREL
Execution of
STOP Instruction
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 17-3. Stop Mode Release Timing When Initiated by an Interrupt Request
17-12
S3C7335/P7335
ELECTRICAL DATA
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Measurement
Points
Figure 17-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 17-5. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 17-6. Clock Timing Measurement at XTIN
17-13
ELECTRICAL DATA
S3C7335/P7335
tRSL
RESET
0.2 VDD
Figure 17-7. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4,
KS0 to KS2
0.8 VDD
0.2 VDD
Figure 17-8. Input Timing for External Interrupts and Quasi-Interrupts
17-14
S3C7335/P7335
MECHANICAL DATA
18 MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
— Pad/pin coordinate data table
23.90 ± 0.30
20.00 ± 0.20
0-8
+ 0.10
0.15 - 0.05
0.10 MAX
80-QFP-1420C
#80
#1
0.35 + 0.10
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.80
0.15 MAX
(0.80)
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 18-1. 80-QFP-1420C Package Dimensions
18-1
S3C7335/P7335
S3P7335 OTP
19 S3P7335 OTP
OVERVIEW
The S3P7335 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7335
microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a serial data
format.
The S3P7335 is fully compatible with the S3C7335, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7335 is ideal for use as an evaluation chip for the S3C7335.
19-1
S3P7335 OTP
S3C7335/P7335
P4.1/SO
P4.2/SI
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
FMIF
AMIF
VSS1
VCOAM
VCOFM
P2.3
P2.2
P2.1
P4.3/CLO
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
P6.0/KS0
P6.1/KS1
SDAT/P6.2/KS2
SCLK/P6.3/KS3
VDD/VDD0
VSS/VSS0
XOUT
9
P2.0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SEG27/P13.3
SEG26/P13.2
SEG25/P13.1
SEG24/P13.0
SEG23/P12.3
SEG22/P12.2
SEG21/P12.1
SEG20/P12.0
SEG19/11.3
SEG18/P11.2
SEG17/P11.1
SEG16/P11.0
SEG15/P10.3
SEG14/P10.2
SEG13/P10.3
S3P7335
(80-QFP Top View)
XIN
VPP/TEST
XTIN
XTOUT
RESET /RESET
BIAS
VLC0
VLC1
VLC2
COM0
Figure 19-1. S3P7335 Pin Assignments (80-QFP)
19-2
S3C7335/P7335
S3P7335 OTP
Table 19-1. Pin Descriptions Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P6.2
Pin Name
SDAT
Pin No.
I/O
Function
10
I/O
Serial data pin. Output port when reading and input port
when writing. Can be assigned as a Input or push-pull
output port.
P6.3
SCLK
11
16
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing (indicates that
OTP enters into the writing mode). When 12.5 V is
applied, OTP is in writing mode and when 5 V is applied,
OTP is in reading mode.
19
I
I
Chip initialization
RESET
RESET
VDD / VSS
VDD / VSS
Logic power supply pin. VDD should be tied to +5 V
during programming.
12/13
Table 19-2. Comparison of S3P7335 and S3C7335 Features
Characteristic S3P7335
16K bytes EPROM
S3C7335
Program Memory
16K bytes mask ROM
Operating Voltage (VDD
)
1.8 V to 5.5 V
1.8 V to 5.5 V
2.5 V to 3.5 V or 4.0 V to 5.5 V
at PLL/IFC operation
2.5 V to 3.5 V or 4.0 V to 5.5 V
at PLL/IFC operation
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
80 QFP
80 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp (TEST) pin of the S3P7335, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 19-3. Operating Mode Selection Criteria
V
Vpp(TEST)
Address(A15-A0)
Mode
EPROM read
DD
REG/MEM
R/W
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means low level; "1" means high level.
19-3
S3P7335 OTP
S3C7335/P7335
Table 19-4. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those specified
below
–
V
VIH2
0.8 VDD
VDD
P0.2, P1, P4.0, P4.2, P5, P6, CE and
RESET
VIH3
VIL1
XIN, XOUT, XTIN, and XTOUT
VDD–0.1
–
VDD
0.3 VDD
Input low
voltage
All input pins except those specified
below
–
–
VIL2
0.2 VDD
P0.2, P1, P4.0, P4.2, P5, P6, CE and
RESET
VIL3
XIN, XOUT, XTIN, and XTOUT
0.1
VOH1
VDD = 4.5 V to 5.5 V, EO;
IOH = – 1 mA
VDD–2.0
VDD–1.0
VDD
Output high
voltage
VOH2
VDD = 4.5 V to 5.5 V;
VDD
Other output ports;
IOH = – 1 mA
VOL1
VOL2
ILIH
VDD = 4.5 V to 5.5 V, EO;
IOL = 1 mA,
Output low
voltage
–
–
–
–
–
–
2.0
2
VDD = 4.5 V to 5.5 V
Other output ports; IOL = 10 mA
VIN = VDD
Input high
leakage
current(note)
3
mA
All input pins
ILIL
ILOH
ILOL
VIN = 0 V
Input low
leakage
–
–
–
–
–
–
– 3
3
All input pins
current(note)
VOUT = VDD
Output high
leakage
current(note)
All output pins
VOUT = 0 V
Output low
leakage
current (note)
– 3
All output pins
NOTE: Except for X , X
, XT , and XT
OUT
IN OUT
IN
19-4
S3C7335/P7335
S3P7335 OTP
Table 19-4. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
°
VLC0 output
voltage
VLC0
0.6 VDD
0.2
–
–
–
0.6 VDD
0.6 VDD
+ 0.2
V
TA = 25 C
°
VLC1 output
voltage
VLC1
VLC2
VDC
0.4 VDD
0.2
0.4 VDD
0.2 VDD
± 45
0.4 VDD
+ 0.2
TA = 25 C
°
VLC2 output
voltage
0.2 VDD
0.2
0.2 VDD
+ 0.2
TA = 25 C
VDD = 5V, (VLC0 - COMi I = 0 - 3
)
)
COM output
voltage
deviation
–
mV
± 120
± 120
150
IO = ± 15 mA (I = 0 - 3)
VDS
VDD = 5V, (VLC0 - COMi I = 0 - 3
SEG output
voltage
deviation
± 45
100
IO = ± 15 mA (I = 0 - 3)
°
RLCD
LCD output
voltage
70
kW
TA = 25 C
deviation
°
ROSC1
Oscillator
feed back
resistors
300
600
1500
4500
VDD = 5.0 V, TA = 25 C
XIN = VDD, XOUT = 0 V
°
ROSC2
1500
3000
VDD = 5.0 V, TA = 25 C
XTIN = VDD, XTOUT = 0 V
RD
VDD = 5.0 V, VIN = VDD;
Pull-down
resistor
15
25
30
47
45
VCOFM, VCOAM, AMIF, and FMIF
VIN = 0 V; VDD = 5 V
Ports 1, 2, 3, 4, 5, and 6
VDD = 3 V
RL1
Pull-up
resistor
100
50
95
200
400
RL2
VIN = 0 V; VDD = 5 V
100
220
RESET
VDD = 3 V
200
450
800
19-5
S3P7335 OTP
S3C7335/P7335
Table 19-4. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter Symbol
Conditions
Min
Typ
Max
Units
(2)
Supply
Current(1)
Main operating:
4.5 MHz
–
5.5
27
mA
IDD1
PCON = 0011B, SCMOD = 0000B
CE = VDD
;
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
(2)
CE Low mate:
6.0 MHz
–
3.5
2.5
8
IDD2
PCON = 0011B, SCMOD = 0000B 4.5 MHz
CE = 0 V
5.5
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
6.0 MHz
4.5 MHz
6.0 MHz
4.5 MHz
1.6
1.2
1.0
0.9
4
VDD = 3 V ± 10%
3
(2)
Main idle mode:
–
2.5
2.0
IDD3
PCON = 0111B, SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
VDD = 5 V ± 10%
6.0 MHz
4.5MHz
0.5
0.4
15
1.0
0.8
30
VDD = 3 V ± 10%
(2)
(2)
Sub operating mode:
PCON = 0011B, SCMOD = 1001B
CE = 0 V;
–
–
uA
IDD4
VDD = 3 V ± 10%
32 kHz crystal oscillator
Sub idle mode:
6
15
3
IDD5
PCON = 0111B, SCMOD = 1001B
CE = 0 V;
VDD = 3 V ± 10%
32 kHz crystal oscillator
Stop mode:
(2)
(2)
–
–
0.5
IDD6
CPU = fxt/4, SCMOD = 1101B
CE = 0 V;
VDD = 5 V ± 10%
Stop mode:
IDD7
CPU = fx/4, SCMOD = 0100B
VDD = 5 V ± 10%
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors and LCD voltage dividing resistors.
2. Data includes the power consumption for sub-system clock oscillation.
19-6
S3C7335/P7335
S3P7335 OTP
Table 19-5. Main System Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
Oscillation frequency
(1)
0.4
–
6
MHz
XIN
XOUT
C1
C2
Stabilization time (2)
Stabilization occurs
when VDD is equal to
–
–
–
4
6
ms
the minimum oscillator
voltage range.
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
Oscillation frequency
(1)
0.4
MHz
XIN
XOUT
C1
C2
Stabilization time (2)
VDD = 4.5 V to 5.5 V
VDD = 1.8 V to 4.5 V
–
–
–
–
–
–
10
30
6
ms
XIN input frequency (1)
External
Clock
0.4
MHz
XIN
XOUT
XIN input high and low
level width (tXH, tXL)
–
83.3
–
–
ns
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
19-7
S3P7335 OTP
S3C7335/P7335
Table 19-6. Subsystem Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillato
r
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max Units
Crystal
Oscillator
Oscillation frequency
(1)
–
32
32.768
35
kHz
XTIN XTOUT
C1
C2
(2)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 4.5 V
–
–
–
1.0
–
2
s
Stabilization time
10
XTIN input frequency (1)
External
Clock
32
–
100
kHz
XTIN XTOUT
XT input high and low
IN
–
5
–
15
ms
level width (tXTL, tXTH
)
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
19-8
S3C7335/P7335
S3P7335 OTP
Table 19-7. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Symbol
Condition
Min
Typ
Max
Units
CIN
fCLK = 1 MHz; Unmeasured
pins are returned to VSS
–
–
15
pF
capacitance
COUT
CIO
Output
capacitance
–
–
–
–
15
15
pF
pF
I/O capacitance
Table 19-8. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction cycle
0.67
–
64
ms
(1)
VDD = 1.8 V to 5.5 V
INT0
1.3
64
–
time
(2)
tINTH, tINTL
Interrupt input
high, low width
–
1
ms
ms
INT1, INT2, INT4, KS0–KS2
Input
10
10
tRSL
–
RESET and CE
Input Low Width
NOTES:
1. Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
2. Minimum value for INT0 is based on a clock of 2t or 128/fxx as assigned by the IMOD0 register setting.
CY
Table 19-8. A.C. Electrical Characteristics (continued)
(TA = – 10 C to + 70 C, VDD = 3.5 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
A/D converting
Resolution
–
–
–
8
–
bits
Absolute accuracy
–
–
–
–
–
LSB
± 2
34/fxx (note)
tCON
AD conversion
time
17
–
ms
VIAN
RAN
VSS
2
VDD
–
Analog input
voltage
–
–
V
VDD = 5 V
Analog input
impedance
1000
MW
NOTE: fxx stands for the system clock (fx or fxt).
19-9
S3P7335 OTP
S3C7335/P7335
Table 19-8. A.C. Electrical Characteristics (Continued)
(TA = – 40 C to + 85 C, VDD = 2.5 V to 3.5 V or VDD = 4.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Sine wave input
Min
Typ
Max
Units
VIN
VDD
VCOFM, VCOAM,
FMIF and AMIF
Input Voltage
0.3
–
V
(Peak to Peak)
fVCOAM
fVCOFM
fAMIF
Frequency
VCOAM mode, sine wave input;
VIN = 0.3VP-P
0.5
30
0.1
5
–
30
150
1.0
15
MHz
VCOFM mode, sine wave input;
VIN = 0.3VP-P
AMIF mode, sine wave input;
VIN = 0.3VP-P
fFMIF
FMIF mode, sine wave input;
VIN = 0.3VP-P
19-10
S3C7335/P7335
S3P7335 OTP
Table 19-8. A.C. Electrical Characteristics (continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction cycle
time (1)
0.67
–
64
ms
VDD = 1.8 V to 5.5 V
1.3
–
64
With subsystem clock (fxt)
VDD = 2.7 V to 5.5 V
114
0
122
–
125
1.5
fTI
TCL0 input
frequency
MHz
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7. V to 5.5 V
1
–
tTIH, tTIL
TCL0 input high,
low width
0.48
–
–
VDD = 1.8. V to 5.5 V
1.8
tKCY
VDD = 2.7 V to 5.5 V
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
Internal SCK source
VDD = 2.7 V to 5.5 V
External SCK source
Internal SCK source
800
–
–
ns
SCK cycle time
650
3200
3800
400
tKH, tKL
–
SCK high, low
width
tKCY/2- 50
1600
VDD = 1.8 V to 5.5 V
External SCK source
tKCY/2-150
100
Internal SCK source
External SCK source
Internal SCK source
tSIK
SI setup time to
–
–
–
–
–
150
SCK high
tKSI
SI hold time to
400
External SCK source
Internal SCK source
400
SCK high
tKSO
VDD = 2.7 V to 5.5 V
External SCK source
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
Output delay for
–
300
SCK to SO
250
1000
1000
Internal SCK source
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock/4 (fx/4) source.
19-11
S3P7335 OTP
S3C7335/P7335
CPU Clock
1.5 MHz
Main Oscillator Frequency
6 MHz
1.0475 MHz
1 MHz
4.19 MHz
3 MHz
750 kHz
250 kHz
15.6 kHz
400 kHz
1
2
3
4
5
6
7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
When PLL/IFC operation, operating voltage range is 2.5 V
to 3.5 V or 4.0 V to 5.5 V.
Figure 19-2. Standard Operating Voltage Range
Table 19-9. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Normal operation
VDDDR = 1.8 V
Min
Typ
Max
Unit
VDDDR
Data retention supply voltage
1.8
–
5.5
V
IDDDR
Data retention supply current
–
0.1
1
mA
19-12
S3C7335/P7335
S3P7335 OTP
TIMING WAVEFORMS
Internal RESET
Operation
Idle Mode
Stop Mode
Operating Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instruction
RESET
tWAIT
tSREL
Figure 19-3. Stop Mode Release Timing When Initiated by RESET
Idle Mode
Normal
Operating
Mode
Stop Mode
Data Retention
VDD
VDDDR
tSREL
Execution of
STOP Instruction
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 19-4. Stop Mode Release Timing When Initiated by an Interrupt Request
19-13
S3P7335 OTP
S3C7335/P7335
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Measurement
Points
Figure 19-5. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 19-6. Clock Timing Measurement at XIN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 19-7. Clock Timing Measurement at XTIN
19-14
S3C7335/P7335
S3P7335 OTP
tRSL
RESET
0.2 VDD
Figure 19-8. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4,
KS0 to KS2
0.8 VDD
0.2 VDD
Figure 19-9. Input Timing for External Interrupts and Quasi-Interrupts
19-15
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