S3C921F [SAMSUNG]
SAM88RCRI family of 8-bit single-chip CMOS microcontrollers; SAM88RCRI系列的8位单芯片CMOS微控制器
| 型号： | S3C921F |
| 厂家： | 
SAMSUNG |
| 描述： | SAM88RCRI family of 8-bit single-chip CMOS microcontrollers |
| 文件： | 总30页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C921F/P921F
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide
range of integrated peripherals, and supports OTP device.
A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C921F/P921F MICROCONTROLLER
The S3C921F can be used for dedicated control functions in a variety of applications, and is especially designed
for application with voice synthesizer or etc.
The S3C921F/P921F single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built
around the powerful SAM88RCRI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C921F/P921F has 64 Kbytes of
program ROM and 192 Kbytes of data ROM on-chip (S3C921F), and 720 bytes of RAM including 16 bytes of
working register and 128 bytes of LCD display RAM.
Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:
— Four configurable I/O ports including ports shared with segment/common drive outputs
— 8-bit programmable pins for external interrupts
— One 8-bit basic timer for oscillation stabilization and watch-dog functions
— One 8-bit and one 16-bit timer/counter with selectable operating modes
— Watch timer for real time
— Two PWM modules for direct speaker drive
OTP
The S3C921F microcontroller is also available in OTP (One Time Programmable) version. S3P921F
microcontroller has an on-chip 256 Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P921F is comparable to S3C921F, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C921F/P921F
FEATURES
CPU
LCD Controller/Driver
•
SAM88RCRI CPU core
•
64 segments and 16 common terminals
•
•
8, 12, and 16 common selectable
Internal resistor circuit for LCD bias
Memory
•
64K ´ 8 bits program memory(ROM)
Two PWM Modules
•
•
192K ´ 8 bits data memory(ROM)
592 ´ 8 bits data memory(RAM)
•
5/6/7/8-bits PWM Selectable
(Excluding LCD data memory)
•
•
Direct speaker drive
2-bit extendable
Instruction Set
•
•
41 instructions
Voltage Level Detector
Idle and Stop instructions added for power-down
modes
•
•
Programmable low voltage detector
Two criteria voltage(2.7 V, 4.0 V)
32 I/O Pins
Two Power-Down Modes
•
•
I/O: 8 pins
I/O: 24 pins(Sharing with segment drive outputs)
•
•
Idle: only CPU clock stops
Stop: selected system clock and CPU clock stop
Interrupts
Oscillation Sources
•
•
15 interrupt source and 1 vector
One interrupt level
•
Crystal, ceramic, or RC for main clock
Main clock frequency: 0.4 MHz - 8MHz
•
•
32.768 kHz crystal oscillation circuit for
sub clock
8-Bit Basic Timer
•
•
Watchdog timer function
3 kinds of clock source
Instruction Execution Times
500nS at 8 MHz fx(minimum)
•
One 8-Bit Timer/Counter 0
Operating Voltage Range
•
Programmable interval timer
•
•
•
2.4 V to 5.5 V at 0.4 - 3MHz
2.7 V to 5.5 V at 0.4 - 4MHz
4.5 V to 5.5 V at 0.4 - 8MHz
•
•
External event counter function
PWM and Capture function
One 16-bit Timer/Counter 1
Operating Temperature Range
-40 °C to +85 °C
•
•
One 16-bit Timer/Counter mode
Two 8-bit Timer/Counters A/B mode
•
Watch Timer
Package Type
100-pin QFP Package
•
Interval time: 3.91mS, 0.25S, 0.5S, and 1S
•
at 32.768 kHz
•
2/4/8/16 kHz Selectable buzzer output
1-2
S3C921F/P921F
PRODUCT OVERVIEW
BLOCK DIAGRAM
P4.0/SEG48-
P4.7/SEG55
P3.0/SEG56-
P3.7/SEG63
RESET
TEST
Port 4
Port 3
Internal Bus
Basic
Timer
P2.0/COM8-
P2.3/COM11
Port 2
XIN
RC/X-tal
Main
OSC
P2.4/COM12-
P2.7/COM15
Port I/O and Interrupt
Control
OUT
X
Sub
XTIN
OSC
XTOUT
P1.0/INT
P1.1/INT
Watch
Timer
P1.2/BUZ
P1.2/BUZ/INT
P1.3/T0CK/INT
P1.4/T0/INT
P1.5/T1CK/INT
P1.6/TA/INT
P1.7/TB/INT
SAM88RCRI CPU
Port 1
P1.3/T0CK
P1.4/T0
Timer 0
P1.5/T1CK
Timer A
Timer B
VLC1
P1.6/TA
P1.7/TB
592-Byte
64-Kbyte ROM
COM0-COM7
COM8/P2.0-
Register File
LCD Driver/
Controller
COM15/P2.7
SEG0-SEG47
PWM0
PWM1
PWM
Module
SEG48/P4.0-
SEG55/P4.7
SEG56/P3.0-
SEG63/P3.7
Voltage
Level
192-Kbyte
Data
Detector
ROM
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C921F/P921F
PIN ASSIGNMENTS
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG1
SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
VLC1
RC/X-tal
PWM0
PWM1
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
(SDAT)
(SCLK)
S3C921F
(100-QFP-1420C)
RESET
P1.0/INT
P1.1/INT
P1.2/BUZ/INT
P1.3/T0CK/INT
P1.4/T0/INT
P1.5/T1CK/INT
P1.6/TA/INT
P1.7/TB/INT
P4.0/SEG48
P4.1/SEG49
P4.2/SEG50
P4.3/SEG51
Figure 1-2. Pin Assignment (100 Pin)
1-4
S3C921F/P921F
Pin Names
PRODUCT OVERVIEW
Table 1-1. Pin Descriptions
Pin Description
Pin
Type
Circuit
Number
Pin
Share
Pins
Numbers
P1.0, P1.1
P1.2
P1.3
I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, open-
drain output and software assignable pull-
ups;
E-2
23, 24
25
26
INT
I/O
BUZ/INT
T0CK/INT
T0/INT
P1.4
27
P1.5
P1.6
P1.7
Alternately used for external interrupt
input(noise filters, interrupt enable and
pending control).
28
29
30
T1CK/INT
TA/INT
TB/INT
P2.0 - P2.7
P3.0 - P3.7
P4.0 - P4.7
I/O port with nibble-programmable pins;
Schmitt trigger input or push-pull, open-
drain output and software assignable pull-
ups.
H-9
H-8
38 - 31
46 - 39
54 - 47
COM8-
COM15
I/O
I/O
I/O port with bit-programmable pins;
Schmitt trigger input or push-pull, open-
drain output and software assignable pull-
ups.
SEG56-
SEG63
I/O port with nibble-programmable pins;
Schmitt trigger input or push-pull output
and software assignable pull-ups.
H-10
C
SEG48-
SEG55
I/O
O
PWM0
PWM1
PWM output pins.
13
14
–
VLC1
INT
LCD power supply pin.
–
11
–
I
External interrupt input pins.
E-2
23, 24
25
26
P1.0, P1.1
P1.2/BUZ
P1.3/T0CK
P1.4/T0
I/O
27
28
29
P1.5/T1CK
P1.6/TA
30
P1.7/TB
BUZ
Output pin for buzzer signal.
Timer 0 clock input.
E-2
E-2
E-2
E-2
E-2
E-2
H-4
H-9
H-5
25
26
P1.2/INT
P1.3/INT
P1.4/INT
P1.5
I/O
I/O
I/O
I/O
I/O
I/O
O
T0CK
T0
Capture input or interval/PWM output.
Timer 1/A external clock input.
Timer 1/A clock output.
27
T1CK
28
TA
29
P1.6
TB
Timer B clock output.
30
P1.7
COM0-COM7
COM8-COM15
SEG0-SEG47
LCD common data outputs.
LCD common data outputs.
LCD segment data outputs.
10 - 3
38 - 31
–
P2.0 - P2.7
–
I/O
O
2-1
100-55
SEG48-SEG55
SEG56-SEG63
LCD segment data outputs.
H-10
H-8
54 - 47
46 - 39
P4.0 - P4.7
P3.0 - P3.7
I/O
1-5
PRODUCT OVERVIEW
Pin Names
S3C921F/P921F
Table 1-1. Pin Descriptions (Continued)
Pin Description Circuit
Pin
Pin
Numbers
Share
Pins
Type
Number
I
System reset pin
B
22
–
–
–
–
RESET
XTIN,XTOUT
–
–
–
Crystal oscillator pins for sub clock.
Main oscillator pins.
–
–
–
20, 21
18, 17
12
XIN,XOUT
RC/X-tal
Main oscillator type selection pin
("High" for RC osc. and "Low" for X-tal)
–
–
TEST
I
Test input: it must be connected to V
–
–
19
SS
VDD,VSS
–
Power input pins
15, 16
1-6
S3C921F/P921F
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
N-Channel
In
In
Schmitt Trigger
Figure 1-4. Pin Circuit Type B
Figure 1-3. Pin Circuit Type A
VDD
VDD
Pull-Up
Resistor
P-Channel
Pull-Up
Resistor
Enable
Data
P-Channel
In
Out
N-Channel
Output
Disable
Schmitt Trigger
Figure 1-5. Pin Circuit Type A-3
Figure 1-6. Pin Circuit Type C
1-7
PRODUCT OVERVIEW
S3C921F/P921F
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open-Drain
P-CH
I/O
Data
N-CH
Output
Disable
External
Interrupt
Input
Noise
Filter
Figure 1-7. Pin Circuit Type E-2
VDD
Pull-up
Resistor
Resistor
Enable
P-Channel
I/O
Data
Circuit
Type C
Output
Disable
Figure 1-8. Pin Circuit Type E-3
1-8
S3C921F/P921F
PRODUCT OVERVIEW
VLC1
VLC2
Out
COM Data
VLC5
VSS
Figure 1-9. Pin Circuit Type H-4
VLC1
VLC3
SEG Data
Out
VLC4
VSS
Figure 1-10. Pin Circuit Type H-5
1-9
PRODUCT OVERVIEW
S3C921F/P921F
VLC1
VLC2
COM
Output
Disable
VLC5
VSS
Figure 1-11. Pin Circuit Type H-6
VLC1
VLC3
SEG
Out
Output
Disable
VLC4
VSS
Figure 1-12. Pin Circuit Type H-7
1-10
S3C921F/P921F
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
VDD
Resistor
Open-Drain
Enable
P-CH
I/O
Data
N-CH
Output Disable 1
SEG
Output Disable 2
Circuit
Type H-7
Figure 1-13. Pin Circuit Type H-8
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Open-Drain
P-CH
I/O
Data
N-CH
Output Disable 1
COM
Output Disable 2
Circuit
Type H-6
Figure 1-14. Pin Circuit Type H-9
1-11
PRODUCT OVERVIEW
S3C921F/P921F
VDD
Pull-up
Resistor
VDD
Resistor
Enable
P-CH
I/O
Data
Output Disable 1
N-CH
SEG
Output Disable 2
Circuit
Type H-7
Figure 1-15. Pin Circuit Type H-10
1-12
S3C921F/P921F
ELECTRICAL DATA
17 ELECTRICAL DATA
OVERVIEW
In this chapter, S3C921F electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by an external interrupt
— Stop mode release timing when initiated by a Reset
— I/O capacitance
— A.C. electrical characteristics
— Input timing for external interrupts (port 1)
— Input timing for RESET
— Oscillation characteristics
— Oscillation stabilization time
17-1
ELECTRICAL DATA
S3C921F/P921F
Table 17-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
VDD
–
– 0.3 to + 6.5
V
Input voltage
VIN
VO
Ports 1, 2, 3 and 4
All output pins
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 18
V
V
Output voltage
Output current
High
IOH
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 60
Output current
Low
IOL
+ 30 (Peak Value)
mA
Total pin current for ports 1-4
–
+ 100 (Peak Value)
– 40 to + 85
°
C
Operating
temperature
TA
°
C
Storage
temperature
TSTG
–
– 65 to + 150
17-2
S3C921F/P921F
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.4 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Operating Voltage
VDD
fx = 8MHz
4.5
–
5.5
V
(Instruction clock = 2.0MHz)
fx = 4MHz
(Instruction clock = 1.0MHz)
2.7
2.4
–
–
–
5.5
5.5
fx = 3MHz
(Instruction clock = 0.75MHz)
Input High
voltage
VIH1
Ports 1-4
0.8 VDD
VDD
V
V
VIH2
VIH3
0.7 VDD
VDD
VDD
RESET
VDD – 0.1
XIN, XOUT and XTIN
Input Low voltage
VIL1
VIL2
VIL3
Ports 1-4
–
–
0.2 VDD
0.2 VDD
0.1
RESET
XIN, XOUT and XTIN
Output High
voltage
VOH
VDD = 4.5 to 5.5 V;
IOH = –1 mA
Ports 1-4
VDD – 1.0
–
–
–
V
V
Output Low
voltage
VOL
VDD = 4.5 to 5.5 V;
IOL= 10 mA
–
2.0
Ports 1-4
VDD = 2.4 to 5.5 V;
IOL= 1.6 mA
0.4
3
Input High
ILIH1
V = V
I
;
DD
–
–
–
–
µA
leakage current
All input pins except those
specified below for ILIH2
ILIH2
ILIL1
VI = VDD
;
20
–3
XIN
X XT
,
OUT IN
,
Input Low
leakage current
V = 0 V; All input pins except
I
RESET, XIN
X XT
,
OUT IN
,
ILIL2
V = 0 V;
I
–20
XIN
X XT
,
OUT IN
,
Output High
leakage current
ILOH
ILOL
VO = VDD
All output pins
VO = 0 V
–
–
–
–
3
Output Low
–3
leakage current
All output pins
17-3
ELECTRICAL DATA
S3C921F/P921F
Table 17-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 2.4 V to 5.5 V)
Unit
Parameter
Symbol
Conditions
Min
Typ
Max
Pull-Up Resistor
RL1
VI = 0 V; VDD = 5V
25
50
75
kW
Ports 1-4
VDD = 3V
50
100
250
150
350
RL2
150
VI = 0 V; VDD = 5V; RESET
VDD = 3V
250
38
500
54
750
70
LCD Voltage
Dividing Resistor
RLCD1
RLCD2
VDC
TA = + 25 °C
kW
When LCON.1 = "0"
19
–
27
–
35
TA = + 25 °C
When LCON.1 = "1"
V
½
–15 uA per common pin
120
mV
-COMi½
LCD
Voltage Drop
(i = 0-15)
V
VDS
–15 uA per common pin
–
–
120
½
LCD-SEGx½
Voltage Drop
(x = 0–63)
Middle Output
Voltage (note)
VLC2
VDD 2.4 V to 5.5 V,
=
1/5 bias
0.8VDD–0.2
0.8VDD
0.8VDD+ 0.2
V
LCD clock = 0Hz,
VLC1 = VDD
VLC3
VLC4
VLC5
0.6VDD–0.2
0.4VDD–0.2
0.2VDD–0.2
0.6VDD
0.4VDD
0.2VDD
0.6VDD+ 0.2
0.4VDD+ 0.2
0.2VDD+ 0.2
NOTE: It is middle output voltage when LCD controller/driver is 1/16 duty and 1/5 bias.
17-4
S3C921F/P921F
ELECTRICAL DATA
Table 17-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 2.4 V to 5.5 V)
Unit
Parameter
Symbol
Conditions
Min
Typ
Max
(2)
Supply current (1) IDD1
8 MHz
–
5.0
10.0
mA
VDD = 5 V ± 10%
Crystal oscillator
C1 = C2 = 22pF
VDD = 3 V ± 10%
4.19 MHz
4.0 MHz
3.0
1.4
6.4
2.8
(2)
Idle mode
VDD = 5 V ± 10%
8 MHz
–
1.0
2.0
IDD2
Crystal oscillator
C1 = C2 = 22pF
4.19 MHz
4 MHz
0.8
1.6
0.3
15
0.6
30
VDD = 3 V ± 10%
(3)
(3)
–
–
µA
VDD = 3 V ± 10%,
32 kHz crystal oscillator
IDD3
Idle mode;
6
15
IDD4
VDD = 3 V ± 10%,
32 kHz crystal oscillator
IDD5
Stop mode;
VDD=5 V ± 10%,
OSCCON.2="1"
–
0.3
0.1
3
1
VDD=3 V ± 10%,
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors, PWM, or external output current loads.
2.
I
and I
include power consumption for sub clock oscillation.
DD1
DD3
DD2
DD4
3.
I
and I
are current when main clock oscillation stops and the sub clock is used.
4. Every values in this table is measured when bits 4-3 of the system clock control register (CLKCON.4-.3) is set to 11B.
17-5
ELECTRICAL DATA
S3C921F/P921F
Table 17-3. Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply
voltage
VDDDR
–
2.2
–
5.5
V
Data retention supply
current
IDDDR
tWAIT
Stop mode,
VDDDR=2.2 V
–
–
1
µA
ms
216/fx (1)
Oscillator stabilization
wait time
–
–
–
–
Released by RESET
(2)
Released by interrupt
NOTES:
1. fx is the main oscillator frequency.
2. The duration of the oscillation stabilization time (t
) when it is released by an interrupt is determined by
WAIT
the setting in the basic timer control register, BTCON.
Idle Mode
(Basic Timer Active)
Stop Mode
Normal
Operating Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instruction
0.8 VDD
tWAIT
Interrupt
Request
Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt
17-6
S3C921F/P921F
ELECTRICAL DATA
RESET
Occurs
Oscillation
Stabilization
TIme
Stop Mode
Normal
Operating Mode
Data Retention Mode
VDD
tSRL
VDDDR
Execution of
STOP Instrction
RESET
0.7 VDD
tWAIT
0.2 VDD
Figure 17-2. Stop Mode Release Timing When Initiated by a RESET
17-7
ELECTRICAL DATA
S3C921F/P921F
Table 17-4. Input/Output Capacitance
°
°
(TA = – 40 C to + 85 C, VDD = 0 V)
Parameter
Input
capacitance
Symbol
Conditions
Min
Typ
Max
Unit
CIN
f = 1 MHz; unmeasured pins
are connected to VSS
–
–
10
pF
Output
capacitance
COUT
CIO
I/O capacitance
Table 17-5. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
tINTH
tINTL
Conditions
P1.0 – P1.7
VDD = 5 V
Min
Typ
Max
Unit
Interrupt input,
High, Low width
150
200
–
ns
,
tRSL
Input
VDD = 5 V
10
–
–
ms
RESET input Low
width
tINTL
tINTH
External
Interrupt
0.8 VDD
0.2 VDD
NOTE:
The unit tCPU means one CPU clock period.
Figure 17-3. Input Timing for External Interrupts (P1.0–P1.7)
tRSL
RESET
0.2 VDD
Figure 17-4. Input Timing for RESET
17-8
S3C921F/P921F
ELECTRICAL DATA
Table 17-6. Main Oscillation Characteristics
°
°
(TA = – 40 C + 85 C)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency(1)
Ceramic
Oscillator
RC/X-tal = 0 V
0.4
–
8.0
MHz
XIN
XOUT
C1
C2
Stabilization time(2)
Stabilization occurs
when VDD is equal to
the minimum
oscillator voltage
range.
–
–
–
4
ms
Oscillation frequency(1)
Crystal
RC/X-tal = 0 V
0.4
8.0
MHz
XIN
XOUT
Oscillator
C1
C2
Stabilization time(2)
VDD = 4.5 V to 5.5 V
–
–
10
ms
VDD = 1.8 V to 5.5 V
RC/X-tal = 0 V
–
–
–
30
XIN input frequency(1)
External
Clock
0.4
8.0
MHz
XIN
XOUT
XIN input high and low
level width (tXH, tXL)
–
62.0
–
–
4
1250
–
ns
Frequency(1)
RC
VDD = 2.7 V to 5.5 V
RC/X-tal = VDD
MHz
XIN
XOUT
Oscillator
R
VDD = 2.4 V to 5.5 V
RC/X-tal = VDD
–
2
–
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
17-9
ELECTRICAL DATA
S3C921F/P921F
1/fx
tXL
tX
XIN
VDD-0.1 V
0.1 V
Figure 17-5. Clock Timing Measurement at XIN
17-10
S3C921F/P921F
ELECTRICAL DATA
Table 17-7. Sub Oscillation Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 2.4 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency(1)
Crystal
Oscillator
–
32
32.768
35
kHz
XTIN XTOUT
C1
C2
(2)
VDD = 4.5 V to 5.5 V
VDD = 2.4 V to 4.5 V
–
–
–
1.0
–
2
s
Stabilization time
10
XT input frequency(1)
IN
External
Clock
32
–
100
kHz
XTIN XTOUT
XTIN input high and low
–
5
–
15
us
level width (tXTL, tXTH
)
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs .
1/fxt
tXTL
tXTH
XTIN
VDD-0.1 V
0.1 V
Figure 17-6. Clock Timing Measurement at XTIN
17-11
ELECTRICAL DATA
S3C921F/P921F
Table 17-8. PWM0/PWM1 Electrical Characteristics
°
°
( TA = – 40 C + 85 C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
PWM Output
Voltage
VPWM0
VDD = 2.4 V
IPWMh0 = –8mA
VDD – 0.5
–
–
V
IPWMl0 = 15 mA
–
0.5
–
VPWM1
VPWM2
VPWM3
VDD = 2.4 V
VDD = 2.4 V
VDD = 2.4 V
IPWMh1 = –12mA VDD – 0.5
IPWMl1 = 20 mA
IPWMh2 = –16mA VDD – 0.5
IPWMl2 = 25 mA
IPWMh3 = –20mA VDD – 0.5
IPWMl3 = 30 mA
–
0.5
–
–
0.5
–
–
0.5
Table 17-9. VLD Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.4 V to 5.5 V)
Parameter
VLD Voltage
Symbol
Conditions
Min
Typ
Max
Unit
VVLD
BLDCON.4 = 0B
2.4
2.7
3.0
V
BLDCON.4 = 1B
fw = 32.768 kHz
3.7
–
4.0
–
4.3
1.0
VLD Circuit Response
Time
TB
mS
uA
VLD Operating Current
IBL
–
50
100
17-12
S3C921F/P921F
ELECTRICAL DATA
fx
(Main oscillation
frequency)
Clock
2 MHz
8 MHz
1.0 MHz
750 kHz
4 MHz
3 MHz
400 kHz
8.32 kHz
1
2
5.5 6
2.4 2.7
4.5
Supply Voltage (V)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 17-7. Operating Voltage Range
17-13
S3C921F/P921F
MECHANICAL DATA
18 MECHANICAL DATA
OVERVIEW
The S3C921F microcontroller is currently available in a 100-pin QFP package.
23.90 ± 0.30
20.00 ± 0.20
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
100-QFP-1420C
#100
+ 0.10
- 0.05
#1
0.30
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.65
0.15 MAX
(0.58)
0.80 ± 0.20
NOTE: Dimensions are in millimeters.
Figure 19-1. 100-QFP-1420C Package Dimensions
18-1
S3C921F/P921F
S3P921F OTP
19 S3P921F OTP
OVERVIEW
The S3P921F single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C921F
microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data
format.
The S3P921F is fully compatible with the S3C921F, both in function in D.C. electrical characteristics and in pin
configuration. Because of its simple programming requirements, the S3P921F is ideal as an evaluation chip for
the S3C921F.
19-1
S3P921F OTP
S3C921F/P921F
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG1
SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
1
2
3
4
5
6
7
8
9
COM0
VLC1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RC/X-tal
SDAT/PWM0
SCLK/PWM1
VDD/VDD
VSS/VSS
XOUT
S3P921F
(100-QFP-1420C)
XIN
VPP/TEST
XTIN
XTOUT
RESET/RESET
P1.0/INT
P1.1/INT
P1.2/BUZ/INT
P1.3/T0CK/INT
P1.4/T0/INT
P1.5/T1CK/INT
P1.6/TA/INT
P1.7/TB/INT
P4.0/SEG48
P4.1/SEG49
P4.2/SEG50
P4.3/SEG51
Figure 19-1. S3P921F Pin Assignments (100-Pin QFP Package)
19-2
S3C921F/P921F
S3P921F OTP
Table 19-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
PWM0
Pin Name
Pin No.
I/O
Function
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
PWM1
TEST
SCLK
VPP
14
19
I
I
Serial clock pin. Input only pin.
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option)
22
I
Chip Initialization
RESET
RESET
VDD/VSS
VDD/VSS
Logic power supply pin. VDD should be tied to
+5 V during programming.
15/16
–
Table 19-2. Comparison of S3P921F and S3C921F Features
S3P921F
Characteristic
S3C921F
Program Memory
Data Memory
64-Kbyte EPROM
192-Kbyte EPROM
2.4 V to 5.5 V
64-Kbyte mask ROM
192-Kbyte mask ROM
2.4 V to 5.5 V
Operating Voltage (VDD
)
VDD = 5 V, VPP (EA) = 12.5 V
OTP Programming Mode
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (EA) pin of the S3P921F, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 21-3 below.
Table 19-3. Operating Mode Selection Criteria
VDD
VPP
(EA)
REG/
Address
(A17–A0)
R/W
Mode
MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
19-3
S3P921F OTP
S3C921F/P921F
fx
(Main oscillation
frequency)
Clock
2 MHz
8 MHz
1.0 MHz
750 kHz
4 MHz
3 MHz
400 kHz
8.32 kHz
1
2
5.5 6
2.4 2.7
4.5
Supply Voltage (V)
Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)
Figure 19-2. Operating Voltage Range
19-4
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