S3C9424XX-SO [SAMSUNG]
Microcontroller, 8-Bit, MROM, SAM87RI CPU, 16MHz, CMOS, PDSO32, 0.450 INCH, SOP-32;
| 型号： | S3C9424XX-SO |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, MROM, SAM87RI CPU, 16MHz, CMOS, PDSO32, 0.450 INCH, SOP-32 微控制器 |
| 文件： | 总26页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C9424/C9428/P9428
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung’s SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9424/C9428/P9428 MICROCONTROLLER
The S3C9424/C9428/P9428 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is
built around the powerful SAM87Ri CPU core. The S3C9424/C9428/P9428 is a versatile microcontroller, with its
A/D converter, SIO, IIC and a zero-crossing detection capability it can be used in a wide range of general
purpose applications.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9424/C9428/P9428 have 4K-byte or
8K-byte of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM.
Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:
•
•
•
•
•
•
•
Four configurable I/O ports (24 pins)
Nine interrupt sources with one vector and one interrupt level
Two 8-bit timer/counter with various operating modes
Analog to digital converter with 12 input channels and 10-bit resolution
One synchronous SIO module
One IIC module
Two 12-bit PWM output
The S3C9424/C9428/P9428 microcontroller is ideal for use in a wide range of electronic applications requiring
simple timer/counter, PWM, ADC, SIO, IIC, ZCD and capture functions. S3C9424/C9428/P9428 is available in a
28/32-pin SOP and a 30-pin SDIP package.
OTP
The S3P9428 is an OTP (One Time Programmable) version of the S3C9424/C9428 microcontroller. The
S3P9428 has on-chip 8-K-byte one-time-programmable EPROM instead of masked ROM. The S3P9428 is fully
compatible with the S3C9424/C9428, in function, in D.C. electrical characteristics and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C9424/C9428/P9428
FEATURES
CPU
Timer/Counters
•
SAM87RI CPU core
•
•
One 8-bit basic timer for watchdog function
One 8-bit timer/counter with three operating
mode
Memory
•
•
208-byte general purpose register area (RAM)
4K/8K byte internal program memory (ROM)
•
One 8-bit timer/counter
PWM module
Instruction Set
•
•
•
12-bit PWM 2-ch (Max: 250KHz)
•
•
41 instructions
6-bit base + 6-bit extension frame
One 8-bit timer/counter
The SAM87RI core provides all the SAM87 core
instruction except the word-oriented instruction,
multiplication, division, and some one-byte
instruction
A/D Converter
•
•
12 analog input pins
10-bit conversion resolution
Instruction Execution Time
375 ns at 16 MHz fosc(minimum)
•
Buzzer Frequency Range
200 Hz to 20 kHz signal can be generated
Interrupts
•
•
•
9 interrupt sources and 1 vector
One interrupt level
Oscillator Freqeuncy
•
1-MHz to 16-MHz external crystal oscillator
Maximum 16-MHz CPU clock
General I/O
•
RC: 4MHz(typ)
•
•
Four I/O ports (total 24pins)
Bit programmable ports
Operating Temperature Range
°
°
•
– 40 C to + 85 C
Serial I/O
•
•
One synchronous serial I/O module
Selectable transmit and receive rates
Operating Voltage Range
•
•
3.0 V to 5.5 V (LVD)
1.8 V to 5.5 V (No LVD)
Multi-Master IIC-Bus
Serial peripheral interface
•
OTP Interface Protocol Spec
Serial OTP
•
Zero-Crossing Detection Circuit
•
Zero crossing detection circuit that generates a
digital signal in synchronism with an AC signal
input
Package Types
•
S3C9424/C9428
32-pin SOP-450 (3V LVD)
30-pin SDIP-400 (3V LVD)
28-pin SOP-375
Built-in reset Circuit (LVD)
•
Low voltage detector for safe reset
1-2
S3C9424/C9428/P9428
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7
P1.0-P1.3
SCK,SO, SI, AD8-AD11 T0, BUZ, INT0, INT1
Port 0
Port 1
Basic
Timer
X
OUT
IN
OSC
X
P2.0-P2.7
AD0-AD7
Port 2
Port I/O and Interrupt
Control
T0 (CAP)
T0(PWM)
Timer 0
Timer 1
ADC
Port 3
P3.0-P3.3
ZCD
ZCD
IIC
AD0-AD11
P1.1/BUZ
SAM87RI CPU
P2.7/SCLK
P2.6/SDAT
BUZ
P0.0/SCK
P0.1/SO
P0.2/SI
P0.7/PWM0
P1.3/PWM1
PWM
SIO
208-Byte
Register File
4K/8K ROM
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C9424/C9428/P9428
PIN ASSIGNMENTS
VSS
XIN
XOUT
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P3.3
P1.0/T0/ZCD
P1.1/BUZ
TEST
P0.1/SO
P0.0/SCK
RESET
P3.0
S3C9424/C9428
32-SOP
(Top View)
P3.2
9
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
10
11
12
13
14
15
16
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
Figure 1-2. Pin Assignment Diagram (32-Pin SOP Package)
1-4
S3C9424/C9428/P9428
PRODUCT OVERVIEW
PIN ASSIGNMENTS (Continued)
VSS
XIN
XOUT
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
TEST
P0.1/SO
P0.0/SCK
RESET
P3.0
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
S3C9424/C9428
30-SDIP
(Top View)
9
10
11
12
13
14
15
Figure 1-3. Pin Assignment Diagram (30-Pin SDIP Package)
VSS
XIN
XOUT
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
TEST
P0.1/SO
P0.0/SCK
RESET
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
S3C9424/C9428
28-SOP
(Top View)
9
10
11
12
13
14
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
Figure 1-4. Pin Assignment Diagram (28-Pin SOP Package)
1-5
PRODUCT OVERVIEW
S3C9424/C9428/P9428
PIN DESCRIPTIONS
Table 1-1. S3C9424/C9428/P9428 Pin Descriptions
Pin Description
Pin
Names
Pin
Type
Pin
Type
Share
Pins
P0.0-P0.7
I/O
Bit-programmable I/O port for Schmitt trigger input or push-
pull, open-drain output. Pull-up resistors are assignable by
software.
E
SCK,SO,SI
, CLO,
AD8-AD11
E-1
D
P1.0-P1.3
I/O
Bit-programmable I/O port for Schmitt trigger input or push-
pull output.
T0/ZCD
BUZ
Pull-up resistors are assignable by software. Port 1 pins can
also be used as alternative functions.
INT0
INT1
P2.0-P2.7
I/O
O
Bit-programmable I/O port for Schmitt trigger input or push-
pull, open drain output. Pull up resistors are assignable by
software. Port 2 can also be used as external interrupt, A/D
input.
E-1
E-2
AD0-AD7
P3.0-P3.3
XIN, XOUT
Push-pull or open-drain output port.
Pull-up resistors are assignable by software.
–
–
I
Crystal/ceramic, or RC oscillator signal for system clock.
–
B
–
–
–
–
RESET
System RESET signal input pin.
TEST
I
Test signal input pin (for factory use only: must be connected
to VSS
)
AVREF, AVSS
VDD, VSS
–
–
A/D converter reference voltage input and ground
Voltage input pin and ground
–
–
–
–
SCK
SO
I/O
O
Serial interface clock input or output
Serial data output
E
E
P0.0
P0.1
P0.2
P0.3
SI
I
Serial data output
E
CLO
O
System clock output port
E
SCLK
SDAT
I/O
IIC CLOCK
IIC DATA
E-1
P2.7
P2.6
BUZ
ZCD
T0
O
I
200 Hz-20 kHz frequency output for buzzer sound.
Zero crossing detector input
D
D
D
D
P1.1
P1.0
P1.0
I/O
I
Timer 0 capture input or 10-bit PWM output
External interrupt input
INT0
INT1
P1.2
P1.3
PWM0
PWM1
O
I
12-bit PWM output
A/D converter input
E-1
D
P0.7
P1.3
AD0-AD11
E-1
P2.0-P2.7
P0.4-P0.7
1-6
S3C9424/C9428/P9428
PRODUCT OVERVIEW
PIN CIRCUITS
VDD
VDD
P-Channel
N-Channel
P-Channel
Out
Data
In
N-Channel
Output
DIsable
Figure 1-5. Pin Circuit Type A
Figure 1-7. Pin Circuit Type C
VDD
Pull-up
Resistor
VDD
Resistor
Enable
Pull-Up
Resistor
P-Channel
Data
Circuit
In
I/O
Type C
Output
DIsable
Data
Figure 1-6. Pin Circuit Type B
Figure 1-8. Pin Circuit Type D
1-7
PRODUCT OVERVIEW
S3C9424/C9428/P9428
VDD
DD
V
Pull-up
PNE
Resistor
DD
V
47K
PNE
VDD
Pull-up
Enable
I/O
P-CH
N-CH
Pull-up
Enable
Data
Data
Out
Output
Disable
Output
Disable
Input
Figure 1-11. Pin Circuit Type E-2
Figure 1-9. Pin Circuit Type E
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Enable
I/O
P-CH
N-CH
Data
Output
Disable
Input
Analog Input
Figure 1-10. Pin Circuit Type E-1
1-8
S3C9424/C9428/P9428
ELECTRICAL DATA
16 ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9424/C9428/P9428 electrical characteristics are presented in tables and graphs:
— Absolute maximum ratings
— D.C. electrical characteristics
— A.C. electrical characteristics
— Operating Voltage Range
— Schmitt trigger input characteristics
— Oscillator characteristics
— Oscillation stabilization time
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by a RESET
— Power-on RESET circuit characteristics
— A/D converter electrical characteristics
— Zero-crossing detector
— Zero Crossing Waveform Diagram
16-1
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Supply voltage
Input voltage
Symbol
Conditions
–
Rating
Unit
V
VDD
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 25
VI
VO
IOH
All input ports
All output ports
One I/O pin active
V
Output voltage
Output current
V
mA
high
All I/O pins active
One I/O pin active
– 80
+ 30
IOL
Output current
mA
low
Total pin current for ports 1, 2, 3
+ 100
+ 200
Total pin current for ports 0
–
TA
°
C
Operating
– 40 to + 85
temperature
TSTG
°
C
Storage
–
– 65 to + 150
temperature
16-2
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics(30SDIP, 32SOP)
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Input high
Symbol
Conditions
Min
Typ
Max
Unit
VIH1
VDD= 3.0 to 5.5 V
0.8 VDD
VDD
Ports 0, 1, 2 and
–
V
voltage
RESET
VIH3
VIL1
XIN and XOUT
VDD – 0.1
–
VDD= 3.0 to 5.5 V
0.2 VDD
Input low
voltage
Ports 0, 1, 2 and
RESET
–
V
VIL2
VOH
XIN and XOUT
0.1
–
IOH = – 10 mA
ports 0-3
VDD= 4.5 to 5.5 V
VDD= 4.5 to 5.5 V
VIN = VDD
VDD – 1.5 VDD
0.4
–
Output high
voltage
V
V
VOL
IOL = 25 mA
port 0-3
Output low
voltage
–
0.4
2.0
1
ILIH1
Input high
leakage current
All input pins except
ILIH2
–
–
mA
ILIH2
ILIL1
XIN, XOUT
VIN = VDD
VIN = 0 V
20
Input low
All input pins except
–
–
– 1
mA
leakage current
ILIL2 and RESET
ILIL2
ILOH
XIN, XOUT
VIN = 0 V
– 20
2
VOUT = VDD
Output high
leakage current
All output pins
–
–
–
–
mA
mA
ILOL
RP
VOUT = 0 V
Output low
leakage current
All output pins
– 2
VIN = 0 V Port 0-2
VDD = 5 V
Pull-up resistor
30
100
–
47
70
350
20
KW
VDD = 5 V
200
11
RESET
IDD1
IDD2
IDD3
VDD = 4.5 to 5.5 V
Supply current
RUN mode 16-MHz
CPU clock
mA
VDD = 3 V
4-MHz CPU clock
1.5
3
4
8
VDD = 4.5 to 5.5 V
Idle mode 16-MHz
CPU clock
–
–
VDD = 3.3 V
4-MHz CPU clock
Stop mode
0.5
65
45
2
VDD = 4.5 to 5.5 V
VDD = 3.3 V
100
80
mA
NOTE: D.C. electrical values for Supply current (I
to I
) do not include current drawn through internal pull-up
DD3
DD1
resisters, output port drive current, ZCD and ADC.
16-3
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-3. D.C. Electrical Characteristics (28SOP)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Input high
Symbol
Conditions
Min
Typ
Max
Unit
VIH1
VDD= 1.8 to 5.5 V
0.8 VDD
VDD
Ports 0, 1, 2 and
–
V
voltage
RESET
VIH3
VIL1
XIN and XOUT
VDD – 0.1
–
VDD= 1.8 to 5.5 V
0.2 VDD
Input low
voltage
Ports 0, 1, 2 and
RESET
–
V
VIL2
VOH
XIN and XOUT
0.1
–
IOH = – 10 mA
ports 0-3
VDD= 4.5 to 5.5 V
VDD= 4.5 to 5.5 V
VIN = VDD
VDD – 1.0 VDD
0.4
–
Output high
voltage
V
V
VOL
IOL = 25 mA
port 0-3
Output low
voltage
–
0.4
2.0
1
ILIH1
Input high
leakage current
All input pins except
ILIH2
–
–
mA
ILIH2
ILIL1
XIN, XOUT
VIN = VDD
VIN = 0 V
20
Input low
All input pins except
–
–
– 1
mA
leakage current
ILIL2 and RESET
ILIL2
ILOH
XIN, XOUT
VIN = 0 V
– 20
2
VOUT = VDD
Output high
leakage current
All output pins
–
–
–
–
mA
mA
ILOL
RP
VOUT = 0 V
Output low
leakage current
All output pins
– 2
VIN = 0 V Port 0-2
VDD = 5 V
Pull-up resistor
30
100
–
47
70
350
20
KW
VDD = 5 V
200
11
RESET
IDD1
IDD2
IDD3
VDD = 4.5 to 5.5 V
Supply current
RUN mode 16-MHz
CPU clock
mA
VDD = 1.8 to 2.2 V
VDD = 4.5 to 5.5 V
3-MHz CPU clock
1
3
3
9
Idle mode 16-MHz
CPU clock
–
–
VDD = 1.8 to 2.2 V
VDD = 4.5 to 5.5 V
VDD = 3 V
3-MHz CPU clock
Stop mode
0.3
0.1
1.0
5
mA
VDD = 1.8 to 2.2 V
NOTE: D.C. electrical values for Supply current (I
to I
) do not include current drawn through internal pull-up
DD3
DD1
resisters, output port drive current, ZCD and ADC.
16-4
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-4. A.C. Electrical Characteristics
°
°
(TA = –40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
tINTH
tINTL
Conditions
Min
Typ
Max
Unit
,
Interrupt input
high, low width
–
200
–
ns
Port 1v(INT0, INT1)
VDD = 5V ± 10%
tRSL
–
–
1
–
us
RESET input
low width
Input
VDD = 5V ± 10%
1/tCPU
tINTL
tRSL
tINTH
0.8 VDD
0.2 VDD
NOTE:
The unit tcpu means one CPU clock period.
Figure 16-1. Input Timing Measurement Points
16-5
ELECTRICAL DATA
S3C9424/C9428/P9428
CPU Clock
16MHz
8MHz
4MHz
3MHz
2MHz
1MHz
1
1.8 2 2.73
4 4.5 5 5.5 6
7
Supply Voltage (V)
Figure 16-2. Operating Voltage Range (KS86C4204/C4208)
VOUT
VDD
A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD
VSS
VIN
A
B
C
D
0.3 VDD
0.7 VDD
Figure 16-3. Schimtt Trigger Input Characteristic Diagram
16-6
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-5. Oscillator Characteristics (30SDIP, 32SOP)
°
°
(T = – 40 C to + 85 C)
A
Oscillator
Clock Circuit
Test Condition
VDD = 4.5 to 5.5 V
Min
Typ
Max
Unit
Main crystal or
ceramic
1
1
–
–
16
8
MHz
XIN
XOUT
VDD = 3.0 to 4.5 V
C1
C2
External clock
(Main system)
1
1
–
–
16
8
VDD = 4.5 to 5.5 V
VDD = 3.0 to 4.5 V
XIN
XOUT
VDD = 4.75 to 5.25 V
Tolerance: 10%
RC oscillator
–
4
–
XIN
XOUT
R
Table 16-6. Oscillation Stabilization Time (28SOP)
°
°
(T = – 40 C to + 85 C)
A
Oscillator
Clock Circuit
Test Condition
VDD = 4.5 to 5.5 V
VDD = 2.7 to 4.5 V
VDD = 1.8 to 2.7 V
Min
Typ
Max
Unit
Main crystal or
ceramic
1
1
1
–
–
–
16
8
3
MHz
XIN
XOUT
C1
C2
External clock
(Main system)
1
1
1
–
–
–
16
8
3
VDD = 4.5 to 5.5 V
VDD = 2.7 to 4.5 V
VDD = 1.8 to 2.7 V
XIN
XOUT
VDD = 4.75 to 5.25 V
Tolerance: 10%
RC oscillator
–
4
–
XIN
XOUT
R
16-7
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-7. Oscillation Stabilization Time
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Oscillator
Main crystal
Main ceramic
Test Condition
Min
–
Typ
–
Max
20
Unit
fosc > 1.0 MHz
ms
Oscillation stabilization occurs when VDD is equal
to the minimum oscillator voltage range.
XIN input high and low width (tXH, tXL)
–
–
10
External clock
(main system)
25
–
–
500
–
ns
tWAIT when released by a reset (1)
16
/fosc
Oscillator
stabilization
ms
2
tWAIT when released by an interrupt (2)
wait time
–
–
–
NOTES:
1. fosc is the oscillator frequency.
2. The duration of the oscillator stabilization wait time, t
setting in the basic timer control register, BTCON.
, when it is released by an interrupt is determined by the
WAIT
16-8
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-8. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5V)
A
Parameter
Symbol
Conditions
Stop mode
Min
Typ
Max
Unit
VDDDR
Data retention
supply voltage
1.8
–
5.5
V
IDDDR
Stop mode; VDDDR = 1.8 V
Data retention
supply current
–
0.1
5
µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Internal RESET
Operation
Oscillation
Stabilization Time
Stop Mode
Normal
Operating
Data Retention Mode
Mode
VDD
VDDDR
Execution Of
Stop Instrction
RESET
0.8 VDD
0.2 VDD
tWAIT
NOTE: tWAIT is the same as 4096 x 16 x 1/fosc
Figure 16-4. Stop Mode Release Timing When Initiated by a RESET
16-9
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-9. Power-on RESET Circuit Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
A
Parameter
Power-on reset
Symbol
Conditions
Min
Typ
Max
Unit
VDDH
3.0
–
5.5
V
voltage high
VDDL
tr
Power-on reset
voltage low
0
2.6
3.0
(1)
V
us
s
Power supply
voltage rise time
10
0.5
toff
Power supply
voltage off time
IDDPR
Power-on reset circuit
cunsumption current (2)
NOTES:
65
45
100
80
VDD = 5 V ± 10%
mA
VDD = 3.3 V
1. 216/fx (= 6.55 ms at fx = 10 MHz)
2. Current consumed when power-on reset circuit is provided internally.
VDD
VDDH
VDDL
toff
tr
Figure16-5. Power-on RESET Timing
16-10
S3C9424/C9428/P9428
ELECTRICAL DATA
Table 16-10. A/D Converter Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 1.8/3.0 V to 5.5 V, VSS = 0 V)
A
Parameter
Total accuracy
Symbol
Test Conditions
VDD = 5.12 V
Min
Typ
Max
Unit
–
–
LSB
± 3
CPU clock = 10 MHz
AVREF = 5.12 V
AVSS = 0 V
Integral linearity error
Differential linearity error
Offset error of top
ILE
“
–
–
–
–
LSB
± 2
± 1
DLE
EOT
EOB
tCON
“
“
–
±1
±1
–
±3
Offset error of bottom
Conversion time(1)
“
–
± 2
fosc = 10 MHz
20
AVSS
–
ms
V
VIAN
RAN
AVREF
Analog input voltage
–
–
–
–
–
–
–
–
Analog input impedance
ADC reference voltage
ADC reference ground
2
–
MW
V
AVREF
AVSS
VDD
2.5
VSS
VSS
0.3
+
V
IADIN
IADC
AVREF = VDD = 5 V
AVREF = VDD = 5 V
AVREF = VDD = 3 V
Analog input current
ADC block
–
–
–
1
10
3
mA
mA
current (2)
0.5
100
1.5
AVREF = VDD = 5 V
Power down mode
–
500
nA
NOTES:
1. ‘Conversion time’ is the time required from the moment a conversion operation starts until it ends.
2.
I
is operating current during A/D conversion.
ADC
Digital Output
11 1111 1111
11 1111 1110
11 1111 1101
.
.
.
.
.
.
.
00 0000 0010
00 0000 0001
00 0000 0000
Analog Input
AVSS VEOB
V2
V(K-1) V(K)
VEOT AVREF
Figure 16-6. Definition of DLE and ILE
16-11
ELECTRICAL DATA
S3C9424/C9428/P9428
Table 16-11. Zero Crossing Detector
°
°
(T = – 40 C to + 85 C, VDD = 4.5 V to 5.5 V, VSS = 0 V)
A
Parameter
Symbol
Test Conditions
AC connection
c = 0.1 mF
Min
Typ
Max
Unit
VZC
Zero-crossing
detection input
voltage
1.0
–
3.0
Vp-p
Zero-crossing
detection accuracy
–
–
–
mV
Hz
± 150
VAZC
fZC = 60 Hz
(sine wave)
VDD = 5 V
fOSC = 10 MHz
Zero-crossing
detection input
frequency
–
40
200
fZC
1/fzc
AC input
VAZC
VAZ(P-P)
ZCINT
Figure 16-7. Zero Crossing Waveform Diagram
16-12
S3C9424/C9428/P9428
MECHANICAL DATA
17 MECHANICAL DATA
OVERVIEW
The S3C9424/C9428 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package
(32-SOP-450A) and a 28-pin SOP package (28-SOP-375). Package dimensions are shown in Figures 17-1, 17-2,
and 17-3
#30
#16
0-15
30-SDIP-400
#1
#15
27.88MAX
27.48 ± 0.2
0.56 ± 0.1
1.12 ± 0.1
1.778
(1.30)
NOTE: Dimensions are in millimeters.
Figure 17-1. 30-Pin SDIP Package Dimensions
17-1
MECHANICAL DATA
S3C9424/C9428/P9428
#32
#17
32-SOP-450A
#1
#16
+ 0.1
0.20
- 0.05
19.90 ± 0.2
1.27
(0.43)
0.40 ± 0.1
NOTE: Dimensions are in millimeters
Figure 17-2. 32-SOP-450A Package Dimensions
17-2
S3C9424/C9428/P9428
MECHANICAL DATA
#28
#15
28-SOP-375
#1
#14
+ 0.10
- 0.05
0.15
18.02 MAX
17.62 ± 0.2
1.27
(0.56)
0.41 ± 0.1
NOTE: Dimensions are in millimeters
Figure 17-3. 28-SOP-375 Package Dimensions
17-3
S3C9424/C9428/P9428
S3P9428 OTP
18 S3P9428 OTP
OVERVIEW
The S3P9428 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C9424/C9428 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P9428 is fully compatible with the S3C9424/C9428, both in function and in pin configuration. Because of
its simple programming requirements, the S3P9428 is ideal for use as an evaluation chip for the
S3C9424/C9428.
VSS
XIN
XOUT
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
TEST/VPP
P0.1/SO
P0.0/SCK
RESET
P3.0
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P1.0/T0/ZCD
P1.1/BUZ
S3P9428
30-SDIP
(Top View)
9
10
11
12
13
14
15
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
NOTE:
The bolds indicate an OTP pin name.
Figure 18-1. Pin Assignment Diagram (30-Pin SDIP Package)
18-1
S3P9428 OTP
S3C9424/C9428/P9428
VSS
XIN
XOUT
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P3.3
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
TEST/VPP
P0.1/SO
P0.0/SCK
RESET
P3.0
S3P9428
32-SOP
(Top View)
P3.2
9
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
10
11
12
13
14
15
16
NOTE:
The bolds indicate an OTP pin name.
Figure 18-2. Pin Assignment Diagram (32-Pin SOP Package)
VSS
XIN
XOUT
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
TEST/VPP
P0.1/SO
P0.0/SCK
RESET
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AVSS
S3P9428
28-SOP
(Top View)
9
10
11
12
13
14
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AVREF
NOTE:
The bolds indicate an OTP pin name.
Figure 18-3. Pin Assignment Diagram (28-Pin SOP Package)
18-2
S3C9424/C9428/P9428
Main Chip
S3P9428 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Pin Name
P0.3
Pin Name
Pin No.
I/O
Function
SDAT
SCLK
S3P9428
- 30 SDIP: 28
- 32 SOP: 30
I/O
Serial data pin (output when reading, Input
when writing) Input and push-pull output
port can be assigned
P0.2
S3P9428
- 30 SDIP: 29
- 32 SOP: 31
I
I
Serial clock pin (input only pin)
VPP (TEST)
TEST
4
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)
7
I
I
Chip Initialization
RESET
RESET
VDD/VSS
VDD/VSS
S3P9428
Logic power supply pin.
- 30 SDIP: 30/1
- 32 SOP: 32/1
Table 18-2. Comparison of S3P9428 and S3C9424/C9428 Features
Characteristic
S3P9428
S3C9424/C9428
Program Memory
8-Kbyte EPROM
4/8-Kbyte mask ROM
Operating Voltage (VDD
)
3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5)
3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5)
V
DD
= 5 V, V (TEST) = 12.5 V
PP
OTP Programming Mode
Pin Configuration
30 SDIP/32 SOP/28SOP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the S3P9428, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 18-3 below.
Table 18-3. Operating Mode Selection Criteria
VDD
Vpp (TEST)
ADDRESS(A15-A0)
R/W
MODE
REG/MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
EPROM program
EPROM verify
12.5 V
12.5 V
12.5 V
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
18-3
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