S3P7565 [SAMSUNG]
single-chip CMOS microcontroller; 单芯片CMOS微控制器
| 型号： | S3P7565 |
| 厂家： | 
SAMSUNG |
| 描述： | single-chip CMOS microcontroller |
| 文件： | 总42页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C7565/P7565
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7565/P7565 single-chip CMOS microcontroller is designed for high performance in the application for
Caller-ID, Telephone using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangable Microcontrollers).
Featuring a DTMF generator, up-to-960-dot LCD direct drive capability, one 8-bit timer/counter and flexible two
8-bit timer/counters, and serial I/O interface, the S3C7565/P7565 offer an excellent design solution for a wide
variety of applications requiring DTMF, LCD support.
Up to 43 (including COM/SEG) pins in the 100-pin QFP package can be dedicated to I/O. Nine vectored
interrupts provide a fast response to internal and external events. In addition the advanced CMOS technology a
of the S3C7565/P7565 ensures low power consumption with a wide operating voltage range.
OTP
The S3C7565 microcontroller is also available in OTP (One Time Programmable) version, S3P7565.
S3P7565 microcontroller has an on-chip 16 K-byte one-time-programmable EPROM instead of masked ROM.
The S3P7565 is comparable to S3C7565, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7565/P7565
FEATURES SUMMARY
Memory
8-bit Serial I/O Interface
•
•
•
8-bit transmit/receive mode
8-bit receive mode
•
•
16K ´ 8-bit ROM
5,120 ´ 4-bit RAM (excluding LCD RAM)
LSB-first or MSB-first transmission selectable
I/O Pins
LCD Controller/Driver
•
Input only:4pins (Not including COM/SEG)
6pins (Including COM/SEG)
•
•
•
•
•
60 SEG x 16 COM terminals
8, 12 and 16 com selectable
COM 8–15: shared with port
SEG40–59: shared with port
Two kinds of LCD bias resistor value
•
I/O:15pins (Not including COM/SEG)
43pins (Including COM/SEG)
Memory-Mapped I/O Structure
Data memory bank 15
8-bit Basic Timer
•
Bit Sequential Carrier
•
Supports 16-bit serial data transfer in arbitrary
format
•
•
Four interval timer functions
Watchdog timer
Interrupts
•
•
•
Four external interrupt vectors
8-bit Timer/Counter
Five internal interrupt vectors
Two quasi-interrupts
•
•
•
•
Programmable 8-bit timer
External event counter
Power-Down Modes
Arbitrary clock frequency output
External clock signal divider
•
•
•
Idle mode (only CPU clock stops)
Stop mode (main system oscillation stops)
Subsystem clock stop mode
16-Bit Timer/Counter
•
•
•
•
•
•
Programmable 16-bit timer
External event counter
Oscillation Sources
•
•
•
RC, Crystal or Ceramic for system clock
Oscillation frequency: 0.4–6.0 MHz
CPU clock divider circuit (by 4, 8, or 64)
Arbitrary clock frequency output
External clock signal divider
Configurable as two 8-bit Timers
Serial I/O interface clock generator
Instruction Execution Times
•
•
•
1.12, 2.23, 17.88 µs at 3.58 MHz
0.67, 1.33, 10.7 µs at 6.0 MHz
122 µs at 32.768 kHz (subsystem)
Watch Timer
•
Time interval generation: 0.5 s, 3.9 ms
at 32.768 kHz
Operating Temperature
•
4 frequency outputs to BUZ pin (0.5, 1, 2, 4 kHz)
at 32.768 kHz
°
°
•
– 40 C to 85 C
Operating Voltage Range
Comparator
•
•
•
1.8 V to 5.5 V (except DTMF and Comparator)
2 V to 5.5 V (include DTMF)
•
4-channel mode: Internal reference (4-bit
resolution); 16-step variable reference voltage
4.0 V to 5.5 V (include Comparator)
•
3-channel mode: External reference
Package Type
100-pin QFP (1420C)
DTMF Generator
•
•
16 dual-tone for tone dialing
1-2
S3C7565/P7565
PRODUCT OVERVIEW
BLOCK DIAGRAM
P7.0/SEG55/CIN0
P7.1/SEG54/CIN1
P7.2/SEG53/CIN2
P7.3/SEG52/CIN3
Basic
Timer
Watchdog
Timer
Comparator
Input Port 1
I/O Port 2
X
IN
IN
X
OUT
OUT
RESET
XT
XT
P1.0-P1.3/
INT0-INT4
Watch
Timer
P2.0/CLO
P2.1/VLC1
P2.2
Interrupt
Control
Block
Instruction
Register
VLC1
Clock
P3.0/TCLO0
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
COM0-COM7
LCD
Driver/
Controller
I/O Port 3
P4.0-P5.3/
COM8-COM15
SEG0-SEG39
Program
Counter
Internal
Interrupts
P4.0-P4.3/
COM8-COM11
P10.3-P6.0/
SEG40-SEG59
I/O Port 4
I/O Port 5
P5.0-P5.3/
COM12-COM15
Serial I/O
I/O Port 0
Instruction Dcoder
P6.0-P6.3
SEG59-SEG56/
KS4-KS7
Program
Status Word
I/O Port 6
I/O Port 7
P0.0/SCK/KO
P0.1/SO/K1
P0.2/SI/K2
Arithmetic
and
Logic Unit
P7.0/SEG55/CIN0
P7.1/SEG54/CIN1
P7.2/SEG53/CIN2
P7.3/SEG52/CIN3
P0.3/BUZ/K3
Stack
Pointer
DTMF
Generator
DTMF
P8.0/SEG51/LCDCK
P8.1/SEG50/LCDSY
P8.2/SEG49
I/O Port 8
I/O Port 9
P8.3/SEG48
5K x 4-bit
RAM
16-Bit
P9.0-P9.3/
SEG47-SEG44
8-Bit
Timer/
Counter
Timer/Counter
(Two 8Bit
Timer/Counter)
P10.0-P10.3/
SEG43-SEG40
16KB ROM
I/O Port 10
Figure 1-1. S3C7565 Block Diagram
1-3
PRODUCT OVERVIEW
S3C7565/P7565
PIN ASSIGNMENTS
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P10.3/SEG40
P10.2/SEG41
P10.1/SEG42
P10.0/SEG43
P9.3/SEG44
P9.2/SEG45
P9.1/SEG46
P9.0/SEG47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
1
2
3
4
5
6
7
8
9
DTMF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
P8.3/SEG48
P8.2/SEG49
P8.1/SEG50/LCDSY
P8.0/SEG51/LCDCK
P7.3/SEG52/CIN3
P7.2/SEG53/CIN2
P7.1/SEG54/CIN1
P7.0/SEG55/CIN0
P6.3/SEG56/K7
P6.2/SEG57/K6
P6.1/SEG58/K5
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/VLC1
P2.2
P3.0/TCLO0
Figure 1-2. S3C7565 Pin Assignments (100-QFP Package)
1-4
S3C7565/P7565
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7565 Pin Descriptions
Description
Pin Name
P0.0
P0.1
P0.2
P0.3
Pin Type
I/O
Share Pin
4-bit I/O port.
SCK/K0
SO/K1
SI/K2
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-drain or
push-pull output.
BUZ/K3
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test is possible.
4-bit pull-up resistors are software assignable.
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
I/O
I/O
Same as port 0 except that port 2 is a 3-bit I/O port.
Same as port 0.
CLO
VLC1
P3.0
P3.1
P3.2
P3.3
TCLO0
TCLO1
TCL0
TCL1
P4.0–P4.3
P5.0–P5.3
I/O
4-bit I/O ports.
COM8–COM11
COM12–COM15
1-, 4-bit or 8-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P6.0–P6.3
I/O
I/O
Same as P4, P5.
SEG59–
SEG56/K4–K7
P7.0–P7.3
P8.0–P8.1
SEG55/CIN0–
SEG52/CIN3
Input ports.
SEG51/LCDCK
SEG50/LCDSY
1, 4-bit or 8-bit read and test is possible.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
These pins can not be used as push-pull output. Refer to
the NOTES of table 10-3. Port Mode Group Flags.
P8.2–P8.3
I/O
Same as P4, P5.
SEG49
SEG48
P9.0–P9.3
SEG47–SEG44
SEG43–SEG40
P0.0/K0
P10.0–P10.3
I/O
I/O
Same as P4, P5.
Serial I/O interface clock signal.
SCK
SO
I/O
Serial data output.
P0.1/K1
1-5
PRODUCT OVERVIEW
S3C7565/P7565
Share Pin
Table 1-1. S3C7565 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Serial data input.
SI
I/O
I/O
I
P0.2/K2
BUZ
0.5, 1, 2, or 4 kHz frequency output for buzzer sound.
P0.3/K3
INT0, INT1
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
P1.0, P1.1
INT2
INT4
I
I
Quasi-interrupt with detection of rising or falling edges.
P1.2
P1.3
External interrupt with a detection of rising and falling
edge.
CLO
I/O
I/O
I/O
I/O
I/O
I/O
Clock output .
P2.0
P3.0
P3.1
P3.2
P3.3
TCLO0
TCLO1
TCL0
TCL1
Timer/counter 0 clock output.
Timer/counter 1 clock output.
External clock input for timer/counter 0.
External clock input for timer/counter 1.
CIN0
CIN1
CIN2
CIN3
4-Channel comparator input
CIN0–CIN2: comparator input only
CIN3: comparator input or external reference input
P7.0/SEG55
P7.1/SEG54
P7.2/SEG53
P7.3/SEG52
DTMF
O
DTMF output
–
P8.0/SEG51
P8.1/SEG50
–
LCDCK
I/O
I/O
O
LCD clock output
LCDSY
LCD synchronization clock output.
LCD common signal output.
COM0–COM7
COM8–COM11
COM12–COM15
SEG0–SEG39
SEG40–SEG59
K0–K3
I/O
P4.0–P4.3
P5.0–P5.3
–
O
LCD segment signal output.
I/O
I/O
P10.3–P6.0
P0.0–P0.3
P6.0–P6.3
–
External interrupt (triggering edge is selectable)
K4–K7
VDD
–
–
I
Main power supply.
VSS
Ground.
–
Reset signal.
–
RESET
VLC1
–
–
–
I
LCD power supply.
P2.1
XIN
X
OUT
Crystal, Ceramic or RC oscillator pins for system clock.
Crystal oscillator pins for subsystem clock.
–
–
–
,
XTIN, XTOUT
TEST
Chip test input pin.
Hold GND when the device is operating.
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
S3C7565/P7565
PRODUCT OVERVIEW
Table 1-2. Supplemental S3C7565 Pin Data
Pin Names
Share Pins
I/O Type
Circuit Type
RESET Value
P0.0–P0.3
I/O
Input
E-4
SCK/K0, SO/K1,
SI/K2, BUZ/K3
P1.0–P1.3
INT0, INT1 and
INT2, INT4
I
Input
A-4
P2.0
P2.1
CLO
VLC1
I/O
I/O
Input
Input
E-4
E-7
P2.2
–
I/O
I/O
I/O
I/O
Input
Input
Input
Input
E-4
E-2
P3.0–P3.1
P3.2–P3.3
TCLO0, TCLO1
TCL0, TCL1
E-4
P4.0–P4.3
P5.0–P5.3
COM8–COM11
COM12–COM15
H-24
I/O
I/O
H-25
H-26
P6.0–P6.3
SEG59/K4–
SEG56/K7
Input
Input
P7.0–P7.2
SEG55/CIN0–
SEG53/CIN2
P7.3
SEG52/CIN3
I/O
I/O
I/O
I/O
I/O
Input
H-27
H-28
H-24
H-24
H-24
P8.0–P8.1
P8.2–P8.3
P9.0–P9.3
P10.0–P10.3
COM0–COM7
SEG0–SEG39
DTMF
SEG51–SEG50
Input
SEG49–SEG48
Input
SEG47–SEG44
Input
SEG43–SEG40
Input
–
–
–
–
O
O
O
–
High
H-3
H-3
G-7
–
High
High impedance
–
VDD
VSS
–
–
–
–
–
–
–
I
–
–
–
–
–
–
–
B
–
–
–
–
RESET
VLC1
–
–
–
I
XIN
X
OUT
,
XTIN XT
,
OUT
TEST
1-7
PRODUCT OVERVIEW
S3C7565/P7565
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
N-Channel
In
In
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
VDD
VDD
Pull-Up
Resistor
P-CH
Pull-Up
Data
Resistor
Enable
Out
N-CH
Output
DIsable
In
Schmitt Trigger
Figure 1-4. Pin Circuit Type A-4
Figure 1-6. Pin Circuit Type C
1-8
S3C7565/P7565
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Resistor
Enable
P-CH
I/O
Data
N-CH
Output
DIsable
Figure 1-7. Pin Circuit Type E-2
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Resistor
Enable
P-CH
N-CH
I/O
Data
Output
DIsable
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-4
1-9
PRODUCT OVERVIEW
S3C7565/P7565
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Resistor
Enable
P-CH
I/O
Data
Output
DIsable
N-CH
Digital
Input
VLCEN
VLC1
Figure 1-9. Pin Circuit Type E-7
1-10
S3C7565/P7565
PRODUCT OVERVIEW
VLC1
VLC2
VLC3
COM/SEG
VLC4
VLC5
VLC6
Figure 1-10. Pin Circuit Type H-3
1-11
PRODUCT OVERVIEW
S3C7565/P7565
VLC1
VLC2
VLC3
SEG/COM
Data
Out
Output
DIsable
VLC4
VLC5
VSS
Figure 1-11. Pin Circuit Type H-23
1-12
S3C7565/P7565
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
Data
Circuit
Type C
I/O
Output
DIsable
Figure 1-12. Pin Circuit Type H-24
V
DD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
Data
Circuit
Type C
I/O
Output
DIsable
Figure 1-13. Pin Circuit Type H-25
1-13
PRODUCT OVERVIEW
S3C7565/P7565
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
P-CH
COM/SEG
LCD_ON
Circuit
Type H-23
Data
Circuit
Type C
I/O
Output
DIsable
Analog
Input SEL
Digital In
Analog In
Figure 1-14. Pin Circuit Type H-26
1-14
S3C7565/P7565
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
P-CH
COM/SEG
Circuit
LCD OUT EN
Type H-23
Data
Circuit
Type C
I/O
Output
DIsable
Analog
Input SEL
Digital In
External
REF SEL
Analog In
External
REF In
Figure 1-15. Pin Circuit Type H-27
1-15
PRODUCT OVERVIEW
S3C7565/P7565
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
LCDCK/CLDSY
Circuit
Type C
LCDCK/LCDSY
Enable
I/O
Output
DIsable
Figure 1-16. Pin Circuit Type H-28
-
DTMF Out
+
Disable
Figure 1-17. Pin Circuit Type G-7
1-16
S3C7565/P7565
ELECTRICAL DATA
16 ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7565 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN
— Clock timing measurement at XTIN
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
16-1
ELECTRICAL DATA
S3C7565/P7565
Table 16-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
V
VDD
VI
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
Ports 0–10
V
VO
IOH
Output Voltage
Output Current High
–
V
One I/O pin active
– 15
mA
All I/O pins active
One I/O pin active
– 35
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
+ 100 (Peak value)
+ 60 (note)
Total for ports 0, 2–10
TA
°
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
TSTG
°
C
– 65 to + 150
NOTE: The values for Output Current Low (I ) are calculated as Peak Value ´ Duty .
OL
Table 16-2. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input High
Voltage
All input pins except those
specified below for VIH2–VIH3
–
V
VIH2
0.8 VDD
VDD
VDD
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
VIH3
VIL1
XIN, XOUT, and XTIN
VDD – 0.1
–
0.3VDD
Input Low
Voltage
All input pins except those
–
V
specified below for V L2–VIL3
I
VIL2
0.2VDD
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
VIL3
VOH
XIN, XOUT, and XTIN
0.1
–
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
VDD – 1.0
Output High
Voltage
–
–
V
V
Ports 0, 2–10
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Output Low
Voltage
–
2.0
Ports 0, 2–10
16-2
S3C7565/P7565
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
ILIH1
VI = VDD
Input High
Leakage
Current
–
–
3
µA
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD
XIN, XTIN
20
ILIL1
V = 0 V
I
Input Low
Leakage
Current
–
–
– 3
µA
All input pins except RESET,
XIN, XTIN
ILIL2
ILOH
V = 0 V
I
XIN, XTIN
– 20
3
VO = VDD
Output High
Leakage
Current
–
–
–
–
µA
µA
kW
All output pins
ILOL
VO = 0 V
Output Low
Leakage
Current
– 3
All output pins
RLI
VI = 0 V; VDD = 5 V, Port 0–10
VDD = 3 V
Pull-Up
Resistor
25
47
100
50
95
200
400
RL2
100
220
VI = 0 V; VDD = 5 V, RESET
VDD = 3 V
200
40
450
55
800
70
RLCD1
LCD Voltage
Dividing
–
kW
Resistor (Note)
V
RLCD2
VDC
20
–
28
–
35
VDD = 2.7 V to 5.5 V
120
mV
|
DD-COMi|
Voltage Drop
(i = 0–15)
– 15 µA per common pin
V
VDS
VDD = 2.7 V to 5.5 V
–
–
120
|
DD-SEGx|
Voltage Drop
(x = 0–59)
– 15 µA per segment pin
V
VLC1
VDD = 2.7 V to 5.5 V
LCD clock = 0 Hz
VDD–0.2
VDD
VDD + 0.2
V
LCX Output
Voltage
VLC2
VLC3
VLC4
VLC5
0.8VDD–0.2 0.8VDD 0.8VDD +0.2
0.6VDD–0.2 0.6VDD 0.6VDD+0.2
0.4VDD–0.2 0.4VDD 0.4VDD+0.2
0.2VDD–0.2 0.2VDD 0.2VDD+0.2
NOTE: R
is the LCD Voltage dividing resistor when LCON.1 = “0”, and R
when LCON.1 = “1”.
LCD1
LCD2
16-3
ELECTRICAL DATA
S3C7565/P7565
Table 16-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Symbol
Conditions
Min
Typ
Max
Units
I
–
3.9
7.0
mA
Run mode; V
= 5 V ± 10 %
DD1
DD
(1)
Current
3.58 MHz X-tal oscillator,
C1 = C2 = 22 pF
(DTMF on)
–
–
2.0
4.0
V
= 3 V ± 10 %
DD
Run mode;
= 5 V ± 10%
I
6.0 MHz
3.58 MHz
4.1
2.7
8.0
5.0
DD2
V
(DTMF off)
DD
Crystal oscillator
C1 = C2 = 22pF
6.0 MHz
3.58 MHz
1.9
1.2
4.0
2.3
V
= 3 V ± 10%
DD
I
Idle mode;
= 5 V ± 10 %
6.0 MHz
3.58 MHz
–
1.2
0.9
2.5
1.8
DD3
V
DD
Crystal oscillator
C1 = C2 = 22pF
6.0 MHz
3.58 MHz
0.5
0.4
1.5
1.0
V
= 3 V ± 10 %
DD
(2)
–
–
–
17.5
45
Run mode; V
= 3 V ± 10 %
mA
mA
mA
I
DD
DD4
32 kHz Crystal oscillator
Idle mode; V = 3 V ± 10 %
(2)
4.8
15
I
DD
DD5
32 kHz Crystal oscillator
I
Stop mode;
SCMOD = 0000
DD6
XT = 0 V
2.0
0.6
5
3
V
V
= 5 V ± 10 %
= 3 V ± 10 %
IN
DD
DD
Stop mode;
SCMOD = 0100
0.2
0.1
3
2
V
= 5 V ± 10 %
DD
DD
V
= 3 V ± 10 %
Row Tone level
V
V
= 2 to 5.5 V
– 16.0
1
– 14.0
2
– 11.0
3
dBV
%
ROW
DD
RL = 12 KW; Temp = – 30 to 60 °C
V = 2 to 5.5 V
DD
RL = 12 KW; Temp = – 30 to 60 °C
Ratio of
Column to Row
tone
dBCR
THD
Distortion
(Dual tone)
V
= 2 to 5.5 V
–
–
5
DD
1 MHz band
RL = 12 KW; Temp = – 30 to 60 °C
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and
output port drive currents.
16-4
S3C7565/P7565
ELECTRICAL DATA
Table 16-3. Main System Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 1.8 V to 5.5 V)
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ Max Units
Configuration
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
0.4
–
6.0
MHz
XIN
XOUT
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
0.4
–
–
–
3
4
Stabilization time (2)
Stabilization occurs
when VDD is equal to
ms
the minimum
oscillator voltage
range; VDD = 3.0 V
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
0.4
–
6.0
MHz
XIN
XOUT
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
–
3
Stabilization time (2)
10
30
6.0
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
–
External
Clock
0.4
MHz
XIN
XOUT
XIN input frequency (1)
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3
XIN input high and low
level width (tXH, tXL)
83.3
1,250
ns
RC
Oscillator
Frequency
–
–
2
–
–
MHz
R = 25 kW, VDD = 5 V
XIN
XOUT
R
1
R = 40 kW, VDD = 3 V
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
16-5
ELECTRICAL DATA
S3C7565/P7565
Table 16-4. Recommended Oscillator Constants
°
°
(TA = – 40 C to + 85 C)
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.0
MAX
5.5
TDK
3.58 MHz–6.0 MHz
3.58 MHz–6.0 MHz
Leaded Type
FCR” ðÿM5
2.0
5.5
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz–6.0 MHz
2.0
5.5
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 16-5. Subsystem Clock Oscillator Characteristics
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
VDD = 1.8 V to 5.5 V
Crystal
Oscillator
32
32.768
35
kHz
XTIN XTOUT
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 1.8 V to 5.5 V
–
–
1.0
–
2
s
10
External
Clock
32
–
100
kHz
XTIN XTOUT
Open
XT input frequency (1)
IN
XT input high and low
IN
–
5
–
15
µs
level width (tXTL, tXTH
)
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
16-6
S3C7565/P7565
ELECTRICAL DATA
Table 16-6. Input/output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
–
–
–
–
15
15
pF
pF
I/O Capacitance
Table 16-7. Comparator Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 4.0 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
–
Condition
Min
Typ
Max
Units
VDD
Input Voltage Range
–
0
–
V
VREF
VDD
± 150
3
Reference Voltage Range
Input Voltage Accuracy
Input Leakage Current
–
–
–
0
–
–
–
–
V
VCIN
mV
mA
ICIN, IREF
– 3
16-7
ELECTRICAL DATA
S3C7565/P7565
Table 16-8. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction Cycle
Time (note)
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
1.33
0
64
fTI0, fTI1
TCL0, TCL1 Input
Frequency
–
–
1.5
MHz
µs
VDD = 1.8 V to 5.5 V
1
–
tTIH0, tTIL0 VDD = 2.7 V to 5.5 V
tTIH1, tTIL1
TCL0, TCL1 Input
High, Low Width
0.48
VDD = 1.8 V to 5.5 V
1.8
tKCY
VDD = 2.7 V to 5.5 V
800
–
–
ns
SCK Cycle Time
External SCK source
650
Internal SCK source
VDD = 1.8 V to 5.5 V
External SCK source
3200
3800
Internal SCK source; Output
16-8
S3C7565/P7565
ELECTRICAL DATA
Table 16-8. A.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
VDD = 2.7 V to 5.5 V
External SCK source
Min
Typ
Max
Units
tKH, tKL
325
–
–
ns
SCK High, Low
Width
TkCY
/
Internal SCK source
2–50
1600
VDD = 1.8 V to 5.5 V
External SCK source
tKCY
/
Internal SCK source
2–150
tSIK
VDD = 2.7 V to 5.5 V; Input
SI Setup Time to
100
–
–
–
–
–
ns
ns
ns
SCK High
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 1.8 V to 5.5 V; Output
VDD = 2.7 V to 5.5 V; Input
150
150
500
400
tKSI
SI Hold Time to
SCK High
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 1.8 V to 5.5 V; Output
VDD = 2.7 V to 5.5 V; Input
400
600
500
–
tKSO
Output Delay for
300
SCK to SO
VDD = 2.7 V to 5.5 V; Output
VDD = 1.8 V to 5.5 V; Input
VDD = 2.7 V to 5.5 V; Output
INT0–INT2, INT4, KS0–KS7
250
1000
1000
–
tINTH, tINTL
tRSL
Interrupt Input
High, Low Width
10
10
–
–
µs
µs
Input
–
RESET Input Low
Width
NOTE: Unless specified the otherwise, Instruction Cycle Time condition values assume a main system clock (fx) source.
16-9
ELECTRICAL DATA
S3C7565/P7565
Main Os. Freq. (Divided by 4)
6MHz
CPU Clock
1.5MHz
4.2MHz
3MHz
1.05MHz
0.75kHz
15.625kHz
1
2
3
4
5
6
7
1.8
2.7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)
Figure 16-1. Standard Operating Voltage Range
Table 16-9. RAM Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
Conditions
Min
1.8
–
Typ
–
Max
Unit
V
VDDDR
Data retention supply voltage
Data retention supply current
–
5.5
10
IDDDR
VDDDR = 1.8 V
0.1
µA
tSREL
tWAIT
Release signal set time
–
0
–
–
–
–
µs
217 / fx
Oscillator stabilization wait
time (1)
ms
Released by RESET
(2)
Released by interrupt
–
–
NOTES:
1. During the oscillator stabilization wait time, all the CPU operations must be stopped to avoid instability that can occur
during the oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay an execution of CPU instructions during the wait time.
16-10
S3C7565/P7565
ELECTRICAL DATA
TIMING WAVEFORMS
InternalReset
Operation
Idle Mode
Stop Mode
Operating
Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instruction
RESET
t
WAIT
t
SREL
Figure 16-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
Normal
Operating
Mode
Stop Mode
Data Retention Mode
VDD
VDDDR
tSREL
Execution of
STOP Instrction
tWAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 16-3. Stop Mode Release Timing When Initiated by Interrupt Request
16-11
ELECTRICAL DATA
S3C7565/P7565
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Measurement
Points
Figure 16-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
tXL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 16-5. Clock Timing Measurement at X
IN
1/fxt
tXTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 16-6. Clock Timing Measurement at XT
IN
16-12
S3C7565/P7565
ELECTRICAL DATA
1/fTI
tTIL
tTIH
TCL0
0.8 VDD
0.2 VDD
Figure 16-7. TCL Timing
tRSL
RESET
0.2 VDD
Figure 16-8. Input Timing for RESET Signal
16-13
ELECTRICAL DATA
S3C7565/P7565
tINTL
tINTH
INT0, 1, 2, 4
K0 to K7
0.8 VDD
0.2 VDD
Figure 16-9. Input Timing for External Interrupts and Quasi-Interrupts
tKCY
tKL
tKH
SCK
0.8 VDD
0.2 VDD
tSIK
tKSI
0.8 VDD
0.2 VDD
SI
Input Data
tKSO
SO
Output Data
Figure 16-10. Serial Data Transfer Timing
16-14
S3C7565/P7565
MECHANICAL DATA
17 MECHANICAL DATA
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
— Pad/pin coordinate data table
23.90 ± 0.3
20.00 ± 0.2
0-8O
+0.10
_0.05
0.15
0.10 MAX
100-QFP-1420C
#100
#1
0.65
(0.58)
0.30 ± 0.1
0.10 MAX
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.80 ± 0.20
Figure 17-1. 100-QFP Package Dimensions
NOTE: Dimensions are in millimeters.
17-1
MECHANICAL DATA
S3C7565/P7565
NOTES
17-2
S3C7565/P7565
S3P7565 OTP
18 S3P7565 OTP
OVERVIEW
The S3P7565 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7565
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P7565 is fully compatible with the S3C7565, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7565 is ideal for use as an evaluation chip for the S3C7565.
18-1
S3P7565 OTP
S3C7565/P7565
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P10.3/SEG40
P10.2/SEG41
P10.1/SEG42
P10.0/SEG43
P9.3/SEG44
P9.2/SEG45
P9.1/SEG46
P9.0/SEG47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
1
2
3
4
5
6
7
8
9
DTMF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.0/SCK/K0
P0.1/SO/K1
SDAT/P0.2/SI/K2
SCLK/P0.3/BUZ/K3
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
XTIN
P8.3/SEG48
P8.2/SEG49
XTOUT
P8.1/SEG50/LCDSY
P8.0/SEG51/LCDCK
P7.3/SEG52/CIN3
P7.2/SEG53/CIN2
P7.1/SEG54/CIN1
P7.0/SEG55/CIN0
P6.3/SEG56/K7
P6.2/SEG57/K6
P6.1/SEG58/K5
RESET/RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/VLC1
P2.2
P3.0/TCLO0
Figure 18-1. S3P7565 Pin Assignments (100-QFP Package)
18-2
S3C7565/P7565
S3P7565 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P0.2
Pin Name
Pin No.
I/O
Function
SDAT
13
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a Input/push-
pull output port.
P0.3
SCLK
14
19
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. When OTP is
operating, hold GND. (Option)
22
I
I
Chip initialization
RESET
RESET
VDD/VSS
VDD/VSS
Logic power supply pin. VDD should be tied to + 5 V
during programming.
15/16
Table 18-2. Comparison of S3P7565 and S3C7565 Features
S3P7565
Characteristic
S3C7565
Program Memory
16-Kbyte EPROM
1.8 V to 5.5 V
16-Kbyte mask ROM
Operating Voltage (VDD
)
1.8 V to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5V
OTP Programming Mode
Pin Configuration
100 QFP
100 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P7565, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 18-3 below.
Table 18-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/MEM
Address
(A15–A0)
0000H
R/W
Mode
5 V
5 V
0
0
0
1
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
0000H
EPROM program
EPROM verify
0000H
0E3FH
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
18-3
S3P7565 OTP
S3C7565/P7565
Table 18-4. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
– 0.3 to + 6.5
Units
VDD
VI
Supply Voltage
Input Voltage
–
V
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 15
Ports 0–10
V
V
VO
IOH
Output Voltage
Output Current High
–
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 35
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
Total for ports 0, 2–10
+ 100 (Peak value)
+ 60 (note)
°
TA
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
°
C
TSTG
– 65 to + 150
NOTE: The values for Output Current Low (I ) are calculated as Peak Value ´ Duty .
OL
18-4
S3C7565/P7565
S3P7565 OTP
Table 18-5. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input High
Voltage
All input pins except those
specified below for VIH2–VIH3
–
V
VIH2
0.8 VDD
VDD
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
VIH3
VIL1
XIN, XOUT, and XTIN
VDD – 0.1
–
VDD
0.3 VDD
Input Low
Voltage
All input pins except those
specified below for VIL2–VIL3
–
V
VIL2
0.2 VDD
Ports 0, 1, 2, 6, P3.2, P3.3,
and RESET
VIL3
VOH
XIN, XOUT, and XTIN
0.1
–
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
VDD – 1.0
Output High
Voltage
–
–
V
V
Ports 0, 2–10
VOL
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Output Low
Voltage
–
2.0
3
Ports 0, 2–10
VI = VDD
ILIH1
Input High
Leakage
Current
–
–
–
–
µA
µA
All input pins except those
specified below for ILIH2
ILIH2
VI = VDD
XIN, XTIN
20
ILIL1
VI = 0 V
Input Low
Leakage
Current
– 3
All input pins except RESET,
XIN, XTIN
ILIL2
VI = 0 V
– 20
3
XIN XT
,
IN
ILOH
VO = VDD
Output High
Leakage
Current
–
–
–
–
µA
µA
All output pins
ILOL
VO = 0 V
Output Low
Leakage
Current
– 3
All output pins
18-5
S3P7565 OTP
S3C7565/P7565
Table 18-5. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
RLI
VI = 0 V; VDD = 5 V,
Port 0–10
Pull-up Resistor
25
47
100
kW
VDD = 3 V
50
95
200
400
RL2
100
220
VI = 0 V; VDD = 5 V, RESET
VDD = 3 V
200
40
450
55
800
70
RLCD1
LCD Voltage
Dividing
–
kW
Resistor (note)
RLCD2
VDC
20
–
28
–
35
|VDD–COMi|
VDD = 2.7 V to 5.5 V
120
mV
Voltage Drop
(i = 0–15)
– 15 µA per common pin
|VDD–SEGx|
VDS
VDD = 2.7 V to 5.5 V
–
–
120
Voltage Drop
(x = 0–59)
– 15 µA per segment pin
VLCX Output
Voltage
VLC1
VDD = 2.7 V to 5.5 V
LCD clock = 0 Hz
VDD–0.2
VDD
VDD+0.2
V
VLC2
VLC3
VLC4
VLC5
0.8VDD–0.2 0.8VDD 0.8VDD+0.2
0.6VDD–0.2 0.6VDD 0.6VDD+0.2
0.4VDD–0.2 0.4VDD 0.4VDD+0.2
0.2VDD–0.2 0.2VDD 0.2VDD+0.2
NOTE: R
is the LCD Voltage dividing resistor when LCON.1 = “0”, and R
is the one when LCON.1 = “1”.
LCD1
LCD2
18-6
S3C7565/P7565
S3P7565 OTP
Table 18-5. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
IDD1
Conditions
Min
Typ
Max
Units
Supply Current (1)
–
3.9
7.0
mA
Run mode; VDD = 5 V ± 10 %
3.58 MHz X-tal oscillator,
C1 = C2 = 22 pF
(DTMF on)
–
2.0
4.0
VDD = 3 V ± 10%
IDD2
Run mode;
VDD = 5 V ± 10 %
6.0 MHz
3.58 MHz
4.1
2.7
8.0
5.0
(DTMF off)
Crystal oscillator
C1 = C2 = 22 pF
V
= 3 V ± 10 %
6.0 MHz
3.58 MHz
1.9
1.2
4.0
2.3
DD
IDD3
Idle mode;
VDD = 5 V ± 10 %
6.0 MHz
3.58 MHz
–
1.2
0.9
2.5
1.8
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
3.58 MHz
0.5
0.4
1.5
1.0
VDD = 3 V ± 10 %
(2)
–
–
–
17.5
45
Run mode; VDD = 3 V ± 10 %
mA
mA
mA
IDD4
32 kHz Crystal oscillator
(2)
y
15
Idle mode; VDD = 3 V ± 10 %
IDD5
32 kHz Crystal oscillator
IDD6
Stop mode;
SCMOD = 0000
2.0
0.6
5
3
XTIN = 0 V
VDD = 5 V ± 10 %
VDD = 3 V ± 10 %
Stop mode;
VDD = 5 V ± 10 %
SCMOD = 0100
0.2
0.1
3
2
VDD = 3 V ± 10 %
VROW
dBCR
THD
VDD = 2 to 5.5 V
Row Tone Level
– 16.0
– 14.0
– 11.0
dBV
%
RL = 12 KW; Temp = – 30 to 60 °C
VDD = 2 to 5.5 V
Ratio of Column to
Row tone
1
–
2
–
3
5
RL = 12 KW; Temp = – 30 to 60 °C
VDD = 2 to 5.5 V
Distortion
(Dual tone)
1 MHz band
RL = 12 KW; Temp = – 30 to 60 °C
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and
output port drive currents.
18-7
S3P7565 OTP
S3C7565/P7565
Table 18-6. Main System Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 1.8 V to 5.5 V)
°
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max Unit
s
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
Ceramic
XIN
XOUT
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
0.4
–
–
–
3.0
4
Stabilization time (2)
ms
Stabilization occurs
when VDD is equal to
the minimum
oscillator voltage
range; VDD = 3.0 V
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
0.4
–
6.0
MHz
Crystal
XIN
XOUT
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
–
3.0
10
Stabilization time (2)
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
–
30
XIN input frequency (1)
0.4
6.0
MHz
External
Clock
XIN
XOUT
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3.0
XIN input high and low
level width (tXH, tXL)
83.3
1,250
ns
–
–
2
–
–
MHz
RC
Oscillator
Frequency
XIN
XOUT
R = 25 kW, VDD = 5 V
R
1
R = 40 kW, VDD = 3 V
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
18-8
S3C7565/P7565
S3P7565 OTP
Table 18-7. Subsystem Clock Oscillator Characteristics
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
VDD = 1.8 V to 5.5 V
Crystal
Oscillator
32 32.768
35
kHz
XTIN XTOUT
C1
C2
Stabilization time (2)
VDD = 2.7 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 1.8 V to 5.5 V
–
–
1.0
–
2
s
10
XTIN input frequency (1)
External
Clock
32
–
100
kHz
XTIN XTOUT
Open
XTIN input high and low
–
5
–
15
µs
level width (tXTL, tXTH
)
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 18-8. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
CIN
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
COUT
CIO
Output
Capacitance
–
–
–
–
15
15
pF
pF
I/O Capacitance
18-9
S3P7565 OTP
S3C7565/P7565
Main Os. Freq. (Divided by 4)
6MHz
CPU Clock
1.5MHz
4.2MHz
3MHz
1.05MHz
0.75kHz
15.625kHz
1
2
3
4
5
6
7
1.8
2.7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)
Figure 18-2. Standard Operating Voltage Range
18-10
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