S3P8475-QZ [SAMSUNG]
Microcontroller, 8-Bit, OTPROM, SAM87RC CPU, 12MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44;
| 型号： | S3P8475-QZ |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, OTPROM, SAM87RC CPU, 12MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总24页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C8478/C8475/P8475
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM87RC PRODUCT FAMILY
Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a
wide range of integrated peripherals, and various mask-programmable ROM sizes.
Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RC
microcontrollers have an external interface that provides access to external memory and other peripheral
devices.
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
one interrupt level at a time.
S3C8478/C8475 MICROCONTROLLER
The S3C8478/C8475 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter,
UART, PWM application field. Its powerful SAM87RC CPU architecture includes. The internal register file is
logically expanded to increase the on-chip register space.
The S3C8478/C8475 has 8/16K bytes of on-chip program ROM. Following Samsung's modular design approach,
the following peripherals are integrated with the SAM87RC core:
— Large number of programmable I/O ports (42 SDIP: 34 pins, 44 QFP: 36 pins)
— One asynchronous UART module
— Analog-to-digital converter with eight input channels and 10-bit resolution
— One 8-bit basic timer for watchdog function
— One 8-bit timer/counter with three operating modes (Timer 0)
— One general-purpose 16-bit timer/counters with three operating modes (Timer 1)
The S3C8478/C8475 is a versatile general-purpose microcontroller that is ideal for use in a wide range of
electronics applications requiring complex timer/counter, PWM, capture, and UART.
It is available in a 42-pin SDIP or 44-pin QFP package.
OTP
The S3C8475 is an OTP (One Time Programmable) version of the S3C8478/C8475 microcontroller. The
S3C8475 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of a masked ROM.
The S3C8475 is comparable to the S3C8478/C8475, both in function in D.C. electrical characteristics and in pin
configuration.
1-1
PRODUCT OVERVIEW
S3C8478/C8475/P8475
FEATURES
CPU
UART
•
SAM87RC CPU core
•
•
One UART module
Full duplex serial I/O interface with three UART
modes
Memory
•
•
272-byte general purpose register area
8/16K-byte internal program memory
A/D Converter
•
•
•
Eight analog input pins
Instruction Set
10-bit conversion resolution
•
•
79 instructions
20 µs conversion time (10 MHz CPU clock)
IDLE and STOP instructions added for
power-down modes
Buzzer Frequency Output
200 Hz to 20 kHz signal can be generated
•
Instruction Execution Time
333 ns at 12 MHz fOSC (minimum)
•
Oscillator Frequency
•
•
1 MHz to 12 MHz external crystal oscillator
Maximum 12 MHz CPU clock
Interrupts
•
•
•
14 interrupt sources and 14 vectors
Operating Temperature Range
Eight interrupt levels
° °
– 40 C to + 85 C
Fast interrupt processing
•
General I/O
Operating Voltage Range
1.8 V to 5.5 V
•
•
•
Five I/O ports (total 36 pins)
•
Four bit-programmable ports
Package Types
42-pin SDIP, 44-pin QFP
Two n-channel open-drain output port
•
Timer/Counters
•
•
One 8-bit basic timer for watchdog function
One 8-bit timer/counter with three operating
modes (timer 0)
•
One 16-bit general-purpose timer/counters with
three operation modes (timer 1)
1-2
S3C8478/C8475/P8475
PRODUCT OVERVIEW
BLOCK DIAGRAM
P1.0-P1.5
T0, T1CK, T1,
BUZ, RxD, TxD
P0.0-P0.7
Port 0
Basic
Timer
Port 1
XIN
XOUT
OSC
Timer 0
Timer 1
ADC
P2.0-P2.7
INT0-INT7
Port 2
Port 3
Port 4
Port I/O and Interrupt
T0(CAP)
T0(PWM)
Control
T1(CAP)
T1(PWM)
P3.0-P3.7
ADC0-ADC7
SAM87RC CPU
ADC0-ADC7
P1.4/RxD
P1.5/TxD
UART
BUZ
P4.0-P4.3
P4.4-P4.5
272-byte
Register
File
8/16-Kbyte
ROM
P1.3/BUZ
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C8478/C8475/P8475
PIN ASSIGNMENTS
P1.0/T0 (CAP/PWM)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P4.3
P4.2
VDD
VSS
XOUT
XIN
TEST
P4.1
1
2
3
4
5
6
7
8
P1.1/T1CK
P1.2/T1 (CAP/PWM)
P1.3/BUZ
P1.4/RxD
P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AVSS
S3C8478
S3C8475
42-SDIP
9
10
11
12
13
14
15
16
17
18
19
20
21
(Top-View)
AVREF
P2.7/INT7
P2.6/INT6
P2.5/INT5
P2.4/INT4
P2.3/INT3
P4.0
RESET
P2.0/INT0
P2.1/INT1
P2.2/INT2
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
1-4
S3C8478/C8475/P8475
PRODUCT OVERVIEW
P1.4/RxD
P1.5/TxD
33
32
31
30
29
28
27
26
25
24
23
P0.1
P0.0
P4.3
P4.2
VDD
VSS
XOUT
XIN
1
2
3
4
5
6
7
8
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AVSS
S3C8478
S3C8475
44-QFP
(Top-View)
TEST
P4.1
P4.0
9
10
11
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
1-5
PRODUCT OVERVIEW
S3C8478/C8475/P8475
Table 1-1. S3C8478/C8475 Pin Descriptions
Pin Description
Pin
Name
Pin
Type
Circuit
Pin
Number
Share
Pins
Number
P0.0–P0.7
I/O
Nibble-programmable I/O port for Schmitt trigger
input or push-pull, open-drain output. Pull-up
resistors are assignable by software.
E
8-1
(2-1,
43-38)
–
P1.0–P1.5
I/O
Bit-programmable I/O port for Schmitt trigger input
or push-pull output. Pull-up resistors are assignable
by software. Port 1 pin can also by used as
D
D
F
42-37
(37-32)
T0, T1CK,
T1, BUZ,
RxD, TxD
alternative function (T0, T1CK, T1, BUZ, RxD, TxD)
P2.0–P2.7
P3.0–P3.7
P4.0–P4.3
I/O
I/O
I/O
Bit-programmable I/O port for Schmitt trigger input
or push-pull output. Pull-up resistors are assignable
by software. Port 2 pins can also be used as
external interrupt.
19-26
(13-20)
INT0-
INT7
Bit-programmable I/O port for Schmitt trigger input
or push-pull output. Pull-up resistors are assignable
by software. Port 3 pins can also be used as A/D
converter by software.
29-36
(24-31)
ADC0-
ADC7
Bit-programmable I/O port for Schmitt trigger input
or push-pull, open-drain output. Pull-up resistors are
assingable by software.
E
17-16,
10-9
(11-10,
4-3)
–
P4.4–P4.5
XIN, XOUT
O
–
Push-pull output only
C
–
(44, 21)
–
–
Crystal or ceramic oscillator signal for system clock.
14, 13
(8, 7)
I
I
System reset signal input pin.
B
–
18 (12)
15 (9)
–
–
RESET
TEST
Test signal input pin (for factory use only; muse be
connected to VSS
)
AVREF,
AVSS
–
–
A/D converter reference voltage input and ground
Voltage input pin and ground
–
–
27, 28
(22, 23)
–
–
VDD, VSS
11, 12
(5, 6)
T0
I/O
I
Timer 0 capture input or PWM output pin
Timer 1 external clock input pin
D
D
D
D
D
D
E
42 (37)
41 (36)
40 (35)
39 (34)
38 (33)
37 (32)
P1.0
P1.1
T1CK
T1
I/O
O
Timer 1 capture input or PWM output pin
200Hz-20kHz frequency output for buzzer sound
UART receive and transmit input or output
UART transmit output
P1.2
BUZ
RxD
P1.3
I/O
O
P1.4
TxD
P1.5
INT0-INT7
I
External interrupt input
19-26
P2.0-P2.7
(13-20)
ADC0-
ADC7
I
A/D converter input
F
29-36
(24-31)
P3.0-P3.7
NOTE: Pin numbers shown in parentheses "( )" are for the 44-pin QFP package.
1-6
S3C8478/C8475/P8475
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
P-Channel
N-Channel
P-Channel
Out
Data
In
N-Channel
Output
DIsable
Figure 1-4. Pin Circuit Type A
Figure 1-6. Pin Circuit Type C
VDD
VDD
Pull-Up
Resistor
Pull-up
Enable
Data
Circuit
Type C
In
In/Out
Output
DIsable
Schmitt Trigger
Data
Figure 1-7. Pin Circuit Type D
Figure 1-5. Pin Circuit Type B
1-7
PRODUCT OVERVIEW
S3C8478/C8475/P8475
VDD
47 K
PNE
VDD
Pull-up
Enable
P-CH
In/Out
Data
N-CH
Output
DIsable
Schmitt Trigger
Figure 1-8. Pin Circuit Type E
VDD
Pull-up
Enable
Data
Circuit
Type C
In/Out
Output
DIsable
Data
TO ADC
Figure 1-9. Pin Circuit Type F
1-8
S3C8478/C8475/P8475
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this chapter, S3C8478/C8475 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— Input/output capacitance
— D.C. electrical characteristics
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time
— Data retention supply voltage in stop mode
— UART timing characteristics in mode 0
— A/D converter electrical characteristics
14-1
ELECTRICAL DATA
Table
1. Absolute Maximum Ratings
°
A = 25 C)
Parameter
Supply Voltage
Input Voltage
Symbol
Conditions
Rating
Unit
V
VDD
–
– 0.3 to + 6.5
VI
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
All ports
V
VO
IOH
Output Voltage
Output Current High
All output ports
V
One I/O pin active
– 18
mA
All I/O pins active
One I/O pin active
– 60
+ 30
IOL
Output Current Low
mA
Total pin current for ports 1, 2, and 3
+ 100
+ 200
Total pin current for ports 0 and 4
–
TA
°
C
Operating
– 40 to + 85
Temperature
TSTG
°
C
Storage Temperature
–
– 65 to + 150
14-2
S3C8478/C8475/P8475
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics
°
°
(T = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
A
Parameter
Input High
Symbol
Test Conditions
Min
Typ
Max
Unit
VIH1
VDD = 2.7 to 5.5 V 0.8 VDD
VDD
Ports 0, 1, 2, 3 ,4
and RESET
–
V
Voltage
VIH3
VIL1
XIN, and XOUT
VDD–0.1
VDD = 2.7 to 5.5 V
Input Low
Voltage
Ports 0, 1, 2, 3, 4
and RESET
–
–
0.2
VDD
V
V
VIL3
VOH
XIN and XOUT
0.1
–
IOH = – 1 mA
Ports 0, 1, 2, 3, 4
IOL = 15 mA
VDD = 4.5 to 5.5 V VDD 1.0
–
Output High
Voltage
–
VOL1
VDD = 4.5 to 5.5 V
Output Low
Voltage
–
0.4
2.0
Port 0, and 4
VOL2
IOL = 4 mA
VDD = 4.5 to 5.5 V
VIN = VDD
0.4
–
2.0
1
V
Ports 1, 2, and 3
All input pins except
ILIH1
Input High
Leakage Current
–
–
uA
I
LIH2 and RESET
ILIH2
ILIL1
XIN, and XOUT
VIN = VDD
VIN = 0 V
20
Input Low
Leakage Current
All input pins except
ILIL2
–
– 1
uA
uA
ILIL2
ILOH
XIN, and XOUT
All output pins
VIN = 0 V
– 20
2
VOUT = VDD
Output High
Leakage Current
–
–
–
–
ILOL
VOUT = 0 V
Output Low
Leakage Current
All output pins
– 2
uA
RP1
RP1
IDD1
VIN = 0 V, Ports 0-4 VDD = 5 V
Pull-up Resistor
30
100
–
47
200
10
70
350
20
KW
VDD = 5 V
RESET
VDD = 4.5 to 5.5 V
Supply Current
RUM mode
mA
12 MHz CPU clock
VDD = 1.8 to 2.2 V
VDD = 4.5 to 5.5 V
3 MHz CPU clock
1.1
4
3
8
IDD2
Idle mode
12 MHz CPU clock
–
–
VDD = 1.8 to 2.2 V
VDD = 4.5 to 5.5 V
VDD = 1.8 to 2.2 V
3 MHz CPU clock
Stop mode
0.6
0.1
0.1
1.5
5
IDD3
uA
3
14-3
ELECTRICAL DATA
S3C8478/C8475/P8475
Table 14-3. A.C. Electrical Characteristics
°
°
(T = - 40 C to + 85 C, VDD = 4.5 V to 5.5 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
tINTH
,
tINTL
Interrupt Input
High, Low Width
Ports 2
VDD = 5 V ± 10 %
–
200
–
ns
tRSL
Input
VDD = 5 V ± 10 %
–
1
–
ms
RESET Input
Low Width
tINTL
tRST
tINTH
0.8 VDD
0.2 VDD
Figure 14-1. Input Timing Measurement Points
14-4
S3C8478/C8475/P8475
ELECTRICAL DATA
Table 14-4. Oscillation Characteristics
°
°
(T = – 40 C + 85 C)
A
Oscillator
Main Crystal or
Ceramic
Clock Circuit
Test Condition
Min
Typ
Max
12
8
Unit
VDD = 4.5 V to 5.5 V
1
–
MHz
VDD = 2.7 V to 4.5 V
VDD = 1.8 V to 2.7 V
3
XIN
XOUT
C1
C2
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 4.5 V
VDD = 1.8 V to 2.7 V
External Clock
(Main System)
1
–
12
8
MHz
3
XIN
XOUT
14-5
ELECTRICAL DATA
S3C8478/C8475/P8475
Main Oscillator Frequency
(Divided by 4)
CPU Clock
12 MHz
10 MHz
8 MHz
6 MHz
4 MHz
2 MHz
1
2
3
4
5
6
7
1.8 V 2.7 V
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 14-2. Operating Voltage Range
Table 14-5. Oscillation Stabilization Time
°
°
(TA = – 40 C + 85 C, VDD = 1.8 V to 5.5 V)
Oscillator
Main Crystal
Main Ceramic
Test Condition
Min
–
Typ
–
Max
20
Unit
ms
fOSC > 1.0 kHz;
Oscillation stabilization occurs when VDD is equal
to the minimum oscillator voltage range.
XIN input High and Low width (tXH, tXL)
–
–
10
ms
External Clock
(Main System)
25
–
500
ns
tWAIT when released by a reset (1)
216/fOSC
–
Oscillator
–
–
–
–
ms
ms
tWAIT when released by an interrupt (2)
Stabilization
Wait Time
NOTES:
1.
f
is the oscillator frequency.
OSC
2. The duration of the oscillator stabilization wait time, t
settings in the basic timer control register, BTCON.
, when it is released by an interrupt is determined by the
WAIT
14-6
S3C8478/C8475/P8475
ELECTRICAL DATA
Table 14-6. UART Timing Characteristics in Mode 0 (10 MHz)
°
°
(T = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V, Load capacitance = 80 pF)
A
Parameter
Symbol
Min
Typ
Max
Unit
tSCK
Serial port clock cycle time
500
700
–
ns
t
t
CPU ´ 6
tS1
tS2
tH1
tH2
Output data setup to clock rising edge
Clock rising edge to input data valid
Output data hold after clock rising edge
Input data hold after clock rising edge
Serial port clock High, Low level width
300
CPU ´ 5
–
tCPU
–
–
tCPU – 50
0
300
–
–
tHIGH, LOW
t
200
400
t
CPU ´ 3
NOTES:
1. All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency.
2. The unit tCPU means one CPU clock period.
t
HIGH
0.8 V
DD
0.2 V
DD
t
LOW
t
SCK
Figure 14-3. Waveform for UART Timing Characteristics
14-7
ELECTRICAL DATA
S3C8478/C8475/P8475
Figure 14-4. A.C. Timing Waveform for the UART Module
14-8
S3C8478/C8475/P8475
ELECTRICAL DATA
Table 14-7. Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Stop mode
Min
Typ
Max
Unit
VDDDR
Data Retention
Supply Voltage
1.8
–
5.5
V
IDDDR
Stop mode, VDDDR = 1.8 V
Data Retention
Supply Current
–
0.1
5
µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
RESET
Oscillation
occurs
Stabilzation
Time
Stop Mode
Data Retention Mode
VDD
Normal
Operating
Mode
VDDDR
Execution of
STOP Instrction
RESET
tWAIT
NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 14-5. Stop Mode Release Timing When Initiated by a Reset
VOUT
VDD
A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD
VSS
A
B
C
D
VIN
Figure 14-6. Schmitt Trigger Input Characteristics
14-9
ELECTRICAL DATA
S3C8478/C8475/P8475
Table 14-8. A/D Converter Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V, VSS = 0 V)
A
Parameter
Symbol
Test Conditions
VDD = 5.12 V
Min
Typ
Max
± 3
Unit
Total accuracy
–
–
–
LSB
Integral linearity
error
ILE
CPU clock = 8 MHz
AVREF = 5.12 V
–
± 2
AVSS = 0 V
Differential
linearity error
DLE
EOT
EOB
tCON
VIAN
–
± 1
± 1
–
± 1
Offset error of
top
± 3
Offset error of
bottom
± 2
fOSC = 10 MHz (3)
Conversion
time (1)
20
AVSS
2
–
AVREF
–
ms
V
Analog input
voltage
–
–
RAN
Analog input
impedance
–
–
–
MW
V
AVREF
AVSS
IADIN
IADC
VDD
VSS + 0.3
10
ADC reference
voltage
2.5
VSS
–
–
ADC reference
ground
–
–
V
AVCC = VCC = 5 V
AVCC = VCC = 5 V
AVCC = VCC = 3 V
Analog input
current
–
mA
mA
Analog block
current (2)
–
1
3
0.5
1.5
AVCC = VCC = 5 V
power down mode
100
500
nA
NOTES:
1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.
2.
I
is operating current during A/D conversion.
ADC
OSC
3.
f
is the main oscillator clock.
14-10
S3C8478/C8475/P8475
ELECTRICAL DATA
Digital Output
11 1111 1111
11 1111 1110
11 1111 1101
.
.
.
.
.
00 0000 0010
00 0000 0001
00 0000 0000
Analog Input
AVSS VEOB V2
V(K-1) V(K)
VEOT AVREF
1LSB = (VEOT-VEOB)/1022
DLE(K) = {(V(K)-V(K-1))-1LSB}/1LSB
ILE(K) = {V(K)-(1LSB x K + VEOB)}/1LSB
DLE = MAX{DLE(K)}
ILE = MAX{ILE(K)}
Figure 14-7. Definition of DLE and ILE
14-11
S3C8478/C8475/P8475
MECHANICAL DATA
15 MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
— Package dimensions in millimeters
— Pad diagram
#42
#22
0-15
42-SDIP-600
#1
#21
39.50 MAX
39.10 ± 0.2
0.50 ± 0.1
1.00 ± 0.1
1.778
(1.77)
NOTE: Dimensions are in millimeters.
Figure 15-1. 42-SDIP-600 Package Dimensions
15-1
MECHANICAL DATA
S3C8478/C8475/P8475
13.20 ± 0.3
10.00 ± 0.2
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
44-QFP-1010
#44
+ 0.10
0.35 - 0.05
#1
0.05 MIN
0.80
(1.00)
2.05 ± 0.10
2.30 MAX
NOTE: Dimensions are in millimeters.
Figure 15-2. 44-QFP-1010 Package Dimensions
15-2
S3C8478/C8475/P8475
S3P8475 OTP
16 S3P8475 OTP
OVERVIEW
The S3P8475 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C8478/C8475 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is
accessed by serial data format.
The S3P8475 is fully compatible with the S3C8478/C8475, both in function in D.C. electrical characteristics and
in pin configuration. Because of its simple programming requirements, the S3P8475 is ideal as an evaluation
chip for the S3C8478/C8475.
P1.0/T0(CAP/PWM)
P1.1/T1CK
P1.2/T1(CAP/PWM)
P1.3/BUZ
P1.4/RxD
P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AVSS
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
1
2
3
4
5
6
7
8
SDAT/P4.3
SCLK/P4.2
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
9
S3P8475
10
11
12
13
14
15
16
17
18
19
20
21
(42-SDIP)
Top-View
AVREF
P2.7/INT7
P2.6/INT6
P2.5/INT5
P2.4/INT4
P2.3/INT3
P4.0
RESET/RESET
P2.0/INT0
P2.1/INT1
P2.2/INT2
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. S3P8475 Pin Assignments (42-SDIP Package)
16-1
S3P8475 OTP
S3C8478/C8475/P8475
P1.4/RxD
P1.5/TxD
33
32
31
30
29
28
27
26
25
24
23
P0.1
P0.0
1
2
3
4
5
6
7
8
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AVSS
SDAT/P4.3
SCLK/P4.2
VDD/VDD
VSS/VSS
XOUT
XIN
VPP/TEST
P4.1
S3P8475
(44-QFP)
Top-View
9
10
11
P4.0
NOTE:
The bolds indicate an OTP pin name.
Figure 16-2. S3P8475 Pin Assignments (44-QFP Package)
16-2
S3C8478/C8475/P8475
Main Chip
S3P8475 OTP
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P4.3
SDAT
9(3)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P4.2
SCLK
VPP
10(4)
I
I
Serial clock pin. Input only pin.
TEST
14(16)
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is aplied, OTP is in reading mode.
(Option)
18(12)
I
Chip Initialization
RESET
RESET
VDD/VSS
VDD/VSS
11(5)/12(6)
–
Logic power supply pin. VDD should be tied to
+5 V during programming.
NOTE: ( ) means 44 QFP package.
Table 16-2. Comparison of S3C8475 and S3C8478/C8475 Features
Characteristic S3C8475 S3C8478/C8475
16-Kbyte EPROM
Program Memory
8/16-Kbyte mask ROM
1.8 V to 5.5 V
Operating Voltage (VDD
)
1.8 V to 5.5 V
OTP Programming Mode
VDD = 5 V, VPP (EA) = 12.5 V
Pin Configuration
42 SDIP/44 QFP
42 SDIP/44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3C8475, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
ADDRESS
(A15–A0)
R/W
MODE
MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-3
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