S3P8615 [SAMSUNG]
S3C8618/C8615/P8615 MICROCONTROLLERS; S3C8618 / C8615 / P8615微控制器
| 型号： | S3P8615 |
| 厂家： | 
SAMSUNG |
| 描述： | S3C8618/C8615/P8615 MICROCONTROLLERS |
| 文件： | 总23页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S3C8618/C8615/P8615
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.
S3C8618/C8615/P8615 MICROCONTROLLERS
The S3C8618/C8615/P8615 single-chip 8-bit
microcontroller is based on the powerful SAM8 CPU
architecture. The internal register file is logically
expanded to increase the on-chip register space. The
S3C8618/C8615/P8615 have 8/16 K bytes of on-chip
program ROM.
— Multi master IIC-bus with DDC support.
The S3C8618/C8615/P8615 are a versatile
microcontroller that is ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, and multi-master IIC-bus support
with DDC. It is available in a 42-pin SDIP or a 44-pin
QFP package.
Following Samsung's modular design approach, the
following peripherals were integrated with the SAM8
core:
— Four programmable I/O ports (total 28 pins)
— One 8-bit basic timer for oscillation stabilization
and watchdog functions
— One 8-bit general-purpose timer/counter with
selectable clock sources
— One 8-bit counter with selectable clock sources,
including Hsync or Csync input
— One 8-bit timer for interval mode
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,
Csync input, and Clamp signal output)
Figure 1-1. S3C8618/C8615/P8615
Microcontrollers
1-1
PRODUCT OVERVIEW
S3C8618/C8615/P8615
FEATURES
— Two selectable internal clock frequencies
CPU
— Hsync (or Csync) input from the sync
processor block
•
SAM8 CPU core
Memory
— External clock source
•
•
8/16-Kbyte internal program memory (ROM)
272-byte general-purpose register area
Pulse Width Modulator
•
Seven 8-bit PWM modules:
— 8-bit basic frame
Instruction Set
•
•
78 instructions
— Four push-pull and three n-channel,
open-drain output channels
IDLE and STOP instructions added for power-
down modes
— Selectable clock frequencies: 46.875 kHz at
12 MHz fosc.
Instruction Execution Time
500 ns minimum (with 12 MHz CPU clock)
•
Sync Processor
•
Detection of sync input signals (Vsync-I, Hsync-I,
and Csync-I)
Interrupts
•
•
•
•
Nine interrupt sources
•
Sync signal separation and output (Hsync-O,
Vsync-O, and Clamp-O)
Nine interrupt vectors
Six interrupt levels
•
•
Pseudo sync signal output
Fast interrupt processing for a select level
Programmable clamp signal output
General I/O
DDC and Multi-Master IIC-Bus
•
Four I/O ports (total 28 pins):
•
•
Serial peripheral interface
8-Bit Basic Timer
Support for display data channel (DDC)
•
Programmable timer for oscillation stabilization
interval control or watchdog timer functions
Oscillator Frequency
•
•
6 MHz to 12 MHz external crystal oscillator
Interval Max. 12MHz CPU clock
•
Three selectable internal clock frequencies
Timer/Counters
Operating Temperature Range
•
One 8-bit general-purpose timer/counter with
programmable operating modes and the following
clock source options:
° °
– 40 C to + 85 C
•
Operating Voltage Range
4.5 V to 5.5 V
— Two selectable internal clock frequencies
One 8-bit timer with interval operating mode
•
•
•
One 8-bit counter with the following clock source
options:
Package Types
42-pin SDIP, 44-pin QFP
•
1-2
S3C8618/C8615/P8615
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0–P0.7/INT0-INT2
P2.0–P2.7
PORT 2
RESET
INT0-INT2
PORT 0
TEST
MAIN
OSC
XIN
OUT
INTERNAL BUS
X
PORT 1
P1.0–P1.3
I/O PORT and INTERRUPT
CONTROL
PWM0
PWM1
8-BIT
PWM
•
•
(7-CH)
•
SAM8 CPU
PWM6
PORT3
P3.0–P3.7
Vsync-I
Hsync-I
Csync-I
Vsync-O
Hsync-O
Clamp-O
SYNC
PRO-
8/16-KBYTE MASK ROM
CESSOR
DDC and
SCL
SDA
272-BYTE REGISTER FILE
Multi master
IIC-bus
TIMER 0
T0CAP
Interval
8-blt
timer
Counter
(TIMER 1)
(TIMER 2)
T1CK
Figure 1-2. Block Diagram
1-3
PRODUCT OVERVIEW
S3C8618/C8615/P8615
PIN ASSIGNMENTS
P3.2
VSS2
P3.3
P3.4
P3.5
P3.6
P3.7
RESET
XOUT
XIN
VSS1
P2.7/Csync-I
Hsync-I
Vsync-I (VCLK)
Clamp-O
Hsync-O
Vsync-O
SCL
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.1
P3.0
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
P0.4/T0CAP
P0.5/T1CK
VDD
1
2
3
4
5
6
7
8
9
S3C8618/8615
42-SDIP
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
10
11
12
13
14
15
16
17
18
19
20
21
(Top View)
P2.0/PWM0
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
SDA
TEST
P2.6/PWM6
Figure 1-3. Pin Assignment Diagram (42-SDIP Package)
1-4
S3C8618/C8615/P8615
PRODUCT OVERVIEW
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
N.C.
34
35
36
37
38
39
40
41
42
43
44
33
32
31
30
29
28
27
26
25
24
23
P0.2/INT2
P0.1/INT1
P0.0/INT0
P3.0
P3.1
NC
P3.2
VSS2
P3.3
P3.4
S3C8618/8615
44-QFP
P2.6/PWM6
TEST
(Top View)
SDA
SCL
Vsync-O
P3.5
Figure 1-4. Pin Assignment Diagram (44-QFP Package)
1-5
PRODUCT OVERVIEW
S3C8618/C8615/P8615
PIN DESCRIPTIONS
Table 1-1. S3C8618/C8615/P8615 Pin Descriptions
Pin
Names
Pin
Type
Pin
Description
Circuit
Type
SDIP Pin
Numbers
Shared
Functions
P0.0
I/O
General-purpose, 8-bit I/O port. Share
functions include three external interrupt
inputs, I/O for timers 0 and 1. You can
selectively configure port 0 pins to input or
output mode.
D-1
3
4
5
6
7
8
10
11
INT0
INT1
INT2
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
T0CAP
T1CK
P1.0–P1.3
I/O
I/O
General purpose, 8-bit I/O port. You can
selectively configure port 1 pins to input or
push-pull output mode.
D-1
12–15
–
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
General purpose, 8-bit I/O port. You can
selectively configure port 2 pins to input or
output mode. The port 2 pin circuit are
designed to push-pull PWM output and
Csync signal input.
D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1
16
17
18
19
20
21
22
31
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Csync-I
P3.0–P3.7
I/O
General-purpose, 8-bit I/O port. You can
selectively configure port 3 pins to input or
output mode.
E
2, 1, 42,
40–36
–
Hsync-I
Vsync-I
Clamp-O
Hsync-O
Vsync-O
SCL
I
I
O
O
O
The pins are sync processor signal I/O and
IIC-bus clock and data I/O
A
A
A
A
A
30
29
28
27
26
25
24
–
I/O
I/O
G-3
G-3
SDA
VDD
VSS1, VSS2
–
Power supply pins
–
9
–
32, 41
XIN, XOUT
–
I
System clock input and output pins
System reset pin
–
B
–
33, 34
35
–
–
–
RESET
TEST
I
Factory test pin input
0 V: normal operation
5 V: factory test mode
23
NOTE: See ‘Pin Circuit Diagrams’ on next two pages for detailed information on circuit types A, B, D-1, E, E-1,and G-3.
1-6
S3C8618/C8615/P8615
PRODUCT OVERVIEW
PIN CIRCUITS
Vdd
Vss
Figure 1-5. Pin Circuit Type A
Vdd
280 K
W
Noise Filter
RESET
Figure 1-6. Pin Circuit Type B (RESET)
Vdd
Data or
Other
function
Output
Output
Disable
Vss
Digital Input
or TTL Input
Figure 1-7. Pin Circuit Type D-1
1-7
PRODUCT OVERVIEW
S3C8618/C8615/P8615
Vdd
Typical
47-K
W
Pull-up
enable
Vdd
Data
Output
Open drain
Output
Disable
Vss
Input
Figure 1-7. Pin Circuit Type E
Vdd
Data
IN/OUT
Open drain
Output
Disable
Vss
Input
Figure 1-8. Pin Circuit Type E-1
1-8
S3C8618/C8615/P8615
PRODUCT OVERVIEW
Output
Data
Input
Vss
Figure 1-9. Pin Circuit Type G-3
1-9
S3C8618/C8615/P8615
ELECTRICAL DATA
16 ELECTRICAL DATA
OVERVIEW
In this section, S3C8618/C8615 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time
— Schmitt trigger characteristics
16-1
ELECTRICAL DATA
S3C8618/C8615/P8615
Table 16-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
VDD
–
– 0.3 to + 7.0
– 0.3 to + 10
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 10
V
Input voltage
V
I
Type C (n-channel, open-drain)
V
1
VI2
VO
All port pins except V
All output pins
I1
Output voltage
V
Output current
High
IOH
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 60
+ 30
Output current
Low
IOL1
mA
IOL2
IOL3
Total pin current except port 3
+ 100
+ 150
Sync-processor I/O pins and IIC-bus
clock and data pins
Operating
temperature
TA
–
– 40 to + 85
– 65 to + 150
°
°
C
Storage
temperature
TSTG
–
C
Table 16-2. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 4.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input High
voltage
VIH1
All input pins except VIH2 and VIH3
0.8 VDD
–
VDD
V
VIH2
VIH3
VIL1
XIN, XOUT
VDD – 0.5
VDD
VDD
TTL input (HsyncI, VsyncI and CsyncI)
2.0
–
Input Low
voltage
All input pins except VIL2
and VIL3
–
–
0.2 VDD
V
V
VIL2
VIL3
XIN, XOUT
0.4
0.8
–
TTL input (HsyncI, VsyncI and CsyncI)
Output High
voltage
VOH1
VDD= 4.5 V to 5.5 V
IOH = – 8 mA Port 1 only
VDD – 1.0
VDD – 1.0
VOH2
VDD = 4.5 V to 5.5 V
IOH = – 2 mA Ports 0, 2, ClampO, H
and VsyncO
VOH3
VDD = 4.5 V to 5.5 V
IOH = – 6 mA, Port 3
VDD – 1.0
16-2
S3C8618/C8615/P8615
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 4.5 V to 5.5 V)
Parameter
Symbol
Conditions
VDD = 4.5 V to 5.5 V
IOL = 8 mA, port 1 only
Min
Typ
Max
Unit
Output Low
voltage
VOL1
–
–
0.4
V
VOL2
IOL = 2 mA
0.4
Port 0, 2, ClampO, HsyncO and
VsyncO
VOL3
ILIH1
IOL = 6 mA
Port 3, SCL and SDA
VIN = VDD
0.4
3
Input High
leakage current
–
–
µA
All input pins except XIN
X
OUT
,
ILIH2
ILIH3
ILIL1
VIN = VDD
XOUT only
–
2.5
–
–
6
–
20
20
VIN = VDD
XIN only
Input Low
leakage current
VIN = 0 V
All input pins except XIN
– 3
µA
µA
X
OUT
,
and RESET
ILIL2
ILIL3
VIN = 0 V; XOUT only
–
– 2.5
–
–
– 6
–
– 20
– 20
3
VIN = 0 V; XIN only
Output High
leakage current
ILOHL
VOUT = VDD
All output pins except port 1
VOUT = 0 V
Output Low
leakage current
ILOL
RL1
–
–
– 3
80
µA
Pull-up resistor
VIN = 0 V;
20
47
kW
VDD = 4.5 V to 5.5 V
Port 3
RL2
VIN = 0 V;
VDD = 4.5 V to 5.5 V
150
–
280
480
RESET only
Supply current
(note)
IDD1
VDD = 4.5 V to 5.5 V
12 MHz CPU clock
15
5
30
10
mA
µA
IDD2
Idle mode;
VDD = 4.5 V to 5.5 V
12 MHz CPU clock
IDD3
Stop mode; VDD = 5.0 V
1
10
NOTE: Supply current does not include drawn internal pull–up resistors and external loads of output.
16-3
ELECTRICAL DATA
S3C8618/C8615/P8615
Table 16-3. Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
VDDDR
Conditions
Stop mode
Min
Typ
Max
Unit
Data retention
supply voltage
2
–
6
V
Data retention
supply current
IDDDR
Stop mode, VDDDR = 2.0 V
–
–
5
µA
NOTES:
1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped.
2. Supply current does not include drawn through internal pull–up resistors and external output current loads.
OSCILLATION
STABILIZATION
RESET
OCCURS
TIME
STOP MODE
NORMAL
OPERATING
MODE
DATA RETENTION MODE
V
DD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
:
t
is the same as 4096 ´ 32 ´ 1 / f
.
NOTE
WAIT
OSC
tWAIT
Figure 16-1. Stop Mode Release Timing When Initiated by a Reset
Table 16-4. Input/Output Capacitance
°
°
(TA = – 40 C to + 85 C, VDD = 0 V)
Parameter
Input
capacitance
Symbol
Conditions
Min
Typ
Max
10
Unit
CIN
f = 1 MHz; unmeasured pins
are connected to VSS
–
–
pF
Output
capacitance
COUT
CIO
I/O capacitance
16-4
S3C8618/C8615/P8615
ELECTRICAL DATA
Table 16-5. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 4.5 V to 5.5V)
Parameter
Noise Filter
Symbol
tNF1H
tNF1L
Conditions
Min
Typ
Max
Unit
P0.2–P0.0, T0CAP and
T1CK (RC delay)
300
–
–
ns
,
tNF2
800
–
–
RESET only (RC delay)
1 tCPU
t
t
NF1H
NF1L
tNF2
0.8 VDD
0.2 V
DD
NOTE
:
The unit t
means one CPU clock period.
CPU
Figure 16-2. Input Timing Measurement Points for P0.0–P0.2, T0CAP and T1CK
16-5
ELECTRICAL DATA
S3C8618/C8615/P8615
Table 16-6. Oscillation Characteristics
°
°
(TA = – 40 C + 85 C)
Oscillator
Clock Circuit
Conditions
Min
Typ
Max
Unit
Main crystal or
ceramic
VDD = 4.5 V to 5.5 V
6
–
12
MHz
C1
XIN
XOUT
C2
External clock
(main)
VDD = 4.5 V to 5.5 V
6
–
12
MHz
XIN
XOUT
NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot
select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.
Table 16-7. Recommended Oscillator Constants
°
°
(TA = – 40 C + 85 C, VDD = 4.5 V to 5.5 V)
Manufacturer
Product Name
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
–
C2
–
MIN
4.5
4.5
4.5
MAX
5.5
FCR8.0MC5 (note)
FCR8.0M5
TDK
On-chip C Leaded Type
Leaded Type
33
–
33
–
5.5
CCR8.0MC5 (note)
5.5
On-chip C SMD Type
NOTE: On-chip C: 30 pF ± 20 % built in.
Table 16-8. Oscillation Stabilization Time
(TA = – 40 C + 85 C, VDD = 4.5 V to 5.5 V)
Oscillator Test Condition
Crystal VDD = 4.5 V to 5.5 V
°
°
Min
Typ
Max
Unit
–
–
20
ms
Ceramic
VDD = 4.5 V to 5.5V
–
–
–
10
External clock
XIN input High and Low level width
(tXH, tXL)
25
500
ns
NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after
a power-on occurs, or when Stop mode is released.
16-6
S3C8618/C8615/P8615
ELECTRICAL DATA
f
1 /
OSC
tXH
tXL
VDD – 0.5 V
0.4 V
XIN
Figure 16-3. Clock Timing Measurement Points for XIN
V
out
V
DD
A : 0.2 V
DD
DD
DD
DD
B : 0.4 V
C : 0.6 V
D : 0.8 V
V
SS
V
in
A
B
C
D
Figure 16-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)
16-7
S3C8618/C8615/P8615
MECHANICAL DATA
17 MECHANICAL DATA
OVERVIEW
The S3C8615 microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP-600) and a
44-QFP package (Samsung part number 44-QFP-1010B).
42
#1
22
21
0 ~ 15 °
42-SDIP-600
39.10 ± 0.2
(1.77)
1.778
0.50 ± 0.1
1.00 ± 0.1
: Dimensions are in millimeters.
NOTE
Figure 17-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)
17-1
MECHANICAL DATA
S3C8618/C8615/P8615
13.20
10.00
± 0.3
± 0.2
0~8°
44-QFP-1010B
0.10 MAX
#44
0.05 MIN
2.05
± 0.10
+0.10
- 0.05
#1
0.80
0.35
2.30 MAX
(1.00)
: Dimensions are in millimeters.
NOTE
Figure 17-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
17-2
S3C8618/C8615/P8615
S3P8615 OTP
18 S3P8615 OTP
OVERVIEW
The S3P8615 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3P8615
microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P8615 is fully compatible with the S3C8618/C8615, both in function and in pin configuration. Because of
its simple programming requirements, the S3P8615 is ideal for use as an evaluation chip for the
S3C8618/C8615.
P3.2
VSS2/VSS2
P3.3
P3.4
P3.5
P3.6
P3.7
RESET/RESET
XOUT
XIN
VSS1/VSS1
P2.7/Csync-I
Hsync-I
Vsync-I (VCLK)
Clamp-O
Hsync-O
Vsync-O
SCL
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3.1
P3.0
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
P0.4/T0CAP
P0.5/T1CK
VDD/VDD
P0.6
1
2
3
4
5
6
7
8
9
S3P8618/8615
42-SDIP
10
11
12
13
14
15
16
17
18
19
20
21
P0.7
SCLK/P1.0
SDAT/P1.1
P1.2
(Top View)
P1.3
P2.0/PWM0
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
SDA
TEST/VPP
P2.6/PWM6
NOTE:
The bolds indicate an OTP pin name.
Figure 18-1. S3P8615 Pin Assignments (42-SDIP Package)
18-1
S3P8615 OTP
S3C8618/C8615/P8615
P2.1/PWM1
P2.2/PWM2
P2.3/PWM3
P2.4/PWM4
P2.5/PWM5
N.C.
P2.6/PWM6
VPP/TEST
SDA
34
35
36
37
38
39
40
41
42
43
44
33
32
31
30
29
28
27
26
25
24
23
P0.2/INT2
P0.1/INT1
P0.0/INT0
P3.0
P3.1
NC
P3.2
VSS2/VSS2
P3.3
P3.4
P3.5
S3C8618/8615
44-QFP
(Top View)
SCL
Vsync-O
Figure 18-2. S3P8615 Pin Assignments (44-QFP Package)
18-2
S3C8618/C8615/P8615
S3P8615 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P1.1
Pin Name
Pin No.
I/O
Function
SDAT
13 (*30)
I/O
Serial DATa Pin (Output when reading, Input
when writing) Input & Push-pull Output Port can
be assigned
P1.0
SCLK
12 (*29)
23 (*41)
I
I
Serial CLocK Pin (Input Only Pin)
TEST
VPP (TEST)
EPROM Cell Writing Power Supply Pin
(Indicates OTP Mode Entering) When writing
12.5 V is applied and when reading 5V is
applied.(Option)
35 (*9)
I
I
Chip Initialization
RESET
RESET
VDD/VSS1/VSS2
VDD/VSS/VSS
9 / 32 / 41
Logic Power Supply Pin. V
should be tied to 5
DD
(*26 / 6 / 15)
V during programming.
NOTE: * means the 44-QFP OTP pin number.
Table 18-2. Comparison of S3P8615 and S3C8618/C8615 Features
Characteristic S3P8615 S3C8618/C8615
16 K byte EPROM 16 K byte mask ROM
Program Memory
Operating Voltage (VDD
)
4.5 V to 5.5 V
4.5 V to 5.5V
OTP Programming Mode
VDD = 5 V, VPP (TEST)=12.5V
Pin Configuration
42-SDIP, 44-QFP
42-SDIP, 44-QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P8615, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 18-3. Operating Mode Selection Criteria
VDD
VPP
(TEST)
REG/
ADDRESS
(A15–A0)
MODE
R/W
MEM
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
18-3
S3P8615 OTP
S3C8618/C8615/P8615
D.C. ELECTRICAL CHARACTERISTICS
Table 18-4. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, V
= 4.5 V to 5.5 V)
DD
Parameter
Input High
leakage current
Symbol
Conditions
Min
Typ
Max
Unit
ILIH1
VIN = VDD
–
–
3
µA
;
All input pins except XIN
X
,
,
OUT
OUT
ILIH2
ILIH3
ILIL1
VIN = VDD
X
OUT only
20
20
;
VIN = V
X
IN only
2.5
–
6
–
DD;
Input Low
leakage current
VIN = 0 V;
– 3
µA
All input pins except XIN
X
and RESET
ILIL2
ILIL3
VIN = 0 V; XOUT only
–
– 2.5
–
–
– 6
–
– 20
– 20
3
VIN = 0 V; XIN only
VOUT = VDD
Output High
ILOH1
µA
leakage current
Output Low
leakage current
ILOL1
IDD1
IDD2
IDD3
VOUT = 0 V
–
–
–
– 3
30
µA
Supply current
Normal operating mode;
12 MHz CPU clock
15
mA
IDLE mode;
12 MHz CPU clock
5
10
Stop mode; VDD = 5.0 V
–
2
1
–
10
6
µA
V
Data retention
supply voltage
VDDDR Stop mode
Data retention
supply voltage
IDDDR Stop mode; VDDDR = 2V
–
–
5
µA
18-4
S3C8618/C8615/P8615
S3P8615 OTP
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 18-3. OTP Programming Algorithm
18-5
相关型号：
S3P863A-QZ
Microcontroller, 8-Bit, OTPROM, SAM8 CPU, 12MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44
SAMSUNG
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