S3P863A [SAMSUNG]
S3C8639/C863A/P863A MICROCONTROLLERS; S3C8639 / C863A / P863A微控制器型号: | S3P863A |
厂家: | SAMSUNG |
描述: | S3C8639/C863A/P863A MICROCONTROLLERS |
文件: | 总23页 (文件大小:166K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
S3C8639/C863A/P863A
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU with a wide
range of integrated peripherals, in various mask-programmable ROM sizes. Analog its major CPU features are:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
The sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned
to specific interrupt levels.
S3C8639/C863A/P863A MICROCONTROLLERS
S3C8639/C863A/P863A single-chip 8-bit
microcontrollers are based on the powerful SAM8
CPU architecture. The internal register file is logically
expanded to increase the on-chip register space.
S3C8639/C863A/P863A contain 32/48 Kbytes of on-
chip program ROM.
— One 12-bit counter with selectable clock sources,
including Hsync or Csync input
— PWM block with seven 8-bit PWM circuits
— Sync processor block (for Vsync and Hsync I/O,
Csync input, and Clamp signal output)
— DDC Multi-master and slave-only IIC-Bus
— 4-channel A/D converter (8-bit resolution)
In line with Samsung's modular design approach, the
following peripherals are integrated with the SAM8
core:
S3C8639/C863A/P863A are a versatile
— Four programmable I/O ports (total 27 pins)
microcontrollers which are ideal for use in multi-sync
monitors or in general-purpose applications that
require sophisticated timer/counter, PWM, sync
signal processing, A/D converter, and multi-master
IIC-bus support with DDC. They are available in a
42-pin SDIP or a 44-pin QFP package.
— One 8-bit basic timer for oscillation stabilization
and watchdog functions
— One 8-bit general-purpose timer/counter with
selectable clock sources
— One interval timer
OTP
S3C8639/C863A microcontrollers are also available in OTP (One Time Programmable) version named,
S3P863A. S3P863A microcontroller has an on-chip 48-Kbyte one-time-programmable EPROM instead of
masked ROM. S3P863A is comparable to S3C8639/C863A, both in function and pin configuration except its
ROM size.
1-1
PRODUCT OVERVIEW
S3C8639/C863A/P863A
FEATURES
CPU
Low Voltage Reset (LVR)
LVR level is 2.4 V ± 200 mV
•
SAM88RC CPU core
•
Memory
Pulse Width Modulator (PWM)
8-bit PWM: 7-CH
(6-bit basic frame with 2-bit extension)
•
•
S3C8639: 32-Kbyte internal program memory
•
(ROM)
S3C863A: 48-Kbyte internal program memory
(ROM)
Sync-Processor Block
•
Vsync-I, Hsync-I, Csync-I input and Vsync-O,
Hsync-O, Clamp-O output pins
S3C8639: 784-byte general-purpose
register area
S3C863A: 1040-byte general-purpose
register area
•
•
•
•
Programmable Pseudo sync signal generation
Auto SOG detection
Instruction Set
Auto H-/V-sync polarity detection
Composite sync detection
•
•
78 instructions
IDLE and STOP instructions added for
power-down modes
DDC Multi-Master IIC-Bus 1-Ch
•
•
Serial Peripheral Interface
Instruction Execution Time
Minimum 333 ns (with 12 MHz CPU clock)
Support for Display Data Channel
(DDC1/DDC2B/DDC2Bi/DDC2B+)
•
Interrupts
Slave Only IIC-Bus 1-Ch
Serial Peripheral Interface
•
•
•
Ten interrupt sources/vectors
•
Eight interrupt level
Fast interrupt feature
A/D Converter
•
4-channel; 8-bit resolution
General I/O
Oscillator Frequency
•
Four I/O Ports (total 27pins)
•
•
8 MHz to 12 MHz crystal operation
Internal Max. 12 MHz CPU clock
8-Bit Basic Timer
•
Programmable timer for oscillation stabilization
interval control or watchdog timer function
Operating Temperature Range
– 40 °C to + 85 °C
•
•
Three selective internal clock frequencies
Operating Voltage Range
3.0 V to 5.5 V
Timer/Counters
•
•
•
•
One 8-bit Timer/Counter with several clock
sources (Capture mode)
Package Types
42-pin SDIP, 44-pin QFP
One 12-bit Counter with H-/C-sync and several
clock sources
•
One Interval Timer
1-2
S3C8639/C863A/P863A
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0-P0.7/INT0-INT2
Port 0
P2.0-P2.7
Port 2
V
V
TEST
DD1, VDD2
SS1, VSS2
RESET
INT0-INT2
Main
Osc
X
OUT
IN
X
Port 1
P1.0-P1.2
I/O Port and Interrupt
PWM0
Control
8-Bit
PWM
(7-Ch)
Port 3
ADC
PWM6
P3.0-P3.7
AD0-AD3
Vsync-I
Hsync-I
Csync-I
Vsync-O
Hsync-O
Clamp-O
SAM8 CPU
Sync-
Processor
32/48-
Kbyte
ROM
784/1040-
Byte
Register File
SCL1
SDA1
8-Bit
Counter
(Timer M0)
Slave
Only
IIC-Bus
TM0CAP
* S3C8639
- 32 Kbyte ROM
- 784 Byte RAM
* S3C863A
- 48 Kbyte ROM
- 1040 Byte RAM
12-Bit
Counter
(Timer M1)
Interval
Timer
(Timer M2)
Multi-master IIC-Bus
and DDC1/2B/2Bi/2B+
SCL0
SDA0
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
S3C8639/C863A/P863A
PIN ASSIGNMENTS
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0/AD0
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
1
2
3
4
5
6
7
8
P0.4/TM0CAP
P0.5
P0.6
P0.7
P1.0/SDA1
P1.1/SCL1
V
V
DD2
9
S3C8639
/C863A
(42-SDIP)
SS2
10
11
12
13
14
15
16
17
18
19
20
21
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
V
DD1
SS1
OUT
IN
V
X
X
TEST (GND)
SDA0
Clamp-O
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
SCL0
RESET
P1.2
P2.0/PWM0
P2.1/PWM1
NOTE: The TEST pin must connect to V SS (GND) in the normal operation mode.
Figure 1-2. S3C8639/C863A 42-SDIP Pin Assignment
1-4
S3C8639/C863A/P863A
PRODUCT OVERVIEW
P0.5
P0.6
P0.7
P3.2/AD2
P3.1/AD1
P3.0/AD0
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
DD2
V
P1.0/SDA1
P1.1/SCL1
S3C8639
/C863A
44-QFP
VSS2
DD1
V
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
VSS1
OUT
X
(Top View)
IN
X
TEST (GND)
SDA0
9
10
11
Clamp-O
SS
NOTE: The TEST pin must connect to V
(GND) in the normal operation mode.
Figure 1-3. S3C8639/C863A 44-QFP Pin Assignment
1-5
PRODUCT OVERVIEW
S3C8639/C863A/P863A
PIN DESCRIPTIONS
Table 1-1. S3C8639/C863A Pin Descriptions
Pin
Pin
Pin
Circuit
SDIP Pin
Shared
Names
Type
Description
Type
Numbers Functions
P0.0
I/O
General-purpose, 8-bit I/O port. Shared
functions include three external interrupt inputs
and I/O for timer M0. Selective configuration of
port 0 pins to input or output mode is
supported.
D-1
D-1
D-1
D-1
D-1
D-1
D-1
D-1
1
2
3
4
5
6
7
8
INT0
INT1
INT2
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
TM0CAP
P1.0
P1.1
P1.2
I/O
I/O
General-purpose, 8-bit I/O port. Selective
configuration is available for port 1 pins to
input, push-pull output, n-channel open-drain
mode, or IIC-bus clock and data I/O.
E-1
E-1
E-1
9
10
19
SDA1
SCL1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
General-purpose, 8-bit I/O port Selective
configuration of port 2 pins to input or output
mode is supported. The port 2 pin circuits are
designed to push-pull PWM output and Csync
(SOG) signal input.
D-1
D-1
D-1
D-1
E-1
E-1
E-1
D-1
20
21
22
23
24
25
26
32
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
Csync-I
P3.0–P3.3
P3.4–P3.7
I/O
General-purpose, 8-bit I/O port Selective
configuration port 3 pins to input or output
mode is supported. Multiplexed for alternative
use as A/D converter inputs AD0–AD3.
E-1
E
35–38
39–42
AD0–AD3
Hsync-I
Vsync-I
Clamp-O
Hsync-O
Vsync-O
SDA0
I
I
O
O
O
The pins are sync processor signal I/O and IIC-
bus clock and data I/O.
A-3
A-3
A
A
A
31
30
27
28
29
16
17
–
I/O
I/O
G-3
G-3
SCL0
VDD1, VSS1
VDD2, VSS2
,
–
Power pins
–
–
11, 12
34, 33
–
–
XIN, XOUT
–
System clock I/O pins
System RESET pin
–
14, 13
I
I
B
–
18
15
–
–
RESET
TEST
Factory test pin input
0 V: Normal operation, 5 V: Factory test mode
1-6
S3C8639/C863A/P863A
PRODUCT OVERVIEW
PIN CIRCUITS DIAGRAM
DD
V
VDD
Input
Output
Data
Output
300 k
W
Typical
SS
V
VSS
VSS
Figure 1-5. Pin Circuit Type A-3
Figure 1-4. Pin Circuit Type A
DD
V
Data or
Other
Function
Output
VDD
Output
280 k
W
Disable
Noise
Filter
VSS
RESET
Digital Input,
TTL Input
NOTE:
The noise filter must be built in the
external interrupts.
Figure 1-7. Pin Circuit Type D-1
Figure 1-6. Pin Circuit Type B (RESET)
1-7
PRODUCT OVERVIEW
S3C8639/C863A/P863A
VDD
Typical
47 k
VDD
W
Pull-up
Enable
Data
VDD
Output
Open
Drain
Data
Output
Output
Disable
Open
Drain
V
SS
Digital Input
or ADC Input
Output
Disable
VSS
Input
Figure 1-8. Pin Circuit Type E
Figure 1-9. Pin Circuit Type E-1
Output
Data
Input
V
SS
Figure 1-10. Pin Circuit Type G-3
1-8
S3C8639/C863A/P863A
ELECTRICAL DATA
19 ELECTRICAL DATA
OVERVIEW
In this section, S3C8639/C863A electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— Data retention supply voltage in stop mode
— Stop mode release timing when initiated by a reset
— I/O capacitance
— A/D Converter electrical characteristics
— A.C. electrical characteristics
— Input timing measurement points for P0.0–P0.2 and TM0CAP
— Oscillation characteristics
— Oscillation stabilization time
— Clock timing measurement points for XIN
— Schmitt trigger characteristics
— Power-on reset circuit characteristics
19-1
ELECTRICAL DATA
S3C8639/C863A/P863A
Table 19-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Supply voltage
Input voltage
Symbol
VDD
VI1
Conditions
Rating
Unit
–
– 0.3 to + 6.5
– 0.3 to + 7.0
V
Type G-3 (n-channel open drain)
VI2
All port pins except V
All output pins
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 10
I1
VO
Output voltage
IOH
Output current
High
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 60
+ 30
IOL
Output current
Low
Total pin current except port 3
+ 100
+ 150
Sync-processor I/O pins and IIC-bus
clock and data pins
°
C
TA
Operating
temperature
–
– 40 to + 85
– 65 to + 150
TSTG
Storage
–
temperature
Table 19-2. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Input High
voltage
Symbol
VIH1
VIH2
VIH3
VIH4
VIL1
Conditions
All input pins except VIH2, VIH3 and VIH4
XIN
Min
Typ
Max
Unit
0.8 VDD
VDD–0.5
2.0
VDD
VDD
–
V
VDD
TTL input (Hsync-I, Vsync-I, and Csync-I)
SCL0/SDA0, SCL1/SDA1
All input pins except VIL2 and VIL3
XIN
0.7VDD
–
VDD
0.2 VDD
0.4
Input Low
voltage
VIL2
VIL3
TTL input (Hsync-I, Vsync-I, and Csync-I)
SCL0/SDA0, SCL1/SDA1
0.8
VIL4
0.3VDD
–
VOH1
VDD – 1.0
Output High
voltage
VDD = 5 V ± 10%; IOH = – 15 mA;
Port 3.6–3.7
VOH2
VOH3
VOH4
VDD = 5 V ± 10%; IOH = – 4 mA;
Port 1.2, Port 3.0–3.5
VDD = 5 V ± 10%; IOH = – 2 mA;
Port 0, 2, Clamp-O, H, and Vsync-O
VDD = 5 V ± 10%; IOH = – 6 mA;
Port 1.0–P1.1, SCL0 and SDA0
19-2
S3C8639/C863A/P863A
ELECTRICAL DATA
Table 19-2. D.C. Electrical Characteristics (Continued)
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOL1
Output Low
voltage
–
–
0.4
V
VDD = 5 V ± 10%; IOL = 15 mA
Port 3.6–3.7
VOL2
VOL3
VOL4
ILIH1
0.4
0.4
0.6
3
VDD = 5 V ± 10%; IOL = 4 mA
Port 3.0–3.5 and Port 1.2
VDD = 5 V ± 10%; IOL = 2 mA
Port 0, 2, Clamp-O, H, and Vsync-O
VDD = 5 V ± 10%; IOL = 6 mA
Port 1.0–1.1; SCL0 and SDA0
VIN = VDD
Input High
–
–
µA
leakage current
All input pins except XIN
X
OUT
,
ILIH2
ILIH3
ILIL1
VIN = VDD XOUT only
;
–
2.5
–
–
6
–
20
20
VIN = VDD
XIN only
;
VIN = 0 V; All input pins except XIN
Input Low
– 3
,
leakage current
RESET , HsyncI & VsyncI
,
XOUT
ILIL2
ILIL3
VIN = 0 V; XOUT only
VIN = 0 V; XIN only
VOUT = VDD
–
– 2.5
–
–
– 6
–
– 20
– 20
3
ILOH1
Output High
leakage current
ILOL1
RU1
VOUT = 0 V
Output Low
leakage current
–
–
– 3
80
Pull-up resistor
20
47
VIN = 0 V; VDD = 5 V ± 10%
kW
Ports 3.7–3.4
RU2
RD
150
150
–
280
300
10
480
500
20
VIN = 0 V; VDD = 5 V ± 10%
RESET only
Pull-down
resistor
VIN = 0 V; VDD = 5 V ± 10%
HsyncI & VsyncI
IDD1
Supply current
(note)
mA
µA
VDD = 5 V ± 10%
Operation mode; 12 MHz crystal
C1 = C2 = 22pF
IDD2
4
8
VDD = 5 V ± 10%
Idle mode; 12 MHz crystal
C1 = C2 = 22pF
IDD3
100
150
VDD = 5 V ± 10%
Stop mode
NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.
19-3
ELECTRICAL DATA
S3C8639/C863A/P863A
Table 19-3. Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 40 C to + 85 C)
Parameter
Symbol
VDDDR
Conditions
Stop mode
Min
Typ
Max
Unit
Data retention
supply voltage
2
–
5.5
V
IDDDR
Stop mode, VDDDR = 2.0 V
Data retention
supply current
–
–
5
µA
NOTES:
1. During the oscillator stabilization wait time (t
), all CPU operations must be stopped.
WAIT
2. Supply current does not include drawn through internal pull–up resistors and external output current loads.
RESET
Oscillation
occurs
Stabilzation
Time
Stop Mode
Data Retention Mode
V
DD
Normal
Operating
Mode
VDDDR
Execution of
STOP Instrction
RESET
t
WAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/f OSC.
Figure 19-1. Stop Mode Release Timing When Initiated by a Reset
Table 19-4. Input/Output Capacitance
°
°
(TA = –40 C to + 85 C, VDD = 0 V)
Parameter
Input
Symbol
Conditions
Min
Typ
Max
Unit
CIN
f = 1 MHz; unmeasured pins
are connected to VSS
–
–
10
pF
capacitance
COUT
CIO
Output
capacitance
I/O capacitance
19-4
S3C8639/C863A/P863A
ELECTRICAL DATA
Table 19-5. A/D Converter Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V, VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
Min
–
Typ
8
Max
–
Unit
bit
VDD = 5 V
Total accuracy
–
–
LSB
± 2
Conversion time = 5 ms
AVREF = 5 V
Integral linearity error
ILE
–
–
± 1
± 1
AVSS = 0 V
Differential linearity error
DLE
Offset error of top
Offset error of bottom
Conversion time (1)
EOT
EOB
tCON
± 1
± 0.5
–
± 2
± 2
170
8 bit conversion
(3) n=1,4,8,16
20
ms
40 x n/fOSC
,
V
AVSS
2
AVREF
Analog input voltage
Analog input impedance
Analog reference voltage
Analog ground
–
–
–
–
–
1000
–
V
IAN
R
–
VDD
VSS + 0.3
10
MW
V
AN
AV
2.5
VSS
–
REF
AV
SS
–
V
I
AVREF = VDD = 5V
AVREF = VDD = 5V
AVREF = VDD = 3V
Analog input current
–
mA
mA
mA
nA
ADIN
Analog block Current (2)
I
–
1
3
ADC
0.5
100
1.5
AVREF = VDD = 5V
500
When power down mode
NOTES:
1. "Conversion time" is the time required from the moment a conversion operation starts until it ends.
2.
I
is an operating current during the A/D conversion.
ADC
OSC
3.
f
is the main oscillator clock.
19-5
ELECTRICAL DATA
S3C8639/C863A/P863A
Table 19-6. A.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5V)
Parameter
Noise Filter
Symbol
Conditions
Min
Typ
Max
Unit
tNF1H
tNF1L
INT0–2 and TM0CAP (RC
delay)
300
–
–
ns
tNF2
RESET only (RC delay)
1000
–
–
t
NF1L
NF2
tNF1H
t
0.8 VDD
0.2 VDD
Figure 19-2. Input Timing Measurement Points for P0.0–P0.2 and TM0CAP
19-6
S3C8639/C863A/P863A
ELECTRICAL DATA
Table 19-7. Oscillation Characteristics
°
°
(TA = – 40 C + 85 C)
Oscillator
Clock Circuit
Conditions
Min
Typ
Max
Unit
VDD = 3.0 V to 5.5 V
Main crystal or
ceramic
8
–
12
MHz
C1
XIN
XOUT
C2
VDD = 3.0 V to 5.5 V
External clock
(main)
8
–
12
MHz
XIN
XOUT
NOTE: The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannot
select a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.
Table 19-8. Oscillation Stabilization Time
°
°
(TA = – 40 C + 85 C, VDD = 3.0 V to 5.5 V)
Oscillator Test Condition
VDD = 3.0 V to 5.5 V
Min
Typ
Max
Unit
Crystal
–
–
20
ms
VDD = 3.0 V to 5.5V
Ceramic
–
–
–
10
XIN input high and low level width
External clock
25
500
ns
(tXH, tXL
)
NOTE: Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a
power-on occurs, or when Stop mode is released.
1/fx
t
XL
tXH
XIN
VDD - 0.5 V
0.4 V
Figure 19-3. Clock Timing Measurement Points for XIN
19-7
ELECTRICAL DATA
S3C8639/C863A/P863A
V
OUT
V
DD
A = 0.2 VDD
B = 0.4 VDD
C = 0.6 VDD
D = 0.8 VDD
VSS
A
B
C
D
VIN
Figure 19-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)
Table 19-9. Power-on Reset Circuit Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VODLVD
Power-on reset release
voltage
2.7
–
5.5
V
VLVD
tr
Power-on reset detection
voltage
2.2
10
10
2.4
–
2.6
(1)
V
Power supply voltage
rise time
us
toff
Power supply voltage off
time
–
–
ms
mA
mA
IDDPR
Power-on reset circuit
consumption current (2)
100
60
150
VDD = 5 V ± 10%
VDD = 3 V
100
NOTES:
16
1.
2
/f
(= 5.46 ms at f /12MHz)
OSC
OSC
2. Current contained when power-on reset circuit is provided internally.
19-8
S3C8639/C863A/P863A
ELECTRICAL DATA
V
DD
VDDLVD
V
LVD
t
off
t
r
Figure 19-5. Power-on Reset Timing
19-9
S3C8639/C863A/P863A
MECHANICAL DATA
20 MECHANICAL DATA
OVERVIEW
The S3C8639/C863A microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP-
600) and a 44-QFP package (Samsung part number 44-QFP-1010B).
#42
#22
0-15
42-SDIP-600
#1
#21
39.50 MAX
39.10 ± 0.2
0.50
±
0.1
1.778
(1.77)
1.00 0.1
±
NOTE: Dimensions are in millimeters.
Figure 20-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)
20-1
MECHANICAL DATA
S3C8639/C863A/P863A
13.20 ± 0.3
10.00 ± 0.2
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
44-QFP-1010B
#44
+ 0.10
0.35 - 0.05
#1
0.05 MIN
2.05 ± 0.10
2.30 MAX
0.80
(1.00)
NOTE: Dimensions are in millimeters.
Figure 20-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
20-2
S3C8639/C863A/P863A
S3P863A OTP
21 S3P863A OTP
OVERVIEW
The S3P863A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C8639/C863A microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P863A is fully compatible with the S3C8639/C863A, both in function and in pin configuration. Because of
its simple programming requirements, the S3P863A is ideal for use as an evaluation chip for the
S3C8639/C863A.
P3.7
P3.6
P3.5
P3.4
P3.3/AD3
P3.2/AD2
P3.1/AD1
P3.0/AD0
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3
1
2
3
4
5
6
7
8
P0.4/TM0CAP
P0.5
P0.6
P0.7
SDAT/P1.0/SDA1
SCLK/P1.1/SCL1
V
V
DD2
9
SS2
10
11
12
13
14
15
16
17
18
19
20
21
S3P863A
42-SDIP
(Top View)
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
V
DD1
V
SS
X
OUT
X
IN
V
/TEST (GND)
PP
Clamp-O
SDA0
SCL0
RESET/RESET
P2.6/PWM6
P2.5/PWM5
P2.4/PWM4
P2.3/PWM3
P2.2/PWM2
P1.2
P2.0/PWM0
P2.1/PWM1
NOTE:
The bolds indicate an OTP pin name.
Figure 21-1. S3P863A Pin Assignments (42-SDIP Package)
21-1
S3P863A OTP
S3C8639/C863A/P863A
P3.2/AD2
P3.1/AD1
P3.0/AD0
33
32
31
30
29
28
27
26
25
24
23
P0.5
P0.6
P0.7
1
2
3
4
5
6
7
8
V
V
DD2
SDAT/P1.0/SDA1
SCLK/P1.1/SCL1
S3P863A
44-QFP
(Top View)
SS2
P2.7/Csync-I (SOG)
Hsync-I
Vsync-I
Vsync-O
Hsync-O
V
DD1
V
SS1
XOUT
X
9
10
11
IN
V
PP/TEST (GND)
Clamp-O
SDA0
NOTE:
The bolds indicate an OTP pin name.
Figure 21-2. S3P863A Pin Assignments (44-QFP Package)
21-2
S3C8639/C863A/P863A
Main Chip
S3P863A OTP
Table 21-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P1.0
SDAT
9 (4)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a
Input/push-pull output port.
P1.1
SCLK
10 (5)
I
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
15 (10)
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
18 (13)
I
I
Chip Initialization
RESET
RESET
VDD1/VSS1
VDD1/VSS1
Logic power supply pin. VDD should be tied to +5 V
during programming.
11/12 (6/7)
NOTE: Parentheses indicate 44-QFP OTP pin number.
Table 21-2. Comparison of S3P863A and S3C8639/C863A Features
Characteristic S3P863A S3C8639/C863A
48-Kbyte EPROM
Program Memory
32/48-Kbyte mask ROM
3.0 V to 5.5V
Operating Voltage (VDD
)
3.0 V to 5.5 V
VDD = 5 V, VPP (TEST)=12.5V
OTP Programming Mode
Pin Configuration
42SDIP, 44QFP
42SDIP, 44QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP(TEST) pin of the S3P863A, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 21-3 below.
Table 21-3. Operating Mode Selection Criteria
VDD
VPP (TEST) REG/MEM Address (A15–A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
21-3
S3P863A OTP
S3C8639/C863A/P863A
D.C. ELECTRICAL CHARACTERISTICS
Table 21-4. D.C. Electrical Characteristics
(TA = – 40 C to + 85 C, VDD = 3.0 V to 5.5 V)
°
°
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
ILIH1
VIN = VDD
All input pins except XIN
Input High
leakage current
–
–
3
µA
X
,
OUT
ILIH2
ILIH3
ILIL1
VIN = VDD XOUT only
;
–
2.5
–
–
6
–
20
20
VIN = VDD
XIN only
;
VIN = 0 V; All input pins except XIN
Input Low
– 3
,
leakage current
RESET , Hsync-I and Vsync-I
,
XOUT
ILIL2
ILIL3
VIN = 0 V; XOUT only
VIN = 0 V; XIN only
VOUT = VDD
–
– 2.5
–
–
– 6
–
– 20
– 20
3
ILOH1
Output High
leakage current
ILOL1
RU1
VOUT = 0 V
Output Low
leakage current
–
–
– 3
80
Pull-up resistor
20
47
VIN = 0 V; VDD = 5 V ± 10%
kW
Port 3.7–3.4
RU2
RD
150
150
–
280
300
10
480
500
20
VIN = 0 V; VDD = 5 V ± 10%
RESET only
Pull-down
resistor
VIN = 0 V; VDD = 5 V ± 10%
Hsync-I and Vsync-I
IDD1
Supply current
(note)
mA
µA
VDD = 5 V ± 10%
Operation mode; 12 MHz crystal
C1 = C2 = 22pF
IDD2
4
8
VDD = 5 V ± 10%
Idle mode; 12 MHz crystal
C1 = C2 = 22pF
IDD3
100
150
VDD = 5 V ± 10%
Stop mode
NOTE: Supply current does not include drawn internal pull-up/pull-down resistors and external loads of output.
21-4
相关型号:
S3P863A-QZ
Microcontroller, 8-Bit, OTPROM, SAM8 CPU, 12MHz, CMOS, PQFP44, 10 X 10 MM, QFP-44
SAMSUNG
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