S524A40X11-RC [SAMSUNG]
EEPROM, 128X8, Serial, CMOS, PDSO8, TSSOP-8;
| 型号： | S524A40X11-RC |
| 厂家： | 
SAMSUNG |
| 描述： | EEPROM, 128X8, Serial, CMOS, PDSO8, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 双倍数据速率 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S524A40X11/40X21/
40X41/60X81/60X51
1K/2K/4K/8K/16K-bit
Serial EEPROM for Low Power
Data Sheet
OVERVIEW
The S524A40X11/40X21/40X41/60X81/60X51 serial EEPROM has a 1,024/2,048/4,096/8,192/16,384-bit
capacity, supporting the standard I2C™-bus serial interface. It is fabricated using Samsung’s most advanced
CMOS technology. It has been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its
major feature is a hardware-based write protection circuit for the entire memory area. Hardware-based write
protection is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to
16 bytes of data into the EEPROM in a single write operation. Another significant feature of the
S524A40X11/40X21/40X41/60X81/60X51 is its support for fast mode and standard mode.
FEATURES
I2C-Bus Interface
Operating Characteristics
·
·
Two-wire serial interface
·
Operating voltage
— 1.8 V to 5.5 V
Automatic word address increment
EEPROM
·
Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 mA at 5.5 V
— Maximum stand-by current: < 1 mA at 5.5 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
·
1K/2K/4K/8K/16K-bit
(128/256/512/1,024/2,048-byte) storage area
·
·
16-byte page buffer
Typical 3 ms write cycle time with
auto-erase function
·
·
·
·
·
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
·
·
1,000,000 erase/write cycles
100 years data retention
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 500 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
·
1-1
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
DATA SHEET
SDA
WP
Start/Stop
Logic
HV Generation
Timing Control
Control Logic
EEPROM
Cell Array
128 x 8 bits
256 x 8 bits
512 x 8 bits
1024 x 8 bits
2048 x 8 bits
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
A0
A1
A2
Column Decoder
Data Register
DOUT and ACK
Figure 1-1. S524A40X11/40X21/40X41/60X81/60X51 Block Diagram
1-2
DATA SHEET
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
VCC WP SCL SDA
S524A40X11/40X21/
40X41/60X81/60X51
A0
A1
A2
VSS
NOTE:
The S524A40X11/40X21/40X41/60X81/60X51
is available in 8-pin DIP, SOP, and TSSOP package.
Figure 1-2. Pin Assignment Diagram
Table 1-1. S524A40X11/40X21/40X41/60X81/60X51 Pin Descriptions
Name
Type
Description
Circuit
Type
A0, A1, A2
Input
Input pins for device address selection. To configure a device address,
these pins should be connected to the VCC or VSS of the device.
1
These pins are internally pulled down to VSS
.
VSS
–
Ground pin.
–
3
SDA
I/O
Bi-directional data pin for the I2C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor must
be connected to VCC. Typical values for this pull-up resistor are 4.7 kW
(100 kHz) and 1 kW (400 kHz).
SCL
WP
Input
Input
Schmitt trigger input pin for serial clock input.
Input pin for hardware write protection control. If you tie this pin to VCC,
2
1
the write function is disabled to protect previously written data in the
entire memory; if you tie it to VSS, the write function is enabled.
This pin is internally pulled down to VSS
.
VCC
–
Single power supply.
–
NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.
1-3
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
DATA SHEET
A0, A1,
A2, WP
Noise
Filter
SCL
Figure 1-3. Pin Circuit Type 1
Figure 1-4. Pin Circuit Type 2
SDA
Data Out
Data In
VSS
Noise
Filter
Figure 1-5. Pin Circuit Type 3
1-4
DATA SHEET
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The S524A40X11/40X21/40X41/60X81/60X51 supports the I2C-bus serial interface data transmission protocol.
The two-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines
must be connected to VCC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524A40X11/40X21 (four
S524A40X41, two for S524A60X81, one for S524A60X51) devices can be connected to the same I2C-bus as
slaves (see Figure 1-6). Both the master and slaves can operate as transmitter or receiver, but the master device
determines which bus operating mode would be active.
VCC
VCC
R
R
SDA
SCL
Slave 1
S524A40X21
Slave 2
S524A40X21
Slave 3
S524A40X21
Slave 8
S524A40X21
Bus Master
(Transmitter/
Receiver)
Tx/Rx
A0 A1 A2
Tx/Rx
A0 A1 A2
Tx/Rx
A0 A1 A2
Tx/Rx
A0 A1 A2
MCU
To VCC or VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
NOTES:
1. The A0 does not affect the device address of the S524A40X41.
2. The A0, A1 do not affect the device address of the S524A60X81.
3. The A0, A1, and A2 do not affect the device address of the S524A60X51.
Figure 1-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus)
1-5
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
DATA SHEET
I2C-BUS PROTOCOLS
Here are several rules for I2C-bus transfers:
— A new data transfer can be initiated only when the bus is currently not busy.
— MSB is always transferred first in transmitting data.
— During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High.
The I2C-bus interface supports the following communication protocols:
·
·
Bus not busy: The SDA and the SCL lines remain High level when the bus is not active.
Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High
level. All bus commands must be preceded by a start condition.
·
Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains
High level. All bus operations must be completed by a stop condition (see Figure 1-7).
SCL
SDA
Start
Data or
Data
Stop
Condition
ACK Valid Change
Condition
Figure 1-7. Data Transmission Sequence
·
·
Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration
of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock
pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total
number of bytes that can be transferred in one operation is theoretically unlimited.
ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter
(the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master
generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of
data (see Figure 1-8). But the slave does not send an ACK if an internal write cycle is still in progress.
In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors
the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to
transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition
to be issued by the master before returning to its stand-by mode.
1-6
DATA SHEET
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
Master
SCL Line
Bit 1
Bit 9
Data from
Transmitter
ACK from
Receiver
ACK
Figure 1-8. Acknowledge Response From Receiver
·
Slave Address: After the master initiates a Start condition, it must output the address of the device to be
accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier
for the S524A40X11/40X21/40X41/60X81/60X51 is “1010B”. The next three bits comprise the address of a
specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing
scheme, you can cascade up to eight S524A40X11/40X21 or four S524A40X41 or two S524A60X81 or one
S524A60X51 on the bus (see Table 1-2 below). The b1 for S524A40X41 or the b1, b2 for S524A60X81 or the
b1, b2, b3 for S524A60X51 are used by the master to select which of the blocks of internal memory (1 block
= 256 words) are to be accessed. The bits are in effect the most significant bits of the word address.
·
Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the
R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed.
Table 1-2. Slave Device Addressing
Device
Device Identifier
Device Address
R/W Bit
b0
b7 b6 b5 b4
b3
b2
b1
S524A40X11/40X2
1
1
0
1
0
A2
A1
A0
R/W
S524A40X41
S524A60X81
S524A60X51
1
1
1
0
0
0
1
1
1
0
0
0
A2
A2
B2
A1
B1
B1
B0
B0
B0
R/W
R/W
R/W
NOTE: The B2, B1, B0 correspond to the MSB of the memory array address word.
1-7
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
BYTE WRITE OPERATION
DATA SHEET
In a complete byte write operation, the master transmits the slave address, word address, and one data byte to
the S524A40X11/40X21/40X41/60X81/60X51 slave device (see Figure 1-9).
Start Slave Address
Word Address
Data
Stop
A
C
K
A
C
K
A
C
K
Figure 1-9. Byte Write Operation
Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and an
R/W bit set to “0” onto the bus. Then the addressed S524A40X11/40X21/40X41/60X81/60X51 generates an ACK
and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8-bit address
is written into the word address pointer of the S524A40X11/40X21/40X41/60X81/60X51.
When the S524A40X11/40X21/40X41/60X81/60X51 receives the word address, it responds by issuing an ACK
and then waits for the next 8-bit data. When it receives the data byte, the
S524A40X11/40X21/40X41/60X81/60X51 again responds with an ACK. The master terminates the transfer by
generating a Stop condition, at which time the S524A40X11/40X21/40X41/60X81/60X51 begins the internal write
cycle.
While the internal write cycle is in progress, all S524A40X11/40X21/40X41/60X81/60X51 inputs are disabled and
the S524A40X11/40X21/40X41/60X81/60X51 does not respond to additional requests from the master.
1-8
DATA SHEET
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
PAGE WRITE OPERATION
The S524A40X11/40X21/40X41/60X81/60X51 can also perform 16-byte page write operation. A page write
operation is initiated in the same way as a byte write operation. However, instead of finishing the write operation
after the first data byte is transferred, the master can transmit up to 15 additional bytes. The
S524A40X11/40X21/40X41/60X81/60X51 responds with an ACK each time it receives a complete byte of data
(see Figure 1-10).
Start Slave Address
Word Address (n)
Data (n)
Data (
£
n + 15)
Stop
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 1-10. Page Write Operation
The S524A40X11/40X21/40X41/60X81/60X51 automatically increments the word address pointer each time it
receives a complete data byte. When one byte has been received, the internal word address pointer increments
to the next address and the next data byte can be received.
If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation,
the S524A40X11/40X21/40X41/60X81/60X51 word address pointer value “rolls over” and the previously received
data is overwritten. If the master transmits less than 16 bytes and generates a stop condition, the
S524A40X11/40X21/40X41/60X81/60X51 writes the received data to the corresponding EEPROM address.
During a page write operation, all inputs are disabled and there is no response to additional requests from the
master until the internal write cycle is completed.
1-9
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
POLLING FOR AN ACK SIGNAL
DATA SHEET
When the master issues a stop condition to initiate a write cycle, the S524A40X11/40X21/40X41/60X81/60X51
starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device.
To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address.
As long as the S524A40X11/40X21/40X41/60X81/60X51 remains busy with the write operation, no ACK is
returned. When the S524A40X11/40X21/40X41/60X81/60X51 completes the write operation, it returns an ACK
and the master can then proceed with the next read or write operation (see Figure 1-11).
Send Write
Command
Send Stop Condition to
Initiate Write Cycle
Send Start
Condition
Send Slave Address
with R/
W bit = "0"
No
ACK = "0" ?
Yes
Start Next
Operation
Figure 1-11. Master Polling for an ACK Signal from a Slave Device
1-10
DATA SHEET
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the S524A40X11/40X21/40X41/60X81/60X51. This method
of write protection is controlled by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored.
The S524A40X11/40X21/40X41/60X81/60X51 will acknowledge slave and word address, but it will not generate
an acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop
condition is generated. By connecting the WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to prevent data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the S524A40X11/40X21/40X41/60X81/60X51 receives a slave address with the R/W bit set to “1”, it issues
an ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a
Stop condition. In this way, the S524A40X11/40X21/40X41/60X81/60X51 effectively stops the transmission (see
Figure 1-12).
Start Slave Address
Data
Stop
A
C
K
N
O
A
C
K
Figure 1-12. Current Address Byte Read Operation
1-11
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
RANDOM ADDRESS BYTE READ OPERATION
DATA SHEET
Using random read operations, the master can access any memory location at any time. Before it issues the
slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. This operation
is performed in the following steps:
1. The master first issues a Start condition, the slave address, and the word address to be read. (This step sets
the internal word address pointer of the S524A40X11/40X21/40X41/60X81/60X51 to the desired address.)
2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed
by another slave address, with the R/W bit set to “1”.
3. The S524A40X11/40X21/40X41/60X81/60X51 then sends an ACK and the 8-bit data stored at the desired
address.
4. At this point, the master does not acknowledge the transmission, but generates a stop condition instead.
5. In response, the S524A40X11/40X21/40X41/60X81/60X51 stops transmitting data and reverts to its stand-by
mode (see Figure 1-13).
Start Slave Address
Word Address
Start Slave Address
Data (n)
Stop
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 1-13. Random Address Byte Read Operation
1-12
DATA SHEET
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
SEQUENTIAL READ OPERATION
Sequential read operations can be performed in two ways: as a series of current address reads or as random
address reads. The first data is sent in the same way as the previous read mode used on the bus. The next time,
however, the master responds with an ACK, indicating that it requires additional data.
The S524A40X11/40X21/40X41/60X81/60X51 continues to output data for each ACK it receives. To stop the
sequential read operation, the master does not respond with an ACK, but instead issues a Stop condition.
Using this method, data is output sequentially with the data from address “n” followed by the data from “n+1”. The
word address pointer for read operations increments all word addresses, allowing the entire EEPROM to be read
sequentially in a single operation. After the entire EEPROM is read, the word address pointer “rolls over” and the
S524A40X11/40X21/40X41/60X81/60X51 continues to transmit data for each ACK it receives from the master
(see Figure 1-14).
Start Slave Address
Data (n)
Data (n + x)
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 1-14. Sequential Read Operation
1-13
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
DATA SHEET
ELECTRICAL DATA
Table 1-3. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Unit
VCC
–
– 0.3 to + 7.0
V
Supply voltage
VIN
VO
–
–
– 0.3 to + 7.0
– 0.3 to + 7.0
– 40 to + 85
– 65 to + 150
5000
V
V
Input voltage
Output voltage
°
C
TA
–
Operating temperature
Storage temperature
Electrostatic discharge
°
C
TSTG
VESD
–
HBM
MM
V
500
Table 1-4. D.C. Electrical Characteristics
°
°
°
°
(TA = – 25 C to + 70 C (C), – 40 C to + 85 C (I), VCC = 1.8 V to 5.5 V)
Parameter
Input low voltage
Symbol
Conditions
Min
–
Typ
Max
Unit
VIL
0.3 VCC
–
–
–
–
–
–
–
V
V
SCL, SDA, A0, A1, A2
VIH
ILI
0.7 VCC
–
10
10
0.4
3
Input high voltage
Input leakage current
–
–
–
–
–
VIN = 0 to VCC
µA
µA
V
ILO
VOL
VO = 0 to VCC
Output leakage current
Output low voltage
IOL = 3 mA, VCC = 2.5 V
VCC = 5.5 V, 400 kHz
VCC = 1.8 V, 100 kHz
VCC = 5.5 V, 400 kHz
VCC = 1.8 V, 100 kHz
mA
ICC1
ICC2
ICC3
ICC4
ICC5
Supply current
Write
1
Read
–
–
–
–
–
–
0.2
60
1
µA
µA
VCC = SDA = SCL = 5.5 V,
all other inputs = 0 V
Stand-by current
ICC6
–
–
1
VCC = SDA = SCL = 1.8 V,
all other inputs = 0 V
1-14
DATA SHEET
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
Table 1-4. D.C. Electrical Characteristics (Continued)
°
°
°
°
(TA = – 25 C to + 70 C (C), – 40 C to + 85 C (I), VCC = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CIN
–
–
10
pF
°
Input capacitance
25 C, 1MHz,
VCC = 5 V, VIN = 0 V,
A0, A1, A2, SCL and WP pin
CI/O
–
–
10
°
Input/output capacitance
25 C, 1MHz,
VCC = 5 V, VI/O = 0 V,
SDA pin
Table 1-5. A.C. Electrical Characteristics
°
°
°
°
(TA = – 25 C to + 70 C (C), – 40 C to + 85 C (I), VCC = 1.8 V to 5.5 V)
Parameter
Symbol Conditions
VCC = 1.8 to 5.5 V
(Standard Mode)
VCC = 2.5 to 5.5 V
(Fast Mode)
Unit
Min
Max
Min
Max
FCLK
tHIGH
tLOW
External clock frequency
Clock high time
–
0
100
0
400
kHz
–
4
4.7
–
–
–
0.6
1.3
–
–
–
ms
Clock low time
–
tR
Rising time
SDA, SCL
1
0.3
0.3
–
tF
Falling time
SDA, SCL
–
0.3
–
–
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Bus free time
–
–
–
–
–
4
0.6
0.6
0
4.7
0
–
–
–
–
0.25
4
–
0.1
0.6
1.3
–
–
–
Before new
4.7
–
–
transmission
tAA
Data output valid from
clock low (note)
–
0.3
3.5
–
0.9
tSP
Noise spike width
Write cycle time
–
–
–
–
100
5
–
–
50
5
ns
tWR
ms
NOTE: When acting as a transmitter, the S524A40X11/40X21/40X41/60X81/60X51 must provide an internal minimum
delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid
unintended generation of a start or stop condition.
1-15
S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
DATA SHEET
tF
tHIGH
tR
tLOW
SCL
SDA In
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tAA
SDA Out
Figure 1-15. Timing Diagram for Bus Operations
SCL
SDA
8th Bit
ACK
WORDn
tWR
Stop
Condition
Start
Condition
Figure 1-16. Write Cycle Timing Diagram
1-16
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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