S6B0108 [SAMSUNG]
64 CH SEGMENT DRIVER FOR DOT MATRIX LCD; 64 CH段驱动点矩阵LCD
| 型号： | S6B0108 |
| 厂家： | 
SAMSUNG |
| 描述： | 64 CH SEGMENT DRIVER FOR DOT MATRIX LCD |
| 文件： | 总23页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S6B0108
64 CH SEGMENT DRIVER FOR DOT MATRIX LCD
June. 2000.
Ver. 0.0
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
INTRODUCTION
The S6B0108 is a LCD driver LSI with 64 channel output for dot matrix liquid crystal graphic display systems.
This device consists of the display RAM, 64 bit data latch, 64 bit drivers and decoder logic. It has the internal dis-
play RAM for storing the display data transferred from a 8 bit micro controller and generates the dot matrix Iiquid
crystal driving signals corresponding to stored data. The S6B0108 composed of the liquid crystal display system
in combination with the S6B0107 (64 channel common driver).
FEATURES
·
·
Dot matrix LCD segment driver with 64 channel output
Input and output signal
- Input: 8 bit parallel display data control signal from MPU divided bias voltage
(V0R, V0L, V2R, V2L, V3R, V3L, V5R, V5L)
- Output: 64 channel for LCD driving.
·
·
Display data is stored in display data RAM from MPU.
Interface RAM
- Capacity: 512 bytes (4096 bits)
- RAM bit data: RAM bit data = 1: On
RAM bit data = 0: Off
·
·
Applicable LCD duty: 1/32-1/64
LCD driving voltage: 8V-17V (VDD-VEE
)
·
·
Power supply voltage: + 5V ± 10%
Interface
Drivers
Controller
Common
S6B0107
Segment
Other S6B0108
MPU
·
·
High voltage CMOS process.
Bare chip available
2
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
BLOCK DIAGRAM
DB<0:7>
CS1B
CS2B
CS3
R/W
RS
Input
Register
Output
Register
E
RSTB
8
8
Display
On/Off
Instruction
Decoder
Busy
1
6
3
Y-Counter
6
ADC
X-Decoder
8
Y-Counter
64
6
CL
Display Data RAM
512 8 = 4096bits
64
6
8
´
FRM
64
Data Latch
64
V0L
V2L
V3L
V5L
M
V0R
V2R
V3R
V5R
LCD Driver
3
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PAD DIAGRAM
V3R
V2R
V5R
V0R
4
5
6
7
8
9
77 V3L
76 V2L
75 V5L
74 V0L
VEE2
73
VEE1
S64
72 S1
71 S2
70 S3
69 S4
68 S5
67 S6
66 S7
65 S8
64 S9
63 S10
62 S11
61 S12
60 S13
59 S14
58 S15
57 S16
56 S17
55 S18
54 S19
53 S20
52 S21
S63 10
S62 11
S61 12
S60 13
S59 14
S58 15
S57 16
S56 17
S55 18
S54 19
S53 20
S52 21
S51 22
S50 23
S49 24
S48 25
S47 26
S46 27
S45 28
S44 29
Y
(0, 0)
X
´
Chip size: 4090 4020
PAD size: 100 100
Unit
´
:m m
There is mark of S6B0108 on the bottom left in the chip.
4
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PAD CENTER COORDINATES
S6B0108
Coordinate
Coordinate
Coordinate
PAD
PAD
Pad
Pad
Pad
Pad
Number Name
Number Name
Number Name
X
Y
X
Y
X
Y
1
ADC
M
-1140
-1275
-1410
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1882
-1487
-1187
-1062
-937
1845
1845
1845
1809
1684
1559
1434
1309
1165
1040
915
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
-687
-562
-437
-312
-187
-62
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1845
-1379
-1239
-1099
-959
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
S4
S3
1882
1882
1882
1882
1882
1882
1882
1882
1882
1412
1277
1142
1007
882
791
2
916
3
VDD
V3R
V2R
V5R
V0R
VEE2
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S2
1041
1166
1310
1435
1559
1684
1809
1845
1845
1845
1845
1845
1845
1845
1845
1845
4
S1
5
VEE1
V0L
V5L
V2L
V3L
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
6
7
62
8
187
9
312
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
437
562
790
687
665
812
540
937
415
1062
1187
1487
1882
1882
1882
1882
1882
1882
1882
1882
1882
1882
1882
1882
1882
1882
1882
1882
1882
757
290
632
165
507
40
382
-84
NC
-209
-334
-459
-584
-709
-834
-959
-1099
-1239
-1379
-1845
-1845
-1845
-1845
-1845
NC
NC
-834
CS3
SC2B
SC1B
RSTB
R/W
RS
245
1845
1845
1845
1845
1845
1845
-709
120
-584
-5
-459
-130
-255
-380
-505
-630
-755
-880
-1005
-334
-209
-84
CL
1845
1845
1845
1845
1845
41
P2
166
P1
S8
291
E
S7
416
FRM
S6
541
-812
S5
666
5
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION
Table 1. Pin Description
Pin Number
QFP(TQFP)
Input /
Output
Symbol
Description
For internal logic circuit (+5V ± 10%)
GND (0V)
For LCD driver circuit
VDD
VSS
3(1)
78(76)
Power
73(71), 8(6)
VSS = 0V, VDD = +5V ± 10%, VDD-VEE = 8V - 17V
VEE1 and VEE2 is connected by the same voltage.
VEE1.2
Bias supply voltage terminals to drive the LCD.
74(72), 7(5)
76(74), 5(3)
77(75), 4(2)
75(73), 6(4)
V0L, V0R
V2L, V2R
V3L, V3R
V5L, V5R
Select Level
Non-Select Level
V2L(R), V3L(R)
Power
V0L(R), V5L(R)
V0L and V0R (V2L & V2R, V3L & V3R, V5L & V5R) should be
connected by the same voltage.
92(89)
91(87)
90(86)
CS1B
CS2B
CS3
Chip selection
Input
Input
In order to interface data for input or output, the terminals
have to be CS1B = L, CS2B = L, and CS3 = H.
2(100)
M
Alternating signal input for LCD driving.
Address control signal to determine the relation between Y
address of display RAM and terminals from which the data is
output.
ADC = H ® Y0: S1 - Y63: S64
ADC = L ® Y0: S64 - Y63: S1
1(99)
ADC
Input
Input
Input
Synchronous control signal.
Presets the 6-bit Z counter and synchronizes the common
signal with the frame signal when the frame signal becomes
high.
100(98)
99(97)
FRM
E
Enable signal.
Write mode (R/W = L) ® data of DB<0:7> is latched at the
falling edge of E.
Read mode (R/W = H) ® DB<0:7> appears the reading data
while E is at high level.
2 phase clock signal for internal operation.
Used to execute operations for input/output of display RAM
data and others.
98(96)
97(95)
CLK1
CLK2
Input
Input
Input
Display synchronous signal.
Display data is latched at rising time of the CL signal and
increments the Z-address counter at the CL falling time.
96(94)
95(93)
CL
RS
Data or Instruction.
RS = H ® DB<0:7>: Display RAM data
RS = L ® DB<0:7>: Instruction data
6
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
Table 1. Pin Description (Continued)
Input /
Pin Number
QFP(TQFP)
Symbol
R/W
Description
Output
Read or Write.
R/W = H ® Data appears at DB<0:7> and can be read by the
CPU while E = H, CS1B = L, CS2B = L and
CS3 = H .
94(92)
Input
R/W = L ® Display data DB<0:7> can be written at falling of E
when CS1B = L, CS2B = L and CS3 = H.
79-86
(77-84)
Data bus.
Three state I/O common terminal.
DB0-DB7
Input/Output
Output
LCD segment driver output.
Display RAM data 1: On
Display RAM data 0: Off (relation of display RAM data & M)
M
L
Data
L
Output Level
72-9
(70-7)
S1-S64
V2
V0
V3
V5
H
L
H
H
Reset signal.
When RSTB=L,
- ON / OFF register becomes set by 0. (display off)
– Display start line register becomes set by 0 (Z-address 0
set,
display from line 0)
After releasing reset, this condition can be changed only by
instruction.
93(91)
RSTB
NC
Input
87(85), 88(88)
89(90)
No connection. (open)
7
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
MAXIMUM ABSOLUTE LIMIT
Characteristic
Operating voltage
Symbol
Value
Unit
V
Note
VDD
(1)
-0.3 to +7.0
VEE
VB
VDD-19.0 to VDD+0.3
-0.3 to VDD+0.3
VEE-0.3 to VDD+0.3
(4)
(1), (3)
(2)
Supply voltage
V
V
Driver supply voltage
VLCD
TOPR
TSTG
V
Operating temperature
Storage temperature
-30 to +85
°C
°C
-55 to +125
NOTES:
1. Based on V = 0V.
SS
2. Applies the same supply voltage to V
and V
. V
=V -V
.
EE1
EE2 LCD DD EE
3. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0 - DB7.
4. Applies to V0L(R), V2L(R), V3L(R) and V5L(R).
Voltage level: V ³ V0L = V0R ³ V2L = V2R ³ V3L = V3R ³ V5L = V5R ³ V
.
DD
EE
8
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (VDD = +5V ± 10%, VSS = 0V, VDD-VEE = 8 to 17V, Ta =-30 to +85°C)
Characteristic
Symbol
Condition
Min
0.7VDD
2.0
0
Typ
Max
VDD
VDD
0.3VDD
0.8
Unit
V
Note
VIH1
(1)
-
-
-
-
-
-
-
-
-
-
-
Input high voltage
VIH2
VIL1
VIL2
VOH
VOL
ILKG
(2)
(1)
(2)
(3)
(3)
(4)
V
V
Input low voltage
0
V
IOH = -200mA
Output high voltage
Output low voltage
Input leakage current
2.4
-
-
V
IOL = 1.6mA
0.4
V
VIN = VSS - VDD
-1.0
1.0
mA
Three-state(off) input
current
ITSL
VIN = VSS - VDD
(5)
-5.0
-
5.0
mA
Driver input leakage
current
IDIL
IDD1
IDD2
VIN = VEE - VDD
During display
(6)
(7)
(7)
-2.0
-
-
-
2.0
100
500
mA
mA
mA
-
-
Operating current
On resistance
During access
Access cycle = 1MHz
VDD-VEE = 15V
RON
(8)
-
-
7.5
KW
ILOAD = ± 0.1mA
NOTES:
1. CL, FRM, M RSTB, CLK1, CLK2
2. CS1B, CS2B, CS3, E, R/W, RS, DB0 - DB7
3. DB0 - DB7
4. Except DB0 - DB7
5. DB0 - DB7 at high impedance
6. V0L(R), V2L(R), V3L(R), V5L(R)
7. 1/64 duty, FCLK = 250kHz, frame frequency = 70HZ, output: no load
8. - V = 15.5V
V
DD
EE
V0L(R) > V2L(R) = V
- 2/7 (V -V ) > V3L(R) = V + 2/7 (V -V ) > V5L(R)
DD
DD EE
EE
DD EE
9
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
AC CHARACTERISTICS (VDD = +5V ± 10%, VSS = 0V, Ta =-30 to +85°C)
Clock Timing
Characteristic
CLK1, CLK2 cycle time
Symbol
Min
2.5
625
625
1875
1875
625
625
-
Typ
Max
Unit
tCY
-
-
-
-
-
-
-
-
-
20
ms
tWL1
tWL2
tWH1
tWH2
tD12
tD21
tR
CLK1 "low" level width
CLK2 "low" level width
CLK1 "high" level width
CLK2 "high" level width
CLK1-CLK2 phase difference
CLK2-CLK1 phase difference
CLK1, CLK2 rise time
-
-
-
-
-
ns
-
150
150
tF
CLK1, CLK2 fall time
-
tCY
tWH1
tF
tR
0.7VDD
0.3VDD
CLK1
CLK2
tD12
tD21
tWL1
0.7VDD
0.3VDD
tWH2
tWL2
tF
tR
tCY
Figure 1. External Clock Waveform
10
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Display Control Timing
S6B0108
Characteristic
Symbol
Min
Typ
Max
Unit
tDF
FRM delay time
-2
-
+2
us
tDM
tWL
tWH
M delay time
-2
35
35
-
-
-
+2
-
us
us
us
CL "low" level width
CL "high" level width
-
tWL
0.7VDD
0.3VDD
tWH
tDF
tDF
0.7VDD
0.3VDD
tDM
0.7VDD
0.3VDD
Figure 2. Display Control Waveform
11
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
MPU Interface
Characteristic
Symbol
Min
Typ
Max
Unit
tC
E cycle
1000
-
-
ns
tWH
tWL
tR
E high level width
E low level width
E rise time
450
450
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
25
25
-
tF
E fall time
-
tASU
tAH
tDSU
tD
tDHW
tDHR
Address set-up time
Address hold time
Data set-up time
Data delay time
Data hold time (write)
Data hold time (read)
140
10
200
-
-
-
320
-
10
20
-
tC
tWL
2.0V
0.8V
E
tWH
tR
tF
tASU
tAH
tAH
R/W
tASU
CS1B, CS2B,
CS3, RS
0.8V
2.0V
tDSU tDHW
DB0 - 7
Figure 3. MPU Write Timing
12
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
tC
tWL
E
tWH
tR
tASU
tASU
tF
tAH
tAH
R/W
CS1B, CS2B,
CS3, RS
tD
tDHR
DB0 - 7
Figure 4. MPU Read Timing
13
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
OPERATING PRINCIPLES AND METHODS
I/O BUFFER
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in active
mode, Input or output of data and instruction does not execute. Therefore internal state is not change. But RSTB
and ADC can operate regardless CS1B-CS3.
INPUT REGISTER
Input register is provided to interface with MPU which is different operating frequency. Input register stores the
data temporarily before writing it into display RAM. When CS1B to CS3 are in the active mode, R/W and RS
select the input register. The data from MPU is written into input register. Then Writing it into display RAM. Data
latched for falling of the E signal and write automatically into the display data RAM by internal operation.
OUTPUT REGISTER
Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in active
mode and R/W and RS = H, stored data in display data RAM is latched in output register. When CS1B to CS3 is
in active mode and R/W = H, RS = L, status data (busy check) can read out. To read the contents of display data
RAM, twice access of read instruction is needed. In first access, data in display data RAM is latched into output
register. In second access, MPU can read data which is latched. That is, to read the data in display data RAM, it
needs dummy read. But status read is not needed dummy read.
RS
R/W
L
Function
Instruction
L
H
Status read (busy check)
L
Data write (from input register to display data RAM)
Data read (from display data RAM to output register)
H
H
14
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
RESET
S6B0108
The system can be initialized by setting RSTB terminal at low level when turning power on, receiving instruction
from MPU.
When RSTB becomes low, following procedure is occurred.
·
·
Display off
Display start line register become set by 0. (Z-address 0)
While RSTB is low, No instruction except status read can be accepted. Therefore, execute other instructions after
making sure that DB4 = 0 (clear RSTB) and DB7 = 0 (ready) by status read instruction. The Conditions of power
supply at initial power up are shown in table 1.
Table 2. Power Supply Initial Conditions
Item
Symbol
Min
Typ
Max
Unit
tRS
Reset time
Rise time
1.0
-
-
us
tR
-
-
200
ns
4.5V
VDD
tRS
tR
0.7VDD
0.3VDD
RSTB
15
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Busy Flag
Busy Flag indicates that S6B0108 is operating or no operating. When busy flag is high, S6B0108 is in internal
operating. When busy flag is low, S6B0108 can accept the data or instruction. DB7 indicates busy flag of the
S6B0108.
RS
R/W
E
N
N + 1
N + 2
Address
Output register
DB0-DB7
Data at address N Data at address N+1
Read data
Busy
Write
Busy Read data Busy
check address N check (dummy) check
Busy
check
Data read
address N + 1
at address
N
Busy Check
E
Busy Flag
T Busy
1/fCLK < T Busy < 3/fCLK
fCLK is CLK1, CLK2 frequency
Busy Flag
16
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
Display ON / OFF Flip - Flop
S6B0108
The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low), selective
voltage or non selective voltage appears on segment output terminals. When flip-flop is set (logic high), non
selective voltage appears on segment output terminals regardless of display RAM data. The display on/off flip-
flop can changes status by instruction. The display data at all segment disappear while RSTB is low. The status
of the flip-flop is output to DB5 by status read instruction. The display on/off flip-flop synchronized by CL signal.
X Page Register
X page register designates pages of the internal display data RAM. Count function is not available. An address is
set by instruction.
Y Address Counter
Y address counter designates address of the internal display data RAM. An address is set by instruction and is
increased by 1 automatically by read or write operations of display data.
Display Data RAM
Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of liquid crystal
display, write data 1. The other way, off state, writes 0.
Display data RAM address and segment output can be controlled by ADC signal.
·
·
ADC = H ® Y-address 0:S1 - Y address 63:S64
ADC = L ® Y-address 0:S64 - Y address 63:S1
ADC terminal connect the VDD or VSS
.
Display Start Line Register
The display start line register indicates of display data RAM to display top line of liquid crystal display. Bit data
(DB<0:5>) of the display start line set instruction is latched in display start line register. Latched data is
transferred to the Z address counter while FRM is high, presetting the Z address counter. It is used for scrolling of
the liquid crystal display screen.
17
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
DISPLAY CONTROL INSTRUCTION
The display control instructions control the internal state of the S6B0108. Instruction is received from MPU to
S6B0108 for the display control. The following table shows various instructions.
Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Function
Controls the display on or off.
Internal status and display
RAM data is not affected.
L: OFF, H: ON
Display
on/off
L
L
L
L
L
L
L
H
H
H
H
H
L/H
Set
address
Sets the Y address in the Y
address counter.
H
Y address (0 - 63)
(Y address)
Set page
(X address)
Sets the X address at the X
address register.
L
L
L
L
H
H
L
H
H
H
Page (0 - 7)
Display
start line
(Z address)
Indicates the display data
RAM displayed at the top of
the screen.
H
Display start line (0 - 63)
Read status.
BUSY L: Ready
H: In operation
ON/OFF L: Display ON
H: Display OFF
RESET L: Normal
H: Reset
On
/
Off
Status read
L
H
Busy
L
Reset
L
L
L
L
Writes data (DB0:7) into
display data RAM. After
writing instruction, Y address
is increased by 1
Write
display
data
H
H
L
Write data
Read data
automatically.
Read
display
data
Reads data (DB0: 7) from
display data RAM to the data
bus.
H
18
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
DISPLAY ON / OFF
S6B0108
RS
0
R/W
0
DB7
0
DB6
0
DB5
1
DB4
1
DB3
1
DB2
1
DB1
1
DB0
D
The display data appears when D is 1 and disappears when D is 0. Though the data is not on the screen with D =
0, it remains in the display data RAM. Therefore, you can make it appear by changing D = 0 into D = 1.
SET ADDRESS (Y ADDRESS)
S
0
R/W
0
DB7
0
DB6
1
DB5
AC5
DB4
AC4
DB3
AC3
DB2
AC2
DB1
AC1
DB0
AC0
Y address (AC0 - AC5) of the display data RAM is set in the Y address counter. An address is set by instruction
and increased by 1 automatically by read or write operations of display data.
SET PAGE (X ADDRESS)
RS
0
R/W
0
DB7
1
DB6
0
DB5
1
DB4
1
DB3
1
DB2
AC2
DB1
AC1
DB0
AC0
X address(AC0 - AC2) of the display data RAM is set in the X address register. Writing or reading to or from MPU
is executed in this specified page until the next page is set.
DISPLAY START LINE (Z ADDRESS)
RS
0
R/W
0
DB7
1
DB6
1
DB5
AC5
DB4
AC4
DB3
AC3
DB2
AC2
DB1
AC1
DB0
AC0
Z address (AC0 - AC5) of the display data RAM is set in the display start line register and displayed at the top of
the screen. When the display duty cycle is 1/64 or others(1/32 - 1/64), the data of total line number of LCD
screen, from the line specified by display start line instruction, is displayed.
19
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
STATUS READ
RS
0
R/W
DB7
DB6
0
DB5
DB4
DB3
0
DB2
0
DB1
0
DB0
0
1
BUSY
ON/OFF RESET
·
·
·
BUSY
When BUSY is 1, the Chip is executing internal operation and no instructions are accepted.
When BUSY is 0, the Chip is ready to accept any instructions.
ON/OFF
When ON/OFF is 1, the display is OFF.
When ON/OFF is 0, the display is ON.
RESET
When RESET is 1, the system is being initialized.
In this condition, no instructions except status read can be accepted.
When RESET is 0, initializing has finished and the system is in the usual operation condition.
WRITE DISPLAY DATA
RS
1
R/W
0
DB7
D7
DB6
D6
DB5
D5
DB4
D4
DB3
D3
DB2
D2
DB1
D1
DB0
D0
Writes data (D0 - D7) into the display data RAM. After writing instruction, Y address is increased by 1
automatically.
READ DISPLAY DATA
RS
1
R/W
1
DB7
D7
DB6
D6
DB5
D5
DB4
D4
DB3
D3
DB2
D2
DB1
D1
DB0
D0
Reads data (D0 - D7) from the display data RAM. After reading instruction, Y address is increased by 1
automatically.
20
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
APPLICATION CIRCUIT
1/64 DUTY COMMON DRIVER (S6B0107) INTERFACE CIRCUIT
R1
R2
From MPU
-
-
VDD
VDD
ADC
V0R, V0L
V5R, V5L
V1R, V1L
V4R, V4L
VEE
DIO1
DIO2
M
FRM
CLK1
CLK2
CL2
Open
Open
V0
V5
V1
V4
VEE
V0R, V0L
V5R, V5L
V2R, V2L
V3R, V3L
VEE1, VEE2
VSS
V0
V5
V2
V3
VEE
M
S6B0108
FRM
CLK1
CLK2
CL2
VSS
S6B0107
VDD
VDD
SHL
FS
S64
S1
MS
PCLK2
SD2
DS1
VSS
SEG1
COM1
SEG64
C1
LCD
C64
COM64
VDD
V0
V1
V2
V3
V4
V5
R1
R1
R2
R1
R1
VEE
21
S6B0108
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
TIMING DIAGRAM (1/64 DUTY)
CLK1
1
2
3
48
49
CLK2
64
1
2
3
64
1
2
3
64
1
CL
Input
FRM
1 Frame
1 Frame
M
V0
V1
V5
V4
V4
V4
V0
C1
C2
V5
V5
V1
V1
V1
V4
V4
Common
V0
V0
V1
V1
C64
V4
V4
V5
V0
V0
V2
V2
V2
S1
V3
V3
V3
V3
V5
V5
Segment
V2
S64
22
64CH SEGMENT DRIVER FOR DOT MATRIX LCD
S6B0108
LCD PANEL INTERFACE APPLICATION CIRCUIT
S6B0108
No. 1
S1 ..... S64
S6B0108
No. 2
S1 ..... S64
S6B0108
No. 8
S1 ..... S64
.....
.....
.....
.....
COM1
COM2
COM3
S6B0107
(master)
C1
C2
C3
Cf
Rf
CR
COM64
COM65
R
C64
LCD Panel
´ 512dots)
(128
C1
C2
C3
COM66
COM67
C64
COM128
S6B0107
(slave)
.....
.....
.....
S1 ..... S64
No. 9
S6B0108
S1 ..... S64
No. 10
S6B0108
S1 ..... S64
No. 16
S6B0108
.....
23
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