S6C0641 [SAMSUNG]
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER; 6位三百〇九分之三百沟道TFT -LCD源极驱动器
| 型号： | S6C0641 |
| 厂家： | 
SAMSUNG |
| 描述： | 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER |
| 文件： | 总22页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
November. 1999.
Ver. 0.1
Prepared by:
Sangho Park
mrno1@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641 Specification Revision History
Content
Version
Date
0.0
0.1
Original
The content of page 21 has been modified
Aug.1999
Nov.1999
2
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
CONTENTS
INTRODUCTION ................................................................................................................................................. 4
FEATURES ......................................................................................................................................................... 4
BLOCK DIAGRAM .............................................................................................................................................. 5
PIN ASSINGMENTS............................................................................................................................................ 6
PIN DESCRIPTIONS ........................................................................................................................................... 7
OPERATION DESCRIPTION............................................................................................................................... 8
DISPLAY DATA TRANSFER............................................................................................................................ 8
EXTENSION OF OUTPUT ............................................................................................................................... 8
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE .................................................. 9
ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 18
RECOMMENDED OPERATION CONDITIONS.................................................................................................. 18
DC CHARACTERISTICS................................................................................................................................... 19
AC CHARACTERISTICS................................................................................................................................... 20
WAVEFORMS................................................................................................................................................... 21
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD........................ 22
3
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
INTRODUCTION
The S6C0641 is a 300 channel or 309 channel output, TFT-LCD source driver for 64 gray scale displays. Data
input is based on digital input consisting of 6 bits by 3 dots, which can realize a full-color display of 260,000 colors
by output of 64 values gamma-corrected.
This device has an internal D/A (Digital-to-Analog) converter for each output and 9 or 11 external power supplies.
S6C0641 can be adopted to larger panel, and SHL (Shift Direction Selection) pin makes use of the LCD panel
connection conveniently. Maximum operation clock frequency is 55 MHz at a 3.3 V logic operation. It can be
applied to the TFT-LCD panel of SVGA, XGA standards.
FEATURES
·
·
·
·
·
·
·
·
·
·
·
TFT active matrix LCD source driver LSI
64 gray scale is possible through 9 or 11 external power supply and D/A converter
Line inversion display is possible
CMOS level input
Compatible with gamma-correction
Logic supply voltage: 3.0 - 5.5 V
LCD driver supply voltage: 3.0 - 5.5 V
Output dynamic range: 2.6 - 5.1 Vp-p
Maximum operating frequency: fMAX = 55 MHz (internal data transmission rate at 3.3 V operation)
Output: 300 / 309 outputs
TCP available
4
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
BLOCK DIAGRAM
Output Buffer
D/A Converter
Data Latch
VGMA1 -
VGMA11
11
6
6
6
6
6
6
6
6
6
6
6
6
CLK1
Data Register
18
6
6
6
D00 - D05
D10 - D15
D20 - D25
100 / 103 bit Shift Register
DIO2
SELT
SHL
TESTB DIO1
CLK2
Figure 1. S6C0641 Block Diagram
5
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
PIN ASSIGNMENTS
Y001
Y002
Y003
Y004
VSS2
VDD2
VGMA10
VGMA8
VGMA6
VGMA4
VGMA2
D05
D04
D03
D02
D01
D00
D15
D14
D13
D12
D11
D10
DIO1
VSS1
SELT
CLK2
VDD1
DIO2
CLK1
D25
D24
D23
D22
D21
D20
SHL
VGMA1
VGMA3
VGMA5
VGMA7
VGMA9
VGMA11
VDD2
VSS2
Y306
Y307
Y308
Y309
Figure 2. S6C0641 Pin Assignments
6
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
PIN DESCRIPTIONS
Symbol
VDD1
Pin Name
Logic power supply
Driver power supply
Logic ground
Description
3.0- 5.5 V
VDD2
3.0 - 5.5 V
VSS1
Ground (0 V)
Ground (0 V)
VSS2
Driver ground
Y1 – Y309
Driver outputs
The D/A converted 64 gray scale analog voltage is output.
D0<0:5>
- D2<0:5>
The display data is input with a width of 18 bits,
gray-scale data (6 bits) by 3 dots (R,G,B) DX0: LSB, DX5: MSB
Display data input
This pin controls the direction of shift register in cascade connection.
The shift direction of the shift registers is as follows.
SHL = H: DIO1 input, Y1 ® Y309, DIO2 output
SHL
Shift direction control input
SHL = L: DIO2 input, Y309 ® Y1, DIO1 output
SHL = H: Used as the start pulse input pin.
SHL = L: Used as the start pulse output pin.
DIO1
DIO2
CLK2
Start pulse input / output
Start pulse input / output
Shift clock input
SHL = H: Used as the start pulse output pin.
SHL = L: Used as the start pulse input pin.
Refer to the shift register's shift clock input. the display data is loaded
to the data register at the rising edge of CLK2.
Latches the contents of the data register at rising edge and transfers
them to the D/A converter. Also, after CLK1 input, clears the internal
shift register contents. After 1 pulse input on start, operates normally.
CLK1 input timing refers to the "Relationships between CLK1 start
pulse (DIO1, DIO2) and blanking period" of the switching
characteristic waveform.
CLK1
SELT
Latch input
This pin controls 300CH or 309CH output.
SELT = H: 309CH output ® Y151 to Y159 are useless.
SELT = L: 300CH output.
300 / 309CH output
control input
® Y151 to Y159 are useless.
This pin is internally pulled-up.(Rpu = 30 kW)
Input the gamma corrected power supplies from external source.
VDD2 ³ VGMA1 > VGMA2 > ¼ ¼ ¼ > VGMA10 > VGMA11 ³ VSS2
Keep gray-scale power supply unchanged during the gray-scale
voltage output.
VGMA1
–
VGMA11
Gamma corrected power
supplies
TESTB = H: Normal operation mode
TESTB
Test input
TESTB = L: Test mode (OP AMP CUT-OFF)
This pin is internally pulled-up.(Rpu = 30kW)
7
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
OPERATION DESCRIPTION
DISPLAY DATA TRANSFER
When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse
enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the
data of 300 / 309 channels are loaded into internal latch, it goes into stand-by state automatically, and any
new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or
DIO2) is provided, new display data is valid on the next rising edge of CLK2 after the falling edge of DIO1 (or
DIO2).
EXTENSION OF OUTPUT
Output pin can be adjusted to an extended screen by cascade connection.
(1) SHL = "L"
Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins
except DIO1 and DIO2 are connected together in each device.
(2) SHL = "H"
Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins
except DIO2 and DIO1 are connected together in each device.
8
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE
The LCD drive output voltages are determined by the input data and 11 gamma corrected power supplies
(VGMA1 - VGMA11).
SHL = H
OUTPUT
Y3
......
......
Y1
Y2
Y307
Y308
Last
Y309
-
First
DATA
D00 - D05 D10 - D15 D20 - D25
D00 - D05 D10 - D15 D20 - D25
SHL = L
OUTPUT
-
Y3
......
......
Y1
Y2
Y307
Y308
First
Y309
Last
DATA
D00 - D05 D10 - D15 D20 - D25
D00 - D05 D10 - D15 D20 - D25
Figure 3. Relationship between Shift Direction and Output Data
VDD2
VGMA1
VGMA2
VGMA3
VGMA4
VGMA5
VGMA6
VGMA7
VGMA8
VGMA9
VGMA10
VGMA11
VSS2
00H
07H
0FH
17H
1FH
27H
2FH
37H
3FH
Figure 4. Gamma Correction Curve
9
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value:
In case of using 11 levels of Gamma-corrected power supplies (VGMA1 to VGMA11)
Input data
G/S
Output voltage
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VGMA1
00H
01H
02H
03H
04H
05H
06H
07H
VH0
VH1
VH2
VH3
VH4
VH5
VH6
VH7
VGMA3 + (VGMA2 – VGMA3) ´ 6/7
VGMA3 + (VGMA2 – VGMA3) ´ 5/7
VGMA3 + (VGMA2 – VGMA3) ´ 4/7
VGMA3 + (VGMA2 – VGMA3) ´ 3/7
VGMA3 + (VGMA2 – VGMA3) ´ 2/7
VGMA3 + (VGMA2 – VGMA3) ´ 1/7
VGMA3
VGMA4 + (VGMA3 – VGMA4) ´ 7/8
VGMA4 + (VGMA3 – VGMA4) ´ 6/8
VGMA4 + (VGMA3 – VGMA4) ´ 5/8
VGMA4 + (VGMA3 – VGMA4) ´ 4/8
VGMA4 + (VGMA3 – VGMA4) ´ 3/8
VGMA4 + (VGMA3 – VGMA4) ´ 2/8
VGMA4 + (VGMA3 – VGMA4) ´ 1/8
VGMA4
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
VH8
VH9
VH10
VH11
VH12
VH13
VH14
VH15
VGMA5 + (VGMA4 – VGMA5) ´ 7/8
VGMA5 + (VGMA4 – VGMA5) ´ 6/8
VGMA5 + (VGMA4 – VGMA5) ´ 5/8
VGMA5 + (VGMA4 – VGMA5) ´ 4/8
VGMA5 + (VGMA4 – VGMA5) ´ 3/8
VGMA5 + (VGMA4 – VGMA5) ´ 2/8
VGMA5 + (VGMA4 – VGMA5) ´ 1/8
VGMA5
10H
11H
12H
13H
14H
15H
16H
17H
VH16
VH17
VH18
VH19
VH20
VH21
VH22
VH23
VGMA6 + (VGMA5 – VGMA6) ´ 7/8
VGMA6 + (VGMA5 – VGMA6) ´ 6/8
VGMA6 + (VGMA5 – VGMA6) ´ 5/8
VGMA6 + (VGMA5 – VGMA6) ´ 4/8
VGMA6 + (VGMA5 – VGMA6) ´ 3/8
VGMA6 + (VGMA5 – VGMA6) ´ 2/8
VGMA6 + (VGMA5 – VGMA6) ´ 1/8
VGMA6
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
VH24
VH25
VH26
VH27
VH28
VH29
VH30
VH31
NOTE: VDD2³ VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11³ VSS2
10
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
Table 2. Relationship between Input Data and Output Voltage Value (Continued)
Input data
G/S
Output voltage
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7
20H
21H
22H
23H
24H
25H
26H
27H
VH32
VH33
VH34
VH35
VH36
VH37
VH38
VH39
VGMA8 + (VGMA7 – VGMA8) ´ 7/8
VGMA8 + (VGMA7 – VGMA8) ´ 6/8
VGMA8 + (VGMA7 – VGMA8) ´ 5/8
VGMA8 + (VGMA7 – VGMA8) ´ 4/8
VGMA8 + (VGMA7 – VGMA8) ´ 3/8
VGMA8 + (VGMA7 – VGMA8) ´ 2/8
VGMA8 + (VGMA7 – VGMA8) ´ 1/8
VGMA8
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
VH40
VH41
VH42
VH43
VH44
VH45
VH46
VH47
VGMA9 + (VGMA8 – VGMA9) ´ 7/8
VGMA9 + (VGMA8 – VGMA9) ´ 6/8
VGMA9 + (VGMA8 – VGMA9) ´ 5/8
VGMA9 + (VGMA8 – VGMA9) ´ 4/8
VGMA9 + (VGMA8 – VGMA9) ´ 3/8
VGMA9 + (VGMA8 – VGMA9) ´ 2/8
VGMA9 + (VGMA8 – VGMA9) ´ 1/8
VGMA9
30H
31H
32H
33H
34H
35H
36H
37H
VH48
VH49
VH50
VH51
VH52
VH53
VH54
VH55
VGMA10 + (VGMA9 – VGMA10) ´ 6/7
VGMA10 + (VGMA9 – VGMA10) ´ 5/7
VGMA10 + (VGMA9 – VGMA10) ´ 4/7
VGMA10 + (VGMA9 – VGMA10) ´ 3/7
VGMA10 + (VGMA9 – VGMA10) ´ 2/7
VGMA10 + (VGMA9 – VGMA10) ´ 1/7
VGMA10
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
VH56
VH57
VH58
VH59
VH60
VH61
VH62
VH63
VGMA11
RGMA (Gamma-Corrected Resistance) Ratio. (if the RGMA1 equals 1)
RGMA1
RGMA2
RGMA3
RGMA4
1.00
2.00
2.77
1.50
0.90
RGMA6
RGMA7
RGMA8
RGMA9
RGMA10
0.84
0.66
0.84
1.42
1.05
RGMA5
RGMA1 = 2.31 kW
11
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 3. Relationship between Input Data and Output Voltage Value:
In case of using 10 levels of Gamma-corrected power supplies (VGMA1 = OPEN)
Input data
G/S
Output voltage
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VGMA2
00H
01H
02H
03H
04H
05H
06H
07H
VH0
VH1
VH2
VH3
VH4
VH5
VH6
VH7
VGMA3 + (VGMA2 – VGMA3) ´ 6/7
VGMA3 + (VGMA2 – VGMA3) ´ 5/7
VGMA3 + (VGMA2 – VGMA3) ´ 4/7
VGMA3 + (VGMA2 – VGMA3) ´ 3/7
VGMA3 + (VGMA2 – VGMA3) ´ 2/7
VGMA3 + (VGMA2 – VGMA3) ´ 1/7
VGMA3
VGMA4 + (VGMA3 – VGMA4) ´ 7/8
VGMA4 + (VGMA3 – VGMA4) ´ 6/8
VGMA4 + (VGMA3 – VGMA4) ´ 5/8
VGMA4 + (VGMA3 – VGMA4) ´ 4/8
VGMA4 + (VGMA3 – VGMA4) ´ 3/8
VGMA4 + (VGMA3 – VGMA4) ´ 2/8
VGMA4 + (VGMA3 – VGMA4) ´ 1/8
VGMA4
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
VH8
VH9
VH10
VH11
VH12
VH13
VH14
VH15
VGMA5 + (VGMA4 – VGMA5) ´ 7/8
VGMA5 + (VGMA4 – VGMA5) ´ 6/8
VGMA5 + (VGMA4 – VGMA5) ´ 5/8
VGMA5 + (VGMA4 – VGMA5) ´ 4/8
VGMA5 + (VGMA4 – VGMA5) ´ 3/8
VGMA5 + (VGMA4 – VGMA5) ´ 2/8
VGMA5 + (VGMA4 – VGMA5) ´ 1/8
VGMA5
10H
11H
12H
13H
14H
15H
16H
17H
VH16
VH17
VH18
VH19
VH20
VH21
VH22
VH23
VGMA6 + (VGMA5 – VGMA6) ´ 7/8
VGMA6 + (VGMA5 – VGMA6) ´ 6/8
VGMA6 + (VGMA5 – VGMA6) ´ 5/8
VGMA6 + (VGMA5 – VGMA6) ´ 4/8
VGMA6 + (VGMA5 – VGMA6) ´ 3/8
VGMA6 + (VGMA5 – VGMA6) ´ 2/8
VGMA6 + (VGMA5 – VGMA6) ´ 1/8
VGMA6
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
VH24
VH25
VH26
VH27
VH28
VH29
VH30
VH31
NOTE: VDD2³ VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11³ VSS2
12
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
Table 3. Relationship between Input Data and Output Voltage Value (Continued)
Input data
G/S
Output voltage
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7
20H
21H
22H
23H
24H
25H
26H
27H
VH32
VH33
VH34
VH35
VH36
VH37
VH38
VH39
VGMA8 + (VGMA7 – VGMA8) ´ 7/8
VGMA8 + (VGMA7 – VGMA8) ´ 6/8
VGMA8 + (VGMA7 – VGMA8) ´ 5/8
VGMA8 + (VGMA7 – VGMA8) ´ 4/8
VGMA8 + (VGMA7 – VGMA8) ´ 3/8
VGMA8 + (VGMA7 – VGMA8) ´ 2/8
VGMA8 + (VGMA7 – VGMA8) ´ 1/8
VGMA8
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
VH40
VH41
VH42
VH43
VH44
VH45
VH46
VH47
VGMA9 + (VGMA8 – VGMA9) ´ 7/8
VGMA9 + (VGMA8 – VGMA9) ´ 6/8
VGMA9 + (VGMA8 – VGMA9) ´ 5/8
VGMA9 + (VGMA8 – VGMA9) ´ 4/8
VGMA9 + (VGMA8 – VGMA9) ´ 3/8
VGMA9 + (VGMA8 – VGMA9) ´ 2/8
VGMA9 + (VGMA8 – VGMA9) ´ 1/8
VGMA9
30H
31H
32H
33H
34H
35H
36H
37H
VH48
VH49
VH50
VH51
VH52
VH53
VH54
VH55
VGMA10 + (VGMA9 – VGMA10) ´ 6/7
VGMA10 + (VGMA9 – VGMA10) ´ 5/7
VGMA10 + (VGMA9 – VGMA10) ´ 4/7
VGMA10 + (VGMA9 – VGMA10) ´ 3/7
VGMA10 + (VGMA9 – VGMA10) ´ 2/7
VGMA10 + (VGMA9 – VGMA10) ´ 1/7
VGMA10
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
VH56
VH57
VH58
VH59
VH60
VH61
VH62
VH63
VGMA11
RGMA (Gamma-Corrected Resistance) Ratio. (if the RGMA2 equals 1)
RGMA1
RGMA2
RGMA3
RGMA4
-
RGMA6
RGMA7
RGMA8
RGMA9
RGMA10
0.42
0.33
0.42
0.71
0.53
1.00
1.39
0.75
0.45
RGMA5
RGMA1 = 4.62 kW
13
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 4. Relationship between Input Data and Output Voltage Value:
In case of using 10 levels of Gamma-corrected power supplies (VGMA2 = OPEN)
Input data
G/S
Output voltage
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VGMA3 + (VGMA2 – VGMA3) ´ 7/8
VGMA3 + (VGMA2 – VGMA3) ´ 6/8
VGMA3 + (VGMA2 – VGMA3) ´ 5/8
VGMA3 + (VGMA2 – VGMA3) ´ 4/8
VGMA3 + (VGMA2 – VGMA3) ´ 3/8
VGMA3 + (VGMA2 – VGMA3) ´ 2/8
VGMA3 + (VGMA2 – VGMA3) ´ 1/8
VGMA3
00H
01H
02H
03H
04H
05H
06H
07H
VH0
VH1
VH2
VH3
VH4
VH5
VH6
VH7
VGMA4 + (VGMA3 – VGMA4) ´ 7/8
VGMA4 + (VGMA3 – VGMA4) ´ 6/8
VGMA4 + (VGMA3 – VGMA4) ´ 5/8
VGMA4 + (VGMA3 – VGMA4) ´ 4/8
VGMA4 + (VGMA3 – VGMA4) ´ 3/8
VGMA4 + (VGMA3 – VGMA4) ´ 2/8
VGMA4 + (VGMA3 – VGMA4) ´ 1/8
VGMA4
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
VH8
VH9
VH10
VH11
VH12
VH13
VH14
VH15
VGMA5 + (VGMA4 – VGMA5) ´ 7/8
VGMA5 + (VGMA4 – VGMA5) ´ 6/8
VGMA5 + (VGMA4 – VGMA5) ´ 5/8
VGMA5 + (VGMA4 – VGMA5) ´ 4/8
VGMA5 + (VGMA4 – VGMA5) ´ 3/8
VGMA5 + (VGMA4 – VGMA5) ´ 2/8
VGMA5 + (VGMA4 – VGMA5) ´ 1/8
VGMA5
10H
11H
12H
13H
14H
15H
16H
17H
VH16
VH17
VH18
VH19
VH20
VH21
VH22
VH23
VGMA6 + (VGMA5 – VGMA6) ´ 7/8
VGMA6 + (VGMA5 – VGMA6) ´ 6/8
VGMA6 + (VGMA5 – VGMA6) ´ 5/8
VGMA6 + (VGMA5 – VGMA6) ´ 4/8
VGMA6 + (VGMA5 – VGMA6) ´ 3/8
VGMA6 + (VGMA5 – VGMA6) ´ 2/8
VGMA6 + (VGMA5 – VGMA6) ´ 1/8
VGMA6
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
VH24
VH25
VH26
VH27
VH28
VH29
VH30
VH31
NOTE: VDD2³ VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11³ VSS2
14
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
Table 4. Relationship between Input Data and Output Voltage Value (Continued)
Input data
G/S
Output voltage
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7
20H
21H
22H
23H
24H
25H
26H
27H
VH32
VH33
VH34
VH35
VH36
VH37
VH38
VH39
VGMA8 + (VGMA7 – VGMA8) ´ 7/8
VGMA8 + (VGMA7 – VGMA8) ´ 6/8
VGMA8 + (VGMA7 – VGMA8) ´ 5/8
VGMA8 + (VGMA7 – VGMA8) ´ 4/8
VGMA8 + (VGMA7 – VGMA8) ´ 3/8
VGMA8 + (VGMA7 – VGMA8) ´ 2/8
VGMA8 + (VGMA7 – VGMA8) ´ 1/8
VGMA8
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
VH40
VH41
VH42
VH43
VH44
VH45
VH46
VH47
VGMA9 + (VGMA8 – VGMA9) ´ 7/8
VGMA9 + (VGMA8 – VGMA9) ´ 6/8
VGMA9 + (VGMA8 – VGMA9) ´ 5/8
VGMA9 + (VGMA8 – VGMA9) ´ 4/8
VGMA9 + (VGMA8 – VGMA9) ´ 3/8
VGMA9 + (VGMA8 – VGMA9) ´ 2/8
VGMA9 + (VGMA8 – VGMA9) ´ 1/8
VGMA9
30H
31H
32H
33H
34H
35H
36H
37H
VH48
VH49
VH50
VH51
VH52
VH53
VH54
VH55
VGMA10 + (VGMA9 – VGMA10) ´ 6/7
VGMA10 + (VGMA9 – VGMA10) ´ 5/7
VGMA10 + (VGMA9 – VGMA10) ´ 4/7
VGMA10 + (VGMA9 – VGMA10) ´ 3/7
VGMA10 + (VGMA9 – VGMA10) ´ 2/7
VGMA10 + (VGMA9 – VGMA10) ´ 1/7
VGMA10
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
VH56
VH57
VH58
VH59
VH60
VH61
VH62
VH63
VGMA11
RGMA (Gamma-Corrected Resistance) Ratio. (if the sum of RGMA1 and RGMA2 equals 1)
RGMA1
RGMA2
RGMA3
RGMA4
RGMA6
RGMA7
RGMA8
RGMA9
RGMA10
0.37
0.29
0.37
0.62
0.46
1.00
1.21
0.66
0.39
RGMA5
RGMA1 + RGMA2 = 5.28 kW
15
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
Table 5. Relationship between Input Data and Output Voltage Value:
In case of using 9 levels of Gamma-corrected power supplies (VGMA2, VGMA10 = OPEN)
Input data
G/S
Output voltage
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VGMA3 + (VGMA2 – VGMA3) ´ 7/8
VGMA3 + (VGMA2 – VGMA3) ´ 6/8
VGMA3 + (VGMA2 – VGMA3) ´ 5/8
VGMA3 + (VGMA2 – VGMA3) ´ 4/8
VGMA3 + (VGMA2 – VGMA3) ´ 3/8
VGMA3 + (VGMA2 – VGMA3) ´ 2/8
VGMA3 + (VGMA2 – VGMA3) ´ 1/8
VGMA3
00H
01H
02H
03H
04H
05H
06H
07H
VH0
VH1
VH2
VH3
VH4
VH5
VH6
VH7
VGMA4 + (VGMA3 – VGMA4) ´ 7/8
VGMA4 + (VGMA3 – VGMA4) ´ 6/8
VGMA4 + (VGMA3 – VGMA4) ´ 5/8
VGMA4 + (VGMA3 – VGMA4) ´ 4/8
VGMA4 + (VGMA3 – VGMA4) ´ 3/8
VGMA4 + (VGMA3 – VGMA4) ´ 2/8
VGMA4 + (VGMA3 – VGMA4) ´ 1/8
VGMA4
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
VH8
VH9
VH10
VH11
VH12
VH13
VH14
VH15
VGMA5 + (VGMA4 – VGMA5) ´ 7/8
VGMA5 + (VGMA4 – VGMA5) ´ 6/8
VGMA5 + (VGMA4 – VGMA5) ´ 5/8
VGMA5 + (VGMA4 – VGMA5) ´ 4/8
VGMA5 + (VGMA4 – VGMA5) ´ 3/8
VGMA5 + (VGMA4 – VGMA5) ´ 2/8
VGMA5 + (VGMA4 – VGMA5) ´ 1/8
VGMA5
10H
11H
12H
13H
14H
15H
16H
17H
VH16
VH17
VH18
VH19
VH20
VH21
VH22
VH23
VGMA6 + (VGMA5 – VGMA6) ´ 7/8
VGMA6 + (VGMA5 – VGMA6) ´ 6/8
VGMA6 + (VGMA5 – VGMA6) ´ 5/8
VGMA6 + (VGMA5 – VGMA6) ´ 4/8
VGMA6 + (VGMA5 – VGMA6) ´ 3/8
VGMA6 + (VGMA5 – VGMA6) ´ 2/8
VGMA6 + (VGMA5 – VGMA6) ´ 1/8
VGMA6
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
VH24
VH25
VH26
VH27
VH28
VH29
VH30
VH31
NOTE: VDD2³ VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11³ VSS2
16
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
Table 5. Relationship between Input Data and Output Voltage Value (Continued)
Input data
G/S
Output voltage
DX5 DX4 DX3 DX2 DX1 DX0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7 + (VGMA6 – VGMA7) ´ 7/8
VGMA7
20H
21H
22H
23H
24H
25H
26H
27H
VH32
VH33
VH34
VH35
VH36
VH37
VH38
VH39
VGMA8 + (VGMA7 – VGMA8) ´ 7/8
VGMA8 + (VGMA7 – VGMA8) ´ 6/8
VGMA8 + (VGMA7 – VGMA8) ´ 5/8
VGMA8 + (VGMA7 – VGMA8) ´ 4/8
VGMA8 + (VGMA7 – VGMA8) ´ 3/8
VGMA8 + (VGMA7 – VGMA8) ´ 2/8
VGMA8 + (VGMA7 – VGMA8) ´ 1/8
VGMA8
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
VH40
VH41
VH42
VH43
VH44
VH45
VH46
VH47
VGMA9 + (VGMA8 – VGMA9) ´ 7/8
VGMA9 + (VGMA8 – VGMA9) ´ 6/8
VGMA9 + (VGMA8 – VGMA9) ´ 5/8
VGMA9 + (VGMA8 – VGMA9) ´ 4/8
VGMA9 + (VGMA8 – VGMA9) ´ 3/8
VGMA9 + (VGMA8 – VGMA9) ´ 2/8
VGMA9 + (VGMA8 – VGMA9) ´ 1/8
VGMA9
30H
31H
32H
33H
34H
35H
36H
37H
VH48
VH49
VH50
VH51
VH52
VH53
VH54
VH55
VGMA11 + (VGMA9 – VGMA11) ´ 7/8
VGMA11 + (VGMA9 – VGMA11) ´ 6/8
VGMA11 + (VGMA9 – VGMA11) ´ 5/8
VGMA11 + (VGMA9 – VGMA11) ´ 4/8
VGMA11 + (VGMA9 – VGMA11) ´ 3/8
VGMA11 + (VGMA9 – VGMA11) ´ 2/8
VGMA11 + (VGMA9 – VGMA11) ´ 1/8
VGMA11
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
VH56
VH57
VH58
VH59
VH60
VH61
VH62
VH63
RGMA (Gamma-Corrected Resistance) Ratio. (if the sum of RGMA1 and RGMA2 equals 1)
RGMA1
RGMA2
RGMA3
RGMA4
RGMA6
RGMA7
RGMA8
RGMA9
RGMA10
0.37
0.29
0.37
1.00
1.21
0.66
0.39
0.71
RGMA5
RGMA1 + RGMA2 = 5.28 kW
17
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
ABSOLUTE MAXIMUM RATINGS
Table 6. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)
Parameter
Symbol
VDD1
Ratings
-0.3 to 6.5
Unit
Logic supply voltage
Driver supply voltage
VDD2
-0.3 to 6.5
VGMA1 - 10
Others
-0.3 to VDD2 + 0.3
-0.3 to VDD1 + 0.3
-0.3 to VDD1 + 0.3
-0.3 to VDD2 + 0.3
-20 to 75
Input voltage
V
DIO1, 2
Y1 - Y309
Topr
Output voltage
Operation temperature
Storage temperature
°C
Tstg
-55 to 125
CAUTIONS:
If LSIs are stressed beyond those listed above “ absolute maximum ratings” , they may be permanently
destroyed. These are stress ratings only, and functional operation of the device at these or any other
condition beyond those indicated under “ recommended operating conditions” is not implied. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability.
Turn on power order: VDD1 ® control signal input ® VDD2 ® VGMA1 - VGMA11
Turn off power order: VGMA1 - VGMA11 ® VDD2 ® control signal input ® VDD1
RECOMMENDED OPERATION CONDITIONS
Table 7. Recommended Operation Conditions (Ta = -20 to 75 °C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Min.
3.0
Typ.
3.3
5.0
-
Max.
5.5
Unit
Logic supply voltage
VDD1
V
V
Driver supply voltage
Gamma corrected voltage
Maximum clock frequency
Output load capacitance
VDD2
3.0
5.5
VGMA1 – VGMA11
VSS2
VDD2
55
V
fmax
CL
VDD1 = 3.3 V
-
MHz
pF / PIN
-
150
18
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
DC CHARACTERISTICS
Table 8. DC Characteristics (Ta = -20 to 75 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 3.0 to 5.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
VIH
Condition
Min.
0.7 VDD1
0
Typ.
Max.
VDD1
0.3 VDD1
0.5
Unit
V
High level input voltage
Low level input voltage
Input leakage current
-
-
-
SHL, CLK2, D00 – D25,
CLK1, DIO1 (DIO2)
VIL
IL
-0.5
mA
DIO1 (DIO2), VDD1=3.3V
IO = -1.0 mA
High level output voltage
VOH
VDD1 - 0.5
-
-
-
V
DIO1 (DIO2), VDD1=3.3V
IO = +1.0 mA
Low level output voltage
Resistor
VOL
R0 - R62
IVOH
-
0.5
Rn ´ 1.3
-0.5
Rn ´ 0.7
W
VDD2 = 5.0 V,
Vx = 3.5 V, Vyo = 4.5 V
-
-1.5
0.5
mA
Driver output current
VDD2 = 5.0 V,
Vx = 1.5 V, Vyo = 0.5 V
IVOL
0.5
-
mA
VSS2 + 0.2 V to
VDD2 - 1.5 V
Output voltage deviation
Output voltage range
DVO
Vyo
-
±10
-
±20
VDD2 - 0.2
5.5
mV
V
Input data: 00H to 3FH
VDD1 = 3.0 V (2)
VSS2 + 0.2
-
Logic part dynamic
current
IDD1
3.5
mA
VDD1 = 3.0 V,
VDD2 = 5.0 V,
VGMA1 = 4.5 V,
VGMA11 = 0.5 V
Driver part dynamic
current
IDD2
-
5.5
7.0
NOTES:
1. Vyo is the output voltage of analog output pins Y1 to Y309. Vx is the voltage applied to analog output pins Y1 to Y309.
2. CLK1 period is defined to be 30 ms at fCLK2 = 30 MHz, data pattern = 101010 , (checkerboard pattern), Ta = 25 °C
19
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
AC CHARACTERISTICS
Table 9. AC Characteristics (Ta = -20 to 75 °C, VDD2 = 3.0 to 5.5 V, VDD1 = 3.0 to 5.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
PWCLK
Condition
Min.
18
4
Typ.
Max.
Unit
Clock pulse width
Clock pulse low period
Clock pulse high period
Data setup time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PWCLK(L)
PWCLK(H)
tSETUP1
tHOLD1
-
(1)
4
4
(1)
(1)
(1)
ns
Data hold time
0
Start pulse setup time
Start pulse hold time
tSETUP2
tHOLD2
4
0
VDD1 = 3.3 V
CL = 35 pF
Start pulse delay time
CLK1 setup time
tPLH1
-
-
-
14
-
CLK2
period
tSETUP3
-
1
(2)
(3)
Driver output delay time1
Driver output delay time2
tPHL1
tPHL2
-
-
-
-
3
ms
10
CLK2
period
CLK1 pulse high period
Data invalid period
PWCLK1
tINV
-
2
-
-
CLK2
period
DIO1 (2) • ® CLK2•
1
Last data timing
CLK1-CLK2 time
tLDT
-
0
6
-
-
-
-
ns
ns
tCLK1–CLK2
CLK1• ® CLK2•
NOTES:
1. Input condition (VIH = 0.7 VDD1, VIL = 0.3 VDD1)
2. The value is specified when the drive voltage value reaches the target output voltage level of 90%
3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.
20
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
S6C0641
WAVEFORMS
Figure 5. Waveforms
21
S6C0641
6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND
BLANKING PERIOD
Figure 6. Waveforms
22
相关型号：
©2020 ICPDF网 联系我们和版权申明