MD2203-D576 [SANDISK]
Flash Memory Drive, CMOS, PDIP32, DIP-32;
| 型号： | MD2203-D576 |
| 厂家： | 
SANDISK CORPORATION |
| 描述： | Flash Memory Drive, CMOS, PDIP32, DIP-32 光电二极管 |
| 文件： | 总29页 (文件大小：323K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DiskOnChip 2000 DIP
From 16MByte to 1GByte
Data Sheet, March 2006
Highlights
DiskOnChip 2000 DIP is a member of
M-Systems’ family of DiskOnChip flash disk
products. It is available in densities of 16MByte
to 1GByte.
DiskOnChip 2000 DIP features:
Single-chip plug-n-play flash disk
TrueFFS Software
Low power, single 3.3V or 5V power
supply
Full hard-disk read/write emulation for
transparent file system management
16MByte (MB) to 1GByte (GB) density
Simple, easy-to-integrate interface
8KB sized memory window
Boot OS capability
Proprietary TrueFFS® technology for full
hard-disk emulation, high data reliability
and maximum flash lifetime
Identical software for all DiskOnChip
capacities
Patented methods to extend flash lifetime,
including:
Dynamic virtual mapping
Dynamic and static wear-leveling
Support for all major OSs, including:
VxWorks, Windows CE/.NET, Linux,
Windows NT/XP, QNX and others.
Software tools for programming,
duplicating, testing, and debugging
Operates with TrueFFS Software
Development Kit (SDK) in OS-less
environment.
Reliability
On-the-fly Reed-Solomon Error Detection
Code/Error Correction Code (EDC/ECC)
RoHS Support
Guaranteed data integrity, even after power
failure
RoHS version available (16MB-96MB)
Transparent bad-block management
Dynamic and static wear-leveling
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
Hardware Compatibility
32-pin DIP, JEDEC standard,
EEPROM-compatible pinout
Compatible with all major CPUs, including:
x86
StrongARM
XScale
Geode® SCxxxx
PowerPC™ MPC8xx
MediaGX
68K
MIPS
SuperH™ SH-x
8-bit, 16-bit and 32-bit bus architecture
support
Applications
Embedded systems
Internet access devices
Internet set-top boxes/ITV, Web browsers
WBT, thin clients, network computers
Routers, networking
Web phones, car PCs, DVD, HPC
Point of sale, industrial PCs
Telecom, medical
Densities
Low profile: 16, 32, 48, 64, 96, 128, 192, 256,
384MB
High profile: 576, 768, 1024MB
Commercial (0°C to 70°C) and extended
temperature range (-40°C to +85°C) for all
densities
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
TABLE OF CONTENTS
1. Introduction ...............................................................................................................................5
2. Product Overview......................................................................................................................6
2.1 Product Description ............................................................................................................6
2.2 I/O Operation......................................................................................................................7
2.3 Pin Diagram........................................................................................................................7
2.4 Signal Descriptions.............................................................................................................8
3. Theory of Operation ..................................................................................................................9
3.1 Overview.............................................................................................................................9
3.2 System Interface.................................................................................................................9
3.3 Boot Block ........................................................................................................................10
3.4 Error Detection Code/Error Correction Code (EDC/ECC)................................................10
3.5 Flash Control ....................................................................................................................10
4. Operating Modes.....................................................................................................................11
5. TrueFFS Technology...............................................................................................................12
5.1 General Description..........................................................................................................12
5.1.1 Built-In Operating System Support..................................................................................... 13
5.1.2 TrueFFS Software Development Kit (SDK)........................................................................ 13
5.1.3 File Management................................................................................................................ 13
5.1.4 Bad-Block Management..................................................................................................... 13
5.1.5 Wear-Leveling .................................................................................................................... 13
5.2 Power Failure Management .............................................................................................14
5.2.1 Error Detection/Correction.................................................................................................. 14
5.2.2 Special Features through I/O Control (IOCTL) Mechanism............................................... 15
5.2.3 Compatibility....................................................................................................................... 15
5.3 8KB Memory Window.......................................................................................................16
6. Booting from DiskOnChip 2000 .............................................................................................17
6.1 Introduction.......................................................................................................................17
6.2 Boot Procedure in PC-Compatible Platforms ...................................................................17
7. Design Considerations ...........................................................................................................19
7.1 Design Environment .........................................................................................................19
7.2 System Interface...............................................................................................................19
7.3 Connecting Signals...........................................................................................................20
7.4 Platform-Specific Issues...................................................................................................20
7.4.1 Wait State........................................................................................................................... 20
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
7.4.2 Big and Little Endian Systems............................................................................................ 20
7.4.3 Working with 8/16/32-Bit Systems...................................................................................... 21
8. Product Specifications ...........................................................................................................22
8.1 Environmental Specifications ...........................................................................................22
8.1.1 Temperature Ranges ......................................................................................................... 22
8.1.2 DiskOnChip Assembly........................................................................................................ 22
8.1.3 Humidity.............................................................................................................................. 22
8.1.4 Shock and Vibration ........................................................................................................... 22
8.2 Electrical Specifications....................................................................................................22
8.2.1 Absolute Maximum Ratings................................................................................................ 22
8.2.2 Capacitance........................................................................................................................ 23
8.2.3 DC Electrical Characteristics over Operating Range......................................................... 23
8.2.4 AC Operating Conditions.................................................................................................... 24
8.3 Timing Specifications........................................................................................................25
8.3.1 Read Cycle Timing............................................................................................................. 25
8.3.2 Write Cycle Timing ............................................................................................................. 26
8.4 Mechanical Dimensions....................................................................................................27
9. Ordering Information...............................................................................................................28
How to Contact Us ........................................................................................................................29
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
1.
INTRODUCTION
This data sheet includes the following sections:
Section 1:
Section 2:
Overview of data sheet contents
Product overview, including brief product description, a pin diagram and signal
descriptions
Section 3:
Section 4:
Section 5:
Section 6:
Section 7:
Theory of operation for the major building blocks
Modes of operation
Description of TrueFFS technology
Using DiskOnChip 2000 DIP as a boot device
Design considerations for implementing popular applications and for maximizing
built-in flexibility features
Section 8:
Environmental, mechanical, electrical and production specifications
To contact SanDisk’s worldwide offices for general information and technical support, please see
the listing on the back page, or visit SanDisk’s website (www.SanDisk.com).
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
2.
PRODUCT OVERVIEW
2.1 Product Description
The DiskOnChip 2000 product line is the second-generation of SanDisk’s DiskOnChip series of
products. The DiskOnChip 2000 series provides a small, single-chip, solid-state flash disk in a
standard 32-pin DIP package. Combining a disk controller with flash memory on a single chip,
DiskOnChip 2000 is the solution where minimal weight, space, and power consumption are
essential. DiskOnChip 2000 is used in a wide range of products, such as information appliances,
set-top boxes, thin clients, thin servers, network computers, and embedded, portable computers.
By placing DiskOnChip 2000 in a standard socket, physical space requirements are reduced. Unlike
standard IDE drives, no cables or extra space are required. DiskOnChip 2000 has no moving parts,
resulting in significantly decreased power consumption and increased reliability. It is easy to use
and reduces integration overhead. DiskOnChip 2000 is therefore a very attractive alternative to
conventional hard and floppy disk drives.
Using TrueFFS technology, DiskOnChip 2000 delivers full hard disk emulation. As such, the
design and integration stages can be considerably reduced, thereby enabling very fast time-to-
market and ease of production. Combined with its very attractive cost structure, DiskOnChip 2000
is a superior alternative to resident flash array (RFA).
DiskOnChip 2000 products are available in capacities ranging from 16MB to 1GB. DiskOnChip
technology provides broad support for all major operating systems and processors in the market,
enabling it to be readily integrated with any architecture.
DiskOnChip 2000 is shipped as a plug-and-play device that is fully tested and formatted, and
programmed with a DOS driver. Future driver, software or content upgrades, or formatting, can be
made on-board or off-board using DiskOnChip utilities and accessories provided by SanDisk.
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
2.2 I/O Operation
See Figure 1 for a simplified I/O diagram.
A[12:0]
D[7:0]
DiskOnChip 2000
OE#
WE#
CE#
Figure 1: Simplified I/O Diagram
2.3 Pin Diagram
1
NC
NC
NC
A12
A7
VCC
WE#
NC
NC
NC
A8
32
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
4
5
A6
6
A5
A9
7
A4
8
A11
OE#
A10
CE#
D7
DiskOnChip
2000 DIP
A3
9
A2
10
11
12
13
14
15
16
A1
A0
D0
D1
D2
VSS
D6
D5
D4
D3
Figure 2: Package Description and Pinout
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
2.4 Signal Descriptions
Table 1: DiskOnChip 2000 Signal Descriptions
Signal
Pin
Number
Input
Type
Description
Signal
Type
System Interface
Address signals
A[12:0] 4 to 12, 23,
25 to 27
ST
IN
Input
D[7:0]
13 to 15,
17 to 21
Data signals
Input/
Output
CE#
OE#
WE#
22
24
31
ST
ST
ST
Chip Enable, active low
Output Enable, active low
Write Enable, active low
Power
Input
Input
Input
VCC
VSS
32
16
-
-
Device supply
Ground
Supply
Supply
Other
NC
1, 2, 3, 28,
29, 30
-
Not Connected. These pins should be left floating. Absolute
maximum ratings must be observed.
The following abbreviations are used:
1. IN: Standard (non-Schmidt) input
2. ST: Schmidt Trigger input
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
3.
THEORY OF OPERATION
3.1 Overview
DiskOnChip 2000 consists of the following major functional blocks, as shown in Figure 3:
•
•
System Interface for host interface.
Boot Block that contains IPL ROM required for recognition during BIOS expansion search in
PC architectures.
•
•
Reed-Solomon-based Error Detection and Error Correction Code (EDC/ECC) for on-the-
fly error handling.
Flash Control block that contains registers responsible for transferring the address, data and
control information between the TrueFFS driver and the flash media.
CE#
WE#
Flash
Control
System
Interface
OE#
Flash
D[0:7]
A[0:12]
Boot Block
(IPL ROM)
EDC/ECC
Figure 3: DiskOnChip 2000 Simplified Block Diagram
3.2 System Interface
The system interface block provides an easy-to-integrate SRAM-like (also EEPROM-like) interface
to DiskOnChip 2000, enabling it to interface with various CPU interfaces, such as a local bus, ISA
bus, SRAM interface, EEPROM interface or any other compatible interface.
A 13-bit wide address bus enables access to the DiskOnChip 8KB memory window (as shown in
Figure 5). The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger
read and write cycles. A write cycle occurs while both the CE# and the WE# inputs are asserted.
Similarly, a read cycle occurs while both the CE# and OE# inputs are asserted. Note that
DiskOnChip 2000 does not require a clock signal. The CE#, WE# and OE# signals trigger the
controller (e.g., system interface block, bus control and data pipeline) and flash access.
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
3.3 Boot Block
The boot block is responsible for answering the BIOS expansion search in PC architectures. After
the BIOS identifies DiskOnChip 2000 as a valid BIOS expansion device, it executes the code stored
in the boot block. The BIOS then loads the TrueFFS software from the flash memory into the host
memory, delivering full disk capabilities to the operating system. This code is identical for all
DiskOnChip 2000 capacities, since TrueFFS automatically detects the memory density of
DiskOnChip 2000.
3.4 Error Detection Code/Error Correction Code (EDC/ECC)
NAND flash, being an imperfect memory, requires error handling. DiskOnChip 2000 implements
Reed-Solomon Error Detection Code (EDC). A hardware-generated, 6-byte error detection
signature is computed each time a page (512 bytes) is written to or read from DiskOnChip 2000.
The TrueFFS driver implements complementary Error Correction Code (ECC). Unlike error
detection, which is required on every cycle, error correction is relatively seldom required, hence
implemented in software. The combination of DiskOnChip’s built-in EDC mechanism and the
TrueFFS driver ensures highly reliable error detection and correction, while providing maximum
performance.
The following detection and correction capability is provided for each 512 bytes:
•
•
•
•
Corrects up to two 10-bit symbols, including two random bit errors.
Corrects single bursts up to 11 bits.
Detects single bursts up to 31 bits and double bursts up to 11 bits.
Detects up to 4 random bit errors.
3.5 Flash Control
The Flash Control block contains registers responsible for transferring the address, data and control
information between the DiskOnChip TrueFFS driver and the flash media. Additional registers are
used to monitor the status of the flash media (ready/busy) and of the DiskOnChip controller.
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
4.
OPERATING MODES
DiskOnChip 2000 can operate in two modes:
•
•
Normal: The device responds to every valid hardware cycle. While in this mode, all sections
respond to valid read and write cycles.
Reset: The device ignores all write cycles (except for the “leave Reset mode” sequence), and
returns predetermined values for all read cycles.
Mode changes can occur due to any of the following events:
o
o
A valid write sequence to the Control register
Triggering the Boot Detector circuit, which enables automatic driver loading in a PC
environment.
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
5.
TRUEFFS TECHNOLOGY
5.1 General Description
SanDisk’s patented TrueFFS technology was designed to maximize the benefits of flash memory
while overcoming inherent flash limitations that would otherwise reduce its performance, reliability
and lifetime. TrueFFS emulates a hard disk, making it completely transparent to the OS. In addition,
since it operates under the OS file system layer (see Figure 4), it is completely transparent to the
application.
Application
OS File System
TrueFFS
DiskOnChip
Figure 4: TrueFFS Location in System Hierarchy
TrueFFS technology support includes:
•
•
•
•
Binary driver support for all major OSs
TrueFFS Software Development Kit (SDK)
Boot Software Development Kit (BDK)
Support for all major CPUs, including 8-, 16- and 32-bit bus architectures
TrueFFS technology features:
•
•
•
•
•
•
•
•
•
Block device API
Flash file system management
Bad-block management
Dynamic virtual mapping
Dynamic and static wear-leveling
Power failure management
Implementation of Reed-Solomon EDC/ECC
Performance optimization
Compatible with all DiskOnChip products
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
5.1.1 Built-In Operating System Support
The TrueFFS driver is integrated into all major OSs, including: Windows CE/NT/NT
Embedded/XP, Linux (various kernels), VxWorks, Nucleus, QNX, DOS, Symbian, and others. For
a complete listing of all available drivers, please refer to SanDisk’s website www.SanDisk.com. It
is advised to use the latest driver versions that can be downloaded from the DiskOnChip 2000 web
page on the SanDisk site.
5.1.2 TrueFFS Software Development Kit (SDK)
The basic TrueFFS Software Development Kit (SDK) provides the source code of the TrueFFS
driver. It can be used in an OS-less environment or when special customization of the driver is
required for proprietary OSs.
5.1.3 File Management
TrueFFS accesses the flash memory within DiskOnChip 2000 through an 8KB window in the CPU
memory space. It provides block device API, by using standard file system calls, identical to those
used by a mechanical hard disk, to enable reading from and writing to any sector on DiskOnChip
2000. This makes it compatible with any file system and file system utilities such as diagnostic tools
and applications. When using the File Allocation Table (FAT) file system, the data stored on
DiskOnChip 2000 uses FAT-16.
Note: DiskOnChip 2000 is shipped formatted, and contains the FAT file system.
5.1.4 Bad-Block Management
NAND flash, being an imperfect storage media, contains some bad blocks that cannot be used for
storage because of their high error rates. TrueFFS automatically detects and maps bad blocks upon
system initialization, ensuring that they are not used for storage. This management process is
completely transparent to the user, who remains unaware of the existence and location of bad
blocks, while remaining confident of the integrity of data stored. The Bad Block Table in
DiskOnChip 2000 DIP is stored in a protected area for ensured reliability.
5.1.5 Wear-Leveling
Flash memory can be erased a limited number of times. This number is called the erase cycle limit
or write endurance limit and is defined by the flash array vendor. The erase cycle limit applies to
each individual erase block in the flash device. After reaching the cycle limit, as given by the flash
vendor, the erase block begins to make storage errors at a rate significantly higher than the error rate
that is typical to the flash.
In a typical application and especially if a file system is used, a specific page or pages are constantly
updated (e.g., the page/s that contain the FAT, registry etc.). Without any special handling, these
pages would wear out more rapidly than other pages, reducing the lifetime of the entire flash.
To overcome this inherent deficiency, TrueFFS uses SanDisk’s patented wear-leveling algorithm.
The wear-leveling algorithm ensures that consecutive writes of a specific sector are not written
physically to the same page in the flash. This spreads flash media usage evenly across all pages,
thereby maximizing flash lifetime. TrueFFS wear-leveling extends the flash lifetime 10 to 15 years
beyond the lifetime of a typical application.
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
Dynamic Wear-Leveling
TrueFFS uses statistical allocation to perform dynamic wear-leveling on newly written data. This
not only minimizes the number of erase cycles per block, it also minimizes the total number of erase
cycles. Because a block erase is the most time-consuming operation, dynamic wear-leveling has a
major impact on overall performance. This impact cannot be noticed during the first write to flash
(since there is no need to erase blocks beforehand), but it is more and more noticeable as the flash
media becomes full.
Static Wear-Leveling
Areas on the flash media may contain static files, characterized by blocks of data that remain
unchanged for very long periods of time, or even for the whole device lifetime. If wear-leveling
were only applied on newly written pages, static areas would never be cycled. This limited
application of wear-leveling would lower life expectancy significantly in cases where flash memory
contains large static areas. To overcome this problem, TrueFFS forces data transfer in static areas as
well as in dynamic areas, thereby applying wear-leveling to the entire media.
5.2 Power Failure Management
TrueFFS uses algorithms based on “erase after write” instead of "erase before write" to ensure data
integrity during normal operation and in the event of a power failure. Used areas are reclaimed for
erasing and writing the flash management information into them only after an operation is
complete. This procedure serves as a check on data integrity.
The “erase after write” algorithm is also used to update and store mapping information on the flash
memory. This keeps the mapping information coherent even during power failures. The only
mapping information held in RAM is a table pointing to the location of the actual mapping
information. This table is reconstructed during power-up or after reset from the information stored
in the flash memory.
To prevent data from being lost or corrupted, TrueFFS uses the following mechanisms:
•
•
When writing, copying, or erasing the flash device, the data format remains valid at all
intermediate stages. Previous data is never erased until the operation has been completed and
the new data has been verified.
A data sector cannot exist in a partially written state. Either the operation is successfully
completed, in which case the new sector contents are valid, or the operation has not yet been
completed or has failed, in which case the old sector contents remain valid.
5.2.1 Error Detection/Correction
TrueFFS implements a Reed-Solomon Error Correction Code (ECC) algorithm to ensure data
reliability. Refer to Section 3.4 for further information on the EDC/ECC mechanism.
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
5.2.2 Special Features through I/O Control (IOCTL) Mechanism
In addition to standard storage device functionality, the TrueFFS driver provides extended
functionality. This functionality goes beyond simple data storage capabilities to include features
such as: format the media, binary partition(s) access, flash defragmentation, and other options. This
unique functionality is available in all TrueFFS-based drivers through the standard I/O control
command of the native file system.
For further information, please refer to application note AP-DOC-046, Extended Functions of the
TrueFFS Driver for DiskOnChip.
5.2.3 Compatibility
The TrueFFS driver supports all released DiskOnChip products. Upgrading from one product to
another requires no additional software integration.
When using different drivers (e.g. TrueFFS SDK, BDK, BIOS extension firmware, etc.) to access
DiskOnChip, the user must verify that all software is based on the same code base version. It is also
important to use only tools (e.g. DFORMAT, DINFO, GETIMAGE, etc.) derived from the same
version as the firmware version and the TrueFFS drivers used in the application. Failure to do so
may lead to unexpected results, such as lost or corrupted data. The driver and firmware version can
be verified by the sign-on messages displayed, or by the version information stored in the driver or
tool.
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
5.3 8KB Memory Window
The DiskOnChip 2000 memory map occupies a total address space of 8KB. This space consists of
four 2KB sections, as shown in Figure 5and described below.
•
Section 0: Boot Block
This section includes data that is typically used for booting code from the CPU. The available
size is 64 bytes, aliased 32 times in the 2KB section. The second half of the boot block is
located in Section 2.
•
Section 1: Boot Block
This section includes the second 64 bytes of the Boot Block. The first 64 bytes can be found in
Section 0, aliased 32 times.
•
•
Section 2: Control Registers
Used to control the behavior of DiskOnChip 2000 and the flash media.
Section 3: Flash Area Window
Used as a window to the flash media for data to be written or read.
Reset Mode
Normal Mode
000H
800H
Boot
Block
Boot
Block
Section 0
Section 1
Section 2
Boot
Block
Boot
Block
1000H
1800H
Control
Registers
00H
00H
Flash Area
Window
Section 3
Figure 5: DiskOnChip 2000 Memory Map
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
6.
BOOTING FROM DISKONCHIP 2000
6.1 Introduction
DiskOnChip 2000 can operate as the OS boot device. The DiskOnChip default firmware contains
drivers to enable it to perform as the OS boot device under DOS. For other OSs, please refer to the
TrueFFS driver readme file.
6.2 Boot Procedure in PC-Compatible Platforms
When used in PC-compatible platforms, DiskOnChip 2000 is connected to an 8KB memory
window in the BIOS expansion memory range, typically located between 0C8000H to 0EFFFFH.
During the boot process, the BIOS loads the TrueFFS firmware into the PC memory and installs
DiskOnChip 2000 as a disk drive in the system. When the operating system is loaded, DiskOnChip
2000 is recognized as a standard disk. No external software is required to boot from DiskOnChip
2000. Figure 6 illustrates the location of the DiskOnChip 2000 memory window in the PC memory
map.
Extended Memory
1M
0FFFFFH
BIOS
0F0000H
8k
DiskOnChip
Display
0C8000H
0B0000H
640k
RAM
0
Figure 6: DiskOnChip 2000 Memory Window in the PC Memory Map
After reset, the BIOS code first executes the Power On Self-Test (POST) and then searches for all
expansion ROM devices. When DiskOnChip 2000 is found, the BIOS code executes from it the IPL
(Initial Program Loader) code, located in the boot block. This code loads the TrueFFS driver into
system memory, installs DiskOnChip 2000 as a disk in the system, and then returns control to the
BIOS code. The operating system subsequently identifies DiskOnChip 2000 as an available disk.
TrueFFS responds by emulating a hard disk.
From this point onward, DiskOnChip 2000 appears as a standard disk drive. It is assigned a drive
letter and can be used by any application, without any modifications to either the BIOS set-up or the
autoexec.bat/config.sys files. DiskOnChip 2000 can be used as the only disk in the system, with or
without a floppy drive, and with or without hard disks.
The drive letter assigned depends on how DiskOnChip 2000 is used in the system, as follows:
•
If DiskOnChip 2000 is used as the only disk in the system, the system boots directly from it
and assigns it drive C.
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Data Sheet, Rev. 3.9
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DiskOnChip 2000 DIP
•
•
If DiskOnChip 2000 is used with other disks in the system:
o
DiskOnChip 2000 can be configured as the last drive (the default configuration). The
system assigns drive C to the hard disk and drive D to DiskOnChip 2000.
o
Alternatively, DiskOnChip 2000 can be configured as the system’s first drive. The system
assigns drive D to the hard disk and drive C to DiskOnChip 2000.
If DiskOnChip 2000 is used as the OS boot device when configured as drive C, it must be
formatted as a bootable device by copying the OS files onto it. This is done by using the SYS
command when running DOS.
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Data Sheet, Rev. 3.9
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DiskOnChip 2000 DIP
7.
DESIGN CONSIDERATIONS
7.1 Design Environment
DiskOnChip 2000 provides a complete design environment consisting of:
•
Evaluation Boards (EVBs) for enabling software integration and development with
DiskOnChip 2000, even before the target platform is available. An EVB with an ISA standard
connector and a PCI standard connector for immediate plug and play usage are available.
•
Programming solutions:
o
o
o
GANG programmer
Programming house
On-board programming
•
•
•
•
•
•
TrueFFS Software Development Kit (SDK) and BDK
DOS utilities:
DFORMAT
GETIMG/PUTIMG
DINFO
Documentation:
o
o
o
o
o
Data sheet
Application notes
Technical notes
Articles
White papers
Please visit SanDisk’s website (www.SanDisk.com) for the most updated documentation, utilities
and drivers.
7.2 System Interface
DiskOnChip 2000 uses an SRAM-like interface that can easily be connected to any microprocessor
bus. With a standard interface, it requires 13 address lines, 8 data lines and basic memory control
signals (CE#, OE#, WE#), as shown in Figure 7 below. Typically, DiskOnChip 2000 can be
mapped to any free 8KB memory space. In a PC-compatible platform, it is usually mapped into the
BIOS expansion area. If the allocated memory window is larger than 8KB, an automatic anti-
aliasing mechanism prevents the firmware from being loaded more than once during the ROM
expansion search.
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Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
3.3V or 5V
0.1 uF
10 nF
VCC
Address
Data
A[12:0]
D[7:0]
DiskOnChip 2000
Output Enable
Write Enable
Chip Enable
OE#
WE#
CE#
VSS
Figure 7: DiskOnChip 2000 System Interface
Notes: 1. The 0.1 µF and the 10 nF low-inductance high-frequency capacitors must be attached to
each of the device’s VCC and VSS pins.
2. DiskOnChip 2000 is an edge-sensitive device. CE#, OE# and WE# should be
properly terminated (according to board layout, serial parallel, or both terminations)
to avoid signal ringing.
7.3 Connecting Signals
DiskOnChip 2000 uses standard SRAM-like control signals, which should be connected as follows:
•
•
•
Address (A[12:0]) – Connect these signals to the host address bus.
Data (D[7:0]) – Connect these signals to the host data bus.
Write (WE#) and Output Enable (OE#) – Connect these signals to the host WR# and RD#
signals, respectively.
•
Chip Enable (CE#) – Connect this signal to the memory address decoder.
7.4 Platform-Specific Issues
The following section describes hardware design issues.
7.4.1 Wait State
Wait states can be implemented only when DiskOnChip 2000 is designed in a bus that supports a
Wait state insertion, and supplies a WAIT signal.
7.4.2 Big and Little Endian Systems
PowerPC, ARM, and other RISC processors can use either Big or Little Endian systems.
DiskOnChip 2000 uses the Little Endian system. Therefore, byte D[7:0] is its Least Significant Byte
(LSB); bit D0 is the least significant bit within that byte. When connecting DiskOnChip 2000 to a
20
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
device that supports Big Endian systems, make sure to that the bytes of the CPU and DiskOnChip
2000 match.
Note: Processors, such as the PowerPC, also change the bit ordering within the bytes. Failing to
follow these rules results in improper connection of DiskOnChip 2000, and prevents the
TrueFFS driver from identifying DiskOnChip 2000.
7.4.3 Working with 8/16/32-Bit Systems
The TrueFFS driver supports 8-bit, 16-bit, and 32-bit bus architectures. Support for the 16-bit and
32-bit bus architectures, typically used in RISC processors, can be achieved by using the LSB of the
data bus as follows:
•
For 16-bit address boundary shifts, shift the address lines by one, so that the host address line
A1 connects to DiskOnChip 2000 address line A0, the host address line A2 connects to
DiskOnChip 2000 line A1, and so on.
•
For 32-bit address boundary shifts, shift the address lines by two, so that the host address line
A2 connects to DiskOnChip 2000 address line A0, the host address line A3 connects to
DiskOnChip 2000 line A1, and so on.
21
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
8.
PRODUCT SPECIFICATIONS
8.1 Environmental Specifications
8.1.1 Temperature Ranges
•
•
•
Commercial operating temperature: 0ºC to +70ºC
Extended operating temperature: -40ºC to +85ºC
Storage temperature: -50ºC to +85ºC
8.1.2 DiskOnChip Assembly
The DiskOnChip 2000 DIP device is not hermetically sealed. Therefore, it must be assembled after
the PCB goes through its final rinse. Assembling DiskOnChip 2000 prior to the rinse phase may
cause it to absorb moisture. Failure to adhere to the above assembly instruction can lead to device
failures not covered by SanDisk’s warranty.
Note: DiskOnChip 2000 DIP requires a DIP socket on the target platform. Due to its plastic shell
and molding material, it cannot be soldered directly to the platform.
8.1.3 Humidity
10% - 90% relative, non-condensing
8.1.4 Shock and Vibration
Table 2: Reliability Tests
Reliability Test
Vibration
Test Conditions
Reference Standard
100 ~ 2000 Hz, 15 G peak, 3 cycles per axis (1hr.), 3 STD-202F, Method 204D
axes
Mechanical Shock
Half-sine shock 50 G, 11 msec, ±3 shocks per axis, 3 STD-202F, Method 213B
axes
8.2 Electrical Specifications
8.2.1 Absolute Maximum Ratings
Table 3: Maximum Ratings
Parameter
DC supply voltage
Input pin voltage2
Input pin current
Power Dissipation
Symbol
VCCS
VIN
3.3V Model Rating1
-0.5 to 4.6
5V Model Rating1
-0.3 to 6.0
Units
V
Notes
-0.5 to VCC + 0.3
Not Specified
1.3
-0.3 to VCC + 0.3
-10 to 10
V
IIN
mA
Watt
+25°C
PD
2.0
1.
2.
3.
The voltage on any pin may undershoot to -2.0V or overshoot to Vcc+2.0V for periods <20 ns.
The unit shall be supplied from limited power source, which meets the requirements, detailed in clause 2.5 of UL 60950-1.
Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
In order to protect DiskOnChip 2000 when it is exposed to overcurrent, a fuse may be added, or
modifications to the power supply’s overcurrent protection mechanism may be considered.
22
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
Figure 8 illustrates the suggested overcurrent protection for DiskOnChip 2000.
Figure 8: Protecting DiskOnChip 2000 from Overcurrent
8.2.2 Capacitance
Table 4: Input/Output Capacitance
Symbol
Parameter
Conditions
3.3V Model Rating 5V Model Rating
Unit
pF
MD2200/2, VIN = 0V
MD2203, VIN = 0V
12
36
15
45
Input/Output
Capacitance
CI/O
pF
Note: Capacitance is not 100% tested.
8.2.3 DC Electrical Characteristics over Operating Range
Table 5: Vcc = 5V Characteristics
Symbol
VCCS
Vih
Parameter
Conditions
Min
4.5
2.0
Typ Max
Unit
System Supply Voltage1
High-level Input Voltage
Low-level Input Voltage
High-level Output Voltage
Low-level Output Voltage
5.0
5.5
V
V
Vil
0.8
V
Voh
IOH = -16 mA
IOL = 16 mA
2.4
V
VOL
0.4
±10
±30
±10
±30
60
V
MD2200, MD2202
MD2203
µA
µA
µA
µA
mA
µA
µA
IIL
Input Leakage Current
Output Leakage Current
MD2200, MD2202
MD2203
IOZ
Ivcc
Supply Current
Standby Current
200 ns Cycle Time, outputs open
MD2200, MD2202
MD2203
40
60
400
Istdby
240 1200
Note: The supply voltage of the extended temperature products listed below is Vcc = 5V ± 0.25V:
MD2202-D192-X, MD2202-D256-X, MD2202-D384-X, MD2203-D576-X, MD2203-D768-X, MD2203-
D1024-X
Table 6: Vcc = 3.3V Characteristics
Symbol
VCCS
Vih
Parameter
Conditions
Min
3.0
2.7
Typ
Max
Unit
V
System Supply Voltage1
High-level Input Voltage
Low-level Input Voltage
3.3
3.6
V
Vil
0.6
V
23
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
VHYS
Voh
Input Voltage Hysteresis
1.1
2.4
1.5
V
V
IOH = -18 mA
IOH = 0 mA
High-level Output
Voltage
Vcc-0.1
V
IOL = 18 mA
IOL = 0 mA
0.4
0.1
V
VOL
Low-level Output Voltage
Input Leakage Current
Output Leakage Current
V
MD2200, MD2202
MD2203
µA
µA
µA
µA
±10
±30
±10
±30
IIL
MD2200, MD2202
MD2203
IOZ
150 ns Cycle Time, outputs
open
Ivcc
Supply Current
Standby Current
30
60
mA
MD2200, MD2202
MD2203
70
400
µA
µA
Istdby
300
1350
Note: The supply voltage of the extended temperature products listed below is Vcc = 3. 3V ± 0.15V:
MD2202-D192-V3-X, MD2202-D256-V3-X, MD2202-D384-V3-X, MD2203-D576-V3-X, MD2203-D768-V3-
X, MD2203-D1024-V3-X
8.2.4 AC Operating Conditions
Timing specifications are based on the following conditions:
Table 7: AC Operating Conditions
Parameter
Supply Voltage1,2
3.3V Model
VCC = 3.3V ±0.3V
0.2V to 2.9V
1 ns
5V Model
VCC = 5V ±0.5V
0.4V to 2.6V
5 ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
1.5V
0.8V and 2.0V
50 pF
100 pF
Notes: 1. The supply voltage of the extended temperature products listed below is Vcc = 3. 3V ±
0.15V: MD2202-D192-V3-X, MD2202-D256-V3-X, MD2202-D384-V3-X, MD2203-
D576-V3-X, MD2203-D768-V3-X, MD2203-D1024-V3-X
2. The supply voltage of the extended temperature products listed below is Vcc = 5V ±
0.25V: MD2202-D192-X, MD2202-D256-X, MD2202-D384-X, MD2203-D576-X,
MD2203-D768-X, MD2203-D1024-X
24
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
8.3 Timing Specifications
8.3.1 Read Cycle Timing
TSU(A)
A[0..12]
CE#
TSU(CE1)
THO(CE1)
OE#
TSU(CE0)
THO(CE0)
TREC
TACC
WE#
TDIS(D)
TEN(D)
D[0..7]
Figure 9: Read Cycle
Table 8: Read Cycle Timing
3.3V
5V
Symbol
Description
Notes
Min (ns)
Max (ns)
Min (ns)
Max (ns)
TSU(A)
THO(A)
Address to OE# È setup
OE#È to Address hold
2
35
0
10
56
0
TSU(CE0) CE# È to OE# È setup
1
2
THO(CE0) OE#Ç to CE# = 0 hold
0
0
THO(CE1) OE# or WE#Ç to CE# = 1 hold
TSU(CE1) CE#Ç to WE# or OE#È setup time
8
42
42
59
8
TREC
OE#Ç to start of next cycle
Read access time
20
Tacc
110
75
130
91
Ten(D)
Tdis(D)
OE#È to D active delay
OE#Ç to D Hi-Z delay
15
7
13
44
1.
CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be
referenced instead to the time CE# was asserted.
2.
CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to OE# negated will be
referenced instead to the time CE# was negated.
25
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
8.3.2 Write Cycle Timing
TSU(A)
THO(A)
A[0..12]
THO(CE1)
CE#
OE#
T
SU(CE1)
THO(CE0)
THO(CE0)
TW(WE)
TREC
WE#
THO(D)
TSU(D)
D[0..7]
Figure 10: Write Cycle
Table 9: Write Cycle Timing
Symbol
Description
3.3V
5V
Notes
Min (ns) Max (ns) Min (ns) Max (ns)
TSU(A)
Address to WE#È setup time
WE#È to Address hold time
WE# asserted width
0
35
62
0
10
56
98
0
THO(A)
TW(WE)
TSU(CE0) CE#È to WE#È setup time
1
2
THO(CE0) WE#Ç to CE# = 0 hold time
THO(CE1) OE# or WE#Ç to CE# = 1 hold time
TSU(CE1) CE#Ç to WE# or OE#È setup time
0
0
8
42
42
59
48
40
8
TREC
TSU(D)
THO(D)
1.
WE#Ç to start of next cycle
D to WE#Ç setup time
WE#Ç to D hold time
22
50
0
CE# may be asserted any time before or after WE# is asserted. If CE# is asserted after WE#, all timing relative to WE# asserted will be
referenced instead to the time CE# was asserted.
2.
CE# may be negated any time before or after WE# is negated. If CE# is negated before WE#, all timing relative to WE# negated will
be referenced instead to the time CE# was negated.
26
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
8.4 Mechanical Dimensions
Figure 11: MD220x Mechanical Dimensions
Table 10: Low-Profile
MD2200
MD2202
Millimeters (max.)
Millimeters (max.)
A
B
C
D
E
F
41.9
18.05
2.54
15.24
5.7
43.95
18.3
2.54
15.24
6.0
4.0
4.0
G
H
0.51
38.2
0.51
38.2
Table 11: High-Profile
MD2203
Millimeters (max.)
A
45.6
18.8
2.54
15.24
13.5
4.0
B
C
D
E
F
G
H
0.51
38.2
Note: The above dimensions are maximum values.
27
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
9.
ORDERING INFORMATION
MD2202-DCCC-V-T-P (Low-Profile)
CCC: Density (MB)
16, 32, 48, 64, 96, 128, 192, 256, 384
V:
T:
P:
Supply Voltage
Blank
V3
5V
3.3V
Temperature Range
(optional)
Blank
X
Commercial: 0°C to +70°C
Extended: -40°C to +85°C
RoHS Compliance
(Optional)
Blank
P
Pb
RoHS compliance (available only in 16,
32, 48, 64, and 96MB)
MD2203-DCCC-V-T (High-Profile)
CCC: Density (MB)
576, 768, 1024
V:
Supply Voltage
Blank
V3
5V
3.3V
T:
Temperature Range
(optional)
Blank
X
Commercial: 0°C to +70°C
Extended: -40°C to +85°C
28
Data Sheet, Rev. 3.9
91-SR-002-42-8L
DiskOnChip 2000 DIP
HOW TO CONTACT US
SanDisk Corporation
Corporate Headquarters • 601 McCarthy Blvd. • Milpitas, CA 95035
Phone (408) 801-1000 • Fax (408) 801-8657
www.SanDisk.com
SanDisk® Corporation general policy does not recommend the use of its products in life
support applications where in a failure or malfunction of the product may directly threaten
life or injury. Per SanDisk Terms and Conditions of Sale, the user of SanDisk products in life
support applications assumes all risk of such use and indemnifies SanDisk against all
damages. See “Disclaimer of Liability.”
This document is for information use only and is subject to change without prior notice.
SanDisk Corporation assumes no responsibility for any errors that may appear in this
document, nor for incidental or consequential damages resulting from the furnishing,
performance or use of this material. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrievable manner or translated into any language or
computer language, in any form or by any means, electronic, mechanical, magnetic,
optical, chemical, manual or otherwise, without the prior written consent of an officer of
SanDisk Corporation.
All parts of the SanDisk documentation are protected by copyright law and all rights are
reserved.
SanDisk and the SanDisk logo are registered trademarks of SanDisk Corporation.
CompactFlash is a U.S. registered trademark of SanDisk Corporation.
Product names mentioned herein are for identification purposes only and may be
trademarks and/or registered trademarks of their respective companies.
© 2007 SanDisk Corporation. All rights reserved.
SanDisk products are covered or licensed under one or more of the following U.S. Patent
Nos. 5,070,032; 5,095,344; 5,168,465; 5,172,338; 5,198,380; 5,200,959; 5,268,318;
5,268,870; 5,272,669; 5,418,752; 5,602,987. Other U.S. and foreign patents awarded and
pending.
Lit. No. 91-SR-002-42-8L Rev. 3.9
Printed in U.S.A.
29
Data Sheet, Rev. 3.9
91-SR-002-42-8L
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