LC35W1000BTS-70U [SANYO]
Asynchronous Silicon Gate 1M (131,072 words x 8 bits) SRAM; 异步硅栅1M （ 131,072字× 8位） SRAM
| 型号： | LC35W1000BTS-70U |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | Asynchronous Silicon Gate 1M (131,072 words x 8 bits) SRAM |
| 文件： | 总9页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : ENN*6624
CMOS IC
LC35W1000BM, BTS-70U/10U
Asynchronous Silicon Gate
1M (131,072 words × 8 bits) SRAM
Preliminary
Overview
The LC35W1000BM and LC35W1000BTS-70U/10U are
asynchronous silicon gate CMOS static RAM devices with
a 131,072-word by 8-bit structure. They provide two chip
enable pins (CE1 and CE2) for device select/deselect
control and one output enable pin (OE) for output control.
They feature high speed, low power, and a wide operating
temperature range.This makes them optimal for use in
systems that require high speed, low power, and battery
backup. They also support easy memory expansion.
Package Dimensions
unit: mm
3205A-SOP32
[LC35W1000BM-70U/10U]
20.5
17
32
Features
1
• Low-voltage operation: 2.7 to 3.6 V
• Wide operating temperature range: –40 to +85°C
• Access time:
16
1.27
0.4
0.15
(0.73)
70 ns (maximum):
LC35W1000BM and LC35W1000BTS-70U.
100 ns (maximum):
LC35W1000BM and LC35W1000BTS-10U.
• Low current drain
SANYO: SOP32
unit: mm
3228A-TSOP32DA
[LC35W1000BTS-70U/10U]
Standby mode: 0.1 µA (typical*) at Ta = +25°C
10.0 µA (maximum) at Ta = –40 to +70°C
20.0 µA (maximum) at Ta = –40 to +85°C
• Data retention voltage: 2.0 to 3.6 V
• No clock required (fully static circuits)
• Input/output shared function pins, 3-state output pins
• Package
8.0
32
17
32-pin SOP (525 mil) plastic package:
LC35W1000BM
32-pin TSOP (8 × 14 mm) plastic package (Normal):
LC35W1000BTS
1
16
0.2
0.5
0.125
(0.25)
SANYO: TSOP32DA
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
41902RM (OT) No. 6624-1/9
LC35W1000BM, BTS-70U/10U
Pin Assignment
A13488
A13487
No. 6624-2/9
LC35W1000BM, BTS-70U/10U
Block Diagram
Memory cell array
Output
buffer
Data control circuit
Input
data
buffer
Pin Functions
A0 to A16
WE
Address input
Ready/write control input
Output enable input
Chip enable input
Data I/O
OE
Control
circuit
CE, CE2
I/O1 to I/O8
VCC, GND
Power supply, ground
Function Table
Mode
CE1
CE2
H
OE
L
WE
I/O
Supply current
Ready cycle
Write cycle
Output disable
L
L
H
L
Data output
Data input
ICCA
ICCA
ICCA
ICCS
ICCS
H
X
L
H
H
X
H
X
X
High impedance
High impedance
High impedance
H
X
X
Unselected
L
X
Note: X indicates H or L.
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Input pin voltage
Symbol
Conditions
Ratings
Unit
V
VCC max
4.6
VIN
–0.3* to VCC + 0.3
–0.3 to VCC + 0.3
–40 to +85
V
I/O pin voltage
VI/O
V
Operating temperature
Topr
Tstg
°C
°C
Storage temperature
–55 to +125
*: For pulse widths under 30 ns: –2.0 V
Note: This chip may be destroyed if any stress in excess of the absolute maximum ratings is applied.
No. 6624-3/9
LC35W1000BM, BTS-70U/10U
DC Allowable Operating Range at Ta = –40 to +85°C
Ratings
typ
Parameter
Symbol
Conditions
Unit
min
2.7
max
3.6
Supply volgate
VCC
VIH
VIL
3.3
V
V
V
High-level input voltage
Low-level input voltage
0.8VCC
VCC + 0.3
0.2VCC
–0.3*
Note: * The minimum value is –3.0 V for pulse width under 50 ns.
DC Electrical Characteristics at Ta = –40 to +85°C, V = 2.7 to 3.6 V
CC
Ratings
typ
Parameter
Input leakage current
I/O leakage current
Symbol
ILI
Conditions
Unit
µA
min
max
+1.0
VIN = 0 to VCC
VCE1 = VIH or VCE2 = VIL or VOE = VIH or
WE = VIL, VI/O = 0 to VCC
–1.0
ILO
–1.0
+1.0
µA
V
VOH1
VOH2
VOL1
VOL2
ICCA2
VOH1 = –2.0 mA
VCC – 0.4
VCC – 0.1
V
V
Outpu high-level voltage
Outpu low-level voltage
VOH2 = –100 µA
VOL1 = 2.0 mA
0.4
0.1
1.2
V
VOL2 = –100 µA
V
Operating supply current
(CMOS inputs)
VCE1 = VIL, VCE2 = VIH, II/O = 0 mA, VIN = VIH or VIL
mA
VCE1 = VIL, VCE2 = VIH
II/O = 0 mA, VIN = VIH or VIL
,
min cycle
70 ns
100 ns
25
20
ICCA3
,
mA
DUTY100%
1 µs cycle
2
Standby mode supply current
(VCC – 0.2 V/0.2 V inputs)
V
CE2 ≤ 0.2 V or
(VCE1 ≥ VCC – 0.2 V,
CE2 ≥ VCC – 0.2 V)
VCE1 = VIH or VCE2 = VIL, VIN = 0 to VCC
Ta ≤ 85°C
Ta ≤ 70°C
Ta ≤ 25°C
20
10
ICCS1
µA
V
0.1
(CMOS inputs)
ICCS2
0.4
mA
Note: * Reference values when VCC = 3.0 V and Ta = 25°C.
I/O Capacitances at Ta = 25°C, f = 1 MHz
Ratings
Parameter
Symbol
Conditions
Unit
min
typ
6
max
10
Input capacitance
I/O capacitance
CIN
VIN = 0 V
VI/O = 0 V
pF
pF
CI/O
6
10
Note: These parameters are not measured for all devices, but are sampled values.
No. 6624-4/9
LC35W1000BM, BTS-70U/10U
AC Electrical Characteristics at Ta = –40 to +85°C, V = 2.7 to 3.6 V
CC
AC test conditions
Input pulse voltage levels: V = 0.2 V , V = 0.8 V
CC
IL
CC
IH
Input rise and fall times: 5 ns
Input and output timing leves: 1/2 V
CC
Output load: 30 pF (including the jig capacitance)
Read cycle
–70U
–10U
Parameter
Symbol
Unit
min
70
max
min
100
max
Read cyle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
CE1 access time
70
70
70
50
100
100
100
50
tCA1
tCA2
tOA
CE2 access time
OE access time
Output hold time
tOH
10
10
10
5
10
10
10
5
CE1 output enable time
CE2 output enable time
OE output enable time
CE1 output disable time
CE2 output disable time
OE output disable time
tCOE1
tCOE2
tOCE
tCOD1
tCOD2
tOOD
40
40
35
35
35
30
Write cycle
–70U
–10U
Parameter
Symbol
Unit
min
70
0
max
min
100
0
max
Write cyle time
tWC
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time
Write pulse width
CE1 setup time
tWP
tCW1
tCW2
tWR
50
60
60
0
70
90
90
0
CE2 setup time
Write recovery time
CE1 write recovery time
CE2 write recovery time
Data setup time
tWR1
tWR2
tDS
0
0
0
0
40
0
50
0
Data hold time
tDH
CE1 data hold time
CE2 data hold time
WE output enable time
WE output disable time
tDH1
tDH2
tWOE
tWOD
0
0
0
0
5
5
35
30
No. 6624-5/9
LC35W1000BM, BTS-70U/10U
Timing Charts
Read cycle (1) : CE1 = OE = V , CE2 = V , WE = V
IH
IL
IH
Read cycle (2) : WE = V
IH
No. 6624-6/9
LC35W1000BM, BTS-70U/10U
Write cycle (6) (WE = control) *6
*3
*4
*4
*5
A13492
Write cycle (2) (CE1 = control) *6
*3
*4
*4
*5
A13493
No. 6624-7/9
LC35W1000BM, BTS-70U/10U
, and t are stipulated as the times until the output reaches the high-impedance
Notes: 1. The times t
, t
, t
COD1 COD2 OOD
WOD
state. They are not stipulated by output voltage level.
2. Do not apply reverse phase signals to the data outputs when the data outputs are in the output state.
3. t is the period that CE1 and WE are at the low level and CE2 is at the high level, and is defined as the time
WP
from the fall of WE until the rise of CE1 or WE or the fall of CE2, whichever occurs first.
4. t
and t
are the period that CE1 and WE are at the low level and CE2 is at the high level, and are defined
CW1
CW2
as the time from the fall of CE1 or the rise of CE2 to the rise of either CE1 or WE or the fall of CE2, whichever
occurs first.
5. The data outputs go to the high-impedance state when any one of the following states hold: OE is at the high
level, CE1 is at the high level, CE2 is at the low level, or WE is at the low level.
6. If OE is at the high level during the write cycle, the data outputs will go to the high-impedance state.
Data Retention Characteristics at Ta = –40 to +85°C
Ratings
Parameter
Symbol
Conditions
Unit
min
2.0
typ
max
3.6
VDR1
VDR2
V
V
CE1 ≥ VCC – 0.2 V, VCE2 ≥ VCC – 0.2 V or VCE2 ≤ 0.2 V
CE2 ≤ 0.2 V
V
V
Data retention supply voltage
2.0
3.6
16
8
VCC = 3.0 V, VCE1 ≥ VCC – 0.2 V,
CE2 ≥ VCC – 0.2 V,
or VCE2 ≤ 0.2 V
–40°C to +85°C
–40°C to +70°C
+25°C
Data retention supply current
ICCDR1
V
µA
0.1
Chip enable setup time
Chip enable hold time
Note: * Ta = +25°C
tCDR
tR
0
5
ns
ms
Data Retention Waveforms (1) (CE1 control)
Data retention mode
A13494
Data Retention Waveforms (2) (CE2 control)
Data retention mode
A13495
No. 6624-8/9
LC35W1000BM, BTS-70U/10U
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of April, 2002. Specifications and information herein are subject to
change without notice.
PS No. 6624-9/9
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